Time sequence convergence system, method and device and storage medium

Abstract

The invention discloses a time sequence convergence system, method and device and a storage medium, and relates to the technical field of chips. A CP port of the convergence register is connected with a clock chip pin processing unit of the input and output module and is used for acquiring a clock signal input by the clock chip pin processing unit; a D port of the convergence register is connected with a Q port of a data register in the high-speed peripheral interface and is used for receiving a data signal sent by the data register; and a Q port of the convergence register is connected with a data chip pin processing unit in the input / output module and is used for sending the data signal to the data chip pin processing unit. According to the technical scheme provided by the embodiment of the invention, the time sequence convergence time of the chip is reduced, the clock signal delay is reduced, and the stability of data transmission of the chip is improved; and meanwhile, the high-speed peripheral interface is not limited by layout placement positions, so that the convenience of chip layout and wiring is improved, and the complexity of chip design is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a timing closure system, method, device and storage medium. Background Art

[0002] With the continuous development of chip technology, under the demand for high-performance functions, the chip area is getting larger and larger, the data path is getting longer and longer, and the layout and wiring in the chip is becoming more and more difficult to meet the timing requirements.

[0003] In the prior art, functional modules equipped with high-speed peripheral interfaces often need to use external clock signals to maintain clock synchronization inside and outside the chip. At this time, in order to make the timing of the chip communication interface converge as quickly as possible, it is usually necessary to place the above-mentioned functional modules close to the chip pin processing unit (IO Pad) at the edge of the chip during the chip version layout stage.

[0004] However, the above-mentioned functional module also needs to consider the timing issues of connecting with other supporting modules in the chip. The functional module is generally configured in the middle position of the chip layout, which restricts the above-mentioned configuration method and makes it impossible to be set near the chip pin processing unit, making it difficult to converge the timing of the chip communication interface. Summary of the invention

[0005] The present invention provides a timing closure system, method, device and storage medium to solve the problem of long timing closure time of a communication interface in a chip.

[0006] According to one aspect of the present invention, a timing convergence system is provided, which is configured on a chip and includes: at least one convergence register; a CP port of the convergence register is connected to a clock chip pin processing unit of an input / output module, and is used to obtain a clock signal input by the clock chip pin processing unit;

[0007] The D port of the convergence register is connected to the Q port of the data register in the high-speed peripheral interface, and is used to receive the data signal sent by the data register;

[0008] The Q port of the convergence register is connected to the data chip pin processing unit in the input-output module, and is used to send the data signal to the data chip pin processing unit;

[0009] A timing path between the convergence register and the data chip pin processing unit is shorter than a timing path between the data register and the data chip pin processing unit.

[0010] A timing path between the convergence register and the data chip pin processing unit is shorter than a timing path between the convergence register and the high-speed peripheral interface.

[0011] The timing closure system is configured in the input-output module.

[0012] The chip includes at least one of an automotive chip, a high-speed interface chip and a communication chip; the high-speed peripheral interface includes a simplified media independent interface configured in an Ethernet media access control module.

[0013] The convergence register has the same physical structure and configuration parameters as the data register.

[0014] The timing convergence system includes a first convergence register, a second convergence register and a third convergence register; the CP port of the first convergence register, the CP port of the second convergence register and the CP port of the third convergence register are all connected to the clock chip pin processing unit of the input-output module; the D port of the first convergence register is connected to the Q port of the first data register in the simplified media independent interface, for receiving the low-bit data signal sent by the first data register; the Q port of the first convergence register is connected to the first data chip pin processing unit in the input-output module, for sending the low-bit data signal to the first data chip pin processing unit; the D port of the second convergence register, The Q port of the second data register in the simplified media independent interface is connected to receive the high-order data signal issued by the second data register; the Q port of the second convergence register is connected to the second data chip pin processing unit in the input-output module, and is used to send the high-order data signal to the second data chip pin processing unit; the D port of the third convergence register is connected to the Q port of the third data register in the simplified media independent interface, and is used to receive the send enable signal issued by the third data register; the Q port of the third convergence register is connected to the third data chip pin processing unit in the input-output module, and is used to send the send enable signal to the third data chip pin processing unit.

[0015] According to another aspect of the present invention, a timing closure method is provided, which is applied to the timing closure system described in any embodiment of the present invention, including:

[0016] The convergence register receives the clock signal input by the clock chip pin processing unit through the CP port;

[0017] The convergence register receives a data signal sent by a data register in the high-speed peripheral interface through a D port;

[0018] The convergence register sends the data signal to the data chip pin processing unit through the Q port based on the clock signal.

[0019] According to another aspect of the present invention, a timing closure device is provided, which is applied to the timing closure system described in any embodiment of the present invention, including:

[0020] A clock signal receiving module, configured in the convergence register, for receiving a clock signal input from a clock chip pin processing unit through a CP port;

[0021] A data signal receiving module, configured in the convergence register, for receiving a data signal sent by a data register in the high-speed peripheral interface through a D port;

[0022] The data signal receiving and sending module is configured in the convergence register and is used to send the data signal to the data chip pin processing unit through the Q port based on the clock signal.

[0023] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the timing closure method described in any embodiment of the present invention when executed.

[0024] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the timing closure method according to any embodiment of the present invention is implemented.

[0025] According to the technical solution of the embodiment of the present invention, the convergence register is connected to the clock chip pin processing unit of the input-output module, and receives the clock signal input by the clock chip pin processing unit; at the same time, the convergence register is connected to the data register in the high-speed peripheral interface, and receives the data signal sent by the data register; in addition, the convergence register is connected to the data chip pin processing unit in the input-output module to send the data signal to the data chip pin processing unit; thereby, the timing convergence time of the chip is reduced, the clock signal delay is reduced, and the stability of the chip transmitting data is improved; at the same time, the high-speed peripheral interface has no restrictions on the layout placement position, which improves the convenience of chip layout and wiring and reduces the complexity of chip design.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a structural schematic diagram of a timing closure system provided according to Embodiment 1 of the present invention;

[0029] Figure 2 It is a schematic diagram of the connection relationship between the high-speed peripheral interface and the input-output module in the conventional technical solution provided in the first embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of the structure of another timing closure system provided according to the second embodiment of the present invention;

[0031] Figure 4 It is a schematic diagram of the connection relationship between the simplified media independent interface and the input and output modules in the conventional technical solution provided in the second embodiment of the present invention;

[0032] Figure 5 is a flow chart of a timing closure method provided according to Embodiment 3 of the present invention;

[0033] Figure 6 It is a structural schematic diagram of a timing convergence device provided according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] Embodiment 1

[0037] Figure 1 A schematic diagram of the structure of a timing closure system provided in Embodiment 1 of the present invention is shown in FIG. Figure 1 As shown, the timing convergence system is configured in a chip, and includes: at least one convergence register 100; a CP port of the convergence register 100 is connected to a clock chip pin processing unit 200 of an input-output module, and is used to obtain a clock signal input by the clock chip pin processing unit 200.

[0038] The D port of the convergence register 100 is connected to the Q port of the data register 300 in the high-speed peripheral interface, and is used to receive the data signal sent by the data register 300; the Q port of the convergence register 100 is connected to the data chip pin processing unit 400 in the input-output module, and is used to send the data signal to the data chip pin processing unit 400; the timing path between the convergence register 100 and the data chip pin processing unit 400 is smaller than the timing path between the data register 300 and the data chip pin processing unit 400.

[0039] Specifically, the chip pin processing unit (IO Pad) is used to process the input and output signals of the chip pins. It can send the processed chip pin signals to the inside of the chip, and can also process the output signals from the inside of the chip and send them to the chip pins; the clock chip pin processing unit 200 refers to a chip pin processing unit used to input the clock signal into the chip; the data chip pin processing unit 400 refers to a chip pin processing unit used to output the data signal to the chip pin, thereby sending it to the outside of the chip; the data register 300 refers to a register in the high-speed peripheral interface used to send data signals.

[0040] In the implementation of the present invention, the high-speed peripheral interface needs to obtain an external input clock signal so that the functional modules inside and outside the chip can maintain clock synchronization; Figure 2As shown, in the traditional technical solution, the CP port of the data register 300 of the high-speed peripheral interface is connected to the clock chip pin processing unit 200 of the input / output (I / O) module, and is used to receive the clock signal issued by the clock chip pin processing unit 200; wherein, the CP port is the clock signal port of the register.

[0041] at the same time Figure 2 In the figure, the Q port of the data register 300 of the high-speed peripheral interface is connected to the data chip pin processing unit 400 of the input-output module, and is used to send the data signal to the data chip pin processing unit 400; wherein the Q port is the data output port of the register; the data chip pin processing unit 400 then sends the received data signal to the outside of the chip. Figure 2 The data transmission delay in is equal to the delay from the clock chip pin processing unit 200 to the CP port of the data register 300, plus the delay from the CP port of the data register 300 to the Q port of the data register 300, plus the delay from the Q port of the data register 300 to the data chip pin processing unit 400.

[0042] In the embodiment of the present invention, Figure 1 As shown, the CP port of the convergence register 100 is connected to the clock chip pin processing unit 200 of the input-output module; the D port of the convergence register 100 is connected to the Q port of the data register 300 in the high-speed peripheral interface; the Q port of the convergence register 100 is connected to the data chip pin processing unit 400 in the input-output module; the data register 300 sends the data signal to the D port of the convergence register 100 through the Q port, and the D port of the convergence register 100 then sends the data signal to the data chip pin processing unit 400 through the Q port; the data chip pin processing unit 400 then sends the data signal to the outside of the chip; Figure 1 The data transmission delay is equal to the delay from the clock chip pin processing unit 200 to the CP port of the convergence register 100, plus the delay from the CP port of the convergence register 100 to the Q port of the convergence register 100, plus the delay from the Q port of the convergence register 100 to the data chip pin processing unit 400.

[0043] Since the delay from the Q port of the convergence register 100 directly to the data chip pin processing unit 400 is shorter than the delay from the Q port of the data register 300 directly to the data chip pin processing unit 400, the data transmission path between the end register (i.e., the convergence register 100) in the embodiment of the present invention and the opposite end register outside the chip is obviously shorter than the data transmission path between the end register (i.e., the data register 300) in the traditional technical solution and the opposite end register outside the chip, and the timing convergence time is also shorter, thereby reducing the clock signal delay and improving the stability of chip data transmission; at the same time, the high-speed peripheral interface has no restrictions on the layout placement position, even if it is placed in the middle of the chip layout, or placed in a position far away from the input and output modules, it will not affect the timing convergence time of the chip, thereby improving the convenience of chip layout and wiring and reducing the complexity of chip design.

[0044] Optionally, in an embodiment of the present invention, the timing path between the convergence register 100 and the data chip pin processing unit 400 is shorter than the timing path between the convergence register 100 and the high-speed peripheral interface. As described in the above technical solution, the convergence register 100 is not only arranged between the data chip pin processing unit 400 and the high-speed peripheral interface, but also arranged on a side closer to the data chip pin processing unit 400, that is, the timing path between the convergence register 100 and the data chip pin processing unit 400 is shorter than the timing path between the convergence register 100 and the high-speed peripheral interface; thereby further shortening the timing path between the convergence register 100 and the data chip pin processing unit 400, that is, shortening the data transmission path, and reducing the timing convergence time.

[0045] Optionally, in an embodiment of the present invention, the timing closure system is configured in the input-output module. The above-mentioned convergence timing closure system can be configured in the input-output module, thereby not only ensuring a shorter data transmission path between the convergence register 100 and the data chip pin processing unit 400, but also making full use of existing resources in the input-output module, improving the resource utilization of the input-output module, and avoiding configuring new hardware components in the chip, thereby increasing the chip area overhead, and reducing the hardware cost and design complexity of the chip.

[0046] Optionally, in an embodiment of the present invention, the chip includes at least one of a vehicle-regulatory chip, a high-speed interface chip, and a communication chip; the high-speed peripheral interface includes a simplified media independent interface configured in an Ethernet media access control module. Existing vehicle-regulatory chips usually use a 28-nanometer manufacturing process, which has high requirements for performance, function, and temperature stability. The Ethernet media access control (Media Access Control, MAC) module used for data transmission includes a variety of external signal interfaces (Physical, PHY), and the clock frequency of the simplified media independent interface (Reduced Media Independent Interface, RMII) is 50 MHz, which has very high timing requirements. By deploying the above-mentioned timing convergence system in the vehicle-regulatory chip, the timing convergence time can be greatly reduced, the data transmission stability of the Ethernet MAC module is improved, and the high-performance use requirements of the vehicle-regulatory chip are met; in addition, the above-mentioned timing convergence system can also be configured in a high-speed interface chip or a communication chip to reduce the timing convergence time of the above-mentioned type of chip.

[0047] Optionally, in an embodiment of the present invention, the convergence register 100 has the same physical structure and configuration parameters as the data register 300. The register newly deployed in the chip by the timing convergence system (i.e., the convergence register 100) not only needs to communicate and connect with the data register 300 in the high-speed peripheral interface, but also needs to replace the data register 300 and communicate and connect with the data chip pin processing unit 400. Therefore, a convergence register 100 having the same physical structure and configuration parameters as the data register 300 is added to the timing convergence system, which not only ensures stable data transmission between the convergence register 100 and the data register 300, but also makes the transmission parameters (for example, transmission speed and transmission protocol) between the convergence register 100 and the data chip pin processing unit 400 consistent with the original transmission parameters between the data register 300 and the data chip pin processing unit 400, thereby ensuring stable transmission of chip data.

[0048] According to the technical solution of the embodiment of the present invention, the convergence register is connected to the clock chip pin processing unit of the input-output module, and receives the clock signal input by the clock chip pin processing unit; at the same time, the convergence register is connected to the data register in the high-speed peripheral interface, and receives the data signal sent by the data register; in addition, the convergence register is connected to the data chip pin processing unit in the input-output module to send the data signal to the data chip pin processing unit; thereby, the timing convergence time of the chip is reduced, the clock signal delay is reduced, and the stability of the chip transmitting data is improved; at the same time, the high-speed peripheral interface has no restrictions on the layout placement position, which improves the convenience of chip layout and wiring and reduces the complexity of chip design.

[0049] Embodiment 2

[0050] Figure 3 A schematic diagram of the structure of a timing closure system provided by the second embodiment of the present invention is as follows: Figure 3 As shown, the timing convergence system includes a first convergence register 101, a second convergence register 102 and a third convergence register 103; the CP port of the first convergence register 101, the CP port of the second convergence register 102 and the CP port of the third convergence register 103 are all connected to the clock chip pin processing unit 200 of the input-output module, and are used to obtain the clock signal input by the clock chip pin processing unit 200.

[0051] The D port of the first convergence register 101 is connected to the Q port of the first data register 301 in the simplified media independent interface, and is used to receive the low-order data signal issued by the first data register 301; the Q port of the first convergence register 101 is connected to the first data chip pin processing unit 401 in the input-output module, and is used to send the low-order data signal to the first data chip pin processing unit 401.

[0052] The D port of the second convergence register 102 is connected to the Q port of the second data register 302 in the simplified media independent interface, and is used to receive the high-order data signal emitted by the second data register 302; the Q port of the second convergence register 102 is connected to the second data chip pin processing unit 402 in the input-output module, and is used to send the high-order data signal to the second data chip pin processing unit 402.

[0053] The D port of the third convergence register 103 is connected to the Q port of the third data register 303 in the simplified media independent interface, and is used to receive a send enable signal issued by the third data register 303; the Q port of the third convergence register 103 is connected to the third data chip pin processing unit 403 in the input-output module, and is used to send the send enable signal to the third data chip pin processing unit 403.

[0054] Specifically, Figure 4 As shown, in the traditional technical solution, the CP port of the first data register 301, the CP port of the second data register 302 and the CP port of the third data register 303 in the simplified media independent interface are all connected to the clock chip pin processing unit 200 of the input and output module, and are used to receive the clock signal issued by the clock chip pin processing unit 200, that is, the "clk_rmii_i" signal.

[0055] At the same time, the Q port of the first data register 301 is connected to the first data chip pin processing unit 401 of the input-output module, and is used to send the low-order data signal, that is, the "eth_phy_txd_o[0]" signal, to the first data chip pin processing unit 401; the Q port of the second data register 302 is connected to the second data chip pin processing unit 402 of the input-output module, and is used to send the high-order data signal, that is, the "eth_phy_txd_o[1]" signal, to the second data chip pin processing unit 402; the Q port of the third data register 303 is connected to the third data chip pin processing unit 403 of the input-output module, and is used to send the sending enable signal, that is, the "eth_phy_txctl_o" signal, to the third data chip pin processing unit 403.

[0056] Taking the first data register 301 as an example, Figure 4 The data transmission delay in is equal to the delay from the clock chip pin processing unit 200 to the CP port of the first data register 301, plus the delay from the CP port of the first data register 301 to the Q port of the first data register 301, plus the delay from the Q port of the first data register 301 to the first data chip pin processing unit 401.

[0057] In the embodiment of the present invention, not only the CP port of the first data register 301, the CP port of the second data register 302 and the CP port of the third data register 303 in the simplified media independent interface are connected to the clock chip pin processing unit 200 of the input and output module for receiving the clock signal issued by the clock chip pin processing unit 200; but also the CP port of the first convergence register 101, the CP port of the second convergence register 102 and the CP port of the third convergence register 103 in the timing convergence system are also connected to the clock chip pin processing unit 200 of the input and output module for receiving the clock signal issued by the clock chip pin processing unit 200.

[0058] Also taking the first data register 301 as an example, Figure 3 The data transmission delay in is equal to the delay from the clock chip pin processing unit 200 to the CP port of the first convergence register 101, plus the delay from the CP port of the first convergence register 101 to the Q port of the first convergence register 101, plus the delay from the Q port of the first convergence register 101 to the first data chip pin processing unit 401.

[0059] Since the delay from the Q port of the first convergence register 101 to the first data chip pin processing unit 401 is shorter than the delay from the Q port of the first data register 301 to the first data chip pin processing unit 401, the data transmission path between the end register in the embodiment of the present invention and the opposite end register outside the chip is obviously shorter than the data transmission path between the end register in the traditional technical solution and the opposite end register outside the chip, and the timing convergence time is also shorter, thereby reducing the clock signal delay and improving the stability of chip data transmission; at the same time, the Ethernet MAC module where the simplified media independent interface is located has no restrictions on the layout placement position, even if it is placed in the middle of the chip layout, or placed far away from the input and output modules, it will not affect the timing convergence time of the chip, thereby improving the convenience of chip layout and wiring and reducing the complexity of chip design.

[0060] The technical solution of the embodiment of the present invention reduces the timing convergence time of the automotive-grade chip, reduces the clock signal delay, and improves the stability of chip data transmission after the timing convergence system is configured in the input and output modules of the automotive-grade chip; at the same time, the Ethernet MAC module in the automotive-grade chip has no restrictions on the layout position, which improves the convenience of chip layout and wiring and reduces the complexity of chip design.

[0061] Embodiment 3

[0062] Figure 5 A flowchart of a timing closure method provided in the third embodiment of the present invention, the method can be executed by a timing closure device, the timing closure device can be implemented in the form of hardware and / or software, the timing closure device can be configured in the timing closure system in any embodiment of the present invention, the timing closure system can be configured in a chip, typically, can be configured in an automotive grade chip, for example, an automotive control chip and an automotive functional chip. Figure 5 As shown, the method includes:

[0063] S101. The convergence register receives a clock signal input from a clock chip pin processing unit through a CP port.

[0064] S102. The convergence register receives a data signal sent by a data register in the high-speed peripheral interface through a D port.

[0065] S103. The convergence register sends the data signal to the data chip pin processing unit through a Q port based on the clock signal.

[0066] According to the technical solution of the embodiment of the present invention, the convergence register is connected to the clock chip pin processing unit of the input-output module, and receives the clock signal input by the clock chip pin processing unit; at the same time, the convergence register is connected to the data register in the high-speed peripheral interface, and receives the data signal sent by the data register; in addition, the convergence register is connected to the data chip pin processing unit in the input-output module to send the data signal to the data chip pin processing unit; thereby, the timing convergence time of the chip is reduced, the clock signal delay is reduced, and the stability of the chip transmitting data is improved; at the same time, the high-speed peripheral interface has no restrictions on the layout placement position, which improves the convenience of chip layout and wiring and reduces the complexity of chip design.

[0067] Embodiment 4

[0068] Figure 6 : is a structural block diagram of a timing closure device provided by Embodiment 4 of the present invention, and the device specifically includes:

[0069] The clock signal receiving module 601 is configured in the convergence register and is used to receive the clock signal input by the clock chip pin processing unit through the CP port;

[0070] A data signal receiving module 602, configured in the convergence register, for receiving a data signal sent by a data register in the high-speed peripheral interface through a D port;

[0071] The data signal receiving and sending module 603 is configured in the convergence register, and is used to send the data signal to the data chip pin processing unit through the Q port based on the clock signal.

[0072] According to the technical solution of the embodiment of the present invention, the convergence register is connected to the clock chip pin processing unit of the input-output module, and receives the clock signal input by the clock chip pin processing unit; at the same time, the convergence register is connected to the data register in the high-speed peripheral interface, and receives the data signal sent by the data register; in addition, the convergence register is connected to the data chip pin processing unit in the input-output module to send the data signal to the data chip pin processing unit; thereby, the timing convergence time of the chip is reduced, the clock signal delay is reduced, and the stability of the chip transmitting data is improved; at the same time, the high-speed peripheral interface has no restrictions on the layout placement position, which improves the convenience of chip layout and wiring and reduces the complexity of chip design.

[0073] The above device can execute the timing closure method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the timing closure method provided by any embodiment of the present invention.

[0074] Embodiment 5

[0075] In some embodiments, the timing closure method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the timing closure method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the timing closure method in any other appropriate manner (e.g., by means of firmware).

[0076] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0077] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0078] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0079] To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0080] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0081] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0082] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0083] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing closure system, characterized in that: Configured in the chip, including: at least one convergence register; the CP port of the convergence register is connected to the clock chip pin processing unit of the input and output module, and is used to obtain the clock signal input by the clock chip pin processing unit; The D port of the convergence register is connected to the Q port of the data register in the high-speed peripheral interface, and is used to receive the data signal sent by the data register; The Q port of the convergence register is connected to the data chip pin processing unit in the input-output module, and is used to send the data signal to the data chip pin processing unit; A timing path between the convergence register and the data chip pin processing unit is shorter than a timing path between the data register and the data chip pin processing unit.

2. The timing closure system according to claim 1, characterized in that: A timing path between the convergence register and the data chip pin processing unit is shorter than a timing path between the convergence register and the high-speed peripheral interface.

3. The timing closure system according to claim 1, characterized in that: The timing closure system is configured in the input-output module.

4. The timing closure system according to claim 1, characterized in that: The chip includes at least one of an automotive chip, a high-speed interface chip and a communication chip; the high-speed peripheral interface includes a simplified media independent interface configured in an Ethernet media access control module.

5. The timing closure system according to claim 1, characterized in that: The convergence register has the same physical structure and configuration parameters as the data register.

6. The timing closure system according to claim 4, characterized in that: The timing closure system includes a first convergence register, a second convergence register and a third convergence register; The CP port of the first convergence register, the CP port of the second convergence register and the CP port of the third convergence register are all connected to the clock chip pin processing unit of the input-output module, and are used to obtain the clock signal input by the clock chip pin processing unit; The D port of the first convergence register is connected to the Q port of the first data register in the simplified media independent interface, and is used to receive the low-bit data signal sent by the first data register; the Q port of the first convergence register is connected to the first data chip pin processing unit in the input and output module, and is used to send the low-bit data signal to the first data chip pin processing unit; The D port of the second convergence register is connected to the Q port of the second data register in the simplified media independent interface, and is used to receive the high-bit data signal sent by the second data register; the Q port of the second convergence register is connected to the second data chip pin processing unit in the input and output module, and is used to send the high-bit data signal to the second data chip pin processing unit; The D port of the third convergence register is connected to the Q port of the third data register in the simplified media independent interface, and is used to receive a send enable signal issued by the third data register; the Q port of the third convergence register is connected to the third data chip pin processing unit in the input-output module, and is used to send the send enable signal to the third data chip pin processing unit.

7. A timing closure method, characterized in that: The timing closure system applied to any one of claims 1 to 6 comprises: The convergence register receives the clock signal input by the clock chip pin processing unit through the CP port; The convergence register receives a data signal sent by a data register in the high-speed peripheral interface through a D port; The convergence register sends the data signal to the data chip pin processing unit through the Q port based on the clock signal.

8. A timing closure device, characterized in that: The timing closure system applied to any one of claims 1 to 6 comprises: A clock signal receiving module, configured in the convergence register, for receiving a clock signal input from a clock chip pin processing unit through a CP port; A data signal receiving module, configured in the convergence register, for receiving a data signal sent by a data register in the high-speed peripheral interface through a D port; The data signal receiving and sending module is configured in the convergence register and is used to send the data signal to the data chip pin processing unit through the Q port based on the clock signal.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the timing closure method of claim 7 when executed.

10. According to another aspect of the present invention, there is provided a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the timing closure method according to claim 7 is implemented.

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