Novel coarseness configurable architecture based on in-memory computing technology

Abstract

The invention discloses a novel coarseness configurable architecture based on an in-memory computing technology, relates to an SRAM (Static Random Access Memory) technology, and provides a scheme aiming at four problems of dependence on an on-chip cache and the like in the prior art. Comprising a dispersion / aggregation module, a management module, a conversion module and an in-memory computing macro. And the in-memory computing macro is used for performing operation under the control of the management module. Compared with other coarse-grained configurable architecture technical schemes based on the von Neumann architecture processing engine, the Von Neumann architecture processing engine has the advantages of being smaller in area, lower in power consumption and higher in throughput capacity. Meanwhile, a feasible solution is provided for four challenges of an SRAM in-memory computing technology: the advantages of the in-memory computing technology in a computing power density and energy efficiency method are fully utilized in the aspect of utilization rate; the computing architecture method flexibly determines the on-chip cache size of the coarse-grained configurable architecture; the calculation completeness meets the calculation requirements of more applications; and in the aspect of software ecology, the software is allowed to be called by an RISC-V CPU, and compilation and acceleration of application under the RISC-V ecology are supported.

Description

Technical Field

[0001] The present invention relates to SRAM technology, and in particular to a novel coarse-grained configurable architecture based on in-memory computing technology. Background Art

[0002] Although SRAM in-memory computing technology has become one of the current mainstream storage-computing integrated solutions due to its advantages of high process maturity and strong robustness, it still faces key issues and challenges including unit circuit design, reliability, utilization, computing architecture, computing completeness, and software ecology. In terms of utilization, due to the different types and sizes of operators, in the face of flexible and changeable operator requirements in real applications, deploying different real applications on an in-memory computing array of fixed size and fixed operators may cause a significant reduction in computing resource utilization, resulting in the inability to fully utilize the performance advantages of SRAM in-memory computing technology in terms of computing power density and energy efficiency. In terms of computing architecture, since some data such as intermediate calculation results still need to rely on on-chip cache during the execution of the algorithm, the limited on-chip cache capacity may become a new system bottleneck, resulting in a significant increase in off-chip memory access overhead. Regarding computing completeness, although in-memory computing can significantly improve computing power density and energy efficiency for matrix-matrix operations, a complete application in real application scenarios still requires scalar operations, vector operations, and nonlinear calculations, which puts forward new requirements for the computing completeness of SRAM-based in-memory computing accelerators. Regarding the software ecosystem, in addition to optimizing the underlying circuits and improving performance, in order to implement in-memory computing technology, a matching compiler and tool chain are also required. How to design a matching instruction set in combination with the existing ecological environment to facilitate participation in compilation and accelerated applications has become a question that needs to be considered. Summary of the invention

[0003] The purpose of the present invention is to provide a novel coarse-grained configurable architecture based on in-memory computing technology to solve the problems existing in the above-mentioned prior art.

[0004] The novel coarse-grained configurable architecture based on in-memory computing technology described in the present invention includes:

[0005] The scatter / gather module is used to split or pack data of different precisions, interact with external modules, and organize sparse data into dense data and send it to the management module;

[0006] The management module is used to decode the instructions and data transmitted by the host, convert the instructions into control commands of the in-memory computing macro, and send the control commands and data to the in-memory computing macro of the corresponding address to participate in the calculation;

[0007] A conversion module, used to transmit signals to a specified address to build an on-chip network;

[0008] The in-memory computing macro includes a 512x256 8T SRAM array, a computing logic unit supporting addition, subtraction, and partial product, a set of addition trees, a control unit, a timing control circuit, and peripheral circuits; the in-memory computing macro is used to perform operations under the control of the management module.

[0009] The scatter / gather module includes two buffers, a left shifter, and a right shifter; the external data is divided into a header and input data;

[0010] The header is used to determine whether the input data is an instruction or a data signal involved in calculation. If the input data is an instruction, it is directly sent to the management module; otherwise, it is sent to the cache for splicing.

[0011] The management module includes two data interaction modules, two CIM managers, a scratchpad memory SPM, a CIM mapping register, and a crossbar switch matrix; the instructions and data signals transmitted from the scatter / gather module are respectively sent to the CIM mapping register and the data interaction module;

[0012] The CIM mapping register is used to store the data movement path and the function selection and mode selection of each in-memory calculation macro. The CIM mapping register outputs commands to the CIM manager;

[0013] The CIM manager is used to manage the conversion modules and in-memory calculation macros of the row;

[0014] The data interaction module is used to receive the data involved in the calculation and send it to the bank for calculation or to the adjacent management module according to the judgment conditions.

[0015] The conversion module includes four data interaction modules for receiving and transmitting data to adjacent conversion modules or in-memory computing macros.

[0016] The calculation process of the in-memory calculation macro is as follows:

[0017] The first step is to select whether to enable the multi-function supported computing logic unit MFU and addition tree module according to the type of operator to be calculated;

[0018] The second step is to configure the function selection of the computing logic unit MFU supported by the multi-function;

[0019] The third step is to write data into the SRAM array;

[0020] Step 4: read two sets of data at the same time to participate in the calculation, and output the results to the conversion module S;

[0021] The fifth step is to determine whether the calculation is finished. If it is finished, the calculation is ended and wait for the next round of calculation. If it is not finished, continue to read data and participate in the calculation until the calculation is finished.

[0022] The novel coarse-grained configurable architecture based on in-memory computing technology described in the present invention has the advantages of smaller area, lower power consumption and higher throughput compared with other coarse-grained configurable architecture technology solutions based on von Neumann architecture processing engines. At the same time, a feasible solution is proposed for the four major challenges of SRAM in-memory computing technology: Regarding utilization, the in-memory computing macro supports five computing methods: vector addition, vector subtraction, vector-matrix multiplication, matrix-matrix multiplication, and comparison operation, making full use of the advantages of in-memory computing technology in computing power density and energy efficiency methods; Regarding computing architecture methods, the in-memory computing mode and memory mode of the in-memory computing macro can flexibly determine the on-chip cache size of the coarse-grained configurable architecture, alleviating the system bottleneck caused by the limited on-chip cache; Regarding computing completeness, the in-memory computing macro not only supports matrix operations, but also supports vector operations, meeting the computing requirements of more applications; Regarding software ecology, the proposed architecture allows being called by RISC-V CPU, supporting compilation and acceleration of applications under the RISC-V ecology. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of the novel coarse-grained configurable architecture described in the present invention.

[0024] Figure 2 It is a schematic diagram of the structure of the dispersion / aggregation module in the present invention.

[0025] Figure 3 It is a structural diagram of the management module in the present invention.

[0026] Figure 4 It is a structural schematic diagram of the conversion module in the present invention.

[0027] Figure 5 It is a structural diagram of the data flow control unit described in the present invention.

[0028] Figure 6 It is a schematic diagram of the structure of the in-memory computing macro described in the present invention.

[0029] Figure 7 It is a schematic diagram of a method for simultaneously reading out three bit lines WBL, WBLb, and RBL by the in-memory computing macro described in the present invention.

[0030] Figure 8 It is a structural schematic diagram of the multifunctional support computing logic unit described in the present invention.

[0031] Fig. 9 It is a schematic diagram of the calculation process of the novel coarse-grained configurable architecture described in the present invention.

[0032] Fig.10It is an instruction representation schematic of the RISC-V extended instruction set matched by the new coarse-grained configurable architecture described in the present invention.

[0033] Fig.11 It is a schematic diagram of the calculation flow of the in-memory calculation macro described in the present invention.

[0034] Fig.12 It is a timing diagram of the calculation process of the in-memory calculation macro described in the present invention.

[0035] Fig.13 It is a schematic diagram of the addition calculation process of the calculation logic unit described in the present invention.

[0036] Fig.14 It is a schematic diagram of the subtraction calculation process of the calculation logic unit described in the present invention.

[0037] Fig.15 It is a schematic diagram of the partial product calculation process of the calculation logic unit described in the present invention.

[0038] Fig.16 It is a schematic diagram of the interactive communication between the novel coarse-grained configurable architecture described in the present invention and the RISC V CPU processor.

[0039] Reference numerals:

[0040] Scatter / gather module S / G Unit, management module MU, conversion module S, in-memory computing macro CIM;

[0041] Precharge module Precharge, read word line decoder RWL Decoder, write word line decoder WWL Decoder, bit line driver BL Driver, sense amplifier SA, multi-function support calculation logic unit MFU, adder tree Adder Tree, control circuit Control Unit, timing control circuit Timing. DETAILED DESCRIPTION

[0042] The present invention discloses a novel coarse-grained configurable architecture SHWCIM based on in-memory computing technology, such as Figure 1The following are shown: a scatter / gather module, which is used to split or pack data of different data precisions such as INT 8, INT 16, INT 32, and INT 64, interact with external modules, and organize sparse data into dense data and send it to the management module to improve data processing efficiency. A management module, which is used to decode the instructions and data transmitted by the host, convert the instructions into control commands of the in-memory calculation macro, and send the control commands and data to the in-memory calculation macro of the corresponding address to participate in the calculation. A conversion module, as a transfer station for various signals, is used to transmit signals to the module of the specified address to create an on-chip network Network on Chip. Multi-function supports configurable in-memory calculation macros, including a 512x256 8T SRAM array, a calculation logic unit that supports addition, subtraction, and partial product, a set of addition trees, a control unit, and other peripheral circuits.

[0043] Scatter / gather module S / G Unit Figure 2 As shown, it includes two buffers, a left shifter LeftShifter, and a right shifter Right Shifter. External data is divided into header Flag and input data Input Data. When the header is FF, it indicates that the input data is an instruction and is directly sent to the management module MU. When the header is data other than FF, it indicates that the input data is a data signal involved in the calculation and is sent to the buffer for splicing. Regardless of the data precision is 8b / 16b / 32b / 64b, it will be spliced ​​into 256b data bit width and sent to the management module MU to complete a data packing process. When SHWCIM data is output, data unpacking is required to unpack the 256b data in the opposite way into data with the precision required by the system.

[0044] The management module MU is as follows Figure 3 As shown, it includes two data interaction modules, two CIM managers, a note memory SPM, a CIM mapping register, and a crossbar switch matrix Crossbar. The instructions and data signals transmitted from the scatter / gather module S / G Unit are sent to the CIM mapping register and the data interaction module respectively. The CIM mapping register is used to store the data movement path in the SHWCIM, that is, the routing table, as well as the function selection and mode selection of each multi-function supporting configurable in-memory calculation macro. The CIM mapping register outputs the command CMD to the CIM manager. The CIM manager is used to manage the conversion module and the multi-function supporting configurable in-memory calculation macro of the row. Each row of units has a CIM manager that is only used for the units in this row. The data interaction module is used to receive the data involved in the calculation, and send it to the row for calculation or to the adjacent management module MU according to the judgment conditions.

[0045] The conversion module is as follows Figure 4 As shown, it includes 4 data exchange modules for receiving and transmitting data to adjacent conversion modules or multi-function support configurable in-memory calculation macros. The data exchange module includes a FIFO to unify the timing and reduce the bit error rate. It also includes a data flow control unit, the specific structure is as follows Figure 5 The data flow control unit receives data from the four data interaction modules, and instructs the arbitrator to guide the input data of channel 0, channel 1, channel 2, and channel 3 to output data to the specified channel through the control register, and then passes it to the corresponding data interaction module.

[0046] In-memory computation macros such as Figure 6 As shown, it includes a 512x 256 8T SRAM storage array, a multi-function support calculation logic unit MFU, a set of addition trees, a control logic circuit, a timing control circuit and other peripheral circuits. The 8T SRAM has two separate word lines WWL and RWL, and three separate bit lines WBL, WBLb and RBL, allowing two sets of data to be read out simultaneously. The specific method is as follows Figure 7 As shown. When matrix multiplication is required, the addition tree circuit will receive the partial product calculation results, and obtain the matrix multiplication results through a series of addition operations. In addition, the control logic circuit and the timing control circuit are used to receive control signals and accurately control the timing relationship of reading, writing, and calculation, respectively, to improve the calculation efficiency. When WWL and RWL of different rows are selected respectively, the 512x 256 size 8T SRAM storage array can output up to two groups of 256-bit data at the same time, and send the data to the multi-function supported calculation logic unit MFU through the sensitive amplifier SA to participate in the calculation.

[0047] The multi-function support calculation logic unit MFU supports two groups of 256-bit data for addition, subtraction and partial product operations. The specific methods are as follows Figure 8 This unit supports vector addition, vector subtraction and matrix multiplication operations, and the subtraction carry input C in_sub , WBLb [i] , WBL [i] , RBL [i] , addition carry input Cin_add, subtraction carry output C out_sub , addition carry output C out_add , Sum / Difference of addition / subtraction, Partial Product of partial product, the specific operation process is as follows Figures 13 to 15 shown.

[0048] A typical calculation process is as follows Fig. 9As shown in the figure: In the first step, the host issues an instruction based on the RISC-V extended instruction set to configure the data movement path of SHWCIM, that is, the routing method. In the second step, the host issues an instruction based on the RISC-V extended instruction set to configure the function selection of each in-memory calculation macro in SHWCIM, including vector addition, vector subtraction, vector-matrix multiplication, matrix-matrix multiplication, comparison operation, and select whether the current in-memory calculation macro is in in-memory calculation mode or memory mode. In the third step, the data is stored in the off-chip memory. The host issues a call DMA instruction to efficiently write the data from the off-chip memory to the SHWCIM through DMA. Through the previously configured routing method, the data is written into the corresponding in-memory calculation macro for calculation, and the calculation result is stored in the nearby in-memory calculation macro in memory mode. In the fourth step, the host issues a read instruction based on the RISC-V extended instruction set to read the calculation result from the SHWCIM and store it in the off-chip memory DRAM. At this point, a typical SHWCIM calculation process is completed.

[0049] Fig.10 The instruction table shown contains 9 RISC-V extended instructions with a 32-bit instruction width. From top to bottom, they are data precision configuration instructions, data storage device / in-memory calculation macro quantity configuration instructions, SHWCIM routing table configuration instructions, vector addition operation instructions, vector subtraction operation instructions, vector-matrix multiplication operation instructions, matrix-matrix multiplication operation instructions, data loading instructions, and data storage instructions.

[0050] The calculation method of the in-memory calculation macro is as follows Fig.11 As shown. First, according to the type of operator to be calculated, choose whether to enable the multi-function supported computing logic unit MFU and the addition tree module. Secondly, configure the function selection of the multi-function supported computing logic unit MFU. The third step is to write data to the SRAM array. The fourth step is to read two sets of data at the same time to participate in the calculation, and output the result to the conversion module S. The fifth step is to determine whether the calculation is completed. If it is completed, the calculation is terminated and wait for the next round of calculation. If it is not completed, continue to read data to participate in the calculation until the calculation is completed.

[0051] The calculation process sequence of the in-memory calculation macro is as follows Fig.12As shown, this is an example of the calculation process of matrix multiplication. First, the multi-function supported calculation logic unit enable MFU_ENABLE and the addition tree module enable Adder_Tree_ENABLE send a pulse signal to turn on the calculation function. Secondly, configure the multi-function supported calculation logic unit function selection signal MFU_CONFIG to 1001, indicating that this calculation is a matrix-matrix multiplication calculation. The third step is to turn on the storage array write enable CIM_WR_ENABLE and write CIM_WR_DATA data. The fourth step is to turn off CIM_WR_ENABLE, turn on the storage array read enable CIM_RD_ENABLE, and start the calculation.

[0052] The calculation logic unit addition operation process is as follows Fig.13 As shown, the two bits of data read out by WBL and RBL are input, and the carry input by the calculation logic unit supported by the lower multi-function is output, and the calculation result is output and the carry is output to the higher calculation logic unit. The subtraction operation process of the calculation logic unit is as follows Fig.14 As shown, by using the characteristic that WBLb is the inverse code of WBL, the inverse code is added by 1 to obtain the complement code, and then the complement code is added to the data read out by RBL to obtain the subtraction operation result. Fig.15 As shown, the data read out from WBL and RBL are subjected to an AND logic operation to obtain a partial product result, which is sent to an addition tree for operation to obtain a final result.

[0053] The interaction between the novel coarse-grained configurable architecture and the RISC V CPU processor described in the present invention is as follows: Fig.16 SHWCIM directly obtains instructions from the instruction decoding module of the RISC-V CPU, and the SHWCIM bus is set separately from the RISC-V CPU instruction bus and data bus to improve computing efficiency.

[0054] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A new coarse-grained configurable architecture based on in-memory computing technology, characterized in that: include: The scatter / gather module is used to split or pack data of different precisions, interact with external modules, and organize sparse data into dense data and send it to the management module; The management module is used to decode the instructions and data transmitted by the host, convert the instructions into control commands of the in-memory computing macro, and send the control commands and data to the in-memory computing macro of the corresponding address to participate in the calculation; A conversion module, used to transmit signals to a specified address to build an on-chip network; The in-memory computation macro includes a 512x256 8T SRAM array, a computational logic unit supporting addition, subtraction, and partial products, a set of addition trees, a control unit, a timing control circuit, and peripheral circuits; In-memory calculation macros are used to perform calculations under the control of the management module.

2. A novel coarse-grained configurable architecture based on in-memory computing technology according to claim 1, characterized in that: The scatter / gather module includes two buffers, a left shifter, and a right shifter; the external data is divided into a header and input data; The header is used to determine whether the input data is an instruction or a data signal involved in calculation. If the input data is an instruction, it is directly sent to the management module; otherwise, it is sent to the cache for splicing.

3. According to claim 1, a novel coarse-grained configurable architecture based on in-memory computing technology is characterized in that: The management module includes two data interaction modules, two CIM managers, a scratchpad memory SPM, a CIM mapping register, and a crossbar switch matrix; the instructions and data signals transmitted from the scatter / gather module are respectively sent to the CIM mapping register and the data interaction module; The CIM mapping register is used to store the data movement path and the function selection and mode selection of each in-memory calculation macro. The CIM mapping register outputs commands to the CIM manager; The CIM manager is used to manage the conversion modules and in-memory calculation macros of the row; The data interaction module is used to receive the data involved in the calculation and send it to the bank for calculation or to the adjacent management module according to the judgment conditions.

4. According to claim 1, a novel coarse-grained configurable architecture based on in-memory computing technology is characterized in that: The conversion module includes four data interaction modules for receiving and transmitting data to adjacent conversion modules or in-memory computing macros.

5. According to claim 1, a novel coarse-grained configurable architecture based on in-memory computing technology is characterized in that: The calculation process of the in-memory calculation macro is as follows: The first step is to select whether to enable the multi-function supported computing logic unit MFU and addition tree module according to the type of operator to be calculated; The second step is to configure the function selection of the computing logic unit MFU supported by the multi-function; The third step is to write data into the SRAM array; Step 4: read two sets of data at the same time to participate in the calculation, and output the results to the conversion module S; The fifth step is to determine whether the calculation is finished. If it is finished, the calculation is ended and wait for the next round of calculation. If it is not finished, continue to read data and participate in the calculation until the calculation is finished.

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