Central processing unit multi-chip packaging system supporting dynamic expansion

Abstract

The invention discloses a central processing unit multi-chip packaging system supporting dynamic expansion, and relates to the technical field of electronics, the system comprises a dynamic regulation and control module used for dynamically regulating and controlling power distribution among chips based on a chip operation state and a power consumption model, and a multi-chip packaging module used for dynamically regulating and controlling the power distribution among the chips based on the chip operation state and the power consumption model. The central processing unit chip packaging module is used for packaging a plurality of central processing unit chips on the same substrate to realize multi-chip interconnection, the high-speed data transmission interface module is used for synchronizing the working frequency and load balance of each chip, and the power consumption monitoring module is used for monitoring the power consumption of each chip in real time and feeding back a regulation and control result to optimize dynamic power distribution; according to the central processing unit multi-chip packaging system supporting dynamic expansion, the problems that in the prior art, the dynamic performance and flexibility of power distribution in a multi-chip packaging system cannot be effectively solved, and the application potential of the multi-chip packaging system in the high-performance computing and dynamic load environment is limited are solved.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and in particular to a central processing unit multi-chip packaging system supporting dynamic expansion. Background Art

[0002] In the existing technology, multi-chip packaging system is a design method widely used in multi-core processors, which improves computing performance and functional density by integrating multiple computing cores in one package. However, the design of multi-chip packaging faces many technical challenges, one of which is the power consumption allocation problem under high load conditions.

[0003] At present, multi-chip packaging systems usually adopt a fixed power allocation strategy, that is, a fixed power is allocated to each core or chip through a preset power cap and scheduling algorithm. However, this method has the following defects: the fixed power allocation method in the prior art cannot dynamically adjust the power supply according to the real-time load of each chip, resulting in some chips overheating due to high-load operation, while other chips waste resources due to low-load operation; in high-load application scenarios, there may be uneven power distribution among multiple chips, resulting in excessive power consumption in local areas, which in turn increases the difficulty of heat dissipation and shortens the life of the chip; the existing power management mechanism mainly relies on hardware-level power limits, lacks dynamic regulation capabilities for actual operating loads and application requirements, and is difficult to cope with complex operating scenarios. In general, the existing technology cannot effectively solve the problems of dynamic and flexibility of power allocation in multi-chip packaging systems, limiting its application potential in high-performance computing and dynamic load environments. Summary of the invention

[0004] The purpose of the present invention is to provide a multi-chip packaging system for a central processing unit that supports dynamic expansion, so as to solve the problem that the prior art cannot effectively solve the dynamic and flexibility problems of power allocation in the multi-chip packaging system, thus limiting its application potential in high-performance computing and dynamic load environments.

[0005] To achieve the above object, the present invention provides the following technical solution: a CPU multi-chip packaging system supporting dynamic expansion, the system comprising:

[0006] The dynamic control module is used to dynamically control the power distribution between chips based on the chip operation status and power consumption model, including establishing a dynamic model of chip power consumption and temperature, and updating the parameters of the chip load and power distribution demand dynamic adjustment in real time. The specific formula is:

[0007] Among them, θ′ represents the rate of change of θ over time, θ represents the adjustment factor of power allocation between chips, γ represents the response speed to the current state when adjusting the power allocation strategy, and V represents the function;

[0008] The multi-chip packaging module connected to the dynamic control module is used to package multiple central processing unit chips on the same substrate to achieve multi-chip interconnection, including analyzing the heat conduction path between each chip and calculating the ability of each chip to dissipate heat through heat conduction. The specific formula is:

[0009]

[0010] Among them, G represents thermal conductivity, π represents pi, T represents the temperature environment when the chip is running, h represents a constant, and τ n It represents the thermal energy transmittance value of the nth material, where n represents the number of materials in the chip;

[0011] A high-speed data transmission interface module connected to the dynamic control module and the multi-chip packaging module is used to synchronize the operating frequency and load balancing of each chip;

[0012] The power consumption monitoring module connected to the dynamic control module and the multi-chip packaging module is used to monitor the power consumption of each chip in real time and feed back the control results to optimize dynamic power allocation.

[0013] Preferably, the multi-chip packaging module packages multiple central processing unit chips on the same substrate, and the multi-chip interconnection includes:

[0014] A thermal fluid model inside the substrate is established to calculate the temperature field and flow field distribution inside the substrate. The specific formula is:

[0015]

[0016] Where u represents the flow velocity distribution of the cooling fluid in the multi-chip package substrate, represents the gradient operator, ρ represents the density of the cooling medium, t represents the time, μ represents the dynamic viscosity of the cooling medium, and τ represents the additional influence factor of the turbulence of the cooling fluid on the chip;

[0017] Optimize the cooling channel design to evenly distribute the cooling fluid in the high-power chip area.

[0018] Preferably, the high-speed data transmission interface module synchronizes the working frequency and load balancing of each chip including:

[0019] Measure the signal-to-noise ratio of the inter-chip communication channel, evaluate the current transmission conditions, and calculate the maximum data transmission rate. The specific formula is: C = Wlog 2 (1+SNR);

[0020] Wherein, C represents the maximum data transmission rate supported by the inter-chip communication interface, W represents the frequency range supported by the communication interface, SNR represents the ratio of signal power to noise power, and log represents logarithmic operation;

[0021] Allocate bandwidth resources according to the transmission rate, dynamically adjust the parameters of the inter-chip communication interface, monitor the channel status in real time, and optimize the modulation method and coding strategy.

[0022] Preferably, the power consumption monitoring module monitors the power consumption of each chip in real time, and feeds back the control result to optimize the dynamic power allocation, including:

[0023] Collect chip power consumption data, define its dynamically changing potential energy function, simulate random fluctuations in power consumption, and analyze the impact of noise on chip power consumption. The specific formula is:

[0024]

[0025] Among them, β represents the response speed of power consumption fluctuation, x represents the power consumption level of the chip, t represents time, U represents the energy distribution of the chip power consumption state, and η represents the influence of random external or internal disturbances on the chip power consumption during operation;

[0026] Predict future power consumption trends, identify abnormal power consumption points, and feed the prediction results back to the dynamic control module.

[0027] Preferably, the dynamic control module also includes a monitoring unit for real-time monitoring of the chip operating status, and a control unit for dynamically adjusting the power allocation strategy according to the monitoring results, so as to optimize the load balancing and power consumption stability among the chips.

[0028] Preferably, the substrate in the multi-chip packaging module is made of a high thermal conductivity material to improve the heat dissipation performance of the chip and ensure stable operation of the system under high load conditions.

[0029] Preferably, the high-speed data transmission interface module supports multiple communication protocols to adapt to different types of inter-chip data interaction requirements.

[0030] Preferably, the power consumption monitoring module includes a storage unit for storing historical power consumption data of the chip, and an analysis unit for predicting future power consumption change trends.

[0031] Preferably, the high-speed data transmission interface module supports error detection and correction functions to improve the reliability and stability of inter-chip communication.

[0032] Preferably, the power consumption monitoring module includes an alarm unit for identifying power consumption anomalies, and can trigger an alarm signal when abnormal chip power consumption is detected.

[0033] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0034] The CPU multi-chip packaging system that supports dynamic expansion dynamically controls the power distribution between chips based on the chip operating status and power consumption model through a dynamic control module. The multi-chip packaging module is used to package multiple CPU chips on the same substrate to achieve multi-chip interconnection. The high-speed data transmission interface module is used to synchronize the operating frequency and load balancing of each chip. The power consumption monitoring module is used to monitor the power consumption of each chip in real time and feedback the control results to optimize the dynamic power distribution. The power distribution can be dynamically adjusted according to the real-time load of each chip, which greatly improves the flexibility of power distribution, effectively avoids the problem of overheating of high-load chips and waste of low-load chips, and significantly improves the problem of excessive local power consumption caused by uneven power distribution in the multi-chip packaging system, effectively reduces the overall heat dissipation difficulty of the system, and improves The stability of chip operation extends the service life of the system. It can quickly respond to dynamic load changes in complex operating scenarios to meet different application requirements. It can adapt to a variety of high-performance computing and dynamic load environments, enhance the application potential of the system, and achieve precise control of energy. It reduces energy waste caused by low-load chip operation, and significantly improves the overall power utilization efficiency of the system. It is particularly suitable for high-energy multi-chip parallel computing scenarios, improves the overall performance and work efficiency of the multi-chip system, and can monitor the chip power consumption status in real time, identify abnormal situations and promptly feedback the control results, thereby avoiding chip failure or system failure caused by improper power allocation. It solves the problem that the existing technology cannot effectively solve the dynamic and flexibility problems of power allocation in multi-chip packaging systems, limiting its application potential in high-performance computing and dynamic load environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the connection of system modules of the present invention;

[0036] Figure 2 This is a schematic diagram of the dynamic control module of the present invention;

[0037] Figure 3 This is a schematic diagram of the power consumption monitoring module of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] like Figure 1-Figure 3 As shown, the present invention provides a technical solution: a central processing unit multi-chip packaging system supporting dynamic expansion, the system comprising:

[0040] The dynamic control module is used to dynamically control the power distribution between chips based on the chip operation status and power consumption model, including establishing a dynamic model of chip power consumption and temperature, and updating the parameters of the chip load and power distribution demand dynamic adjustment in real time. The specific formula is:

[0041] Among them, θ′ represents the rate of change of θ over time, θ represents the adjustment factor of power allocation between chips, γ represents the response speed to the current state when adjusting the power allocation strategy, and V represents the function;

[0042] The multi-chip packaging module connected to the dynamic control module is used to package multiple central processing unit chips on the same substrate to achieve multi-chip interconnection, including analyzing the heat conduction path between each chip and calculating the ability of each chip to dissipate heat through heat conduction. The specific formula is:

[0043]

[0044] Among them, G represents thermal conductivity, π represents pi, T represents the temperature environment when the chip is running, h represents a constant, and τ n It represents the thermal energy transmittance value of the nth material, where n represents the number of materials in the chip;

[0045] A high-speed data transmission interface module connected to the dynamic control module and the multi-chip packaging module is used to synchronize the operating frequency and load balancing of each chip;

[0046] The power consumption monitoring module connected to the dynamic control module and the multi-chip packaging module is used to monitor the power consumption of each chip in real time and feed back the control results to optimize dynamic power allocation.

[0047] The present invention optimizes the power distribution of multiple CPU chips in real time through a dynamic control module. The dynamic control module analyzes the temperature and load change trend of each chip based on the operating status and power consumption model of the chip, and uses the dynamic adjustment formula: Adjust the power allocation strategy in real time to ensure that the power allocation between chips is reasonable and efficient. The chips are interconnected through a multi-chip packaging module, and the operating frequency and load distribution of the chips are synchronized through a high-speed data transmission interface module. The power consumption monitoring module collects chip power consumption data in real time and feeds it back to the dynamic control module, so that the optimization result of power allocation conforms to the actual operating state of the chip, thereby achieving the purpose of reducing power consumption and improving efficiency. The present invention provides an efficient central processing unit multi-chip packaging system, which has the following advantages: intelligent management of power allocation is achieved through a dynamic control module, effectively reducing power consumption; the multi-chip packaging module improves the interconnection performance between multiple central processing unit chips and supports dynamic expansion; the high-speed data transmission interface module ensures real-time synchronization of operating frequency and load between chips, and improves the overall performance of the system; the power consumption monitoring module optimizes the power allocation result through real-time monitoring and feedback, thereby improving the operating stability and reliability of the system.

[0048] The multi-chip packaging module packages multiple CPU chips on the same substrate to achieve multi-chip interconnection including:

[0049] A thermal fluid model inside the substrate is established to calculate the temperature field and flow field distribution inside the substrate. The specific formula is:

[0050]

[0051] Where u represents the flow velocity distribution of the cooling fluid in the multi-chip package substrate, represents the gradient operator, ρ represents the density of the cooling medium, t represents the time, μ represents the dynamic viscosity of the cooling medium, and τ represents the additional influence factor of the turbulence of the cooling fluid on the chip;

[0052] Optimize the cooling channel design to evenly distribute the cooling fluid in the high-power chip area.

[0053] In the present invention, by establishing a thermal fluid model in the substrate, the temperature field and flow field distribution of the CPU multi-chip packaging module can be accurately calculated. Ensure that the flow rate of the cooling fluid in the baseplate is conserved, while combining the equation: Describe the flow state and dynamic characteristics of the cooling fluid. By optimizing the design of the cooling channel, the cooling efficiency of the high-power chip area is maximized, thereby ensuring the uniformity of the temperature distribution between chips, preventing the occurrence of local overheating, and improving the thermal management performance of the system. The present invention has the following beneficial effects through the optimization design of the thermal fluid of the substrate in the multi-chip packaging module: establishing a thermal fluid model in the substrate, accurately simulating the temperature field and flow field distribution, and ensuring efficient heat dissipation of the system; uniform distribution of the cooling fluid in the high-power consumption area, effectively reducing the temperature difference of the chip and preventing the generation of local hot spots; improving the heat dissipation efficiency, reducing the damage of thermal stress to the chip and substrate materials, and extending the life of the system; optimizing the cooling channel design, reducing the energy consumption and operating costs of the cooling system.

[0054] The high-speed data transmission interface module synchronizes the operating frequency and load balancing of each chip including:

[0055] Measure the signal-to-noise ratio of the inter-chip communication channel, evaluate the current transmission conditions, and calculate the maximum data transmission rate. The specific formula is: C = Wlog 2 (1+SNR);

[0056] Wherein, C represents the maximum data transmission rate supported by the inter-chip communication interface, W represents the frequency range supported by the communication interface, SNR represents the ratio of signal power to noise power, and log represents logarithmic operation;

[0057] Allocate bandwidth resources according to the transmission rate, dynamically adjust the parameters of the inter-chip communication interface, monitor the channel status in real time, and optimize the modulation method and coding strategy.

[0058] The present invention realizes efficient communication and load balancing between chips through a high-speed data transmission interface module. The module first measures the signal-to-noise ratio of the communication channel between chips and uses the formula C=Wlog 2(1+SNR) calculates the maximum data transmission rate C of the channel. Based on the calculation results, bandwidth resources are allocated to ensure that high-frequency channels are used to transmit high-priority data packets, while low-frequency channels transmit secondary data. At the same time, the module can dynamically adjust the operating frequency and parameters of the inter-chip communication interface, and select the optimal modulation method and coding strategy according to the real-time monitored data to adapt to changes in communication conditions and improve transmission reliability and efficiency. The high-speed data transmission interface module of the present invention has the following advantages in the central processing unit multi-chip packaging system: based on the real-time measured signal-to-noise ratio and Shannon's theorem, the transmission rate is optimized to ensure the high efficiency of inter-chip communication; bandwidth resources are dynamically allocated, channel usage is optimized according to data priority, and system data transmission performance is improved; real-time optimization of modulation methods and coding strategies enhances the adaptability of the communication system to channel changes and reduces the bit error rate; real-time monitoring and adjustment of communication interface parameters ensure system stability and reliability under high load conditions; while improving data transmission efficiency, communication energy consumption is reduced and the service life of the system is extended.

[0059] The power consumption monitoring module monitors the power consumption of each chip in real time and provides feedback on the control results to optimize dynamic power allocation, including:

[0060] Collect chip power consumption data, define its dynamically changing potential energy function, simulate random fluctuations in power consumption, and analyze the impact of noise on chip power consumption. The specific formula is:

[0061]

[0062] Among them, β represents the response speed of power consumption fluctuation, x represents the power consumption level of the chip, t represents time, U represents the energy distribution of the chip power consumption state, and η represents the influence of random external or internal disturbances on the chip power consumption during operation;

[0063] Predict future power consumption trends, identify abnormal power consumption points, and feed the prediction results back to the dynamic control module.

[0064] The present invention collects the power consumption data of the chip in real time through the power consumption monitoring module and establishes a dynamic potential energy function of the chip power consumption state. The potential energy function describes the change trend of the chip power consumption, combined with the power consumption fluctuation response speed β and random disturbance, and is expressed as Model and analyze the dynamic changes of chip power consumption. The module further uses these data to predict the future trend of chip power consumption and identify abnormal power consumption points, such as excessive or low power consumption. The monitoring results are transmitted to the dynamic control module through the feedback mechanism, and the power allocation strategy is dynamically adjusted to optimize the chip operation state and avoid overheating or energy waste. The power consumption monitoring module of the present invention significantly improves the energy efficiency management capability of the multi-chip packaging system. Its main advantages include: real-time monitoring of chip power consumption, providing accurate data to support dynamic power allocation, quantifying the volatility and change trend of chip power consumption by establishing a dynamic potential energy function, enhancing the accuracy of power consumption analysis, predicting power consumption anomalies in advance, actively adjusting power allocation, preventing the system from overheating or unbalanced energy consumption, and the feedback control mechanism ensures the stability and reliability of chip operation, while reducing unnecessary energy waste, achieving system-level energy efficiency optimization, and improving the service life and performance of the entire multi-chip packaging system.

[0065] The dynamic control module also includes a monitoring unit for real-time monitoring of the chip operation status, and a control unit for dynamically adjusting the power allocation strategy according to the monitoring results to optimize the load balance and power consumption stability between chips. The dynamic control module of the present invention is coordinated by the monitoring unit and the control unit to achieve optimized control. The monitoring unit collects chip operation status data in real time, including temperature, operating frequency, power consumption and load conditions, and processes these data through a built-in analysis algorithm to generate an evaluation result of the real-time operation status. The control unit receives the evaluation result of the monitoring unit and dynamically adjusts the power allocation strategy between chips. For example, for high-load chips, the control unit can allocate more power resources while reducing the power supply of low-load chips to achieve load balancing. In addition, when abnormal power consumption or temperature is detected, the control unit will give priority to adjusting the power allocation strategy to reduce the power output of the abnormal chip, thereby ensuring the overall stability of the system power consumption. Through the closed-loop feedback mechanism of monitoring and control, the operating efficiency and stability of the system in a multi-chip packaging environment are ensured. The dynamic control module of the present invention achieves the following beneficial effects through the coordinated optimization of the monitoring unit and the control unit: real-time monitoring of the operating status of the chip, accurate grasp of the dynamic changes of the system, dynamic adjustment of the power allocation strategy, optimization of resource allocation according to the real-time operating conditions, and improvement of the load balance of the system. When the power consumption or temperature is abnormal, adjustment measures are taken quickly to avoid system failure due to local problems, improve the power consumption stability of the chip operation, reduce the power consumption waste caused by overload or imbalance, improve the overall energy efficiency of the system, and extend the service life of the chip and packaging module.

[0066] The substrate in the multi-chip packaging module is made of high thermal conductivity material to improve the heat dissipation performance of the chip and ensure the stable operation of the system under high load. The present invention significantly improves the heat dissipation performance of the chip by using a substrate made of high thermal conductivity material in the multi-chip packaging module. As the core component of the multi-chip packaging module, the thermal conductivity of the substrate has a key impact on the overall thermal management efficiency of the system. High thermal conductivity materials, such as aluminum-based ceramics, boron nitride, graphene composites or copper-based alloys, can quickly transfer the heat generated during the operation of the chip to a heat dissipation device, such as a heat sink or heat pipe, to avoid local overheating of the chip. Especially under high-load operation, the high thermal conductivity of the substrate can evenly distribute heat, reduce the temperature difference between chips, and prevent performance degradation or system instability caused by overheating. In addition, the high thermal conductivity substrate can also reduce the impact of thermal stress on the chip packaging structure and extend the service life of the system. The present invention achieves the following beneficial effects by using a substrate made of a high thermal conductivity material in a multi-chip packaging module: significantly improving the heat dissipation efficiency of the chip, effectively reducing the chip temperature under high-load operation, reducing the temperature difference between chips, avoiding system performance degradation caused by local overheating, improving the overall stability and reliability of the system, ensuring the long-term operation of the system under high-load conditions, extending the service life of the chip and packaging module, reducing maintenance and replacement costs, and improving system energy efficiency and reducing power consumption by optimizing thermal management performance.

[0067] The high-speed data transmission interface module supports multiple communication protocols to adapt to different types of inter-chip data interaction requirements. The high-speed data transmission interface module of the present invention enhances the adaptability and flexibility of the multi-chip packaging system by supporting multiple communication protocols. The module is compatible with a variety of common communication protocols, and through automatic protocol identification and dynamic switching functions, it selects the appropriate communication protocol according to the data interaction requirements of different types of chips. When the multi-chip system is running, the high-speed data transmission interface module first detects the communication characteristics between chips, including data rate, transmission mode and interface type, and dynamically selects the best communication protocol based on these characteristics. For example, for high-bandwidth high-speed data transmission tasks, PCIe or NVLink protocols can be selected first; for low-power, low-rate data interaction scenarios, I 2C or SPI protocol. The module also has a protocol conversion function, which can seamlessly switch between multiple protocols, thereby realizing efficient data interaction between heterogeneous chips. Through flexible configuration and management, the high performance and compatibility of the multi-chip packaging system in various application scenarios are ensured. The high-speed data transmission interface module of the present invention has the following significant advantages: supporting multiple communication protocols, meeting the diversified data interaction requirements of different types of chips, improving the adaptability and operating efficiency of the system through the dynamic protocol switching function, and realizing seamless communication through protocol conversion in heterogeneous chip systems, enhancing system compatibility, improving the flexibility of data transmission, adapting to a variety of work scenarios, from high-bandwidth data transmission to low-power control signal interaction, simplifying system design, reducing dependence on specific communication protocol hardware interfaces, and saving development costs.

[0068] The power consumption monitoring module includes a storage unit for storing historical power consumption data of the chip, and an analysis unit for predicting future power consumption change trends. The present invention realizes historical record management and future trend prediction of chip power consumption through the storage unit and the analysis unit in the power consumption monitoring module. The storage unit is used to record and store the power consumption data of the chip under different operating states, including parameters such as operating frequency, load, temperature, etc., to form a complete historical power consumption data set. These data provide a reliable basis for subsequent analysis. The analysis unit calculates the future power consumption change trend by analyzing the historical power consumption data in the storage unit using a time series prediction algorithm. The analysis unit can identify the periodicity and mutation points of power consumption changes and predict potential abnormal power consumption situations, such as peak power consumption or continuous overload. The prediction results can be fed back to the dynamic control module, which adjusts the power allocation strategy. For example, when it is predicted that the power consumption may increase suddenly, the system can reduce the load of some chips in advance to avoid system instability caused by excessive power consumption. At the same time, the analysis unit can also optimize the cooling and power consumption management strategies to improve the energy efficiency and operation reliability of the system. The power consumption monitoring module of the present invention achieves the following beneficial effects through the cooperation of the storage unit and the analysis unit: recording the historical power consumption data of the chip, providing a reliable basis for power consumption analysis and optimization, accurately predicting the future power consumption change trend through the time series prediction algorithm, identifying potential abnormal situations, adjusting the power allocation strategy in advance, avoiding performance degradation or system failure caused by power consumption fluctuations, optimizing system cooling and power consumption management strategies, improving energy efficiency and extending chip life, realizing intelligent management of the power consumption monitoring module, and enhancing the stability and reliability of the multi-chip packaging system.

[0069] The high-speed data transmission interface module supports error detection and correction functions, which are used to improve the reliability and stability of inter-chip communication. The high-speed data transmission interface module of the present invention significantly improves the reliability and stability of inter-chip communication by integrating error detection and correction functions. During the data transmission process, the module first uses an error detection algorithm to verify the transmission data to quickly identify transmission errors in data packets. Once an error is detected, the module further calls the error correction mechanism to automatically correct the erroneous data to ensure that the receiving end can recover to the original data. At the same time, in order to reduce the probability of errors, the module can dynamically adjust communication parameters, such as reducing channel noise or increasing signal strength, to optimize the communication environment. Through this closed-loop feedback mechanism of error detection and correction, the high-speed data transmission interface module can maintain communication stability under high load or high noise conditions, avoiding the impact of data transmission errors on system operation. The high-speed data transmission interface module of the present invention achieves the following beneficial effects through the error detection and correction function: improving the reliability of data transmission between chips, reducing the risk of system failure caused by data errors, correcting erroneous data without retransmission through the automatic error correction function, improving communication efficiency, dynamically adjusting communication parameters, optimizing the transmission environment, reducing the probability of errors, enhancing the stability of multi-chip packaging systems under high load and complex communication environments, reducing the additional power consumption caused by data error retransmission, and improving system energy efficiency.

[0070] The power consumption monitoring module includes an alarm unit for identifying power consumption anomalies, and can trigger an alarm signal when abnormal chip power consumption is detected. The power consumption monitoring module of the present invention identifies and processes abnormal chip power consumption in real time through the alarm unit. The alarm unit monitors the chip operating power consumption based on a preset power consumption threshold range. When the chip power consumption exceeds the set normal range, the alarm unit will immediately trigger an alarm signal. The triggered alarm signal can be issued in a variety of ways, such as displaying alarm information through a system control panel, activating an audible and visual alarm device, or sending a remote alarm (such as a text message or email) to a system administrator. At the same time, the alarm unit will record and pass the abnormal power consumption data to the dynamic control module, and the dynamic control module will adjust the power allocation strategy according to the alarm information to quickly restore the normal operating state of the system.

[0071] Through the above mechanism, the present invention can respond in time when the chip power consumption is abnormal, preventing abnormal power consumption from causing more serious problems. The power consumption monitoring module of the present invention brings the following significant advantages through the design of the alarm unit: realizing real-time monitoring and identification of abnormal chip power consumption, improving the security and stability of the system, notifying the system administrator in time through the alarm signal or triggering an automated response, reducing the system downtime caused by abnormal power consumption, recording abnormal power consumption data, providing a basis for subsequent system maintenance and optimization, and cooperating with the dynamic control module to quickly adjust the power allocation strategy to reduce performance fluctuations or hardware damage caused by abnormal power consumption, improve the fault response capability of the multi-chip packaging system, and ensure the long-term stable operation of the system.

[0072] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A CPU multi-chip packaging system supporting dynamic expansion, characterized in that: The system comprises: The dynamic control module is used to dynamically control the power distribution between chips based on the chip operation status and power consumption model, including establishing a dynamic model of chip power consumption and temperature, and updating the parameters of the chip load and power distribution demand dynamic adjustment in real time. The specific formula is: Among them, θ′ represents the rate of change of θ over time, θ represents the adjustment factor of power allocation between chips, γ represents the response speed to the current state when adjusting the power allocation strategy, and V represents the function; The multi-chip packaging module connected to the dynamic control module is used to package multiple central processing unit chips on the same substrate to achieve multi-chip interconnection, including analyzing the heat conduction path between each chip and calculating the ability of each chip to dissipate heat through heat conduction. The specific formula is: Among them, G represents thermal conductivity, π represents pi, T represents the temperature environment when the chip is running, h represents a constant, and τ n It represents the thermal energy transmittance value of the nth material, where n represents the number of materials in the chip; A high-speed data transmission interface module connected to the dynamic control module and the multi-chip packaging module is used to synchronize the operating frequency and load balancing of each chip; The power consumption monitoring module connected to the dynamic control module and the multi-chip packaging module is used to monitor the power consumption of each chip in real time and feed back the control results to optimize dynamic power allocation.

2. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The multi-chip packaging module packages multiple CPU chips on the same substrate, and the multi-chip interconnection is realized by: A thermal fluid model inside the substrate is established to calculate the temperature field and flow field distribution inside the substrate. The specific formula is: Where u represents the flow velocity distribution of the cooling fluid in the multi-chip package substrate, represents the gradient operator, ρ represents the density of the cooling medium, t represents the time, μ represents the dynamic viscosity of the cooling medium, and τ represents the additional influence factor of the turbulence of the cooling fluid on the chip; Optimize the cooling channel design to evenly distribute the cooling fluid in the high-power chip area.

3. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The high-speed data transmission interface module synchronizes the working frequency and load balancing of each chip, including: Measure the signal-to-noise ratio of the inter-chip communication channel, evaluate the current transmission conditions, and calculate the maximum data transmission rate. The specific formula is: C = W log2 (1 + SNR); Wherein, C represents the maximum data transmission rate supported by the inter-chip communication interface, W represents the frequency range supported by the communication interface, SNR represents the ratio of signal power to noise power, and log represents logarithmic operation; Allocate bandwidth resources according to the transmission rate, dynamically adjust the parameters of the inter-chip communication interface, monitor the channel status in real time, and optimize the modulation method and coding strategy.

4. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The power consumption monitoring module monitors the power consumption of each chip in real time and feeds back the control result to optimize the dynamic power allocation, including: Collect chip power consumption data, define its dynamically changing potential energy function, simulate random fluctuations in power consumption, and analyze the impact of noise on chip power consumption. The specific formula is: Among them, β represents the response speed of power consumption fluctuation, x represents the power consumption level of the chip, t represents time, U represents the energy distribution of the chip power consumption state, and η represents the influence of random external or internal disturbances on the chip power consumption during operation; Predict future power consumption trends, identify abnormal power consumption points, and feed the prediction results back to the dynamic control module.

5. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The dynamic control module also includes a monitoring unit for real-time monitoring of the chip operating status, and a control unit for dynamically adjusting the power allocation strategy according to the monitoring results to optimize the load balancing and power consumption stability among the chips.

6. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The substrate in the multi-chip packaging module is made of high thermal conductivity material to improve the heat dissipation performance of the chip and ensure the stable operation of the system under high load conditions.

7. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The high-speed data transmission interface module supports multiple communication protocols and is used to adapt to different types of inter-chip data interaction requirements.

8. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The power consumption monitoring module includes a storage unit for storing historical power consumption data of a chip, and an analysis unit for predicting future power consumption change trends.

9. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The high-speed data transmission interface module supports error detection and correction functions to improve the reliability and stability of inter-chip communication.

10. The CPU multi-chip packaging system supporting dynamic expansion according to claim 1, characterized in that: The power consumption monitoring module includes an alarm unit for identifying power consumption anomalies, and can trigger an alarm signal when abnormal power consumption of a chip is detected.

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