Retention time adjusting method and device, equipment and medium

Abstract

The embodiment of the invention relates to a retention time adjusting method and device, equipment and a medium. The method comprises the steps that time sequence analysis information of a to-be-processed circuit is acquired; wherein the time sequence analysis information comprises an abnormal end point identifier and retention time abnormal information corresponding to the abnormal end point identifier; determining a target number of delay adjustment units according to the retention time exception information; and in the to-be-processed circuit, determining an abnormal path end point corresponding to the abnormal end point identifier, and inserting a target number of delay adjustment units at adjacent positions in front of the abnormal path end point to obtain an adjustment circuit. According to the embodiment of the invention, errors caused by reconnection of the interconnection lines are reduced, the influence of the delay adjustment unit on other paths is reduced, accurate delay control on the end point of a specific path is realized from multiple dimensions, and the difficulty of realizing time sequence convergence is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a method, device, equipment, and medium for adjusting hold time. Background Art

[0002] With the rapid development of the semiconductor industry, chip process features are shrinking, and the integration density of individual chips is increasing, leading to an increase in chip design difficulty. The timing closure phase in the physical design of digital integrated circuits (ICs) is becoming increasingly challenging due to factors such as higher chip frequencies, more complex internal data interactions, and an increase in process corners.

[0003] In related technologies, circuit adjustments are performed on the original chip based on timing analysis results to achieve timing closure. However, this process often involves a significant amount of interconnect rerouting, leading to larger errors and affecting paths that originally had no timing violations, making timing closure more difficult. Summary of the Invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a method, device, equipment and medium for adjusting the holding time.

[0005] The present disclosure provides a method for adjusting a hold time, including:

[0006] Acquire timing analysis information of the circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and hold time abnormality information corresponding to the abnormal endpoint identifier;

[0007] determining a target number of delay adjustment units according to the hold time abnormality information;

[0008] In the circuit to be processed, the abnormal path endpoint corresponding to the abnormal endpoint identifier is determined, and the target number of delay adjustment units are inserted at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit.

[0009] The present disclosure also provides a device for adjusting the holding time, comprising:

[0010] An acquisition module is used to acquire timing analysis information of the circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and hold time abnormality information corresponding to the abnormal endpoint identifier;

[0011] A first determining module is configured to determine a target number of delay adjustment units according to the hold time abnormality information;

[0012] The adjustment module is used to determine the abnormal path endpoint corresponding to the abnormal endpoint identifier in the circuit to be processed, and insert the target number of delay adjustment units at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit.

[0013] An embodiment of the present disclosure also provides an electronic device, which includes: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the retention time adjustment method provided in the embodiment of the present disclosure.

[0014] An embodiment of the present disclosure further provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the method for adjusting the holding time provided in the embodiment of the present disclosure.

[0015] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art: the hold time adjustment solution provided by the embodiments of the present disclosure includes: obtaining timing analysis information of a circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and hold time anomaly information corresponding to the abnormal endpoint identifier; determining a target number of delay adjustment units based on the hold time anomaly information; determining the abnormal path endpoint corresponding to the abnormal endpoint identifier in the circuit to be processed, and inserting a target number of delay adjustment units at positions adjacent to the abnormal path endpoint to obtain an adjustment circuit. Using the above technical solution, the abnormal endpoint identifier of the circuit to be processed and its corresponding hold time anomaly information are obtained, the number of delay adjustment units is determined based on the hold time anomaly information, and a corresponding number of delay adjustment units are inserted at positions adjacent to the abnormal path endpoint corresponding to the abnormal endpoint identifier to obtain an adjustment circuit. By centrally arranging the delay adjustment units at positions immediately before the abnormal path endpoint, the length of the newly added interconnect lines due to the insertion of the delay adjustment units is shortened, thereby reducing errors caused by reconnection of the interconnect lines. Furthermore, the delay adjustment units are specifically applied to the abnormal path endpoint, thereby reducing the impact of the delay adjustment units on other paths. This achieves precise delay control of specific path endpoints from multiple dimensions, thereby reducing the difficulty of achieving hold time timing closure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0017] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic flow chart of a method for adjusting a holding time provided in an embodiment of the present disclosure;

[0019] Figure 2 A flowchart of another method for adjusting the holding time provided in an embodiment of the present disclosure;

[0020] Figure 3 A schematic diagram of an adjustment circuit provided in an embodiment of the present disclosure;

[0021] Figure 4 A flowchart of another method for adjusting the holding time provided in an embodiment of the present disclosure;

[0022] Figure 5 A schematic diagram of a method for adjusting holding time provided in an embodiment of the present disclosure;

[0023] Figure 6 A schematic structural diagram of a holding time adjustment device provided in an embodiment of the present disclosure;

[0024] Figure 7 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0026] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0027] With the rapid development of the semiconductor industry, chip process features are becoming increasingly smaller, and the integration density of individual chips is increasing, leading to greater challenges in chip design and production. Timing closure in the physical design of digital integrated circuits (ICs) is becoming increasingly challenging due to factors such as higher chip frequencies, more complex internal data interactions, and an increase in process corners. Therefore, projects that are eager to tape out but face difficulties in timing closure often choose to sacrifice some functionality or reduce the frequency to achieve timing closure.

[0028] Timing closure can be achieved through timing analysis. Static Timing Analysis (STA) is used to check whether the setup time and hold time of the chip data path meet the requirements according to the definition in the constraint file in the Electronic Design Automation (EDA) tool.

[0029] In related technologies, to achieve timing closure, electronic design automation tools (EDA) automatically converge setup and hold times based on the analysis results from the timing analysis phase, by increasing cell drivers without changing the circuit's logic functionality. The tools then output a timing closure script, which contains the adjustments made by the EDA tool to the circuit during the timing closure process.

[0030] In the related art, there are two problems: First, there are large errors caused by the reconnection of interconnection lines. Since the timing analysis tool cannot simulate the parasitic parameters generated by the reconnection of the actual interconnection lines of the adjusted circuit during the time convergence process, there may be large errors with the actual results. Therefore, multiple iterations are required to achieve timing convergence in real scenarios. Second, new timing non-convergence may be introduced. When converging the timing through electronic design automation tools, adjustments may be made on some common paths, which will eventually cause the timing of other timing paths to non-convergence, increase the number of iterations of the circuit and the difficulty of convergence.

[0031] In related technologies, in the process of achieving timing closure, a large number of interconnect reconnections are introduced, resulting in large errors and affecting paths that originally had no timing violations, increasing the difficulty of achieving timing closure.

[0032] In order to solve the above problems, an embodiment of the present disclosure provides a method for adjusting the holding time, which is described below in conjunction with specific embodiments.

[0033] Figure 1This is a flow chart of a method for adjusting the holding time provided by an embodiment of the present disclosure. The method for adjusting the holding time can be applied to a device for adjusting the holding time. The device for adjusting the holding time can be implemented using software and / or hardware, and the device for adjusting the holding time can generally be integrated into an electronic device. Figure 1 As shown, the method for adjusting the holding time includes:

[0034] Step 101 : Acquire timing analysis information of a circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and retention time abnormality information corresponding to the abnormal endpoint identifier.

[0035] Among them, the circuit to be processed may be a circuit in which the hold time corresponding to the components does not converge. The hold time may be the time during which the data signal actually remains stable after the trigger edge of the clock signal arrives. The non-convergence of the hold time can be understood as the hold time being less than the hold time threshold, that is, the time during which the data signal remains stable after the trigger edge of the clock signal arrives is too short. The hold time threshold may be the minimum time during which the data signal needs to remain stable after the trigger edge of the clock signal arrives. This embodiment does not impose any restrictions on the hold time threshold. The timing analysis information may be the result of analyzing the changes of the signal in the circuit to be processed over time.

[0036] The abnormal endpoint identifier can be used to mark the abnormal path endpoint. The abnormal path endpoint can be the timing path endpoint where the corresponding hold time does not converge. The timing path endpoint can be the data end corresponding to when the data is loaded along the time after passing through the combinational logic. For example, the timing path endpoint can include the data input end of components such as registers or triggers. The hold time exception information can be used to characterize the hold time corresponding to the abnormal path endpoint. This embodiment does not limit the hold time exception information. For example, the hold time exception information can include the specific value of the hold time, or the hold time exception information can include the hold time difference. The hold time difference can be the difference between the current hold time of the abnormal path endpoint and the hold time threshold.

[0037] In an embodiment of the present disclosure, the hold time adjustment device can perform timing analysis on the processing circuit through a timing analysis tool to obtain timing analysis information, which records the abnormal endpoint identifier and the hold time abnormality information corresponding to the abnormal endpoint identifier.

[0038] Step 102: Determine the target number of delay adjustment units according to the hold time abnormality information.

[0039] The delay adjustment unit can be an adjustment unit acting on the endpoint of an abnormal path, and can be used to correct hold time violations at the endpoint of the abnormal path. An adjustment unit, also known as a delay unit or buffer unit, can be used to adjust the arrival time of a signal so that the relevant signal meets the timing requirements of the circuit. The target number can be the number of delay adjustment units inserted into the circuit to be processed.

[0040] In an embodiment of the present disclosure, the holding time adjustment device can determine the target number of delay adjustment units for delaying the path abnormal endpoint based on the holding time abnormality information. Alternatively, the holding time adjustment device can determine the target number of delay adjustment units for delaying the path abnormal endpoint based on the holding time abnormality information and the endpoint constraint condition. The endpoint constraint condition can be a factor in other dimensions other than the holding time that affects the setting of the delay adjustment unit. This embodiment does not limit the endpoint constraint condition. For example, the endpoint constraint condition can include at least one of a pre-set holding time margin, the size of the remaining space around the path abnormal endpoint, and the establishment time margin.

[0041] Specifically, the hold time margin can be used to adjust the hold time threshold. This margin can be positive or negative. For example, if the hold time threshold is 5 nanoseconds and the margin is 1 nanosecond, the adjusted hold time threshold is 6 nanoseconds. If the hold time threshold is 5 nanoseconds and the margin is -1 nanosecond, the adjusted hold time threshold is 4 nanoseconds. The size of the remaining space around the abnormal path endpoint can be used to represent the space currently available for arranging delay adjustment units for the abnormal path endpoint. It can be understood that the space required to arrange the target number of delay adjustment units in the adjustment circuit must be included in this remaining space.

[0042] The setup time margin can be the difference between the current setup time of the abnormal path endpoint and the setup time threshold. The setup time can be the time that the data signal actually remains stable before the trigger edge of the clock signal arrives. The failure of the setup time to converge can be understood as the setup time being less than the setup time threshold, that is, the time that the data signal remains stable before the trigger edge of the clock signal arrives is too short. The setup time threshold can be the minimum time that the data signal actually needs to remain stable before the trigger edge of the clock signal arrives. It can be understood that the early or late arrival of the data signal has opposite effects on the hold time and setup time checks. By setting the setup time margin, after inserting the target number of delay adjustment units, if the change in the setup time exceeds the setup time margin, a setup time prompt message can be issued. Thus, by making the hold time converge, the normal implementation of the function is guaranteed, and the user is prompted to make subsequent adjustments to the setup time.

[0043] In the above solution, the flexible configuration of the holding time adjustment method is achieved by setting the endpoint constraint condition, so that the holding time adjustment method can be adapted to different application scenarios, thereby expanding the scope of application of the method.

[0044] Figure 2 A flow chart of another method for adjusting the holding time provided in an embodiment of the present disclosure is shown as follows: Figure 2 As shown, in some embodiments of the present disclosure, before determining the target number of delay adjustment units according to the hold time abnormality information, the hold time adjustment method further includes:

[0045] Step 201 : performing timing analysis on the series delay chain using a timing analysis tool to obtain the series delay length of the series delay chain; wherein the series delay chain includes a preset number of adjustment units to be tested of the same type connected in series.

[0046] Among them, the timing analysis tool is a software tool for performing timing analysis on the circuit, and the timing analysis tool can have a static timing analysis function. A series delay chain can be used to determine the unit delay length of a type of adjustment unit to be tested. This embodiment does not limit the number of the series delay chains. If the number of the series delay chains is multiple, the unit delay lengths of multiple types of adjustment units to be tested can be measured. The series delay length can be the delay length of the series delay chain as a whole. The unit delay length can be the delay length of a single adjustment unit to be tested. The preset number can be the number of adjustment units to be tested that are pre-set in series in the series delay chain. This embodiment does not limit the preset number. For example, the preset number can be 5 or 7. Since the error in the series determination of the unit delay length is mainly caused by the two measurement adjustment units located at both ends, increasing the preset number can reduce the error in the unit delay length.

[0047] The adjustment unit to be tested may be an adjustment unit for which a unit delay duration measurement is to be performed, and the unit delay durations corresponding to the same type of adjustment units to be tested are the same. The adjustment unit to be tested may include a delay adjustment unit and / or a candidate adjustment unit. Optionally, a preset delay duration of the adjustment unit to be tested may be recorded in a preset document, and the hold time adjustment device may select and determine a delay adjustment unit based on the preset delay duration and hold time anomaly information, and subsequently determine a unit delay duration of the delay adjustment unit with higher accuracy through a timing analysis tool.

[0048] In this embodiment, the hold time adjustment device can simulate a multi-stage series connection of a preset number of the same type of adjustment units under test to obtain a series delay chain corresponding to the adjustment unit under test. Furthermore, the series delay chain can be analyzed using a timing analysis tool to obtain the series delay length of the series delay chain.

[0049] Step 202 : determining the unit delay time of a single adjustment unit to be tested according to the series delay time and the preset number.

[0050] In this embodiment, the hold time adjustment device may divide the series delay length by a preset number, and use the result of the division as the unit delay length of the single adjustment unit under test. If there are multiple series delay chains, the above process may be performed on each of the multiple series delay chains to obtain the unit delay length of the different types of adjustment units under test corresponding to each series delay chain.

[0051] In the above solution, after connecting multiple adjustment units to be tested in series, the extension duration is determined as a whole, which reduces the error caused by the adjustment units to be tested at both ends and improves the accuracy of the unit delay duration of the single adjustment unit to be tested that is finally determined.

[0052] In some embodiments of the present disclosure, the delay adjustment unit is a predetermined single type of adjustment unit, and the adjustment unit to be tested includes the delay adjustment unit. In this embodiment, the delay duration of the delay adjustment unit is recorded in a preset document. The accuracy of the delay duration is relatively low, but it can be used as a basis for selecting the adjustment unit. The hold time adjustment device can determine the delay adjustment unit based on the delay duration recorded in the preset document and the hold time anomaly information, connect a preset number of delay adjustment units in series to obtain a series delay chain, determine the series delay duration of the series delay chain using a timing analysis tool, and determine the unit delay duration of a single delay adjustment unit based on the series delay duration and the preset number.

[0053] Accordingly, the target number of delay adjustment units is determined according to the hold time anomaly information, including: dividing the hold time difference and the unit delay duration of the delay adjustment unit and rounding up to obtain the target number; wherein the hold time difference is determined according to the hold time anomaly information.

[0054] In this embodiment, if the hold time anomaly information is a specific value of the hold time, the hold time adjustment device may subtract the hold time anomaly information from the hold time threshold to obtain a hold time difference. If the hold time anomaly information is a hold time difference, the hold time adjustment device may use the hold time anomaly information as the hold time difference. Furthermore, the hold time adjustment device may divide the hold time difference by the unit delay duration of the currently selected delay adjustment unit and round up to obtain a target number. For example, if the hold time difference is 5 nanoseconds and the unit delay duration is 2 nanoseconds, the target number is 3.

[0055] In the above scheme, the delay adjustment unit is of a single type. The error between the delay duration implemented by the single type of delay adjustment unit in the actual circuit and the delay duration calculated based on the unit delay duration is small, thereby achieving accurate adjustment of the delay duration.

[0056] In some embodiments of the present disclosure, the delay adjustment unit is an adjustment unit obtained by screening multiple types of candidate adjustment units, and the adjustment unit to be tested includes the candidate adjustment unit. Among them, the candidate adjustment unit can be an alternative adjustment unit, and the candidate adjustment unit can be of multiple types. In this embodiment, multiple candidate adjustment units are predetermined, and the adjustment device for holding time can use each candidate adjustment unit as the adjustment unit to be tested, and connect a preset number of the candidate adjustment units in series to obtain a series delay chain, determine the series delay length of the series delay chain through a timing analysis tool, and determine the unit delay length of a single candidate adjustment unit based on the series delay length and the preset number. The unit delay length corresponding to different types of candidate adjustment units is obtained.

[0057] Accordingly, determining the target number of delay adjustment units according to the hold time exception information includes:

[0058] In descending order of unit delay duration, the unit delay duration is determined as the current delay duration, and the holding time difference is determined as the current dividend; wherein the holding time difference is determined based on the holding time anomaly information; the current dividend is divided by the current delay duration to obtain a quotient and a remainder; if the quotient is not less than 1, the candidate adjustment unit corresponding to the current delay duration is determined as the delay adjustment unit, and the quotient is determined as the target number of delay adjustment units; if the remainder is not less than the minimum unit delay duration, the next unit delay duration is determined as the new current delay duration, and the remainder is determined as the new current dividend, and the new quotient and new remainder are determined again until the new remainder is less than the minimum unit delay duration.

[0059] The current delay duration may be the unit delay duration currently serving as the divisor. The current dividend may be the delay duration to be implemented by the currently assigned delay adjustment unit. The quotient may be the integer portion of the quotient. The minimum unit delay duration may be the minimum value among the multiple unit delay durations.

[0060] In this embodiment, after determining the unit delay duration corresponding to each candidate adjustment unit, the hold time adjustment device may sequentially determine each unit delay duration as the current delay duration in descending order of unit delay duration values. Furthermore, the hold time difference may be determined as the first current dividend.

[0061] Furthermore, for each current delay duration, the hold time adjustment device may divide the current dividend by the current delay duration, taking the integer portion of the quotient as the quotient and the portion that is not divisible as the remainder. Furthermore, it is determined whether the quotient is less than 1. If so, the next unit delay duration is determined as the new current delay duration, and the remainder is determined as the new current dividend. The process returns to determine a new quotient and a new remainder until the new remainder is less than the minimum unit delay duration.

[0062] If the quotient is not less than 1, the candidate adjustment unit corresponding to the current delay duration is determined as the delay adjustment unit, and the quotient is determined as the target number corresponding to the delay adjustment unit. Further, determine whether the remainder is less than the minimum unit delay duration. If the remainder is not less than the minimum unit delay duration, the next unit delay duration after the current delay duration is determined as the new current delay duration, and the remainder is determined as the new current dividend. Return to determine the new quotient and the new remainder until the new remainder is less than the minimum unit delay duration. If the remainder is less than the minimum unit delay duration, terminate the iterative process of determining the delay adjustment unit, and add 1 to the target number of delay adjustment units corresponding to the current delay duration; or, determine the candidate adjustment unit corresponding to the minimum unit delay duration as the delay adjustment unit, and add 1 to the target number of delay adjustment units corresponding to the minimum unit delay duration. For example, taking the remainder determined by the last iteration as 0 as an example, if the maintenance time difference is 5 nanoseconds, the unit delay lengths of the candidate adjustment units include 4 nanoseconds, 3 nanoseconds, 2 nanoseconds, and 1 nanosecond, then the delay adjustment unit includes 1 adjustment unit with a unit delay length of 4 nanoseconds and 1 adjustment unit with a unit delay length of 1 nanosecond.

[0063] In the above scheme, the delay adjustment units with higher coverage of the time difference and the target number of the delay adjustment units are determined, and candidate adjustment units with larger unit delay durations are preferentially selected as delay adjustment units, thereby reducing the space occupied by the delay adjustment units.

[0064] Step 103 : in the circuit to be processed, determine the abnormal path endpoint corresponding to the abnormal endpoint identifier, and insert a target number of delay adjustment units at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit.

[0065] In an embodiment of the present disclosure, a hold time adjustment device can determine the endpoint of an abnormal path in a circuit to be processed based on an abnormal endpoint identifier, and insert a target number of delay adjustment units at a location in the circuit to be processed that is before and adjacent to the endpoint of the abnormal path, thereby obtaining an adjusted circuit after the circuit to be processed has been adjusted. The adjacent location can be a location that is before the endpoint of the abnormal path and does not pass through a common path or other components. Figure 3A schematic diagram of an adjustment circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the abnormal path ends at the data terminal of trigger 2 and the data terminal of trigger 3. In the adjustment circuit, a delay adjustment unit is inserted before the data terminal of trigger 2, and a delay adjustment unit is inserted before the data terminal of trigger 3.

[0066] In some embodiments of the present disclosure, a target number of delay adjustment units are inserted at positions adjacent to the end point of the abnormal path to obtain an adjustment circuit, including:

[0067] Using a timing analysis tool, a target number of delay adjustment units are inserted adjacent to the end point of the abnormal path to obtain an intermediate circuit. If the timing analysis tool determines that the intermediate circuit meets the timing closure conditions, the intermediate circuit is determined to be an adjustment circuit.

[0068] Among them, the timing convergence condition can be a pre-set condition for the characterization circuit to achieve timing convergence. This embodiment does not limit the timing convergence condition. For example, the timing convergence condition may include a hold time not greater than a hold time threshold, and the timing convergence condition may also include a setup time not greater than a setup time threshold.

[0069] In this embodiment, the hold time adjustment device can use a timing analysis tool to insert a target number of delay adjustment units at a position before and adjacent to the end point of the abnormal path to obtain an intermediate circuit. The timing analysis tool does not rewire the circuit after the delay adjustment units are inserted into the circuit to be processed, so the intermediate circuit does not take into account the parasitic parameters of the interconnect lines newly added to the circuit to be processed due to the insertion of the delay adjustment units. Furthermore, the hold time adjustment device can use the timing analysis tool to determine whether the intermediate circuit meets the convergence condition. If so, the intermediate circuit is determined to be the adjustment circuit.

[0070] In some embodiments of the present disclosure, determining by a timing analysis tool whether the intermediate circuit meets the timing closure condition includes:

[0071] Perform timing analysis on the intermediate circuit using a timing analysis tool to obtain the setup time and hold time corresponding to the endpoints of each timing path in the intermediate circuit. If the setup time is not less than the setup time threshold and the hold time is not less than the hold time threshold, the intermediate circuit is determined to meet the timing closure conditions.

[0072] In this embodiment, the hold time adjustment device can perform timing analysis on the intermediate circuit using a timing analysis tool to obtain the setup time and hold time of each timing path endpoint in the intermediate circuit. It is determined whether all of the setup times are less than a setup time threshold. If at least one setup time is less than the setup time threshold, it indicates that the setup time corresponding to the corresponding timing path endpoint has not converged, and the intermediate circuit is determined to not meet the timing closure condition. If all setup times are not less than the setup time threshold, it indicates that the intermediate circuit meets the timing closure condition in the setup time dimension.

[0073] Furthermore, a determination is made as to whether all of the hold times are less than a hold time threshold. If at least one hold time is less than the hold time threshold, indicating that the hold time corresponding to the corresponding timing path endpoint has not converged, the intermediate circuit is determined to not meet the timing closure condition. If all hold times are not less than the hold time threshold, the intermediate circuit meets the timing closure condition in the hold time dimension. If the intermediate circuit meets the timing closure condition in both the setup time dimension and the hold time dimension, the intermediate circuit is determined to meet the timing closure condition.

[0074] Based on the calculation principle of the timing analysis method, in terms of data path, the data path can be the length of time spent in the combinational logic. The shorter the data path, the easier it is to meet the setup time threshold and the more difficult it is to meet the hold time threshold; the longer the data path, the opposite is true. In terms of clock frequency, the higher the clock frequency, the more difficult it is to meet the setup time threshold. Although the hold time has no direct relationship with the clock frequency, a higher frequency requires a shorter data path to meet the setup time threshold. On this basis, combined with the opposite effects of the above-mentioned data path on the setup time and hold time, a higher clock frequency also indirectly increases the difficulty of hold time convergence. Based on the above analysis, it can be determined that in this embodiment, adding a target number of delay adjustment units adjacent to the end point of the abnormal path will not only affect the hold time of the circuit, but also the setup time of the circuit. Therefore, both the setup time and the hold time are verified, so that the final adjustment circuit converges in both the setup time and the hold time dimensions.

[0075] The hold time adjustment method provided by the embodiment of the present disclosure includes: obtaining timing analysis information of a circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and hold time abnormality information corresponding to the abnormal endpoint identifier; determining a target number of delay adjustment units based on the hold time abnormality information; determining the abnormal path endpoint corresponding to the abnormal endpoint identifier in the circuit to be processed, and inserting a target number of delay adjustment units at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit. Using the above technical solution, the abnormal endpoint identifier of the circuit to be processed and its corresponding hold time abnormality information are obtained, the number of delay adjustment units is determined based on the hold time abnormality information, and a corresponding number of delay adjustment units are inserted at adjacent positions before the abnormal path endpoint corresponding to the abnormal endpoint identifier to obtain an adjustment circuit. By centrally arranging the delay adjustment units at positions immediately before the abnormal path endpoint, the length of the newly added interconnect line due to the insertion of the delay adjustment units is shortened, thereby reducing the error caused by the reconnection of the interconnect line, and the delay adjustment unit is specifically applied to the abnormal path endpoint, thereby reducing the impact of the delay adjustment unit on other paths, thereby achieving precise delay control of the specific path endpoint from multiple dimensions and reducing the difficulty of achieving hold time timing convergence.

[0076] Figure 4 A flow chart of another method for adjusting the holding time provided in an embodiment of the present disclosure is shown as follows: Figure 4 As shown, in some embodiments of the present disclosure, the method for adjusting the holding time further includes:

[0077] Step 401 : Perform physical implementation processing on the adjustment circuit using a physical design tool to obtain a physicalized circuit.

[0078] Among them, the physical design tool can be a tool for physical design and layout and routing (Physical Design-Place and Route, PR) of the circuit. Through the physical design tool, a target number of delay adjustment units can be inserted into the adjustment unit, and the layout and routing related to the delay adjustment unit can be performed. The circuit determined by the physical design tool takes into account the parasitic parameters of the newly added interconnection lines, and the parasitic parameters include one or more of parasitic capacitance, parasitic resistance, and parasitic inductance. The physical circuit can be a circuit obtained through physical design, layout and routing, etc., and the physical circuit can represent the actual physical structure of the circuit.

[0079] In this embodiment, the tool for physical implementation and the tool for timing analysis in the digital backend process can be different electronic design automation tools. Therefore, after obtaining the adjusted circuit, the hold time adjustment device can output a circuit script for the adjusted circuit obtained by adjusting the circuit to be processed. This circuit script can be imported into the physical design tool. The physical design tool can then re-arrange components and re-route wires for the adjusted portion of the circuit, extract interconnects and parasitic parameters, and finally obtain a physical circuit.

[0080] Step 402: If the physicalized circuit meets the timing closure condition, the physicalized circuit is determined as the target circuit.

[0081] The target circuit may be a circuit that is finally determined to meet the timing closure conditions and has completed physicalization.

[0082] In this embodiment, the hold time adjustment device can perform timing analysis on the physical circuit using a timing analysis tool to obtain the setup time and hold time of each timing path endpoint in the physical circuit. The device then determines whether all setup times are less than a setup time threshold. If at least one setup time is less than the setup time threshold, it indicates that the setup time corresponding to the corresponding timing path endpoint has not converged, and the physical circuit is determined to not meet the timing closure condition. If all setup times are not less than the setup time threshold, it indicates that the physical circuit meets the timing closure condition for the setup time dimension.

[0083] Furthermore, a determination is made as to whether all hold times are less than a hold time threshold. If at least one hold time is less than the hold time threshold, indicating that the hold time corresponding to the corresponding timing path endpoint has not converged, the physicalized circuit is determined to not meet the timing closure conditions. If all hold times are not less than the hold time threshold, the physicalized circuit meets the timing closure conditions in the hold time dimension. If the physicalized circuit meets the timing closure conditions in both the setup time dimension and the hold time dimension, the physicalized circuit is determined to meet the timing closure conditions and is identified as the target circuit.

[0084] Step 403: If the physical circuit does not meet the timing closure condition in the holding time dimension, the physical circuit is used as a new circuit to be processed, and a new physical circuit corresponding to the new circuit to be processed is determined until the new physical circuit meets the timing closure condition.

[0085] In this embodiment, if the physical circuit has at least one hold time that is less than the hold time threshold, indicating that the hold time corresponding to the corresponding timing path endpoint does not converge, it is determined that the physical circuit does not meet the timing convergence condition in the hold time dimension. The physical circuit is then used as a new circuit to be processed, and new timing analysis information of the new circuit to be processed is returned; a new target number of delay adjustment units is determined based on the new hold time anomaly information; in the new circuit to be processed, a new abnormal path endpoint corresponding to the new abnormal endpoint identifier is determined, and a new target number of new delay adjustment units are inserted in the adjacent position before the new abnormal path endpoint to obtain a new adjustment circuit. Further, the new adjustment circuit is physically implemented using a physical design tool to obtain a new physical circuit, until the new physical circuit meets the timing convergence condition, or until the number of iterations of the physical circuit is determined to reach a preset iteration threshold.

[0086] Optionally, the hold time adjustment method further includes: if the physical circuit does not meet the timing convergence condition in the setup time dimension, generating and sending setup time prompt information to prompt the user to optimize the prompt information of the physical circuit.

[0087] In the above solution, since the delay adjustment unit is connected in series, either singly or in multiple stages, before being inserted into the endpoint of the abnormal path, it is processed by the physical implementation tool to be placed close to the endpoint of the abnormal path. The interconnection between the delay adjustment unit and the endpoint of the abnormal path is extremely short, and the delay caused by the reconnection of the interconnection is extremely small. Therefore, after re-introducing the timing analysis tool, the timing closure judgment results are highly consistent with the judgment results obtained previously, which can effectively reduce the number of timing closure iterations and the iteration time.

[0088] Next, the method for adjusting the holding time in the embodiment of the present disclosure is further described through a specific example. Figure 5 A schematic diagram of a method for adjusting the holding time provided by an embodiment of the present disclosure is shown in FIG. Figure 5 As shown:

[0089] First, a timing analysis is performed on the circuit to be processed using a timing analysis tool to obtain an abnormal endpoint identifier and hold time abnormality information. The abnormal timing endpoint corresponding to the abnormal endpoint identifier can be the data input terminal of the trigger, and the hold time abnormality information can be the difference between the hold time corresponding to the abnormal timing endpoint and the hold time threshold. Further, a delay adjustment unit is selected, and the unit delay duration of the delay adjustment unit is determined. The type of the delay adjustment unit can be one, and the unit delay duration can be the unit delay duration of each unit adjustment unit when multiple delay adjustment units are connected in series in multiple stages, as simulated and calculated in the timing analysis tool.

[0090] Furthermore, the target number of delay adjustment units is determined based on the hold time difference and the unit delay duration. Specifically, the hold time adjustment device can divide the hold time difference by the unit delay duration and round up to obtain the target number of delay adjustment units that need to be inserted at the end point of the abnormal path. Further, the target number of delay adjustment units are inserted into adjacent positions before the end point of the abnormal path through a timing analysis tool to obtain an adjustment circuit, and the adjustment circuit is subjected to timing convergence verification. Thus, it is determined whether the hold time converges, and whether the insertion of the delay adjustment unit causes the setup time to not converge. Further, the circuit script is imported into a physical implementation tool. Specifically, the hold time adjustment device can output a circuit script that achieves timing convergence, and import the circuit script into a physical implementation tool, determine the physical circuit through the physical implementation tool, and determine whether the physical circuit meets the timing convergence conditions.

[0091] In the above solution, a delay adjustment unit is inserted at the endpoint of the abnormal path (for example, the data input terminal of the register). The delay adjustment units are connected in series to determine the series delay duration. The unit delay duration of each delay adjustment unit is determined based on the series delay duration, thereby improving the accuracy of the unit delay duration.

[0092] Moreover, it will not cause non-convergence of other timing path endpoints. Specifically, the delay adjustment unit inserted adjacent to the abnormal path endpoint makes the delay adjustment unit only affect the timing of the abnormal path endpoint. The error caused by the reconnection of the interconnection line is reduced. Specifically, since the delay adjustment unit is single or multi-stage series-connected, and directly adjacent to the abnormal sequence path endpoint, in the physical implementation dimension, these delay adjustment units will be placed close to the abnormal path endpoint. The interconnection line between the trigger and the delay adjustment unit is extremely short and the delay is extremely small. Therefore, when the physical circuit is imported into the timing analysis tool, the obtained timing analysis results are highly consistent with the timing analysis results of the adjustment circuit, which can effectively reduce the number of iterations and iteration time for timing convergence.

[0093] Furthermore, flexible configuration is achieved. Specifically, different delay adjustment units can be selected based on the hold time difference, endpoint constraint conditions, etc. For example, the endpoint constraint conditions can include a hold time margin, through which the hold time threshold can be flexibly adjusted to achieve different hold time convergence results. The determination of the target number of delay adjustment units can be further combined with the setup time difference, and the setup time difference can be the difference between the current setup time of the abnormal path endpoint and the setup time threshold. Optionally, the hold time adjustment method can be executed in an electronic design automation tool through a command line, making the execution of the hold time adjustment method more convenient.

[0094] The hold time adjustment method provided by the embodiment of the present disclosure can quickly and effectively converge the hold time while avoiding affecting other timing path endpoints, shortening the iteration time and accelerating the convergence process.

[0095] Figure 6 An embodiment of the present disclosure provides a schematic structural diagram of a device for adjusting a holding time. The device may be implemented by software and / or hardware, and the device may also be integrated into an electronic device.

[0096] like Figure 6 As shown, the holding time adjustment device includes:

[0097] An acquisition module 601 is configured to acquire timing analysis information of a circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and hold time abnormality information corresponding to the abnormal endpoint identifier;

[0098] A first determining module 602 is configured to determine a target number of delay adjustment units according to the hold time abnormality information;

[0099] The adjustment module 603 is configured to determine the abnormal path endpoint corresponding to the abnormal endpoint identifier in the circuit to be processed, and insert the target number of delay adjustment units at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit.

[0100] Optionally, the holding time adjustment device further includes:

[0101] a timing analysis module, configured to perform timing analysis on the series delay chain using a timing analysis tool to obtain a series delay length of the series delay chain before determining a target number of delay adjustment units according to the hold time anomaly information; wherein the series delay chain includes a preset number of adjustment units to be tested of the same type connected in series;

[0102] The second determining module is configured to determine the unit delay time length of a single adjustment unit to be tested according to the series delay time length and the preset number.

[0103] Optionally, the delay adjustment unit is a predetermined single type of adjustment unit, and the adjustment unit to be tested includes the delay adjustment unit;

[0104] Accordingly, the first determining module 602 is configured to:

[0105] The target number is obtained by dividing the holding time difference by the unit delay duration of the delay adjustment unit and rounding up the result; wherein the holding time difference is determined according to the holding time abnormality information.

[0106] Optionally, the delay adjustment unit is an adjustment unit obtained by screening multiple types of candidate adjustment units, and the adjustment unit to be tested includes the candidate adjustment unit;

[0107] Accordingly, the first determining module 602 is configured to:

[0108] In descending order of the unit delay durations, the unit delay durations are sequentially determined as current delay durations, and the holding time difference is determined as a current dividend; wherein the holding time difference is determined based on the holding time anomaly information;

[0109] Dividing the current dividend by the current delay duration to obtain a quotient and a remainder, and if the quotient is not less than 1, determining the candidate adjustment unit corresponding to the current delay duration as the delay adjustment unit, and determining the quotient as the target number of the delay adjustment units;

[0110] If the remainder is not less than the minimum unit delay time, the next unit delay time is determined as the new current delay time, and the remainder is determined as the new current dividend, and the new quotient and the new remainder are determined again until the remainder is less than the minimum unit delay time.

[0111] Optionally, inserting the target number of delay adjustment units at positions adjacent to the end point of the abnormal path to obtain an adjustment circuit includes:

[0112] Using a timing analysis tool, inserting the target number of delay adjustment units adjacent to an end point of the abnormal path to obtain an intermediate circuit;

[0113] If it is determined by the timing analysis tool that the intermediate circuit meets the timing closure condition, the intermediate circuit is determined as the adjustment circuit.

[0114] Optionally, determining, by the timing analysis tool, that the intermediate circuit meets a timing closure condition includes:

[0115] Performing timing analysis on the intermediate circuit using the timing analysis tool to obtain setup time and hold time corresponding to endpoints of each timing path in the intermediate circuit;

[0116] If the setup times are not less than the setup time threshold, and the hold times are not less than the hold time threshold, it is determined that the intermediate circuit meets the timing closure condition.

[0117] Optionally, the holding time adjustment device further includes:

[0118] A physical description is used to perform physical implementation processing on the adjustment circuit using a physical design tool to obtain a physical circuit;

[0119] The third determination module is used to take the physical circuit as a new circuit to be processed if the physical circuit does not meet the timing convergence condition in the maintenance time dimension, and determine a new physical circuit corresponding to the new circuit to be processed until the new physical circuit meets the timing convergence condition.

[0120] It should be noted that Figure 6 The holding time adjustment device 600 shown can execute the various steps in the above-mentioned holding time adjustment method embodiment, and realize the various processes and effects in the above-mentioned holding time adjustment method embodiment, which will not be described in detail here.

[0121] Figure 7 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Figure 7 As shown, electronic device 700 includes one or more processors 701 and memory 702 .

[0122] The processor 701 may be a central processing unit (CPU) or other forms of processing units having a capability of adjusting time and / or executing instructions, and may control other components in the electronic device 700 to perform desired functions.

[0123] The memory 702 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 701 may execute the program instructions to implement the above-described method for adjusting the hold time of the embodiment of the present disclosure and / or other desired functions. Various contents such as input signals, signal components, noise components, etc. may also be stored in the computer-readable storage medium.

[0124] In one example, the electronic device 700 may further include an input device 703 and an output device 704 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0125] In addition, the input device 703 may also include, for example, a keyboard, a mouse, and the like.

[0126] The output device 704 can output various information to the outside, including determined distance information, direction information, etc. The output device 704 can include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.

[0127] Of course, to simplify, Figure 7 Only some of the components related to the present disclosure in the electronic device 700 are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, the electronic device 700 may further include any other appropriate components according to specific application scenarios.

[0128] In addition to the above-mentioned method and device, the embodiment of the present disclosure may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the retention time adjustment method provided by the embodiment of the present disclosure.

[0129] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0130] In addition, the embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the retention time adjustment method provided by the embodiment of the present disclosure.

[0131] The computer-readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can, for example, include but is not limited to a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0132] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0133] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A method for adjusting holding time, characterized in that: include: Acquire timing analysis information of the circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and retention time abnormality information corresponding to the abnormal endpoint identifier; Determine a target number of delay adjustment units according to the hold time exception information; In the circuit to be processed, the abnormal path endpoint corresponding to the abnormal endpoint identifier is determined, and the target number of delay adjustment units are inserted into adjacent positions before the abnormal path endpoint to obtain an adjustment circuit.

2. The method according to claim 1, characterized in that Before determining the target number of delay adjustment units according to the retention time abnormality information, the method further includes: Performing timing analysis on the series delay chain by using a timing analysis tool to obtain the series delay length of the series delay chain; wherein the series delay chain includes a preset number of series-connected adjustment units of the same type to be tested; The unit delay time length of a single adjustment unit to be tested is determined according to the series delay time length and the preset number.

3. The method according to claim 2, characterized in that The delay adjustment unit is a predetermined single type of adjustment unit, and the adjustment unit to be tested includes the delay adjustment unit; Correspondingly, determining the target number of delay adjustment units according to the retention time abnormality information includes: The target number is obtained by dividing the holding time difference and the unit delay duration of the delay adjustment unit and rounding up; wherein the holding time difference is determined according to the holding time abnormality information.

4. The method according to claim 2, characterized in that: The delay adjustment unit is an adjustment unit obtained by screening multiple types of candidate adjustment units, and the adjustment unit to be tested includes the candidate adjustment unit; Correspondingly, determining the target number of delay adjustment units according to the retention time abnormality information includes: According to the order of the unit delay time lengths from large to small, the unit delay time lengths are determined as the current delay time lengths, and the holding time difference is determined as the current dividend; wherein the holding time difference is determined according to the holding time abnormality information; Dividing the current dividend and the current delay duration to obtain a quotient and a remainder, and if the quotient is not less than 1, determining the candidate adjustment unit corresponding to the current delay duration as the delay adjustment unit, and determining the quotient as the target number of the delay adjustment units; If the remainder is not less than the minimum unit delay duration, the next unit delay duration is determined as the new current delay duration, and the remainder is determined as the new current dividend, and the new quotient and the new remainder are determined again until the new remainder is less than the minimum unit delay duration.

5. The method according to claim 1, characterized in that The step of inserting the target number of delay adjustment units at positions adjacent to the end point of the abnormal path to obtain an adjustment circuit includes: By using a timing analysis tool, inserting the target number of delay adjustment units adjacent to the end point of the abnormal path to obtain an intermediate circuit; If it is determined by the timing analysis tool that the intermediate circuit meets the timing closure condition, the intermediate circuit is determined as the adjustment circuit.

6. The method according to claim 5, characterized in that Determining by the timing analysis tool that the intermediate circuit meets the timing closure condition includes: Performing timing analysis on the intermediate circuit by using the timing analysis tool to obtain setup time and hold time corresponding to endpoints of each timing path in the intermediate circuit; If the setup times are not less than the setup time threshold, and the hold times are not less than the hold time threshold, it is determined that the intermediate circuit meets the timing closure condition.

7. The method according to claim 5, characterized in that The method further comprises: Performing physical implementation processing on the adjustment circuit by using a physical design tool to obtain a physicalized circuit; If the physicalized circuit does not meet the timing closure condition in the retention time dimension, the physicalized circuit is used as a new circuit to be processed, and a new physicalized circuit corresponding to the new circuit to be processed is determined until the new physicalized circuit meets the timing closure condition.

8. A device for adjusting holding time, characterized in that: include: An acquisition module, used to acquire timing analysis information of the circuit to be processed; wherein the timing analysis information includes an abnormal endpoint identifier and holding time abnormality information corresponding to the abnormal endpoint identifier; A first determining module, configured to determine a target number of delay adjustment units according to the abnormal retention time information; The adjustment module is used to determine the abnormal path endpoint corresponding to the abnormal endpoint identifier in the circuit to be processed, and insert the target number of delay adjustment units at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit.

9. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the holding time adjustment method described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program is used to execute the method for adjusting the holding time described in any one of claims 1 to 7.

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