Layout optimization evaluation method and device, test structure and storage medium

Abstract

The invention relates to a layout optimization evaluation method, a test structure, a device and a storage medium. The method comprises the following steps: acquiring a first layout; constructing delay relationships corresponding to the various types of test capacitor structures; the delay relation comprises a data relation based on delay of a test capacitor structure, a capacitance value and / or structural design parameters; obtaining a layout optimization type; based on a delay relation corresponding to the layout optimization type, performing delay optimization on the first layout, and / or performing delay evaluation on a second layout; wherein the first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator. According to the method and the device, the delay relation corresponding to various types of test capacitor structures is constructed, and the delay relation is used for carrying out delay optimization on the first layout and / or carrying out delay evaluation on the second layout based on the layout optimization type, so that the performance of the ring oscillator can be evaluated more accurately, and the performance of the ring oscillator is improved.

Description

Technical Field

[0001] The present application relates to the field of test optimization technology, and in particular to a layout optimization evaluation method, a test structure, a device and a storage medium. Background Art

[0002] In complementary metal oxide semiconductor (CMOS) digital circuits, the operating frequency of the circuit is strongly correlated with the performance. The higher the frequency, the better the performance. Complementary metal oxide semiconductor refers to a technology used to manufacture large-scale integrated circuit chips or chips manufactured using this technology. Ring oscillators (RO) are often used to implement frequency control of CMOS digital circuits because of their good compatibility with CMOS processes. The frequency of RO is generally used to characterize the high-frequency performance of digital CMOS circuits.

[0003] In the related art, the structure of the ring oscillator is as follows: Figure 1 As shown, it is composed of an odd number of inverters connected end to end. When RO starts to oscillate, the potential between the stages will jump between high potential and low potential and stabilize at a certain frequency. Due to the characteristics of capacitors passing AC and blocking DC, when RO is working, the inter-stage equivalent capacitance C (parasitic capacitance) will affect the speed of change of the inter-stage potential, thereby affecting the operating frequency of RO. When designing a ring oscillator, currently only the parasitic capacitance of the back-end connection is paid attention to. Only paying attention to the parasitic capacitance of the back-end connection cannot accurately evaluate the performance of the ring oscillator, resulting in poor performance of the ring oscillator. Summary of the invention

[0004] Based on this, it is necessary to provide a layout optimization evaluation method, test structure, device and storage medium for a ring oscillator in response to the above technical problems.

[0005] In a first aspect, the present application provides a layout optimization and evaluation method for a ring oscillator, the method comprising: obtaining a first layout; constructing delay relationships corresponding to multiple types of test capacitor structures; the delay relationship comprising a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure; obtaining a layout optimization type; based on the delay relationship corresponding to the layout optimization type, performing delay optimization on the first layout, and / or performing delay evaluation on the second layout; wherein the first layout is the layout of the original ring oscillator; and the second layout is the layout of the optimized ring oscillator.

[0006] In one embodiment, the construction of delay relationships corresponding to multiple types of test capacitor structures includes: based on the original ring oscillator, constructing multiple types of multiple test capacitor structures, and determining the capacitance value of each of the test capacitor structures; based on the multiple types of multiple test capacitor structures, respectively constructing multiple test ring oscillators; according to the delay of the test ring oscillator, obtaining the delay of each of the test capacitor structures; based on the delay, capacitance value and / or structural design parameters corresponding to each type of the multiple test capacitor structures, constructing the delay relationship of each type of the test capacitor structure.

[0007] In one of the embodiments, multiple types of test capacitor structures are constructed based on the original ring oscillator, including constructing multiple first-type test capacitor structures based on the front-end CMOS capacitor; the structural design parameters of the first-type test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically including: the first-type test capacitor structure includes an active area, a gate, a contact hole and a metal wire; the gate portion covers the active area to form at least one channel; contact holes are respectively set in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the first-type test capacitor structure are respectively set on the gate and the metal wire; the gate length of the channel in the first-type test capacitor structure is adjusted to generate multiple first-type test capacitor structures.

[0008] In one of the embodiments, based on the original ring oscillator, multiple types of multiple test capacitor structures are constructed, including constructing multiple second-type test capacitor structures based on mid-segment capacitors; the structural design parameters of the second-type test capacitor structures include the number of contact holes in the mid-segment capacitor structure; specifically including: the second-type test capacitor structure includes an active area, a gate, a contact hole and a metal wire; the gate portion covers the active area to form at least one channel; contact holes are respectively set in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the second-type test capacitor structure are respectively set on the gate and the metal wire; the number of contact holes in the second-type test capacitor structure is adjusted to generate multiple second-type test capacitor structures.

[0009] In one of the embodiments, based on the original ring oscillator, multiple types of multiple test capacitor structures are constructed, including multiple third-type test capacitor structures for constructing back-end capacitors; the structural design parameters of the third-type test capacitor structure include the facing area between metal wires in the back-end capacitor structure; specifically including: the third-type test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the first metal wire and the second metal wire are respectively arranged on the first metal wire and the second metal wire as the two ends of the third-type test capacitor structure; the facing area between the first metal wire and the second metal wire in the third-type test capacitor structure is adjusted to generate multiple third-type test capacitor structures.

[0010] In one of the embodiments, multiple types of test capacitor structures are constructed based on the original ring oscillator, including constructing multiple fourth-type test capacitor structures based on the front-end junction capacitor; the structural design parameters of the fourth-type test capacitor structure include the area of ​​the doped active area in the front-end junction capacitor structure; specifically including: the fourth-type test capacitor structure includes a first substrate, a second doped active area, a contact hole and a metal wire; the first substrate and the second doped active area form a PN junction, a contact hole is set on the second doped active area, and the contact hole is connected to the metal wire; wherein the first substrate and the second doped active area are a P-type substrate and an N-type doped active area, or an N-type substrate and a P-type doped active area; and the design of the first substrate and the second doped active area matches the structure of the original ring oscillator; the two ends of the fourth-type test capacitor structure are respectively arranged on the first substrate and the metal wire; the area of ​​the second doped active area in the fourth-type test capacitor structure is adjusted to generate multiple fourth-type test capacitor structures.

[0011] In one embodiment, based on the multiple test capacitor structures of the multiple types, a plurality of test ring oscillators are constructed respectively, including: connecting the same test capacitor structure between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; and constructing the plurality of test ring oscillators by adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator; wherein, connecting the same test capacitor structure between each interstage node of the original ring oscillator includes: connecting the two ends of the test capacitor structure to the interstage node and a ground line or a power line respectively.

[0012] In one of the embodiments, based on the delay relationship corresponding to the layout optimization type, the first layout is delayed optimized, including: calculating the delay difference based on the delay of the original ring oscillator and the target delay requirement; determining at least one target delay relationship according to at least one of the layout optimization types; optimizing the structure of the original ring oscillator based on the target delay relationship and the delay difference to obtain the layout of the optimized ring oscillator; wherein the target delay relationship includes a data relationship between the delay and the capacitance value based on the test capacitor structure, a data relationship between the capacitance value and the structural design parameters based on the test capacitor structure, and / or a data relationship between the delay and the structural design parameters based on the test capacitor structure.

[0013] In one of the embodiments, based on the delay relationship corresponding to the layout optimization type, a delay evaluation is performed on the second layout, including: determining at least one target delay relationship according to at least one of the layout optimization types; determining at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator based on the first layout and the second layout; based on the target delay relationship and the structural design parameter difference, evaluating the delay of the optimized ring oscillator to complete the delay evaluation of the second layout; wherein the target delay relationship includes a data relationship between a delay and a capacitance value based on a test capacitor structure, a data relationship between a capacitance value and a structural design parameter based on a test capacitor structure, and / or a data relationship between a delay and a structural design parameter based on a test capacitor structure.

[0014] In a second aspect, the present application also provides a performance test structure of a ring oscillator, including multiple types of test capacitor structures; the performance test structure is applied to the layout optimization evaluation method of the ring oscillator described in any one of the first aspects above; the test capacitor structure is based on a partial structure design of the original ring oscillator, and the partial structure includes at least one of a front-end CMOS structure, a middle-end capacitor structure, a back-end capacitor structure and a front-end junction capacitor structure.

[0015] In one of the embodiments, it includes a first type of test capacitor structure based on a front-end CMOS capacitor; the structural design parameters of the first type of test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically, the first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal lines; the two ends of the first type of test capacitor structure are respectively set on the gate and the metal line; different first type of test capacitor structures have different channel gate lengths.

[0016] In one of the embodiments, a second type of test capacitor structure based on a mid-section capacitor is included; the structural design parameters of the second type of test capacitor structure include the number of contact holes in the mid-section capacitor structure; specifically, the second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal lines; the two ends of the second type of test capacitor structure are respectively provided on the gate and the metal line; different second type of test capacitor structures have different numbers of contact holes.

[0017] In one of the embodiments, a third type of test capacitor structure includes a back-end capacitor; the structural design parameters of the third type of test capacitor structure include the facing area between metal wires in the back-end capacitor structure; specifically, the third type of test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the two ends of the third type of test capacitor structure are respectively arranged on the first metal wire and the second metal wire; different third type test capacitor structures have different facing areas between the first metal wire and the second metal wire.

[0018] In one of the embodiments, a fourth type of test capacitor structure based on a front-end junction capacitor is included; the structural design parameters of the fourth type of test capacitor structure include the area of ​​the doped active region in the front-end junction capacitor structure; specifically, the fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal wire; the first substrate and the second doped active region form a PN junction, a contact hole is arranged on the second doped active region, and the contact hole is connected to the metal wire; wherein the first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; the two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal wire; different fourth type test capacitor structures have different second doped active region areas.

[0019] In one embodiment, at least one test ring oscillator is included; between each interstage node of the original ring oscillator, the same test capacitor structure is respectively connected to form a test ring oscillator corresponding to the test capacitor structure; different test ring oscillators have different types and / or structural design parameters of the test capacitor structure connected in the original ring oscillator; wherein, between each interstage node of the original ring oscillator, the same test capacitor structure is respectively connected, including: connecting two ends of the test capacitor structure to the interstage node and a ground line or a power line respectively.

[0020] In the third aspect, the present application also provides a layout optimization and evaluation device for a ring oscillator, the device comprising: a first acquisition module, used to acquire a first layout; a construction module, used to construct delay relationships corresponding to multiple types of test capacitor structures; the delay relationship includes a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure; a second acquisition module, used to acquire a layout optimization type; an optimization module, used to perform delay optimization on the first layout based on the delay relationship corresponding to the layout optimization type, and / or perform delay evaluation on the second layout; wherein the first layout is the layout of the original ring oscillator; and the second layout is the layout of the optimized ring oscillator.

[0021] In a fourth aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the layout optimization evaluation method for a ring oscillator described in any one of the first aspects is implemented.

[0022] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the layout optimization evaluation method for a ring oscillator described in any one of the first aspects above is implemented.

[0023] The layout optimization evaluation method and performance test structure of the above-mentioned ring oscillator obtains the first layout, and constructs the delay relationship corresponding to various types of test capacitor structures. Among them, the delay relationship includes the data relationship between the delay, capacitance value and / or structural design parameters based on the test capacitor structure. Then obtain the layout optimization type, and based on the delay relationship corresponding to the layout optimization type, perform delay optimization on the first layout and / or perform delay evaluation on the second layout. Among them, the first layout is the layout of the original ring oscillator, and the second layout is the layout of the optimized ring oscillator. By constructing the delay relationship corresponding to various types of test capacitor structures, and then based on the layout optimization type through the delay relationship, the first layout is delayed and / or the second layout is delayed. Evaluation, so that the performance of the ring oscillator can be more accurately evaluated, thereby improving the performance of the ring oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a ring oscillator in one embodiment; Figure 2 A schematic diagram of a flow chart of a layout optimization evaluation method for a ring oscillator in one embodiment; Figure 3 A schematic flow chart of a method for constructing a delay relationship in one embodiment; Figure 4 A schematic diagram of the structure of multiple first-type test capacitor structures in one embodiment; Figure 5 A schematic diagram of the structure of multiple second-type test capacitor structures in one embodiment; Figure 6 A schematic diagram of the structure of multiple third-type test capacitor structures in one embodiment; Figure 7 is a schematic structural diagram of a plurality of fourth-type test capacitor structures in one embodiment; Figure 8 A schematic diagram of the structure of a testing ring oscillator in one embodiment; Fig. 9 It is a schematic diagram of the flow of a first layout delay optimization method in one embodiment; Fig.10 It is a flowchart of the second layout delay evaluation method in one embodiment; Fig.11 A structural block diagram of a layout optimization and evaluation device for a ring oscillator in one embodiment; Fig.12 is an internal structure diagram of a computer device in one embodiment; Fig.13 1 is a diagram showing the relationship between the delays and capacitance values ​​based on four test capacitor structures in one embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] In complementary metal oxide semiconductor (CMOS) digital circuits, the operating frequency of the circuit is strongly correlated with the performance. The higher the frequency, the better the performance. Complementary metal oxide semiconductor refers to a technology used to manufacture large-scale integrated circuit chips or chips manufactured using this technology. Ring oscillators (RO) are often used to implement frequency control of CMOS digital circuits because of their good compatibility with CMOS processes. The frequency of RO is generally used to characterize the high-frequency performance of digital CMOS circuits.

[0027] In the related art, the structure of the ring oscillator is as follows: Figure 1 As shown in the figure, it is composed of an odd number of inverters connected end to end. When RO starts to oscillate, the potential between the stages will jump between high potential and low potential and stabilize at a certain frequency. Due to the characteristics of capacitors passing AC and blocking DC, when RO is working, the inter-stage equivalent capacitance C will affect the speed of change of the inter-stage potential, thereby affecting the operating frequency of RO. When designing a ring oscillator, only the parasitic capacitance of the back-end connection is currently concerned. The inter-stage equivalent capacitance C includes not only the parasitic capacitance of the back-end connection, but also the parasitic capacitance of the middle section, the parasitic capacitance of the front section, and the junction capacitance. The parasitic capacitance of the front section, the parasitic capacitance of the middle section, and the junction capacitance also account for a large proportion of the inter-stage equivalent capacitance, especially with the continuous advancement of process nodes, this part of the parasitic capacitance has become non-negligible.

[0028] The embodiment of the present application constructs test capacitor structures corresponding to the parasitic capacitance of the rear-end connection, the parasitic capacitance of the middle section, the parasitic capacitance of the front section, and the junction capacitance, respectively, and then establishes a corresponding mapping relationship according to each type of test capacitor structure. Thus, according to the mapping relationship, a guiding direction is provided for the process optimization and design optimization of the ring oscillator, and the performance of the ring oscillator can be evaluated more accurately, thereby further improving the performance of the ring oscillator.

[0029] In one embodiment, Figure 2 As shown, a layout optimization evaluation method for a ring oscillator is provided, comprising the following steps: Step 201, obtaining a first layout.

[0030] When performing delay optimization or delay evaluation on a ring oscillator, it is necessary to first obtain a first layout of the ring oscillator, wherein the first layout is the layout of the original ring oscillator, that is, the layout that has not been optimized.

[0031] Step 202: construct delay relationships corresponding to various types of test capacitor structures.

[0032] Construct delay relationships corresponding to various types of test capacitor structures, where the delay relationships can be presented in the form of curves, charts, and relationships, which are not specifically limited in this embodiment. The test capacitor structure is designed based on a partial structure of the original ring oscillator. The partial structure includes: at least one of a front-end CMOS structure, a middle-end capacitor structure, a back-end capacitor structure, and a front-end junction capacitor structure. In the semiconductor manufacturing process, the front-end layer (Front-End-of-Line, FEOL) involves the manufacture and formation of transistors on the wafer, including ion implantation, oxidation, thin film deposition, lithography, and etching processes; the middle-end layer (Middle-of-Line, MOL) involves the metal interconnection between the device of the front-end layer and the back-end layer, including the opening and filling of the contact hole Contact; the back-end layer (Back-End-of-Line, BEOL) involves the formation of metal interconnects in the chip, including metal deposition, lithography, etching, chemical mechanical polishing (CMP) and other processes. The various types of test capacitor structures may include: at least one of the test capacitor structure of the front-end CMOS (i.e., the front-end MOS channel parasitic capacitor Cch), the test capacitor structure of the middle-end capacitor (i.e., the middle-end contact hole parasitic capacitor Cco), the test capacitor structure of the back-end capacitor (i.e., the back-end connection parasitic capacitor Cbeol), and the test capacitor structure of the front-end junction capacitor (i.e., the PN junction parasitic capacitor Cj). The delay relationship includes a data relationship based on the delay, capacitance value, and / or structural design parameters of the test capacitor structure. Among them, the structural design parameters include the gate length of the channel in the front-end CMOS structure, the number of contact holes in the middle-end capacitor structure, the facing area between metal wires in the back-end capacitor structure, and the area of ​​the doped active region in the front-end junction capacitor structure. After constructing various types of test capacitor structures, multiple test ring oscillators can be constructed respectively according to the various types of test capacitor structures; then, according to the test ring oscillators, the delay of the test ring oscillator is determined, that is, the delay of each test capacitor structure is obtained; then, the capacitance value and structural design parameters of each test capacitor structure are determined, thereby determining the delay relationship of the delay, capacitance value, and / or structural design parameters of the test capacitor structure. The delay relationship includes: the delay relationship corresponding to the capacitance structure of the front-end CMOS, the delay relationship corresponding to the capacitance structure of the middle-end capacitor, the delay relationship corresponding to the capacitance structure of the rear-end capacitor, and the delay relationship corresponding to the capacitance structure of the front-end junction capacitor.

[0033] Step 203, obtaining layout optimization type.

[0034] When the first layout needs to be delayed optimized, the layout optimization type is obtained. Or for the second layout that has been optimized, the layout optimization type corresponding to the optimization is obtained. The layout optimization types include: the layout optimization type for the capacitor structure of the front-end CMOS, the layout optimization type for the capacitor structure of the middle-end capacitor, the layout optimization type for the capacitor structure of the back-end capacitor, and the layout optimization type for the capacitor structure of the front-end junction capacitor. That is, the layout optimization type corresponds to the delay relationship. After determining the layout optimization type, the delay relationship corresponding to the corresponding test capacitor structure can be found.

[0035] Step 204 , based on the delay relationship corresponding to the layout optimization type, perform delay optimization on the first layout and / or perform delay evaluation on the second layout.

[0036] According to the layout optimization type, the delay relationship corresponding to the layout optimization type is determined. According to the delay relationship, the first layout is delayed optimized and / or the second layout is delayed evaluated. When delay optimization is required, the first layout can be delayed optimized, and when delay evaluation is required, the second layout can be delayed evaluated; the first layout can also be delayed optimized and the second layout can be delayed evaluated at the same time. Among them, the first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator.

[0037] The above embodiment obtains the first layout and constructs delay relationships corresponding to various types of test capacitor structures. Wherein, the delay relationship includes a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure. Then obtain the layout optimization type, and based on the delay relationship corresponding to the layout optimization type, perform delay optimization on the first layout and / or perform delay evaluation on the second layout. Wherein the first layout is the layout of the original ring oscillator, and the second layout is the layout of the optimized ring oscillator. By constructing delay relationships corresponding to various types of test capacitor structures, and then based on the layout optimization type through the delay relationship, perform delay optimization on the first layout and / or perform delay evaluation on the second layout, the performance of the ring oscillator can be evaluated more accurately, thereby improving the performance of the ring oscillator.

[0038] In one embodiment, if Figure 3 As shown, a method for constructing a delay relationship is provided, comprising the following steps: Step 301 : construct multiple types of test capacitor structures based on the original ring oscillator, and determine the capacitance value of each test capacitor structure.

[0039] Based on the above, the various types of test capacitor structures include: at least one of the test capacitor structure of the front-end CMOS, the test capacitor structure of the middle-end capacitor, the test capacitor structure of the back-end capacitor, and the test capacitor structure of the front-end junction capacitor. According to the original ring oscillator, various types of test capacitor structures are constructed, and multiple test capacitor structures are constructed for each type, and then the capacitance value corresponding to each test capacitor structure is determined.

[0040] For the test capacitor structure of the front-end CMOS, multiple first-type test capacitor structures based on the front-end CMOS capacitor are constructed; the structural design parameters of the first-type test capacitor structure include the gate length of the channel in the front-end CMOS structure. Specifically, Figure 4 As shown, the first type of test capacitor structure includes an active area AA, a gate Gate, a contact hole Contact and a metal line Metal, which is used to characterize the influence of Cch capacitance. The gate partially covers the active area to form at least one channel, and contact holes are respectively set in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line; the two ends of the first type of test capacitor structure are respectively set on the gate and the metal line; the gate length of the channel in the first type of test capacitor structure is adjusted to generate multiple first type test capacitor structures. The gate Gate overlaps with the active area AA, and the two sides of the gate Gate form the source region and the drain region. Contact holes Contact are respectively set in the source region and the drain region, and the contact holes Contact are connected through the Metal layer corresponding to the metal line. For the first type of test capacitor structure, in order to characterize the channel capacitance of the MOS structure Gate itself, the gate length of the channel in the first type of test capacitor structure is adjusted, that is, the overlapping area of ​​Gate and AA is adjusted, so that the size of the parasitic capacitance can be adjusted. For the first type of test capacitor structure, multiple first type of test capacitor structures are constructed with different channel gate lengths. The capacitance value of each first type of test capacitor structure is obtained by testing the multiple first type of test capacitor structures.

[0041] For the test capacitor structure of the mid-segment capacitor, multiple second-type test capacitor structures based on the mid-segment capacitor are constructed; the structural design parameters of the second-type test capacitor structure include the number of contact holes in the mid-segment capacitor structure. Specifically, Figure 5As shown, the second type of test capacitor structure includes an active area AA, a gate Gate, a contact hole Contact and a metal line Metal, which is used to characterize the influence of Cco capacitance. The gate partially covers the active area to form at least one channel; contact holes are respectively set in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line; the two ends of the second type of test capacitor structure are respectively set on the gate and the metal line; the number of contact holes in the second type of test capacitor structure is adjusted to generate multiple second type test capacitor structures. The gate Gate overlaps with the active area AA, and the two sides of the gate Gate form the source region and the drain region. Contact holes Contact are respectively set in the source region and the drain region, and the contact holes Contact are connected through the Metal layer corresponding to the metal line. For the second type of test capacitor structure, a parasitic capacitor will be formed between the gate Gate and the contact hole Contact. By adjusting the number of contact holes Contact, the size of the parasitic capacitor can be adjusted. For the second type of test capacitor structure, multiple second type test capacitor structures are constructed with different numbers of contact holes Contact. By testing a plurality of second-type test capacitor structures, a capacitance value of each second-type test capacitor structure is obtained.

[0042] For the test capacitor structure of the back-end capacitor, multiple third-type test capacitor structures of the back-end capacitor are constructed; the structural design parameters of the third-type test capacitor structure include the facing area between metal wires in the back-end capacitor structure. Specifically, Figure 6 As shown, the third type of test capacitor structure includes a first metal wire and a second metal wire, which is used to characterize the influence of Cbeol capacitance. In this embodiment, the first metal wire and the second metal wire are two metal wires of the same Metal metal layer, respectively. Specifically, the first metal wire and the second metal wire can be two metal wires of the same metal layer in the original ring oscillator; in some other embodiments, the first metal wire and the second metal wire can also be two metal wires of two adjacent metal layers in the original ring oscillator, which is not specifically limited in this embodiment. The two ends of the third type of test capacitor structure are respectively arranged on the first metal wire and the second metal wire; the facing area between the first metal wire and the second metal wire in the third type of test capacitor structure is adjusted to generate multiple third type test capacitor structures. For the third type of test capacitor structure, a parasitic capacitor will be formed between the first metal wire and the second metal wire, and the size of the parasitic capacitor is adjusted by adjusting the facing area between the first metal wire and the second metal wire. For the third type of test capacitor structure, in order to characterize the parasitic capacitance of the back-end connection, multiple third type test capacitor structures are constructed with different facing areas between the first metal wire and the second metal wire. By testing multiple third type test capacitor structures, the capacitance value of each third type test capacitor structure is obtained.

[0043] For the test capacitor structure of the front-end junction capacitor, multiple fourth-type test capacitor structures based on the front-end junction capacitor are constructed; the structural design parameters of the fourth-type test capacitor structure include the area of ​​the doped active region in the front-end junction capacitor structure. Specifically, Figure 7 As shown, the fourth type of test capacitor structure includes a first substrate, a second doped active area, a contact hole Contact and a metal line Metal, in order to characterize the influence of Cj capacitance. In this embodiment, the first substrate is a P-type substrate PW pickup area, and the second doped active area is an N-type doped active area N+ area; in other embodiments, the first substrate and the second doped active area can also be N-type substrate NW pickup and P-type doped active area P+, respectively. This application does not make specific restrictions. Generally, the design of the first substrate and the second doped active area matches the structure of the original ring oscillator. The first substrate and the second doped active area form a PN junction, a contact hole is set on the second doped active area, and the contact hole is connected to the metal line. The two ends of the fourth type of test capacitor structure are respectively set on the first substrate and the metal line; the area of ​​the second doped active area in the fourth type of test capacitor structure is adjusted to generate multiple fourth type test capacitor structures. For the fourth type of test capacitor structure, a parasitic capacitor will be formed between the first substrate and the second doped active area, and the size of the parasitic capacitor is adjusted by adjusting the area of ​​the second doped active area. For the fourth type of test capacitor structure, multiple fourth type test capacitor structures are constructed with different areas of the second doped active region. The capacitance value of each fourth type test capacitor structure is obtained by testing the multiple fourth type test capacitor structures.

[0044] When determining the capacitance value of each test capacitor structure, the corresponding test capacitor structure may be input into the simulation software through the simulation software, and the capacitance value of the corresponding test capacitor structure may be output.

[0045] Step 302 : constructing a plurality of test ring oscillators based on a plurality of test capacitor structures of a plurality of types, respectively.

[0046] In the above steps, a plurality of first-type test capacitor structures, a plurality of second-type test capacitor structures, a plurality of third-type test capacitor structures, and a plurality of fourth-type test capacitor structures are obtained. According to each test capacitor structure of each type, a corresponding test ring oscillator is constructed respectively, which specifically includes the following steps: Step 1: Connect the same test capacitor structure between each inter-stage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure. The structure of the original ring oscillator is not changed, and the test ring oscillator formed by connecting an additional external capacitor is simple and reliable.

[0047] For example, each type includes 4 corresponding test capacitor structures. Figure 4The figure shows four first-class test capacitor structures from left to right: DOE1-DOE4; Figure 5 The figure shows four second-type test capacitor structures from left to right: DOE5-DOE8; Figure 6 The figure shows four third-type test capacitor structures from left to right: DOE9-DOE12; Figure 7 The figure shows four fourth-category test capacitor structures from left to right: DOE13-DOE16. Figure 8 As shown, the original ring oscillator ring is composed of 5 inverters connected end to end. The first interstage node is between the first inverter and the second inverter, the second interstage node is between the second inverter and the third inverter, the third interstage node is between the third inverter and the fourth inverter, the fourth interstage node is between the fourth inverter and the fifth inverter, and the fifth interstage node is between the fifth inverter and the first inverter. DOE1 can be connected to the 5 interstage nodes respectively. Figure 8 The capacitor structure indicated by the dotted box is the equivalent capacitor that characterizes DOE1, forming a test ring oscillator corresponding to the first type of test capacitor structure; DOE12 can be connected to 5 inter-stage nodes respectively to form a test ring oscillator corresponding to the third type of test capacitor structure; the test ring oscillators corresponding to the remaining test capacitor structures are constructed in the same way, and will not be repeated in this application.

[0048] When the test capacitor structure is connected to the ring oscillator, the two ends of the test capacitor structure are connected to the interstage node, and the ground wire or the power line. That is, one end of the test capacitor structure is connected to the interstage node, and the other end is grounded or connected to the power supply. For the third type of test capacitor structure, grounding or connecting to the power supply will form different voltage directions, but the third type of test capacitor structure does not need to consider the directionality of the voltage, so it can be grounded or connected to the power supply. For the first type of test capacitor structure, the second type of test capacitor structure and the fourth type of test capacitor structure, grounding or connecting to the power supply will form different voltage directions, and the connection method of the corresponding structure in the original ring oscillator is the same. If the corresponding structure in the original ring oscillator is grounded, the corresponding test capacitor structure is grounded, and if the corresponding structure in the original ring oscillator is connected to the power supply, the corresponding test capacitor structure is connected to the power supply.

[0049] Step 2: construct multiple test ring oscillators accordingly by adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator.

[0050] For each type of test capacitor structure, and multiple test capacitor structures corresponding to each type, the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator ring can be adjusted to construct multiple test ring oscillators accordingly. For example, first, DOE1 of the first type of test capacitor structure is respectively connected to the original ring oscillator to construct the corresponding test ring oscillator; by adjusting the gate length of the channel in the front-end CMOS structure, DOE2 is respectively connected to the original ring oscillator to construct the corresponding test ring oscillator; then DOE3 and DOE4 are respectively connected to the original ring oscillator in sequence to construct the corresponding test ring oscillator. By adjusting the type of the test capacitor structure, DOE5 of the second type of test capacitor structure is respectively connected to the original ring oscillator to construct the corresponding test ring oscillator; by adjusting the number of contact holes in the middle capacitor structure, DOE6 is respectively connected to the original ring oscillator to construct the corresponding test ring oscillator; then DOE7 and DOE8 are respectively connected to the original ring oscillator in sequence to construct the corresponding test ring oscillator. By adjusting the type of the test capacitor structure, DOE9 of the third type of test capacitor structure is connected to the original ring oscillator to construct the corresponding test ring oscillator; by adjusting the facing area between the metal wires in the back-end capacitor structure, DOE10 is connected to the original ring oscillator to construct the corresponding test ring oscillator; then DOE11 and DOE12 are connected to the original ring oscillator in turn to construct the corresponding test ring oscillator. By adjusting the type of the test capacitor structure, DOE13 of the fourth type of test capacitor structure is connected to the original ring oscillator to construct the corresponding test ring oscillator; by adjusting the area of ​​the doped active region in the front-end junction capacitor structure, DOE14 is connected to the original ring oscillator to construct the corresponding test ring oscillator; then DOE15 and DOE16 are connected to the original ring oscillator in turn to construct the corresponding test ring oscillator. A total of 16 test ring oscillators were constructed, including: 4 test ring oscillators corresponding to the first type of test capacitor structure; 4 test ring oscillators corresponding to the second type of test capacitor structure; 4 test ring oscillators corresponding to the third type of test capacitor structure; and 4 test ring oscillators corresponding to the fourth type of test capacitor structure.

[0051] Step 303: Obtain the delay of each test capacitor structure according to the delay of the test ring oscillator.

[0052] After obtaining multiple test ring oscillators, the output frequency of each test ring oscillator is detected, and the delay of each test ring oscillator is determined according to the output frequency of each test ring oscillator, and the delay of each test capacitor structure is determined according to the delay of each test ring oscillator. For example, the output frequency of the test ring oscillator is detected to obtain the output frequency f. According to the formula f=1 / 2T, the delay T of the test ring oscillator is determined. According to the formula t=T / n, the delay t of each test capacitor structure is determined, where n is the number of test capacitor structures connected to the test ring oscillator.

[0053] Step 304 : constructing a delay relationship for each type of test capacitor structure based on the delays, capacitance values ​​and / or structural design parameters corresponding to the multiple test capacitor structures for each type.

[0054] The delay relationship can be a mapping relationship between the delay corresponding to the test capacitor structure and the capacitance value; it can also be a mapping relationship between the delay corresponding to the test capacitor structure and the structural design parameters; it can also be a mapping relationship between the capacitance value corresponding to the test capacitor structure and the structural design parameters; it can also be a mapping relationship between the delay, capacitance value and structural design parameters corresponding to the test capacitor structure. For example, a total of 16 test ring oscillators are constructed, including: 4 test ring oscillators corresponding to the first type of test capacitor structure; 4 test ring oscillators corresponding to the second type of test capacitor structure; 4 test ring oscillators corresponding to the third type of test capacitor structure; 4 test ring oscillators corresponding to the fourth type of test capacitor structure. According to the delay, capacitance value and structural design parameters corresponding to the four first-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the first-category test capacitor structure; according to the delay, capacitance value and structural design parameters corresponding to the four second-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the second-category test capacitor structure; according to the delay, capacitance value and structural design parameters corresponding to the four third-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the third-category test capacitor structure; according to the delay, capacitance value and structural design parameters corresponding to the four fourth-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the fourth-category test capacitor structure.

[0055] In the above embodiment, multiple test capacitor structures of multiple types are connected to the original ring oscillator to construct multiple test ring oscillators, and then each test ring oscillator is tested to determine the delay of each test capacitor structure, and finally the delay relationship of each type of test capacitor structure is obtained. Based on the delay relationship, the performance of the ring oscillator can be evaluated more accurately, thereby improving the performance of the ring oscillator.

[0056] In one embodiment, if Fig. 9As shown, a first layout delay optimization method is provided, comprising the following steps: Step 801: Calculate a delay difference based on the delay of the original ring oscillator and the target delay requirement.

[0057] When optimizing the first layout, you first need to determine the delay of the original ring oscillator. The method for determining the delay of the original ring oscillator is the same as that for determining the delay of the test ring oscillator. This will not be described in detail here. For details, please refer to the above method for determining the delay of the test ring oscillator. You also need to determine the optimization target, that is, the target delay requirement. Subtract the delay of the original ring oscillator from the target delay requirement to obtain the delay difference.

[0058] Step 802: Determine at least one target delay relationship according to at least one layout optimization type.

[0059] The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor. The delay relationship includes: the delay relationship corresponding to the capacitor structure of the front-end CMOS, the delay relationship corresponding to the capacitor structure of the middle-end capacitor, the delay relationship corresponding to the capacitor structure of the back-end capacitor, and the delay relationship corresponding to the capacitor structure of the front-end junction capacitor. By any one of the graph optimization types, the purpose of reducing delay can be achieved. Therefore, when actually optimizing, any one or more layout optimization types can be selected according to actual needs, and the corresponding delay relationship can be determined to obtain the target delay relationship.

[0060] Step 803 , based on the target delay relationship and the delay difference, optimize the structure of the original ring oscillator to obtain the layout of the optimized ring oscillator.

[0061] If the target delay relationship is the delay relationship corresponding to the capacitor structure of the front-end CMOS, the gate length of the channel in the front-end CMOS structure is determined according to the delay of the original ring oscillator, and then the target delay relationship is found according to the gate length of the channel in the front-end CMOS structure and the delay difference, and the gate length of the channel in the front-end CMOS structure is optimized to obtain the layout of the optimized ring oscillator.

[0062] If the target delay relationship is the delay relationship corresponding to the capacitance structure of the middle capacitor, the number of contact holes in the middle capacitor structure is determined according to the delay of the original ring oscillator, and then the target delay relationship is found according to the number of contact holes in the middle capacitor structure and the delay difference, and the number of contact holes in the middle capacitor structure is optimized to obtain the layout of the optimized ring oscillator.

[0063] If the target delay relationship is the facing area between metal wires in the back-end capacitor structure, the facing area between metal wires in the back-end capacitor structure is determined according to the delay of the original ring oscillator, and then the target delay relationship is found according to the facing area between metal wires in the back-end capacitor structure and the delay difference, and the facing area between metal wires in the back-end capacitor structure is optimized to obtain the layout of the optimized ring oscillator.

[0064] If the target delay relationship is the area of ​​the doped active area in the front-stage junction capacitor structure, the area of ​​the doped active area in the front-stage junction capacitor structure is determined according to the delay of the original ring oscillator, and then the target delay relationship is found according to the area of ​​the doped active area in the front-stage junction capacitor structure and the delay difference, and the area of ​​the doped active area in the front-stage junction capacitor structure is optimized to obtain the layout of the optimized ring oscillator.

[0065] The target delay relationship includes a data relationship between a delay and a capacitance value based on the test capacitor structure, and a data relationship between a capacitance value and a structural design parameter based on the test capacitor structure. Alternatively, the target delay relationship includes a data relationship between a delay and a structural design parameter based on the test capacitor structure.

[0066] The delay difference is determined by determining the target delay requirement for the first layout, and then the target delay relationship is determined according to at least one layout optimization type; thus, the original ring oscillator is optimized according to the target delay relationship and the delay difference to obtain the layout of the optimized ring oscillator, thereby improving the performance of the ring oscillator.

[0067] In one embodiment, if Fig.10 As shown, a second layout delay evaluation method is provided, comprising the following steps: Step 901: Determine at least one target delay relationship according to at least one layout optimization type.

[0068] The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor. The delay relationship includes: the delay relationship corresponding to the capacitor structure of the front-end CMOS, the delay relationship corresponding to the capacitor structure of the middle-end capacitor, the delay relationship corresponding to the capacitor structure of the back-end capacitor, and the delay relationship corresponding to the capacitor structure of the front-end junction capacitor. By any one of the graph optimization types, the purpose of reducing delay can be achieved. Therefore, when actually performing delay evaluation, select any one or more layout optimization types, and determine the corresponding delay relationship to obtain the target delay relationship.

[0069] Step 902 : determining at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator based on the first layout and the second layout.

[0070] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the gate length of the channel in the front-end CMOS structure, then the gate length of the channel in the front-end CMOS structure corresponding to the first layout and the gate length of the channel in the front-end CMOS structure corresponding to the second layout are determined.

[0071] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the number of contact holes in the mid-segment capacitor structure, then the number of contact holes in the mid-segment capacitor structure corresponding to the first layout and the number of contact holes in the mid-segment capacitor structure corresponding to the second layout are determined.

[0072] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the facing area between metal wires in the back-end capacitor structure, then the facing area between metal wires in the back-end capacitor structure corresponding to the first layout and the facing area between metal wires in the back-end capacitor structure corresponding to the second layout are determined.

[0073] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the area of ​​the doped active region in the front-stage junction capacitor structure, then the area of ​​the doped active region in the front-stage junction capacitor structure corresponding to the first layout and the area of ​​the doped active region in the front-stage junction capacitor structure corresponding to the second layout are determined.

[0074] Step 903 , based on the target delay relationship and the structural design parameter difference, the delay of the optimized ring oscillator is evaluated to complete the delay evaluation of the second layout.

[0075] If the structural design parameter is the gate length of the channel in the front-end CMOS structure, the target delay relationship is the delay relationship corresponding to the capacitor structure of the front-end CMOS. The target delay relationship is found according to the gate length of the channel in the front-end CMOS structure corresponding to the first layout, and the delay corresponding to the first layout is determined; the target delay relationship is found according to the gate length of the channel in the front-end CMOS structure corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0076] The channel of the MOS structure Gate itself in the first type of test capacitor structure will form a parasitic capacitor. According to the gate length of the channel in the front-end CMOS structure in multiple first type test capacitor structures, the unit capacitance introduced by the unit gate length is determined. According to the gate length and unit capacitance of the channel in the front-end CMOS structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined, and the target delay relationship is found according to the capacitance value corresponding to the first layout, and the delay corresponding to the first layout is determined; according to the gate length and unit capacitance of the channel in the front-end CMOS structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined, and the target delay relationship is found according to the capacitance value corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0077] If the structural design parameter is the number of contact holes in the mid-section capacitor structure, the target delay relationship is the delay relationship corresponding to the capacitor structure of the mid-section capacitor. The target delay relationship is searched according to the number of contact holes in the mid-section capacitor structure corresponding to the first layout to determine the delay corresponding to the first layout; the target delay relationship is searched according to the number of contact holes in the mid-section capacitor structure corresponding to the second layout to determine the delay corresponding to the second layout.

[0078] In the second type of test capacitor structure, a parasitic capacitor is formed between the gate Gate and the contact hole Contact. According to the number of contact holes in the multiple second type test capacitor structures, the unit capacitance introduced by each contact hole is determined. According to the number of contact holes and unit capacitance in the middle capacitor structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined, and the target delay relationship is searched according to the capacitance value corresponding to the first layout to determine the delay corresponding to the first layout; according to the number of contact holes and unit capacitance in the middle capacitor structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined, and the target delay relationship is searched according to the capacitance value corresponding to the second layout to determine the delay corresponding to the second layout.

[0079] If the structural design parameter is a test capacitor structure of a back-end capacitor, the target delay relationship is the delay relationship corresponding to the capacitor structure of the back-end capacitor. The target delay relationship is searched based on the facing area between metal wires in the back-end capacitor structure corresponding to the first layout, and the delay corresponding to the first layout is determined; the target delay relationship is searched based on the facing area between metal wires in the back-end capacitor structure corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0080] In the third type of test capacitor structure, parasitic capacitance is formed between the first metal wire and the second metal wire. According to the facing area between the metal wires in the back-end capacitor structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined, and the target delay relationship is searched according to the capacitance value corresponding to the first layout to determine the delay corresponding to the first layout; according to the facing area between the metal wires in the back-end capacitor structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined, and the target delay relationship is searched according to the capacitance value corresponding to the second layout to determine the delay corresponding to the second layout.

[0081] If the structural design parameter is the area of ​​the doped active region in the front-stage junction capacitor structure, the target delay relationship is the delay relationship corresponding to the capacitor structure of the front-stage junction capacitor. The target delay relationship is searched according to the area of ​​the doped active region in the front-stage junction capacitor structure corresponding to the first layout, and the delay corresponding to the first layout is determined; the target delay relationship is searched according to the area of ​​the doped active region in the front-stage junction capacitor structure corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0082] The PN junction between the first substrate and the second doped active region in the fourth type of test capacitor structure will form a parasitic capacitor. According to the area of ​​the doped active region in multiple fourth type test capacitor structures, the unit capacitance introduced by the unit area of ​​the doped active region is determined. According to the area and unit capacitance of the doped active region in the front-end junction capacitor structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined, and the target delay relationship is searched according to the capacitance value corresponding to the first layout to determine the delay corresponding to the first layout; according to the area and unit capacitance of the doped active region in the front-end junction capacitor structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined, and the target delay relationship is searched according to the capacitance value corresponding to the second layout to determine the delay corresponding to the second layout.

[0083] After determining the delay corresponding to the first layout and the delay corresponding to the second layout, the delay of the optimized ring oscillator is evaluated, thereby completing the delay evaluation of the second layout. If the delay corresponding to the second layout is less than the delay corresponding to the first layout, the performance of the optimized ring oscillator is better than the performance of the original ring oscillator.

[0084] In one of the specific embodiments, a layout optimization evaluation method for a ring oscillator is provided. By disassembling the front-end CMOS structure Cch, the middle-end capacitor structure Cco, the back-end capacitor structure Cbeol and the front-end junction capacitor structure Cj in the ring oscillator, the influence of each capacitor structure on the RO performance of the ring oscillator is analyzed, providing guidance for process optimization and design optimization.

[0085] The first type of test capacitor structure is Cch external capacitor. Cch external capacitors of different sizes are added between the stages of the original ring oscillator to obtain the effect of Cch external capacitor on delay. Figure 4 As shown, for the Cch external capacitor, different Cch external capacitor values ​​are designed by changing the gate length of the channel. The same Cch external capacitor is connected to each interstage node of the original ring oscillator, and the structure of the original ring oscillator is not changed. This is achieved by additionally connecting a Cch external capacitor. The two ends of the Cch external capacitor are respectively connected between the interstage node (Node) and the ground line (Vss), or between the interstage node (Node) and the power line (Vdd). When one end is connected to the ground line (Vss) or the power line (Vdd), different voltage directions will be formed. The Cch external capacitor needs to consider the directionality of the voltage, which involves matching with N / P, and is generally designed to match the original ring oscillator structure.

[0086] The second type of test capacitor structure is the Cco external capacitor. Different sizes of Cco external capacitors are added between the stages of the original ring oscillator to obtain the effect of the Cco external capacitor on the delay. Figure 5As shown, for the Cco external capacitor, different Cco external capacitor values ​​are designed by changing the number of contact holes Contact. The same Cco external capacitor is connected to each interstage node of the original ring oscillator; the structure of the original ring oscillator is not changed, and it is realized by additionally connecting the Cco external capacitor. The two ends of the Cco external capacitor are respectively connected between the interstage node (Node) and the ground line (Vss), or between the interstage node (Node) and the power line (Vdd). One end is connected to the ground line (Vss) or the power line (Vdd), which will form different voltage directions. The Cco external capacitor needs to consider the directionality of the voltage, and is generally designed to match the original ring oscillator structure.

[0087] The third type of test capacitor structure is Cbeol external capacitor. Different sizes of Cbeol external capacitors are added between the stages of the original ring oscillator to obtain the effect of Cbeol external capacitor on delay. Figure 6 As shown, for the Cbeol external capacitor, the parasitic capacitance value is increased by increasing the area facing each other between the two metal wires. Any metal layer can be selected to construct the Cbeol external capacitor. The same Cbeol external capacitor is connected to each interstage node of the original ring oscillator; the structure of the original ring oscillator is not changed, and it is realized by additionally connecting the Cbeol external capacitor. The two ends of the Cbeol external capacitor are respectively connected between the interstage node (Node) and the ground line (Vss), or between the interstage node (Node) and the power line (Vdd). One end is connected to the ground line (Vss) or the power line (Vdd), which will form different voltage directions, but the Cbeol external capacitor does not need to consider the directionality of the voltage.

[0088] The fourth type of test capacitor structure is Cj external capacitor. Different sizes of Cj external capacitors are added between the stages of the original ring oscillator to obtain the effect of Cj external capacitor on delay. Figure 7 As shown, for the Cj external capacitor, the same Cj external capacitor is connected to each interstage node of the original ring oscillator; the structure of the original ring oscillator is not changed, and it is realized by additionally connecting the Cj external capacitor. The two ends of the Cj external capacitor are respectively connected between the interstage node (Node) and the ground line (Vss), or between the interstage node (Node) and the power line (Vdd), and one end is connected to the ground line (Vss) or the power line (Vdd), which will form different voltage directions. The Cj external capacitor needs to consider the directionality of the voltage, which involves the matching with N / P, and is generally designed to match the original ring oscillator structure. Its PN junction can be a P-type substrate and an N-type doped active area; it can also be an N-type substrate and a P-type doped active area.

[0089] A total of 16 test capacitor structures are constructed, namely Cbeol1, Cbeol2, Cbeol3, Cbeol4, Cco1, Cco2, Cco3, Cco4, Cch1, Cch2, Cch3, Cch4, Cj1, Cj2, Cj3 and Cj4. First, the capacitance values ​​of the 16 test capacitor structures are tested. The 16 test capacitor structures are connected to the original ring oscillator separately, and the frequencies f of the 16 ring oscillators are determined in turn. According to f=1 / 2tn, the delay time corresponding to the test capacitor structure is determined. Among them, t is the delay time, and n is the number of stages of the ring oscillator. According to the capacitance values ​​and delay times corresponding to Cbeol1, Cbeol2, Cbeol3, and Cbeol4, the delay relationship corresponding to the capacitance structure of the rear capacitor is constructed. According to the capacitance values ​​and delay times corresponding to Cco1, Cco2, Cco3, and Cco4, the delay relationship corresponding to the capacitance structure of the middle capacitor is constructed. According to the capacitance values ​​and delay times corresponding to Cch1, Cch2, Cch3, and Cch4, the delay relationship corresponding to the capacitance structure of the front-end CMOS is constructed. According to the capacitance values ​​and delay times corresponding to Cj1, Cj2, Cj3, and Cj4, the delay relationship corresponding to the capacitance structure of the front-end junction capacitance is constructed.

[0090] For example, the delay relationship corresponding to various types of test capacitor structures is constructed, including the data relationship between the delay and capacitance value of the test capacitor structure, and the fitting line of the correlation between the delay time of each type of test capacitor structure and each part of the capacitance is made respectively. The fitting line reflects the influence of each part of the capacitance on the delay. When fitting, all units are normalized to ps / fF. For details, please refer to Fig.13 The four groups of delay relationships shown can be used as a reference when performing subsequent delay optimization or delay evaluation of the ring oscillator. Similarly, other delay relationships can also be constructed, and this application does not make specific limitations.

[0091] When evaluating optimization options for the optimized ring oscillator: As for the Cbeol external capacitor, its influence on the ring oscillator mainly comes from the parasitic capacitance of the back-end connection. After optimizing the original ring oscillator by modifying the layout, the optimized ring oscillator is obtained. Through the simulation tool software, the capacitance value Cbeol0 of each inverter in the original ring oscillator and the capacitance value Cbeolx of each inverter in the optimized ring oscillator are determined. According to Cbeol0 and Cbeolx, the delay relationship corresponding to the capacitance structure of the back-end capacitor is found, and the delay of the ring oscillator before and after optimization is determined, so as to evaluate the optimization scheme.

[0092] For the Cco external capacitor, its influence on the ring oscillator mainly comes from the parasitic capacitance between the contact hole Contact and the gate Gate. When the original ring oscillator is optimized by modifying the layout, the number of contact holes Contact in the ring oscillator layout can be adjusted, or the distance between the contact hole Contact and the gate Gate can be adjusted to obtain the optimized ring oscillator. The capacitance Cco0 introduced by each contact hole Contact is calculated according to Cco1, Cco2, Cco3, and Cco4. According to the number of contact holes Contact n and the capacitance Cco0 in the original ring oscillator, the capacitance value C1 of each inverter in the original ring oscillator is obtained by n×Cco0. According to the number of contact holes Contact n+Δn in the optimized ring oscillator and the distance d+Δd between the contact hole Contact and the gate Gate, the capacitance value C2 of each inverter in the optimized ring oscillator is obtained by Cco0×n×[d / (d+Δd)]×[(n+Δn) / n]. The delay relationship corresponding to the capacitance structure of the middle capacitor is found based on C1 and C2, and the delay of the ring oscillator before and after optimization is determined, so as to evaluate the optimization scheme.

[0093] For the Cch external capacitor, its impact on the ring oscillator mainly comes from the channel capacitance of the MOS structure gate itself. When the original ring oscillator is optimized by modifying the layout, the overlapping area of ​​the gate Gate and AA in the ring oscillator layout can be adjusted to obtain the optimized ring oscillator. The capacitance Cch0 introduced by the overlapping area of ​​the unit gate Gate and AA is calculated according to Cch1, Cch2, Cch3, and Cch4. According to the overlapping area s of the gate Gate and AA in the original ring oscillator and the capacitance Cch0, the capacitance value C3 of each inverter in the original ring oscillator is obtained by s×Cch0. According to the overlapping area s+Δs of the gate Gate and AA in the optimized ring oscillator, the capacitance value C4 of each inverter in the optimized ring oscillator is obtained by Cch0×s×[(s+Δs) / s]. According to C3 and C4, the delay relationship corresponding to the capacitance structure of the front-end CMOS is found to determine the delay of the ring oscillator before and after optimization, so as to evaluate the optimization scheme.

[0094] For the Cj external capacitor, its influence on the ring oscillator mainly comes from the junction capacitance of N+ / PW or P+ / NW. When the original ring oscillator is optimized by modifying the layout, the area of ​​N+ or P+ in the ring oscillator layout can be adjusted to obtain the optimized ring oscillator. The capacitance Cj0 introduced by the unit area of ​​N+ or P+ is calculated according to Cj1, Cj2, Cj3, and Cj4. According to the area z of N+ or P+ in the original ring oscillator and the capacitance Cj0, the capacitance value C5 of each inverter in the original ring oscillator is obtained by z×Cj0. According to the area z+Δz of N+ or P+ in the optimized ring oscillator, the capacitance value C6 of each inverter in the optimized ring oscillator is obtained by Cj0×z×[(z+Δz) / z]. According to C5 and C6, the delay relationship corresponding to the capacitance structure of the front-end junction capacitance is found to determine the delay of the ring oscillator before and after optimization, so as to evaluate the optimization scheme.

[0095] The above method is applicable to various types of ring oscillators. In addition to being applicable to ring oscillators composed of inverters, it is also applicable to ring oscillators composed of other logic gates. Each type of test capacitor structure mentioned above is illustrated by taking 4 as an example. It can be understood that more test capacitor structures can be constructed according to actual use requirements. The more test capacitor structures of each type, the more accurate the delay relationship is. For the four types of test capacitor structures, the four types of test capacitor structures can also be combined to determine the delay relationship corresponding to the combination.

[0096] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0097] Based on the same inventive concept, the embodiment of the present application also provides a performance test structure of a ring oscillator, which is used to implement the layout optimization evaluation method of the ring oscillator involved above. The implementation scheme for solving the problem provided by the performance test structure of the ring oscillator is similar to the implementation scheme recorded in the above method, so the specific limitations in the performance test structure embodiments of one or more ring oscillators provided below can refer to the limitations of the layout optimization evaluation method of the ring oscillator above, and will not be repeated here.

[0098] In one embodiment, a performance test structure of a ring oscillator is provided, including multiple types of test capacitor structures; the test capacitor structure is designed based on a partial structure of the original ring oscillator, and the partial structure includes at least one of a front-end CMOS structure, a middle-end capacitor structure, a back-end capacitor structure, and a front-end junction capacitor structure.

[0099] In one embodiment, if Figure 4 As shown, a first type of test capacitor structure based on a front-end CMOS capacitor; the structural design parameters of the first type of test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically, the first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the first type of test capacitor structure are respectively set on the gate and the metal line; different first type of test capacitor structures have different channel gate lengths.

[0100] In one embodiment, if Figure 5 As shown, a second type of test capacitor structure based on a mid-section capacitor; the structural design parameters of the second type of test capacitor structure include the number of contact holes in the mid-section capacitor structure; specifically including: the second type of test capacitor structure includes an active area, a gate, a contact hole and a metal wire; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the second type of test capacitor structure are respectively set on the gate and the metal wire; different second type of test capacitor structures have different numbers of contact holes.

[0101] In one embodiment, if Figure 6 As shown, a third type of test capacitor structure of a back-end capacitor; the structural design parameters of the third type of test capacitor structure include the facing area between metal wires in the back-end capacitor structure; specifically including: the third type of test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the two ends of the third type of test capacitor structure are respectively arranged on the first metal wire and the second metal wire; different third type test capacitor structures have different facing areas between the first metal wire and the second metal wire.

[0102] In one embodiment, if Figure 7As shown, a fourth type of test capacitor structure based on the front-end junction capacitor; the structural design parameters of the fourth type of test capacitor structure include the area of ​​the doped active area in the front-end junction capacitor structure; specifically including: the fourth type of test capacitor structure includes a first substrate, a second doped active area, a contact hole and a metal wire; the first substrate and the second doped active area form a PN junction, a contact hole is set on the second doped active area, and the contact hole is connected to the metal wire for connection; wherein, the first substrate and the second doped active area are a P-type substrate and an N-type doped active area, or an N-type substrate and a P-type doped active area; and the design of the first substrate and the second doped active area matches the structure of the original ring oscillator; the two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal wire; different fourth type test capacitor structures have different second doped active area areas.

[0103] In one embodiment, at least one test ring oscillator is included; between each interstage node of the original ring oscillator, the same test capacitor structure is respectively connected to form a test ring oscillator corresponding to the test capacitor structure; different test ring oscillators have different types and / or structural design parameters of the test capacitor structure connected in the original ring oscillator; wherein, between each interstage node of the original ring oscillator, the same test capacitor structure is respectively connected, including: connecting two ends of the test capacitor structure to the interstage node and a ground line or a power line respectively.

[0104] In one embodiment, the performance test structure of the ring oscillator is used in the layout optimization evaluation method of the ring oscillator described in any of the above embodiments.

[0105] Based on the same inventive concept, the embodiment of the present application also provides a layout optimization and evaluation device for a ring oscillator for implementing the layout optimization and evaluation method for a ring oscillator involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the layout optimization and evaluation device for one or more ring oscillators provided below can refer to the limitations of the layout optimization and evaluation method for a ring oscillator above, and will not be repeated here.

[0106] In one embodiment, Fig.11 As shown, a layout optimization and evaluation device for a ring oscillator is provided, comprising: a first acquisition module 100, a construction module 200, a second acquisition module 300 and an optimization module 400, wherein: A first acquisition module 100 is used to acquire a first layout; A construction module 200 is used to construct delay relationships corresponding to various types of test capacitor structures; the delay relationships include data relationships based on delay, capacitance value and / or structural design parameters of the test capacitor structure; The second acquisition module 300 is used to acquire the layout optimization type; The optimization module 400 is used to perform delay optimization on the first layout and / or delay evaluation on the second layout based on the delay relationship corresponding to the layout optimization type; wherein the first layout is the layout of the original ring oscillator; and the second layout is the layout of the optimized ring oscillator.

[0107] The construction module 200 is also used to construct multiple types of multiple test capacitor structures based on the original ring oscillator, and determine the capacitance value of each of the test capacitor structures; based on the multiple types of multiple test capacitor structures, respectively construct multiple test ring oscillators; according to the delay of the test ring oscillator, obtain the delay of each of the test capacitor structures; based on the delay, capacitance value and / or structural design parameters corresponding to each type of the multiple test capacitor structures, construct the delay relationship of each type of the test capacitor structure.

[0108] The construction module 200 is also used to construct multiple first-class test capacitor structures based on the front-end CMOS capacitor; the structural design parameters of the first-class test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically including: the first-class test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set in the source area and the drain area at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the first-class test capacitor structure are respectively set on the gate and the metal line; the gate length of the channel in the first-class test capacitor structure is adjusted to generate multiple first-class test capacitor structures.

[0109] The construction module 200 is also used to construct multiple second-type test capacitor structures based on the mid-section capacitor; the structural design parameters of the second-type test capacitor structure include the number of contact holes in the mid-section capacitor structure; specifically including: the second-type test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the second-type test capacitor structure are respectively set on the gate and the metal line; the number of contact holes in the second-type test capacitor structure is adjusted to generate multiple second-type test capacitor structures.

[0110] The construction module 200 is also used to construct multiple third-type test capacitor structures of the back-end capacitor; the structural design parameters of the third-type test capacitor structure include the facing area between the metal wires in the back-end capacitor structure; specifically including: the third-type test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the two ends of the third-type test capacitor structure are respectively arranged on the first metal wire and the second metal wire; the facing area between the first metal wire and the second metal wire in the third-type test capacitor structure is adjusted to generate multiple third-type test capacitor structures.

[0111] The construction module 200 is also used to construct multiple fourth-type test capacitor structures based on the front-stage junction capacitor; the structural design parameters of the fourth-type test capacitor structure include the area of ​​the doped active area in the front-stage junction capacitor structure; specifically including: the fourth-type test capacitor structure includes a first substrate, a second doped active area, a contact hole and a metal wire; the first substrate and the second doped active area form a PN junction, a contact hole is set on the second doped active area, and the contact hole is connected to the metal wire; wherein the first substrate and the second doped active area are a P-type substrate and an N-type doped active area, or an N-type substrate and a P-type doped active area; and the design of the first substrate and the second doped active area matches the structure of the original ring oscillator; the two ends of the fourth-type test capacitor structure are respectively set on the first substrate and the metal wire; the area of ​​the second doped active area in the fourth-type test capacitor structure is adjusted to generate multiple fourth-type test capacitor structures.

[0112] The construction module 200 is further used to connect the same test capacitor structure between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; and to construct a plurality of test ring oscillators by adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator. The method of connecting the same test capacitor structure between each interstage node of the original ring oscillator includes: connecting two ends of the test capacitor structure to the interstage node and a ground line or a power line.

[0113] The optimization module 400 is further used to calculate the delay difference based on the delay of the original ring oscillator and the target delay requirement; determine at least one target delay relationship according to at least one of the layout optimization types; optimize the structure of the original ring oscillator based on the target delay relationship and the delay difference to obtain the layout of the optimized ring oscillator; wherein the target delay relationship includes a data relationship between the delay and the capacitance value based on the test capacitor structure, a data relationship between the capacitance value and the structural design parameters based on the test capacitor structure, and / or a data relationship between the delay and the structural design parameters based on the test capacitor structure.

[0114] The optimization module 400 is further used to determine at least one target delay relationship according to at least one of the layout optimization types; determine at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator based on the first layout and the second layout; evaluate the delay of the optimized ring oscillator based on the target delay relationship and the structural design parameter difference to complete the delay evaluation of the second layout; wherein the target delay relationship includes a data relationship between the delay and the capacitance value based on the test capacitor structure, a data relationship between the capacitance value and the structural design parameters based on the test capacitor structure, and / or a data relationship between the delay and the structural design parameters based on the test capacitor structure.

[0115] Each module in the above-mentioned layout optimization and evaluation device for the ring oscillator can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0116] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.12 As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a layout optimization evaluation method for a ring oscillator is implemented.

[0117] Those skilled in the art will understand that Fig.12The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0118] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, any one of the layout optimization evaluation methods for a ring oscillator in the above embodiments is implemented.

[0119] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any one of the layout optimization and evaluation methods for a ring oscillator in the above embodiments is implemented.

[0120] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0121] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A layout optimization evaluation method for a ring oscillator, characterized in that: The method comprises: Get the first version; Constructing delay relationships corresponding to various types of test capacitor structures; the delay relationships include data relationships based on delay, capacitance value and / or structural design parameters of the test capacitor structure; Get layout optimization type; Based on the delay relationship corresponding to the layout optimization type, performing delay optimization on the first layout, and / or performing delay evaluation on the second layout; The first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator.

2. The method according to claim 1, characterized in that: The delay relationships corresponding to constructing various types of test capacitor structures include: Based on the original ring oscillator, construct multiple types of multiple test capacitor structures, and determine the capacitance value of each of the test capacitor structures; Based on the multiple types of multiple test capacitor structures, construct multiple test ring oscillators respectively; Obtaining the delay of each of the test capacitor structures according to the delay of the test ring oscillator; Based on the delays, capacitance values ​​and / or structural design parameters corresponding to the multiple test capacitor structures of each type, a delay relationship of each type of the test capacitor structure is constructed.

3. The method according to claim 2, characterized in that The method comprises constructing a plurality of test capacitor structures of various types based on the original ring oscillator, including constructing a plurality of first-type test capacitor structures based on the front-end CMOS capacitors; the structural design parameters of the first-type test capacitor structures include the gate length of the channel in the front-end CMOS structure; The first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line for connection; The two ends of the first type of test capacitor structure are respectively arranged on the gate and the metal line; The gate length of the channel in the first-type test capacitor structure is adjusted to generate a plurality of the first-type test capacitor structures.

4. The method according to claim 2, characterized in that: The method comprises constructing a plurality of test capacitor structures of various types based on the original ring oscillator, including constructing a plurality of second-type test capacitor structures based on the mid-segment capacitor; the structural design parameters of the second-type test capacitor structures include the number of contact holes in the mid-segment capacitor structure; The second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line for connection; The two ends of the second type of test capacitor structure are respectively arranged on the gate and the metal line; The number of contact holes in the second-type test capacitor structure is adjusted to generate a plurality of the second-type test capacitor structures.

5. The method according to claim 2, characterized in that: Based on the original ring oscillator, multiple types of multiple test capacitor structures are constructed, including multiple third-type test capacitor structures for constructing back-end capacitors; the structural design parameters of the third-type test capacitor structures include the facing area between metal wires in the back-end capacitor structure; The third type of test capacitor structure includes a first metal line and a second metal line; The first metal wire and the second metal wire are two metal wires of one metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; Two ends of the third type test capacitor structure are respectively arranged on the first metal wire and the second metal wire; The facing area between the first metal line and the second metal line in the third type test capacitor structure is adjusted to generate a plurality of the third type test capacitor structures.

6. The method according to claim 2, characterized in that The method comprises constructing a plurality of test capacitor structures of various types based on the original ring oscillator, including constructing a plurality of fourth-type test capacitor structures based on the front-end junction capacitor; the structural design parameters of the fourth-type test capacitor structure include the area of ​​the doped active region in the front-end junction capacitor structure; The fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal line; the first substrate and the second doped active region form a PN junction, a contact hole is provided on the second doped active region, and the contact hole is connected to the metal line; The first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; Two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal line; The area of ​​the second doped active region in the fourth type test capacitor structure is adjusted to generate a plurality of the fourth type test capacitor structures.

7. The method according to claim 2, characterized in that Based on the multiple types of multiple test capacitor structures, multiple test ring oscillators are constructed respectively, including: Connecting the same test capacitor structure between each inter-stage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; By adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator, a plurality of test ring oscillators are constructed accordingly; The same test capacitor structure is connected between each inter-stage node of the original ring oscillator, including: connecting two ends of the test capacitor structure to the inter-stage node and a ground line or a power line respectively.

8. The method according to claim 1, characterized in that: Based on the delay relationship corresponding to the layout optimization type, delay optimization is performed on the first layout, including: Calculate the delay difference based on the delay of the original ring oscillator and the target delay requirement; Determining at least one target delay relationship according to at least one of the layout optimization types; Based on the target delay relationship and the delay difference, optimizing the structure of the original ring oscillator to obtain the layout of the optimized ring oscillator; Among them, the target delay relationship includes a data relationship between the delay and capacitance value based on the test capacitor structure, a data relationship between the capacitance value and structural design parameters based on the test capacitor structure, and / or a data relationship between the delay and structural design parameters based on the test capacitor structure.

9. The method according to claim 1, characterized in that: Based on the delay relationship corresponding to the layout optimization type, delay evaluation is performed on the second layout, including: Determining at least one target delay relationship according to at least one of the layout optimization types; Based on the first layout and the second layout, determining at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator; Based on the target delay relationship and the difference in structural design parameters, evaluating the delay of the optimized ring oscillator to complete the delay evaluation of the second layout; Among them, the target delay relationship includes a data relationship between the delay and capacitance value based on the test capacitor structure, a data relationship between the capacitance value and structural design parameters based on the test capacitor structure, and / or a data relationship between the delay and structural design parameters based on the test capacitor structure.

10. A performance test structure of a ring oscillator, characterized in that: Comprising multiple types of test capacitor structures; a layout optimization evaluation method for a ring oscillator as claimed in any one of claims 1 to 9; The test capacitor structure is designed based on a partial structure of an original ring oscillator, and the partial structure includes at least one of a front-end CMOS structure, a middle-end capacitor structure, a back-end capacitor structure, and a front-end junction capacitor structure.

11. The performance test structure according to claim 10, characterized in that: It includes a first type of test capacitor structure based on a front-end CMOS capacitor; the structural design parameters of the first type of test capacitor structure include a gate length of a channel in the front-end CMOS structure; The first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line for connection; The two ends of the first type of test capacitor structure are respectively arranged on the gate and the metal line; Different first-type test capacitor structures have different channel gate lengths.

12. The performance test structure according to claim 10, characterized in that: A second type of test capacitor structure based on a mid-segment capacitor is included; the structural design parameters of the second type of test capacitor structure include the number of contact holes in the mid-segment capacitor structure; The second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line for connection; The two ends of the second type of test capacitor structure are respectively arranged on the gate and the metal line; Different second-type test capacitor structures have different numbers of contact holes.

13. The performance test structure according to claim 10, characterized in that: A third type of test capacitor structure including a back-end capacitor; the structural design parameters of the third type of test capacitor structure include the facing area between metal wires in the back-end capacitor structure; The third type of test capacitor structure includes a first metal line and a second metal line; The first metal wire and the second metal wire are two metal wires of one metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; Two ends of the third type test capacitor structure are respectively arranged on the first metal wire and the second metal wire; Different third-type test capacitor structures have different facing areas between the first metal line and the second metal line.

14. The performance test structure according to claim 10, characterized in that: A fourth type of test capacitor structure based on a front-end junction capacitor is included; the structural design parameters of the fourth type of test capacitor structure include the area of ​​the doped active region in the front-end junction capacitor structure; The fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal line; the first substrate and the second doped active region form a PN junction, a contact hole is provided on the second doped active region, and the contact hole is connected to the metal line; The first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; Two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal line; Different fourth-type test capacitor structures have different second doped active region areas.

15. The performance test structure according to claim 10, characterized in that: including at least one test ring oscillator; Connecting the same test capacitor structure between each inter-stage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; Different test ring oscillators have different types and / or structural design parameters of the test capacitor structure connected to the original ring oscillator; The same test capacitor structure is connected between each inter-stage node of the original ring oscillator, including: connecting two ends of the test capacitor structure to the inter-stage node and a ground line or a power line respectively.

16. A layout optimization evaluation device for a ring oscillator, characterized in that: The device comprises: A first acquisition module, used for acquiring a first layout; A construction module, used to construct delay relationships corresponding to various types of test capacitor structures; the delay relationships include data relationships based on delay, capacitance value and / or structural design parameters of the test capacitor structure; The second acquisition module is used to obtain the layout optimization type; An optimization module is used to perform delay optimization on the first layout based on the delay relationship corresponding to the layout optimization type, and / or perform delay evaluation on the second layout; wherein the first layout is the layout of the original ring oscillator; and the second layout is the layout of the optimized ring oscillator.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 9 is implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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