A transistor-level delay optimization method and system based on circuit topology

Abstract

The application discloses a transistor-level delay optimization method and system based on a circuit topology structure, and comprises the following steps: acquiring all units on a timing path to be optimized; performing transistor-level delay optimization on each unit respectively to obtain a timing path after delay optimization; simulating the timing path after delay optimization to obtain a path delay after optimization, and selecting n units with the largest change in timing path delay relative to the original timing path delay as n delay-sensitive units, wherein n is less than or equal to N; and redrawing a layout according to the modification corresponding to the delay optimization for the selected n delay-sensitive units. The application aims to solve the problems that it is difficult to determine the delay-sensitive units on a path and the transistor size that needs to be optimized in a unit during integrated circuit path delay optimization, and realizes transistor-level delay optimization based on a circuit topology structure to quickly and efficiently optimize the path delay.

Description

Technical Field

[0001] The present invention relates to the field of ultra-large-scale integrated circuit timing optimization, and in particular to a transistor-level delay optimization method and system based on circuit topology. Background Art

[0002] With the rapid advancement of integrated circuit technology, circuit design complexity is increasing. Delay optimization at the transistor level has become a crucial task for improving circuit performance. The introduction of standard cells has facilitated circuit design, but there is still significant room for optimizing the delay of specific circuits. Compared to full customization, which consumes significant human resources and time, partial full customization, which only modifies delay-sensitive cells along the path, is more efficient. Research on transistor-level path delay optimization has yielded numerous results, which can be broadly categorized into two types: logic reorganization-based optimization and physical design-based optimization. The former reduces delay by modifying the circuit's logical structure, while the latter optimizes signal propagation paths through layout and routing adjustments. To meet ever-increasing performance demands, designers must effectively optimize transistor-level paths. However, traditional methods for optimizing transistor-level paths often rely on the designer's experience and fail to fully utilize circuit topology information. Summary of the Invention

[0003] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, a transistor-level delay optimization method and system based on circuit topology structure are provided. The present invention aims to solve the problem of difficulty in determining the delay-sensitive units on the path and the transistor sizes that need to be optimized within the units during integrated circuit path delay optimization, and to realize transistor-level delay optimization based on circuit topology structure to quickly and efficiently optimize path delay.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A transistor-level delay optimization method based on circuit topology structure comprises the following steps:

[0006] 1) Obtain all N units on the timing path to be optimized;

[0007] 2) Perform transistor-level delay optimization on each unit to obtain the delay-optimized timing path;

[0008] 3) Simulate the optimized timing path to obtain the optimized path delay, and select n units with the largest delay change relative to the original timing path as n delay-sensitive units, where n is less than or equal to N;

[0009] 4) Redraw the layout for the selected n delay-sensitive units according to the modifications corresponding to the delay optimization.

[0010] Optionally, step 2) includes:

[0011] 2.1) Traverse N cells and obtain a cell as the current cell. If the traversal is successful, jump to step 2.2). Otherwise, it is determined that the delay-optimized timing path has been obtained and jump to step 3).

[0012] 2.2) Find and calculate the number of gates contained in each transistor in the current cell, the number of fins contained in each gate, nfin, and the total number of fins, all_fin_num;

[0013] 2.3) Based on the number of gates per transistor in the current cell (gate_num), the number of fins per gate (nfin), and the total number of fins (all_fin_num), modify the number of gates in the transistors in the current cell based on the cell type and circuit structure to achieve transistor-level delay optimization, and then jump to step 2.1).

[0014] Optionally, step 2.2) includes:

[0015] 2.2.1) Read the row content cell_line from the standard cell netlist of the current cell. If the read is successful, jump to step 2.2.2). Otherwise, jump to step 2.2.3);

[0016] 2.2.2) If the five elements of the cell_line read in the row content (input, output, source or drain, N or P type, and number of fins) match the transistor to be searched, then the number of fins read in the cell_line row content is the number of fins per gate (nfin); jump to step 2.2.1);

[0017] 2.2.3) Record the number of rows where the five elements match the transistor to be searched as the number of gates in the transistor to be searched in the current cell, gate_num. Multiply the number of fins per gate, nfin, by the number of gates per transistor in the current cell, gate_num, to obtain the total number of fins in each transistor, all_fin_num. Jump to step 2.3).

[0018] Optionally, step 2.3) includes:

[0019] 2.3.1A) Get the preset number of gates add_gate_num for the transistors to be added in the pull-up or pull-down path through which the current in the current cell passes;

[0020] 2.3.2A) Determine the number of fins to be added (need_add_num) based on the number of gates (add_gate_num) to be added and the number of fins per gate (nfin) in the pull-up or pull-down path through which the current in the current cell flows.

[0021] 2.3.3A) Determine whether the number of fins to be added, need_add_num, is equal to 0. If not, jump to step 2.3.4A. Otherwise, jump to step 4.

[0022] 2.3.4A) Read the row content cell_line from the standard cell netlist of the current cell to be modified. If the read is successful, jump to step 2.3.5A). Otherwise, jump to step 4);

[0023] 2.3.5A) If the five elements of the cell_line row content read (input, output, source or drain, N or P type, and number of fins) match the transistor being searched, jump to step 2.3.6A). Otherwise, jump to step 2.3.4A) to continue reading the next row;

[0024] 2.3.6A) Read the number of fins in the row content cell_line. If the number of fins in the row content cell_line plus the number of fins to be added, need_add_num, is less than or equal to the preset maximum number of fins that can be added to a gate, max_fin_num, then modify the number of fins nfin in a gate in the row content cell_line representing the information of a gate to the sum of the original number of fins nfin in a gate plus the total number of fins all_fin_num, and then set the number of fins need_add_num to be added to 0; otherwise, modify the number of fins nfin in a gate in the row content cell_line to the preset maximum number of fins that can be added to a gate, max_fin_num, and update the number of fins need_add_num to be added according to the following formula: need_add_num=need_add_num-max_fin_num+nfin; jump to execute step 2.3.4A) to continue reading the next row.

[0025] Optionally, the function expression for determining the number of fins to be added (need_add_num) in step 2.3.2A) is:

[0026] need_add_num=add_gate_num*nfin

[0027] In the above formula, add_gate_num is the number of gates to be added to the transistor on the pull-up or pull-down path through which the current in the current cell passes, and nfin is the number of fins contained in each gate.

[0028] Optionally, step 2.3) comprises:

[0029] 2.3.1B) obtaining a pre-set number of gates minus_gate_num to be reduced from the transistor on the pull-up or pull-down path through which the current in the current cell does not pass;

[0030] 2.3.2B) judging whether the number of gates to be reduced minus_gate_num is equal to 0 and less than the number of gates gate_num contained in each transistor in each current cell, and if the number of gates to be reduced minus_gate_num is not equal to 0 and the number of gates to be reduced minus_gate_num is less than the number of gates gate_num contained in each transistor in each current cell, then jumping to step 2.3.3B; otherwise, jumping to step 4);

[0031] 2.3.3B) reading the row content cell_line from the standard cell netlist of the current cell to be modified by row, and if the reading is successful, then jumping to step 2.3.4B), otherwise, jumping to step 4);

[0032] 2.3.4B) if the five elements of input, output, source or drain, N or P type, and fin number in the read row content cell_line match the transistor to be searched, then jumping to step 2.3.5B), otherwise, jumping to step 2.3.3B) to continue reading the next row;

[0033] 2.3.5B) deleting the row where the read row content cell_line is located, reducing the number of gates to be reduced minus_gate_num by 1, and jumping to step 2.3.3B) to continue reading the next row.

[0034] Optionally, after step 4), further comprising simulating the timing path after the redrawing of the layout to obtain the optimized delay.

[0035] In addition, the present application also provides a transistor-level delay optimization system based on circuit topology structure, comprising a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure.

[0036] In addition, the application also provides a computer readable storage medium, which stores a computer program or instructions programmed or configured to execute the transistor level delay optimization method based on the circuit topology structure by a processor.

[0037] In addition, the application also provides a computer program product, which comprises a computer program or instructions programmed or configured to execute the transistor level delay optimization method based on the circuit topology structure by a processor.

[0038] Compared with the prior art, the application mainly has the following advantages: 1. The method of the application can automatically find the delay sensitive unit and determine the transistor size after optimization of the unit, so that greater delay optimization is obtained with minimum design change, thereby providing guidance for layout design and avoiding blindness and randomness of manual optimization and adjustment of the layout; 2. The method of the application can perform delay optimization on the path according to the circuit topology structure, can quickly and efficiently find the delay sensitive unit and determine the transistor size after optimization of the unit, and has the characteristics of automaticity, high flexibility, good adaptability and the like. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 It is a basic flowchart of the method of the embodiment of the application.

[0040] Figure 2 It is the original timing path in the method of the embodiment of the application.

[0041] Figure 3 It is the timing path after delay optimization of the original timing path in the embodiment of the application. Figure 2 The timing path after delay optimization of the original timing path.

[0042] Figure 4 It is a two-dimensional plane structure schematic diagram of a finFET in the embodiment of the application.

[0043] Figure 5 It is a three-dimensional structure schematic diagram of a finFET in the embodiment of the application.

[0044] Figure 6 It is the original layout stick diagram of a two-input NAND gate unit netlist in the embodiment of the application.

[0045] Figure 7 It is the layout stick diagram after optimization of the two-input NAND gate unit netlist in the embodiment of the application.

[0046] Figure 8 It is a partial layout schematic diagram of a finFET unit netlist in the embodiment of the application.

[0047] Figure 9 It is a partial layout schematic diagram after optimization of a finFET unit netlist in the embodiment of the application. DETAILED DESCRIPTION

[0048] like Figure 1 As shown, the transistor-level delay optimization method based on the circuit topology structure of this embodiment includes the following steps:

[0049] 1) Obtain all N units on the timing path to be optimized;

[0050] 2) Perform transistor-level delay optimization on each unit to obtain the delay-optimized timing path, for example Figure 2 In the original timing path shown, the bold path is the pull-up or pull-down path through which the current passes, and the non-bold path is the pull-up or pull-down path through which the current does not pass; Figure 3 For Figure 2 The timing path after delay optimization adds two gates to the transistors on the bolded path and reduces one gate to the transistors on the unbolded path, and shows the change in the number of fins before and after optimization. BUFV3, NOR2V6, INV6, NOR3V4, and AOI21V4 are the unit names in the timing path, I, A1, A2, A3, and B are inputs, and Z and ZN are outputs. The numbers represent the number of fins in the transistors. N1, N2, P1, and P2 next to the transistors are transistor labels. Other transistors are labeled as inputs, distinguished by N or P type transistors and the current unit name, and are no longer labeled individually.

[0051] 3) Simulate the optimized timing path to obtain the optimized path delay, and select n units with the largest delay change relative to the original timing path as n delay-sensitive units, where n is less than or equal to N;

[0052] 4) Redraw the layout for the selected n delay-sensitive units according to the modifications corresponding to the delay optimization.

[0053] In this embodiment, there are N units in total on the timing path to be optimized. Therefore, step 1) obtains all N units on the timing path to be optimized so as to provide data for subsequent optimization of each unit one by one.

[0054] In this embodiment, step 2) includes:

[0055] 2.1) Traverse N cells and obtain a cell as the current cell. If the traversal is successful, jump to step 2.2). Otherwise, it is determined that the delay-optimized timing path has been obtained and jump to step 3).

[0056] 2.2) Find and calculate the number of gates contained in each transistor in the current cell, the number of fins contained in each gate, nfin, and the total number of fins, all_fin_num;

[0057] 2.3) Based on the number of gates per transistor in the current cell (gate_num), the number of fins per gate (nfin), and the total number of fins (all_fin_num), modify the number of gates in the transistors in the current cell based on the cell type and circuit structure to achieve transistor-level delay optimization, and then jump to step 2.1).

[0058] In this embodiment, step 2.2) includes:

[0059] 2.2.1) Read the row content cell_line from the standard cell netlist of the current cell. If the read is successful, jump to step 2.2.2). Otherwise, jump to step 2.2.3);

[0060] 2.2.2) If the five elements of the cell_line read in the row content (input, output, source or drain, N or P type, and number of fins) match the transistor to be searched, then the number of fins read in the cell_line row content is the number of fins per gate (nfin); jump to step 2.2.1);

[0061] 2.2.3) Record the number of rows where the five elements match the transistor to be searched as the number of gates in the transistor to be searched in the current cell, gate_num. Multiply the number of fins per gate, nfin, by the number of gates per transistor in the current cell, gate_num, to get the total number of fins in each transistor, all_fin_num. For example Figure 4 In the two-dimensional planar structure of the finFET shown, the number of fins (nfin) contained in the gate (denoted as fin1 to fin5 in the figure) is 5. The total number of fins in each transistor, all_fin_num, is obtained by multiplying 5 by the number of gates contained in each transistor in the current unit. Figure 5 The three-dimensional structure of the finFET shown better illustrates the relationship between the gate and the fin in the finFET, where L is the gate length, H is the height of the fin, and W is the width of the fin; skip to step 2.3).

[0062] In this embodiment, step 2.3) includes:

[0063] 2.3.1A) Get the preset number of gates add_gate_num for the transistors to be added in the pull-up or pull-down path through which the current in the current cell passes;

[0064] 2.3.2A) Determine the number of fins to be added (need_add_num) based on the number of gates (add_gate_num) to be added and the number of fins per gate (nfin) in the pull-up or pull-down path through which the current in the current cell flows.

[0065] 2.3.3A) Determine whether the number of fins to be added, need_add_num, is equal to 0. If not, jump to step 2.3.4A. Otherwise, jump to step 4.

[0066] 2.3.4A) Read the row content cell_line from the standard cell netlist of the current cell to be modified. If the read is successful, jump to step 2.3.5A). Otherwise, jump to step 4);

[0067] 2.3.5A) If the five elements of the cell_line row content read (input, output, source or drain, N or P type, and number of fins) match the transistor being searched, jump to step 2.3.6A). Otherwise, jump to step 2.3.4A) to continue reading the next row;

[0068] 2.3.6A) Read the number of fins in the row content cell_line. If the number of fins in the row content cell_line plus the number of fins to be added, need_add_num, is less than or equal to the preset maximum number of fins that can be added to a gate, max_fin_num, then modify the number of fins nfin in a gate in the row content cell_line representing the information of a gate to the sum of the original number of fins nfin in a gate plus the total number of fins all_fin_num, and then set the number of fins need_add_num to be added to 0; otherwise, modify the number of fins nfin in a gate in the row content cell_line to the preset maximum number of fins that can be added to a gate, max_fin_num, and update the number of fins need_add_num to be added according to the following formula: need_add_num=need_add_num-max_fin_num+nfin; jump to execute step 2.3.4A) to continue reading the next row.

[0069] In step 2.3.2A) of this embodiment, the function expression for determining the number of fins to be added, need_add_num, is:

[0070] need_add_num=add_gate_num*nfin

[0071] In the above formula, add_gate_num is the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the current unit, and nfin is the number of fins per gate.

[0072] As shown in steps 2.3.1A) to 2.3.6A), if gates are added to a path, the number of gates to be added (add_gate_num) is obtained. The number of fins to be added is then calculated as need_add_num = add_gate_num * nfin. A loop then begins, looping continuously as long as need_add_num is not equal to 0. The cell_line field is read from the standard cell netlist to be modified, row by row. If the cell_line field's five elements (input, output, source or drain, n-type or p-type, and number of fins) match the transistor being searched, the row to be modified is located. If the sum of nfin in the current cell_line and need_add_num is less than or equal to the maximum number of fins that can be added to a single gate (max_fin_num), the number of fins in that row is modified to equal the sum of the original nfin and all_fin_num. Then, need_add_num is set to 0, completing the addition. If the sum of nfin in the current cell_line row and need_add_num is greater than the maximum number of fins that can be added to a gate (max_fin_num), the number of fins in this row is changed to max_fin_num. The number of fins that need to be added is:

[0073] need_add_num=need_add_num-max_fin_num+nfin,

[0074] Then read the next line of the cell netlist. If it does not match, read the next line of the cell netlist. If cell_line is empty, exit the loop.

[0075] Step 2.3) of this embodiment includes:

[0076] 2.3.1B) Obtain the preset minus_gate_num number of gates to be reduced for transistors on the pull-up or pull-down path that the current does not pass through in the current cell;

[0077] 2.3.2B) Determine whether the number of gates to be reduced, minus_gate_num, is equal to 0 and is less than the number of gates contained in each transistor in each current cell, gate_num. If minus_gate_num is not equal to 0 and is less than the number of gates contained in each transistor in each current cell, jump to step 2.3.3B; otherwise, jump to step 4.

[0078] 2.3.3B) Read the row content cell_line from the standard cell netlist of the current cell to be modified. If the read is successful, jump to step 2.3.4B), otherwise jump to step 4);

[0079] 2.3.4B) If the five elements of the cell_line row content read (input, output, source or drain, N or P type, and number of fins) match the transistor being searched, jump to step 2.3.5B). Otherwise, jump to step 2.3.3B) to continue reading the next row;

[0080] 2.3.5B) Delete the row containing the read row content cell_line, reduce the gate number minus_gate_num by 1, and jump to step 2.3.3B) to continue reading the next row.

[0081] As shown in steps 2.3.1B) to 2.3.5B), if the path is gate reduction, obtain the number of gates to be subtracted, minus_gate_num, and begin a loop. The loop continues as long as minus_gate_num is not equal to 0. If minus_gate_num is greater than or equal to the number of gates in the transistor, the loop indicates that gate reduction is not possible and exits. If minus_gate_num is less than the number of gates in the transistor, the loop continues, reading rows from the standard cell netlist to be modified. If the row's five elements (input, output, source or drain, n-type or p-type, and number of fins) match the transistor being searched, the row to be modified is located and deleted. Because a row in the netlist represents a gate in the transistor, this is equivalent to subtracting a gate. The number of gates to be subtracted is minus_gate_num - 1. Because deleting this row advances the number of rows following it, the loop continues without changing the number of rows. If the row does not match, the next row in the cell netlist is read. If the cell_line content is empty, exit the loop.

[0082] After inputting the information to modify the number of gates, it is determined whether to add or subtract gates. If adding gates, it will loop until add_gate_num is equal to 0. If subtracting gates, it will loop until minus_gate_num is equal to 0. Figure 6 This is a stick diagram of the original layout of the two-input NAND gate (NAND2V3) unit netlist in this embodiment. Figure 7 This is a stick diagram of the layout after the netlist of the two-input NAND gate (NAND2V3) unit in this embodiment is optimized, see Figure 6 and Figure 7 The stick diagrams of the layout before and after optimization show that the optimization program in this embodiment adds two gates to the transistors on the pull-down paths corresponding to the cell inputs A1 and A2, and subtracts one gate from the transistors on the pull-up paths corresponding to the inputs A1 and A2. Figure 6 and Figure 7 In the stick diagram in the middle layout, A1 and A2 are input names, 0-9 are grid names, and ZN and 4 are line names.

[0083] As an optional implementation, after step 4), this embodiment also includes simulating the timing path after redrawing the layout to obtain optimized delays. After obtaining n delay-sensitive cells, the layout is redrawn according to the optimized number of cell fins and a post-simulation is performed to evaluate the optimization results. Optimization is complete. Figure 8 Schematic diagram of the original partial layout of the finFET unit netlist in an embodiment of the present invention, Figure 9 For Figure 8 Adding a gate to the layout is equivalent to adding five fins, where Gate is the gate, A2 is the input port, ZN is the output port, VSS is the ground, M0G is the metal connecting the gate and the through hole, M0 is the metal, and the fins are Fin (represented as fin1 to fin5 in the figure).

[0084] In summary, the transistor-level delay optimization method based on the circuit topology structure of this embodiment includes: (1) obtaining all cells in a path; (2) setting the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the cell as add_gate_num, and the number of gates to be reduced to the transistors on the pull-up or pull-down path through which the current does not pass as minus_gate_num; (3) finding the number of gates contained in each transistor in the cell as gate_num, the number of fins contained in each gate as nfin, and the total number of fins as all_fin_num; (4) modifying the number of gates in the transistors in the cell based on the cell type and the circuit structure, as shown in the attached figure. Figure 2The bold path in the circuit diagram is the pull-up or pull-down path through which current passes. Two gates are added to the transistors on the path, and one gate is removed from the transistors on the pull-up or pull-down path through which current does not pass. The change in the number of fins before and after optimization is displayed. (5) Repeat the above steps (3)-(4) until each unit in the path is modified. (6) Compare the delay results of the original path with the simulation results of the modified path, and find the n units with the largest delay changes before and after the modification as delay-sensitive units. (7) Only the n delay-sensitive units in the path are modified and the entire modified path is simulated. The above-mentioned transistor-level delay optimization method based on circuit topology structure in this embodiment uses a method based on circuit topology structure to automatically find delay-sensitive units for the timing path to be optimized. It can automatically determine the delay-sensitive units and their transistor sizes in the path based on the topology structure of the circuit diagram. It has the characteristics of automation, high flexibility, good adaptability, etc., and can help optimize the delay of the path quickly and efficiently.

[0085] In addition, this embodiment also provides a transistor-level delay optimization system based on circuit topology structure, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure.

[0086] In addition, this embodiment also provides a computer-readable storage medium, which stores a computer program or instructions. The computer program or instructions are programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure through a processor.

[0087] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure through a processor.

[0088] Those skilled in the art should understand that the technical solutions provided by the embodiments of the present application may be in the form of methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0089] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A transistor-level delay optimization method based on circuit topology, characterized in that: The steps include: 1) Obtain all N units on the timing path to be optimized; 2) Perform transistor-level delay optimization on each unit to obtain the delay-optimized timing path; 3) Simulate the optimized timing path to obtain the optimized path delay, and select n units with the largest delay change relative to the original timing path as n delay-sensitive units, where n is less than or equal to N; 4) Redraw the layout for the selected n delay-sensitive units according to the modifications corresponding to the delay optimization; Step 2) includes: 2.1) Traverse N cells and obtain a cell as the current cell. If the traversal is successful, jump to step 2.2). Otherwise, it is determined that the delay-optimized timing path has been obtained and jump to step 3). 2.2) Find and calculate the number of gates contained in each transistor in the current cell, the number of fins contained in each gate, nfin, and the total number of fins, all_fin_num; 2.3) Based on the number of gates in each transistor in the current cell (gate_num), the number of fins in each gate (nfin), and the total number of fins (all_fin_num), the number of gates in the transistors in the current cell is modified based on the cell type and circuit structure to achieve transistor-level delay optimization, and the process then jumps to step 2.

1. Step 2.2) includes: 2.2.1) Read the row content cell_line from the standard cell netlist of the current cell. If the read is successful, jump to step 2.2.2). Otherwise, jump to step 2.2.3); 2.2.2) If the five elements of the cell_line read in the row content (input, output, source or drain, N or P type, and number of fins) match the transistor to be searched, then the number of fins read in the cell_line row content is the number of fins per gate (nfin); jump to step 2.2.1); 2.2.3) Record the number of rows where the five elements match the transistor to be searched as the number of gates in the transistor to be searched in the current cell, gate_num. Multiply the number of fins per gate, nfin, by the number of gates per transistor in the current cell, gate_num, to obtain the total number of fins in each transistor, all_fin_num. Jump to step 2.3).

2. The transistor-level delay optimization method based on circuit topology structure according to claim 1, characterized in that: Step 2.3) includes: 2.3.1A) Get the preset number of gates add_gate_num for the transistors to be added in the pull-up or pull-down path through which the current in the current cell passes; 2.3.2A) Determine the number of fins to be added (need_add_num) based on the number of gates (add_gate_num) to be added and the number of fins per gate (nfin) in the pull-up or pull-down path through which the current in the current cell flows. 2.3.3A) Determine whether the number of fins to be added, need_add_num, is equal to 0. If not, jump to step 2.3.4A. Otherwise, jump to step 4. 2.3.4A) Read the row content cell_line from the standard cell netlist of the current cell to be modified. If the read is successful, jump to step 2.3.5A). Otherwise, jump to step 4); 2.3.5A) If the five elements of the cell_line row content read (input, output, source or drain, N or P type, and number of fins) match the transistor being searched, jump to step 2.3.6A). Otherwise, jump to step 2.3.4A) to continue reading the next row; 2.3.6A) Read the number of fins in the row content cell_line. If the number of fins in the row content cell_line plus the number of fins to be added, need_add_num, is less than or equal to the preset maximum number of fins that can be added to a gate, max_fin_num, then modify the number of fins nfin in a gate in the row content cell_line representing the information of a gate to the sum of the original number of fins nfin in a gate plus the total number of fins all_fin_num, and then set the number of fins need_add_num to be added to 0; otherwise, modify the number of fins nfin in a gate in the row content cell_line to the preset maximum number of fins that can be added to a gate, max_fin_num, and update the number of fins need_add_num to be added according to the following formula: need_add_num=need_add_num-max_fin_num+nfin; jump to execute step 2.3.4A) to continue reading the next row.

3. The transistor-level delay optimization method based on circuit topology structure according to claim 2, characterized in that: The function expression for determining the number of fins to be added (need_add_num) in step 2.3.2A is: need_add_num=add_gate_num*nfin In the above formula, add_gate_num is the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the current unit, and nfin is the number of fins per gate.

4. The transistor-level delay optimization method based on circuit topology structure according to claim 1, characterized in that: Step 2.3) includes: 2.3.1B) Obtain the preset minus_gate_num number of gates to be reduced for transistors on the pull-up or pull-down path that the current does not pass through in the current cell; 2.3.2B) Determine whether the number of gates to be reduced, minus_gate_num, is equal to 0 and is less than the number of gates contained in each transistor in each current cell, gate_num. If minus_gate_num is not equal to 0 and is less than the number of gates contained in each transistor in each current cell, jump to step 2.3.3B; otherwise, jump to step 4. 2.3.3B) Read the row content cell_line from the standard cell netlist of the current cell to be modified. If the read is successful, jump to step 2.3.4B), otherwise jump to step 4); 2.3.4B) If the five elements of the cell_line row content read (input, output, source or drain, N or P type, and number of fins) match the transistor being searched, jump to step 2.3.5B). Otherwise, jump to step 2.3.3B) to continue reading the next row; 2.3.5B) Delete the row containing the read row content cell_line, reduce the gate number minus_gate_num by 1, and jump to step 2.3.3B) to continue reading the next row.

5. The transistor-level delay optimization method based on circuit topology structure according to claim 1, characterized in that: Step 4) also includes simulating the timing path after redrawing the layout to obtain the optimized delay.

6. A transistor-level delay optimization system based on a circuit topology structure, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure according to any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure according to any one of claims 1 to 5 through a processor.

8. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure according to any one of claims 1 to 5 through a processor.

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