A method for quickly adding buffers in high-frequency lines for post-layout simulation

Abstract

The present invention discloses a method for quickly adding buffers in high-frequency lines for post-layout simulation, which relates to the field of integrated circuit technology. The method includes adding metal ideal resistors on high-speed signal lines and placing them at the output end, the middle section of the signal line, and the receiving end of the layout; using StarRC to extract parasitic parameters and generate a parasitic netlist file; searching for the corresponding position metal ideal resistors in the parasitic netlist file and deleting the metal ideal resistors in the parasitic netlist file to generate floating nodes; automatically adding buffers at the corresponding positions and performing post-layout simulation analysis, and then replacing the resistors at the corresponding positions in the layout with buffers; the present invention uses clustering algorithms and decision tree algorithms to automatically identify and decide whether buffers need to be added at critical nodes, quickly add buffers in high-speed signal lines, reduce the time for repeatedly extracting parasitic parameters and modifying the layout, and improve the efficiency of post-layout simulation.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a method for quickly adding buffers in high-frequency lines for post-layout simulation. Background Art

[0002] In the post-layout simulation of high-speed signal lines, in order to ensure signal integrity and timing performance, it is necessary to add an appropriate number and position of buffers in the lines. However, repeatedly adjusting the position and number of buffers in the layout requires multiple extractions of parasitic parameters and simulation validations, greatly increasing the design iteration time and cost. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for quickly adding buffers in high-frequency lines for post-layout simulation, which can quickly add buffers in high-speed signal lines, reduce the time for repeatedly extracting parasitic parameters and modifying the layout, and improve the efficiency of post-layout simulation.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides a method for quickly adding buffers in high-frequency lines for post-layout simulation, including the following steps:

[0006] Add metal ideal resistors on the high-speed signal lines in the schematic, and place the metal ideal resistors at the output end, the middle section of the signal line, and the receiving end positions of the layout;

[0007] Then verify the consistency of the connection of the metal ideal resistors through LVS, extract parasitic parameters using StarRC, and generate a parasitic netlist file;

[0008] Search for the metal ideal resistors at the corresponding positions in the parasitic netlist file, determine their input and output nodes, and delete the metal ideal resistors in the parasitic netlist file to generate floating nodes;

[0009] In the simulation software, automatically add buffers at the corresponding positions according to the floating nodes, and perform post-layout simulation analysis. After the post-layout simulation analysis is completed, replace the resistors at the corresponding positions in the layout with buffers.

[0010] Further, adding metal ideal resistors on the high-speed signal lines in the schematic and placing the metal ideal resistors at the output end, the middle section of the signal line, and the receiving end positions of the layout includes:

[0011] Obtain the routing topology structure data and signal transmission characteristic data of the high-speed signal line as the input data of the machine learning algorithm. Use the clustering algorithm to identify the key nodes of the high-speed signal line, and cluster according to the signal transmission characteristics of the nodes to obtain different types of key nodes.

[0012] According to different types of key nodes, use the decision tree algorithm for analysis. Based on the topological structure characteristics and signal transmission characteristics of the nodes, determine whether a buffer needs to be added. When a key node that needs to add a buffer is identified, determine whether it is an output end, a middle-section node, or a receiving end according to the position of the key node in the signal line.

[0013] Group the key nodes that need to add buffers according to their position attributes to obtain the output-end candidate position set, the middle-section candidate position set, and the receiving-end candidate position set.

[0014] According to the specific routing topology structure of the high-speed signal line, optimize the positions in the candidate position set, eliminate the positions that are not suitable for adding buffers, and then use the optimized candidate position set as the final buffer addition position to output the buffer optimization scheme for the high-speed signal line.

[0015] Further, add a metal ideal resistor to the high-speed signal line in the schematic. After placing the metal ideal resistor at the output end, the middle section of the signal line, and the receiving end positions in the layout, it also includes:

[0016] Obtain the candidate position set, and use a simulation analysis tool to simulate the circuit system after adding a buffer at this position. According to the simulation analysis results, extract the signal integrity index and timing performance index after adding the buffer. Compare the extracted indexes with the preset design requirement thresholds. When both the signal integrity index and the timing performance index meet the design requirement thresholds, mark this position as a valid insertion position.

[0017] When either the signal integrity index or the timing performance index fails to meet the design requirement thresholds, mark this position as an invalid insertion position. Based on the marking results, screen out all valid insertion positions from the candidate position set to form the buffer insertion position scheme.

[0018] Further, according to the buffer insertion position scheme, obtain the routing information of the high-speed signal line in the schematic and the preset set of effective insertion positions; calculate the characteristic impedance and transmission delay of the signal line according to the routing information of the high-speed signal line; use a machine learning algorithm to minimize the impact of the metal ideal resistance on signal integrity as the optimization goal, and optimize the resistance value of the metal ideal resistance; when the optimized resistance value of the metal ideal resistance meets the preset threshold condition, use this resistance value as the optimal resistance value; otherwise, adjust the parameters of the optimization algorithm and re-optimize; according to the optimal resistance value, automatically add a metal ideal resistance in the set of effective insertion positions of the high-speed signal line; use a simulation tool to perform signal integrity analysis on the high-speed signal line after adding the metal ideal resistance to obtain signal integrity indicators.

[0019] Further, according to the position information of the metal ideal resistance in the schematic, automatically generate the layout of the metal ideal resistance at the corresponding position in the layout, use a pattern matching algorithm to identify the position coordinates of the metal ideal resistance, analyze the topological structure of the routing around the layout of the metal ideal resistance, construct a parasitic parameter extraction model, and calculate the parasitic capacitance and inductance values introduced by the layout of the metal ideal resistance; when the parasitic parameters introduced by the layout of the metal ideal resistance exceed the preset threshold, trigger the routing optimization process; use a heuristic search algorithm to adjust and optimize the routing topology and width around the metal ideal resistance under the routing constraint conditions, and judge whether the optimized routing meets the design requirements through parasitic parameter extraction and signal integrity simulation analysis of the optimized routing scheme; when it meets the design requirements, determine the optimized routing scheme, otherwise trigger the routing optimization process to continue optimization; according to the determined optimized routing scheme, update the geometric parameters of the metal ideal resistance and its surrounding routing in the layout, and perform DRC inspection on the routing.

[0020] Further, verify the consistency of the connection of the metal ideal resistance through LVS, and then use StarRC to extract parasitic parameters to generate a parasitic netlist file, including:

[0021] According to the frequency characteristics of the high-speed signal, set the extraction accuracy and frequency range of StarRC, analyze the parasitic parameter netlist extracted by StarRC, and judge whether the impact of the metal ideal resistance on the high-speed signal is within an acceptable range; when the signal attenuation and delay introduced by the metal ideal resistance exceed the design index, it is necessary to optimize the layout and connection method of the metal ideal resistance, reduce the parasitic parameter value of the metal ideal resistance by shortening the length of the metal ideal resistance and increasing the width of the metal ideal resistance, and re-perform LVS verification and StarRC extraction until the parasitic parameters of the metal ideal resistance meet the design requirements for high-speed signal transmission.

[0022] Further, search for the metal ideal resistor at the corresponding position in the parasitic netlist file, determine its input and output nodes, and delete the metal ideal resistor in the parasitic netlist file to generate floating nodes, including:

[0023] According to the parasitic netlist file, use text parsing technology to search for and locate the input and output node information of the metal ideal resistor, judge the nodes connected to both ends of the metal ideal resistor. When a node is only connected to the metal ideal resistor, then this node is a floating node, and mark it as a node to be processed;

[0024] Delete the metal ideal resistor information in the netlist file, while retaining the floating node information, to obtain the netlist topology structure after deleting the metal ideal resistor. According to the netlist topology structure after deleting the metal ideal resistor, use graph theory algorithms to identify the floating nodes and judge their connection relationships with other devices;

[0025] By analyzing the connection methods between the floating nodes and other device nodes, determine the positions where buffers need to be added, establish virtual connections, use the depth-first search algorithm to traverse the netlist topology structure, obtain the path changes before and after adding buffers, and evaluate the delay impact;

[0026] According to the delay evaluation results, determine the optimal buffer addition scheme, generate the netlist file after adding buffers, and complete the elimination of floating nodes and connection repair.

[0027] Further, in the simulation software, automatically add buffers at the corresponding positions according to the floating nodes and perform post-simulation analysis, specifically including:

[0028] Obtain the position information of the floating nodes of the circuit in the simulation software, and judge whether it is necessary to add buffers at the floating node positions according to the preset rules;

[0029] When it is necessary to add buffers, then automatically add buffers at the corresponding positions according to the floating node positions to obtain the circuit after adding buffers, and then perform simulation analysis on the circuit after adding buffers to obtain the simulation analysis result data, including signal integrity and timing performance index data;

[0030] Input the simulation analysis result data into the machine learning model, and optimize the buffer parameters and connection methods through machine learning algorithms to obtain the optimized buffer parameters and connection methods;

[0031] According to the optimized buffer parameters and connection methods, update the circuit after adding buffers to obtain the optimized circuit, and perform simulation analysis on the optimized circuit again to obtain the optimized simulation analysis result data.

[0032] Further, after the post-layout simulation analysis is completed, replace the resistors at the corresponding positions in the layout with buffers, specifically including: obtaining the position coordinate information of the metal ideal resistors that need to be replaced and modified according to the post-layout simulation analysis results, locating the corresponding metal ideal resistors in the layout through the position coordinate information, and then according to the circuit design specifications, using a look-up table algorithm to obtain buffer parameters that are close to the resistance value of the original metal ideal resistor and meet the design requirements from a preset resistor parameter table; according to the obtained buffer parameters, through a circuit construction algorithm, generate a new metal ideal resistor circuit structure including the buffer, and replace the new metal ideal resistor circuit structure at the position of the original metal ideal resistor in the layout to obtain a new layout including the buffer;

[0033] Then, adopt an intelligent layout algorithm based on deep learning, extract the layout features of the new layout through a convolutional neural network, compare them with the preset optimal layout features, obtain the difference information between the new layout and the optimal layout, and according to the difference information, adopt a reinforcement learning algorithm to continuously adjust the positions and connections of the buffers and metal ideal resistors in the new layout to minimize the area increase caused by the buffers, and obtain an optimized new layout.

[0034] Further, after obtaining the optimized new layout, it also includes: performing LVS verification on the new layout to ensure that the new layout complies with the design specifications and the device connections are correct; extracting parasitic parameters from the new layout that passes the LVS verification to obtain parasitic parameter information such as the resistance and capacitance of the wiring; generating a new parasitic netlist file according to the extracted parasitic parameters to obtain a netlist description including the parasitic parameters; comparing the newly generated parasitic netlist file with the original parasitic netlist file to analyze the changes in the netlist before and after adding the buffer; using a timing simulation tool to compare the signal integrity and timing performance indicators before and after adding the buffer to determine whether the design requirements are met; when the performance indicators after adding the buffer do not meet the design requirements, then use an optimization algorithm to adjust the position and parameters of the buffer; then find the best buffer position and parameter configuration through iterative optimization; repeat the judgment and optimization process until the signal integrity and timing performance meet the design requirements, and obtain the optimized buffer position and parameter configuration to complete the layout optimization.

[0035] The beneficial effects of the present invention are:

[0036] In the schematic design stage, clustering algorithms and decision tree algorithms are used to automatically identify and decide whether buffers need to be added to key nodes. This method not only reduces the subjectivity of manual judgment but also greatly improves the automation level of the design process. In this way, designers can quickly locate the areas that need to be optimized, avoiding the cumbersome steps of a large number of manual adjustments and verifications in traditional designs, thus saving a large amount of design time and cost;

[0037] Through intelligent layout algorithms and deep learning-based optimization techniques, the present invention can automatically adjust the positions and parameters of buffers to minimize the impact on circuit area and routing congestion. At the same time, through LVS verification and parasitic parameter extraction, the present invention can ensure that the new layout complies with the design specifications, and through comparative analysis with a timing simulation tool, ensure that signal integrity and timing performance meet the design requirements. This meticulous optimization process not only improves the performance of the circuit but also guarantees the reliability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] For a better understanding and implementation, the technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0039] Figure 1 It is a flowchart showing a method for quickly adding buffers in high-frequency lines for post-layout simulation provided by the present application;

[0040] Figure 2 It is a flowchart showing the process of generating floating nodes for a method for quickly adding buffers in high-frequency lines for post-layout simulation provided by the present application;

[0041] Figure 3 It is a flowchart showing the process of post-layout simulation analysis for a method for quickly adding buffers in high-frequency lines for post-layout simulation provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of methods and systems consistent with some aspects of the present application as detailed in the appended claims.

[0043] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0044] The following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation manners, features, and effects of the present invention.

[0045] Please refer to Figures 1-3 , this embodiment provides a method for quickly adding buffers in a high-frequency line for post-layout simulation, including the following steps:

[0046] S1. To accelerate the post-layout simulation speed of high-speed signal lines, first add metal ideal resistors to the high-speed signal lines in the schematic, and place the metal ideal resistors at positions such as the output end, the middle section of the signal line, and the receiving end in the layout;

[0047] Further, adding metal ideal resistors to the high-speed signal lines in the schematic and placing the metal ideal resistors at the output end, the middle section of the signal line, and the receiving end positions in the layout includes:

[0048] S11. Obtain the wiring topology structure data and signal transmission characteristic data of the high-speed signal line as the input data of the machine learning algorithm, use the clustering algorithm to identify the key nodes of the high-speed signal line, and perform clustering according to the signal transmission characteristics of the nodes to obtain different types of key nodes;

[0049] S12. According to different types of key nodes, use the decision tree algorithm for analysis. According to the topological structure characteristics and signal transmission characteristics of the nodes, determine whether a buffer needs to be added; when a key node that needs to add a buffer is encountered, determine it as the output end, the middle section node, or the receiving end according to the position of the key node in the signal line;

[0050] S13. Group the key nodes that need to add buffers according to their position attributes to obtain an output end candidate position set, a middle section candidate position set, and a receiving end candidate position set;

[0051] S14. According to the specific wiring topology structure of the high-speed signal line, optimize the positions in the candidate position set, eliminate the positions that are not suitable for adding buffers, and then use the optimized candidate position set as the final buffer addition position to output the buffer optimization scheme for the high-speed signal line.

[0052] Specifically, by adding ideal metal resistors to high-speed signal lines in the schematic diagram and combining machine learning algorithms to identify key nodes and using decision tree algorithms for analysis, this method can accurately determine the positions where buffers need to be added at the output end, middle section, and receiving end of the signal lines. This optimization scheme not only speeds up the post-layout simulation, reduces the workload of parasitic parameter extraction and layout iteration, but also improves the efficiency of circuit design and signal integrity, and finally outputs a more efficient and accurate buffer layout scheme for high-speed signal lines.

[0053] Further, after adding ideal metal resistors to the high-speed signal lines in the schematic and placing the ideal metal resistors at the output end, the middle section of the signal line, and the receiving end positions in the layout, it further includes:

[0054] Obtain a set of candidate positions, and use a simulation analysis tool to simulate the circuit system after adding a buffer at this position; according to the simulation analysis results, extract the signal integrity index and timing performance index after adding the buffer; compare the extracted indexes with the preset design requirement thresholds; when both the signal integrity index and the timing performance index meet the design requirement thresholds, mark this position as a valid insertion position;

[0055] When either the signal integrity index or the timing performance index does not meet the design requirement thresholds, mark this position as an invalid insertion position; based on the marking results, screen out all valid insertion positions from the set of candidate positions to form a buffer insertion position scheme.

[0056] Specifically, by adding ideal metal resistors in the schematic diagram and simulating their effects in the circuit, this method can accurately evaluate the signal integrity and timing performance after adding buffers at different positions through a simulation analysis tool. By comparing the simulation results with the design requirements, it effectively screens out the buffer insertion positions that meet the performance standards, thus forming an optimized buffer layout scheme to ensure the stability and reliability of the signal lines while meeting the performance requirements of the circuit design. This method not only optimizes the circuit design process, but also reduces design iterations, improves design efficiency, and the performance of the final product.

[0057] Further, according to the buffer insertion position scheme, obtain the routing information of the high-speed signal line in the schematic and the preset set of valid insertion positions; calculate the characteristic impedance and transmission delay of the signal line based on the routing information of the high-speed signal line; use machine learning algorithms, such as genetic algorithms or particle swarm optimization algorithms, with the goal of minimizing the impact of the ideal metal resistance on signal integrity to optimize the resistance value of the ideal metal resistance; when the optimized resistance value of the ideal metal resistance meets the preset threshold condition, then use this resistance value as the optimal resistance value; otherwise, adjust the parameters of the optimization algorithm and re-optimize; according to the optimal resistance value, automatically add the ideal metal resistance in the set of valid insertion positions of the high-speed signal line; use a simulation tool to perform signal integrity analysis on the high-speed signal line after adding the ideal metal resistance to obtain signal integrity indicators.

[0058] Specifically, by combining the routing information of the high-speed signal line and the preset set of valid insertion positions, this method uses machine learning algorithms, especially genetic algorithms or particle swarm optimization algorithms, to optimize the resistance value of the ideal metal resistance. This optimization aims to minimize the negative impact of the resistance on signal integrity and ensure that the resistance value meets the preset threshold condition. Once the optimal resistance value is found, the system will automatically add these resistances at the valid insertion positions. Finally, perform signal integrity analysis on the high-speed signal line with the ideal metal resistance added through a simulation tool to obtain accurate signal integrity indicators. This method not only improves the automation level of the design but also ensures that the circuit design reaches the optimal in terms of signal integrity and performance, reduces human errors and design iterations, and improves the design efficiency and the quality of the final product.

[0059] Further, according to the position information of the ideal metal resistance in the schematic, automatically generate the layout of the ideal metal resistance at the corresponding position in the layout, use a pattern matching algorithm to identify the position coordinates of the ideal metal resistance, analyze the topological structure of the routing around the layout of the ideal metal resistance to construct a parasitic parameter extraction model, and calculate the parasitic capacitance and inductance values introduced by the layout of the ideal metal resistance; when the parasitic parameters introduced by the layout of the ideal metal resistance exceed the preset threshold, trigger the routing optimization process; use a heuristic search algorithm to adjust and optimize the routing topology and width around the ideal metal resistance under the routing constraint conditions, perform parasitic parameter extraction and signal integrity simulation analysis on the optimized routing scheme to determine whether the optimized routing meets the design requirements; when it meets the design requirements, determine the optimized routing scheme, otherwise trigger the routing optimization process to continue optimization; according to the determined optimized routing scheme, update the geometric parameters of the ideal metal resistance and its surrounding routing in the layout, and perform DRC inspection on the routing to ensure that the optimized layout complies with the design rules.

[0060] Specifically, by determining the position of the ideal metal resistor in the schematic diagram and automatically generating the corresponding resistor layout in the layout, this method uses a pattern matching algorithm to accurately identify the resistor position and constructs a parasitic parameter extraction model to calculate the parasitic capacitance and inductance values introduced by the resistor layout. When the parasitic parameters exceed the preset threshold, the system will automatically start the routing optimization process, use a heuristic search algorithm to adjust the routing topology and width under the routing constraints, and verify the optimization effect through parasitic parameter extraction and signal integrity simulation analysis. This process ensures that the optimized routing scheme meets the design requirements, updates the geometric parameters in the layout after confirmation, and performs DRC checks to ensure that the layout complies with the design rules, thus realizing the automation, accuracy, and efficiency of high-speed signal line design optimization.

[0061] S2. Verify the consistency of the connection of the ideal metal resistor through LVS, and then use StarRC to extract parasitic parameters to generate a parasitic netlist file;

[0062] Furthermore, verify the consistency of the connection of the ideal metal resistor through LVS, and then use StarRC to extract parasitic parameters to generate a parasitic netlist file, including:

[0063] According to the frequency characteristics of high-speed signals, set the extraction accuracy and frequency range of StarRC to ensure the accuracy of the extraction results. Analyze the parasitic parameter netlist extracted by StarRC to determine whether the impact of the ideal metal resistor on high-speed signals is within an acceptable range. When the signal attenuation and delay introduced by the ideal metal resistor exceed the design specifications, it is necessary to optimize the layout and connection method of the ideal metal resistor. By shortening the length of the ideal metal resistor, increasing the width of the ideal metal resistor, etc., reduce the parasitic parameter value of the ideal metal resistor, and perform LVS verification and StarRC extraction again until the parasitic parameters of the ideal metal resistor meet the design requirements for high-speed signal transmission.

[0064] Specifically, verify the connection consistency of the ideal metal resistor through LVS, and then use the StarRC tool to accurately extract parasitic parameters and generate a parasitic netlist file. This method allows engineers to adjust the extraction accuracy and frequency range according to the frequency characteristics of high-speed signals to ensure the accuracy of the results. By analyzing the parasitic parameters, it can be judged whether the impact of the ideal metal resistor on the signal is within an acceptable range. If the signal attenuation and delay introduced by the ideal metal resistor exceed the design specifications, the parasitic parameter value can be reduced by optimizing the layout and connection method, such as shortening the resistor length or increasing the width. This process requires repeated LVS verification and StarRC extraction until the parasitic parameters of the ideal metal resistor meet the design requirements for high-speed signal transmission, thus ensuring the performance and reliability of the circuit.

[0065] S3. Search for the ideal metal resistor at the corresponding position in the parasitic netlist file, determine its input and output nodes, and delete the ideal metal resistor in the parasitic netlist file to generate floating nodes;

[0066] Further, searching for the ideal metal resistor at the corresponding position in the parasitic netlist file, determining its input and output nodes, and deleting the ideal metal resistor in the parasitic netlist file to generate floating nodes includes:

[0067] S31. According to the parasitic netlist file, use text parsing technology to search for and locate the input and output node information of the ideal metal resistor, judge the nodes connected to both ends of the ideal metal resistor. When a node is only connected to the ideal metal resistor, then this node is a floating node, and mark it as a node to be processed;

[0068] S32. Delete the information of the ideal metal resistor in the netlist file, while retaining the information of the floating nodes, to obtain the netlist topology structure after deleting the ideal metal resistor. According to the netlist topology structure after deleting the ideal metal resistor, use graph theory algorithms to identify the floating nodes and judge their connection relationships with other devices;

[0069] S33. By analyzing the connection methods between the floating nodes and the nodes of other devices, determine the positions where buffers need to be added, and establish virtual connections. Use the depth-first search algorithm to traverse the netlist topology structure, obtain the path changes before and after adding buffers, and evaluate the delay impact;

[0070] S34. According to the delay evaluation results, determine the optimal buffer addition scheme, generate the netlist file after adding buffers, and complete the elimination of floating nodes and connection repair.

[0071] Specifically, by accurately searching for and locating the input and output nodes of the ideal metal resistor in the parasitic netlist file and deleting these resistors to generate floating nodes, this method uses text parsing technology to identify the nodes to be processed, and uses graph theory algorithms and depth-first search algorithms to analyze the connection relationships and path changes between the floating nodes and other devices in the circuit. This process not only optimizes the circuit topology structure, but also evaluates the delay impact, thereby determining the optimal buffer addition scheme, and finally generating an updated netlist file, effectively eliminating floating nodes and repairing connections, ensuring the accuracy and signal integrity of the circuit design.

[0072] S4. In the simulation software, automatically add buffers at the corresponding positions according to the floating nodes, and perform post-layout simulation analysis. After the post-layout simulation analysis is completed, replace the resistors at the corresponding positions in the layout with buffers.

[0073] Among them, "schematic" refers to a schematic diagram, which is a diagram that uses graphic symbols to represent circuit components and their interconnections. The schematic diagram is the basis of circuit design and is used to show the working principle and structure of the circuit; StarRC is a software tool used in integrated circuit design, mainly for parasitic parameter extraction. During the semiconductor manufacturing process, the wires and interconnections on the circuit board will generate parasitic effects, such as parasitic resistance, capacitance, and inductance; "buffer" refers to a buffer, which is a circuit component used to enhance signals, reduce signal distortion, improve the driving ability of signals, or improve the timing characteristics of signals.

[0074] Furthermore, in the simulation software, according to the floating nodes, buffers are automatically added at the corresponding positions and post-layout simulation analysis is performed, which specifically includes:

[0075] S41. Obtain the position information of the floating nodes in the circuit in the simulation software, and judge whether a buffer needs to be added at the floating node position according to the preset rules;

[0076] S42. When a buffer needs to be added, then according to the position of the floating node, a buffer is automatically added at the corresponding position to obtain the circuit after adding the buffer, and then the circuit after adding the buffer is simulated and analyzed to obtain the simulation analysis result data, including signal integrity and timing performance index data;

[0077] S43. Input the simulation analysis result data into the machine learning model, and optimize the buffer parameters and connection methods through machine learning algorithms to obtain the optimized buffer parameters and connection methods;

[0078] S44. According to the optimized buffer parameters and connection methods, update the circuit after adding the buffer to obtain the optimized circuit, and perform simulation analysis on the optimized circuit again to obtain the optimized simulation analysis result data.

[0079] Specifically, by automatically adding buffers according to the floating node positions in the simulation software and performing detailed post-layout simulation analysis, the method first judges whether a buffer needs to be added at a specific position according to the preset rules, and then automatically adds and performs simulation analysis to obtain the key data of signal integrity and timing performance. Then, the machine learning model is used to deeply analyze these data to optimize the buffer parameters and connection methods, further improving the circuit performance. Finally, the circuit design is updated according to the optimization results, and simulation analysis is performed again to verify the optimization effect, ensuring that the circuit design reaches the best state in terms of signal integrity and timing performance, thereby realizing efficient and accurate circuit design optimization.

[0080] Furthermore, after the post-layout simulation analysis is completed, the resistors at the corresponding positions in the layout are replaced with buffers, specifically including: optimizing the new layout using an intelligent placement algorithm to minimize the area increase and routing congestion problems caused by the buffers.

[0081] Obtain the position coordinate information of the metal ideal resistors that need to be replaced and modified according to the post-layout simulation analysis results, locate the corresponding metal ideal resistors in the layout through the position coordinate information, and then, according to the circuit design specifications, use a look-up table algorithm to obtain buffer parameters that are close to the resistance value of the original metal ideal resistor and meet the design requirements from a preset resistor parameter table; according to the obtained buffer parameters, generate a new metal ideal resistor circuit structure containing buffers through a circuit construction algorithm, and replace the new metal ideal resistor circuit structure at the position of the original metal ideal resistor in the layout to obtain a new layout containing buffers;

[0082] Then, use an intelligent placement algorithm based on deep learning to extract the layout features of the new layout through a convolutional neural network, compare them with the preset optimal layout features to obtain the difference information between the new layout and the optimal layout, and according to the difference information, use a reinforcement learning algorithm to continuously adjust the positions and connections of the buffers and metal ideal resistors in the new layout to minimize the area increase caused by the buffers and at the same time minimize the routing congestion problem, and obtain an optimized new layout.

[0083] Specifically, after the post-layout simulation analysis is completed, the resistors at the corresponding positions in the layout are replaced with buffers. This method first determines the position coordinates of the resistors to be replaced according to the post-layout simulation analysis results, and then selects buffer parameters that meet the design requirements from a preset resistor parameter table according to the circuit design specifications. Then, use a circuit construction algorithm to generate a new metal ideal resistor circuit structure and replace it at the original position in the layout to form a new layout containing buffers. Finally, through an intelligent placement algorithm based on deep learning, combined with a convolutional neural network to extract layout features and compare them with the optimal layout features, use a reinforcement learning algorithm to continuously adjust the positions and connections of the buffers and metal ideal resistors to minimize the area increase and routing congestion problems caused by the buffers. This process not only improves the automation level of circuit design, but also optimizes the circuit layout, ensuring the circuit performance while also improving the efficiency and quality of circuit design.

[0084] Further, after obtaining the optimized new layout, it further includes: performing LVS verification and parasitic parameter extraction on the new layout to generate a new parasitic netlist file, comparing the new parasitic netlist file with the original parasitic netlist file, and verifying whether the signal integrity and timing performance before and after adding the buffer meet the design requirements.

[0085] Specifically, it includes: performing LVS verification on the new layout to ensure that the new layout complies with the design specifications and the device connections are correct; extracting parasitic parameters from the new layout that passes the LVS verification to obtain parasitic parameter information such as the resistance and capacitance of the wiring; generating a new parasitic netlist file based on the extracted parasitic parameters to obtain a netlist description containing parasitic parameters; comparing the newly generated parasitic netlist file with the original parasitic netlist file to analyze the changes in the netlist before and after adding the buffer; using a timing simulation tool to compare the signal integrity and timing performance metrics before and after adding the buffer to determine whether they meet the design requirements; when the performance metrics after adding the buffer do not meet the design requirements, an optimization algorithm is used to adjust the position and parameters of the buffer; then, iterative optimization is performed to find the optimal buffer position and parameter configuration; the judgment and optimization process are repeated until the signal integrity and timing performance meet the design requirements, obtaining the optimized buffer position and parameter configuration, and completing the layout optimization.

[0086] Specifically, the LVS verification ensures the design specifications of the new layout and the correctness of the device connections, while the extraction of parasitic parameters provides key information such as the resistance and capacitance of the wiring. By comparing the new and old parasitic netlist files, the impact of adding the buffer on the circuit performance can be analyzed. Using a timing simulation tool to compare the performance metrics can determine whether the design meets the standards. If the requirements are not met, the position and parameters of the buffer are adjusted through an optimization algorithm and iteratively optimized until the design standards are satisfied. This process not only improves the accuracy and reliability of the design but also ensures that the circuit achieves the best in terms of signal integrity and timing performance, thus completing high-quality layout optimization.

[0087] As described above, it is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes. However, as long as it does not depart from the content of the technical solution of the present invention, any brief modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for quickly adding buffers in high-frequency lines for post-layout simulation, characterized in that: It includes the following steps: adding metal ideal resistors to the high-speed signal lines in the schematic, and placing the metal ideal resistors at the output end, the middle section of the signal line, and the receiving end positions of the layout; It includes: obtaining the routing topology structure data and signal transmission characteristic data of the high-speed signal line as the input data of the machine learning algorithm, using the clustering algorithm to identify the key nodes of the high-speed signal line, and clustering according to the signal transmission characteristics of the nodes to obtain different types of key nodes; According to different types of key nodes, use the decision tree algorithm for analysis. According to the topological structure characteristics and signal transmission characteristics of the nodes, judge whether a buffer needs to be added; when a key node that needs to add a buffer is found, determine it as the output end, the middle section node, or the receiving end according to the position of the key node in the signal line; Group the key nodes that need to add buffers according to their position attributes to obtain the output end candidate position set, the middle section candidate position set, and the receiving end candidate position set; According to the specific routing topology structure of the high-speed signal line, optimize the positions in the candidate position set, eliminate the positions that are not suitable for adding buffers, and then use the optimized candidate position set as the final buffer addition position to output the buffer optimization scheme for the high-speed signal line; Verify the consistency of the connection of the metal ideal resistor through LVS, and then use StarRC to extract parasitic parameters to generate a parasitic netlist file; Search for the metal ideal resistor at the corresponding position in the parasitic netlist file, determine its input and output nodes, and delete the metal ideal resistor in the parasitic netlist file to generate floating nodes; In the simulation software, automatically add buffers at the corresponding positions according to the floating nodes, and perform post-layout simulation analysis. After the post-layout simulation analysis is completed, replace the resistors at the corresponding positions in the layout with buffers.

2. The method for quickly adding a buffer for post-layout simulation in a high-frequency line according to claim 1, wherein: After adding metal ideal resistors to the high-speed signal lines in the schematic and placing the metal ideal resistors at the output end, the middle section of the signal line, and the receiving end positions of the layout, it further includes: Obtain the candidate position set, and use the simulation analysis tool to simulate the circuit system after adding a buffer at this position; according to the simulation analysis results, extract the signal integrity index and timing performance index after adding the buffer; compare the extracted indexes with the preset design requirement thresholds; when both the signal integrity index and the timing performance index meet the design requirement thresholds, mark this position as a valid insertion position; When any one of the signal integrity index or the timing performance index does not meet the design requirement threshold, mark this position as an invalid insertion position; based on the marking results, screen out all valid insertion positions from the candidate position set to form a buffer insertion position scheme.

3. A method for quickly adding a buffer in a high-frequency line for post-layout simulation according to claim 2, characterized in that: According to the formed buffer insertion position scheme, obtain the routing information of the high-speed signal line in the schematic and the preset valid insertion position set; according to the routing information of the high-speed signal line, calculate the characteristic impedance and transmission delay of the signal line; use the machine learning algorithm to minimize the impact of the metal ideal resistor on signal integrity as the optimization goal to optimize the resistance value of the metal ideal resistor; When the ideal resistance value of the metal obtained by optimization meets the preset threshold condition, this resistance value is taken as the optimal resistance value; otherwise, the parameters of the optimization algorithm are adjusted and the optimization is performed again; according to the optimal resistance value, a metal ideal resistance is automatically added to the set of effective insertion positions of the high-speed signal line; through a simulation tool, signal integrity analysis is performed on the high-speed signal line after adding the metal ideal resistance to obtain signal integrity indicators.

4. A method for quickly adding a buffer in a high-frequency line for post-layout simulation according to claim 3, characterized in that: According to the position information of the metal ideal resistance in the schematic, the layout of the metal ideal resistance at the corresponding position is automatically generated in the layout. The pattern matching algorithm is used to identify the position coordinates of the metal ideal resistance. By analyzing the topological structure of the wiring around the metal ideal resistance layout, a parasitic parameter extraction model is constructed to calculate the parasitic capacitance and inductance values introduced by the metal ideal resistance layout. When the parasitic parameters introduced by the metal ideal resistance layout exceed the preset threshold, the wiring optimization process is triggered. The heuristic search algorithm is used to adjust and optimize the wiring topology and width around the metal ideal resistance under the wiring constraint conditions. Through parasitic parameter extraction and signal integrity simulation analysis of the optimized wiring scheme, it is judged whether the optimized wiring meets the design requirements. When the design requirements are met, the optimized wiring scheme is determined; otherwise, the wiring optimization process is triggered to continue the optimization. According to the determined optimized wiring scheme, the geometric parameters of the metal ideal resistance and its surrounding wiring in the layout are updated, and DRC inspection is performed on the wiring.

5. A method for quickly adding a buffer in a high-frequency line for post-layout simulation according to claim 1, characterized in that: Verify the connection consistency of the metal ideal resistance through LVS, and then use StarRC to extract parasitic parameters to generate a parasitic netlist file, including: According to the frequency characteristics of the high-speed signal, set the extraction accuracy and frequency range of StarRC, analyze the parasitic parameter netlist extracted by StarRC, and judge whether the influence of the metal ideal resistance on the high-speed signal is within the range. When the signal attenuation and delay introduced by the metal ideal resistance exceed the design index, the layout and connection method of the metal ideal resistance need to be optimized. By shortening the length of the metal ideal resistance and increasing the width of the metal ideal resistance, the parasitic parameter value of the metal ideal resistance is reduced, and LVS verification and StarRC extraction are performed again until the parasitic parameters of the metal ideal resistance meet the design requirements for high-speed signal transmission.

6. A method for quickly adding a buffer in a high-frequency line for post-layout simulation according to claim 1, characterized in that: Search for the metal ideal resistance at the corresponding position in the parasitic netlist file, determine its input and output nodes, and delete the metal ideal resistance in the parasitic netlist file to generate floating nodes, including: According to the parasitic netlist file, use text parsing technology to search for and locate the input and output node information of the metal ideal resistance, and judge the nodes connected to both ends of the metal ideal resistance. When a node is only connected to the metal ideal resistance, this node is a floating node and is marked as a node to be processed. Delete the metal ideal resistance information in the netlist file while retaining the floating node information to obtain the netlist topological structure after deleting the metal ideal resistance. According to the netlist topological structure after deleting the metal ideal resistance, use the graph theory algorithm to identify the floating nodes and judge their connection relationship with other devices. By analyzing the connection method between the floating nodes and other device nodes, determine the positions where buffers need to be added, establish virtual connections, and use the depth-first search algorithm to traverse the netlist topology structure, obtain the path changes before and after adding buffers, and evaluate the delay impact; According to the delay evaluation results, determine the optimal buffer addition scheme, generate the netlist file after adding buffers, and complete the elimination of floating nodes and connection repair.

7. A method for quickly adding a buffer in a high-frequency line for post-layout simulation according to claim 1, characterized in that: After the post-layout simulation analysis is completed, replace the resistors at the corresponding positions in the layout with buffers, including: obtaining the position coordinate information of the metal ideal resistors that need to be replaced and modified according to the post-layout simulation analysis results, locating the corresponding metal ideal resistors in the layout through the position coordinate information, and then according to the circuit design specifications, using the look-up table algorithm to obtain the buffer parameters that are close to the resistance value of the original metal ideal resistor and meet the design requirements from the preset resistor parameter table; according to the obtained buffer parameters, use the circuit construction algorithm to generate a new metal ideal resistor circuit structure containing buffers, and replace the new metal ideal resistor circuit structure at the position of the original metal ideal resistor in the layout to obtain a new layout containing buffers.

8. A method for quickly adding a buffer for post-layout simulation in a high-frequency line according to claim 7, characterized in that: After the post-layout simulation analysis is completed, replacing the resistors at the corresponding positions in the layout with buffers also includes: then using an intelligent layout algorithm based on deep learning, extracting the layout features of the new layout through a convolutional neural network, comparing them with the preset optimal layout features, obtaining the difference information between the new layout and the optimal layout, and according to the difference information, using a reinforcement learning algorithm to continuously adjust the positions and connections of the buffers and metal ideal resistors in the new layout to minimize the area increase caused by the buffers and obtain an optimized new layout.

9. A method for quickly adding a buffer to a high-frequency line for post-layout simulation according to claim 8, characterized in that: After obtaining the optimized new layout, it also includes: performing LVS verification on the new layout, then extracting parasitic parameters from the new layout that passes the LVS verification to obtain the parasitic parameter information of the wiring; generating a new parasitic netlist file according to the extracted parasitic parameters to obtain a netlist description containing parasitic parameters; comparing the newly generated parasitic netlist file with the original parasitic netlist file to analyze the changes in the netlist before and after adding buffers; using a timing simulation tool to compare the signal integrity and timing performance indicators before and after adding buffers to determine whether they meet the design requirements; when the performance indicators after adding buffers do not meet the design requirements, use an optimization algorithm to adjust the positions and parameters of the buffers; then find the best buffer position and parameter configuration through iterative optimization; repeat the judgment and optimization process until the signal integrity and timing performance meet the design requirements, obtain the optimized buffer position and parameter configuration, and complete the layout optimization.

Images