Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a winding avoiding area, a wiring area and a winding setting area located in the wiring area. The array substrate further comprises a substrate body and a plurality of pixel driving circuits arranged on the substrate body. The array substrate comprises at least one first signal line and at least one second signal line which extend in the first direction and are arranged in the second direction. The first signal line comprises a first winding section located in the winding setting area, and the second signal line comprises a second winding section located in the winding setting area; wherein the orthographic projection of the first winding section and the orthographic projection of the second winding section which are overlapped in the conduction level transmission stage on the substrate are not overlapped, the first direction intersects with the second direction, and the polarity of the conduction level of the threshold compensation module is opposite to that of the conduction level of the data write-in module. The phenomenon of uneven display of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of display technology, the application of array substrates is becoming more and more extensive, and correspondingly, the requirements for array substrates are becoming higher and higher.

[0003] However, the display panel made of the array substrate in the related art is prone to display unevenness (mura), which affects the display effect. Summary of the invention

[0004] The invention provides an array substrate and a display panel to improve the phenomenon of uneven display of the display panel.

[0005] According to one aspect of the present invention, there is provided an array substrate, the array substrate comprising a winding avoidance area, a wiring area at least partially surrounding the winding avoidance area, and a winding arrangement area located between the wiring area and the winding avoidance area;

[0006] The array substrate further comprises a substrate and at least one pixel driving circuit disposed on the substrate, wherein the pixel driving circuit comprises a data writing module and a threshold compensation module;

[0007] The array substrate comprises at least one first signal line and at least one second signal line extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line comprises a first winding segment located in the winding setting area, and the second signal line comprises a second winding segment located in the winding setting area;

[0008] The orthographic projections of the first winding segment and the second winding segment, whose transmission conduction level stages overlap, on the substrate do not overlap, the first direction intersects with the second direction, and the polarities of the conduction levels of the threshold compensation module and the data writing module are opposite.

[0009] Optionally, the first signal line is used to control the conduction state of the threshold compensation module, and the second signal line is used to control the conduction state of the data writing module; the stage in which the first signal line transmits the conduction level includes N1 stages, and the stage in which the second signal line transmits the conduction level includes one stage; N1≥2;

[0010] Preferably, the orthographic projections of the first winding segment and the second winding segment corresponding to the pixel driving circuits in the same row on the substrate do not overlap; the orthographic projections of the first winding segment corresponding to the pixel driving circuits in the kth row and the second winding segment corresponding to the pixel driving circuits in the k+N2th row on the substrate partially overlap; N2≥N1;

[0011] Preferably, N2 is equal to N1;

[0012] Preferably, the first signal line includes a first straight line segment located in the wiring area, and the second signal line includes a second straight line segment located in the wiring area;

[0013] Preferably, the orthographic projections of the first winding segment whose stages of partial transmission conduction levels do not overlap with those of the second winding segment on the substrate partially overlap.

[0014] Optionally, in the winding setting area, projections of the first N2 first winding segments and any second winding segment on the substrate do not overlap;

[0015] The array substrate further includes N2 first compensation signal lines;

[0016] The N2 first compensation signal lines correspond to the first N2 first winding segments, and along the thickness direction of the array substrate, the first compensation signal lines partially overlap with the orthographic projections of the corresponding first winding segments on the substrate;

[0017] Preferably, the first compensation signal line and the second winding segment are in the same layer.

[0018] Optionally, the first compensation signal line is connected to a first fixed potential;

[0019] Preferably, the array substrate comprises at least one first power signal line, and the first power signal line is used to provide a first power signal for the pixel driving circuit; the N2 first compensation signal lines are connected to one of the first power signal lines;

[0020] Preferably, the first ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line;

[0021] Preferably, the second ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line.

[0022] Optionally, the first winding segment is arranged on a side of the second winding segment away from the substrate;

[0023] The array substrate also includes at least one third signal line extending along the first direction and arranged along the second direction, the third signal line is connected to the pixel driving circuit, and the third signal line includes a third winding segment located in the winding setting area; along the thickness direction of the array substrate, the first N2 first winding segments and any of the third winding segments do not overlap in their orthographic projection on the substrate.

[0024] Optionally, in the winding setting area, the orthographic projections of the last N2 second winding segments and any of the first winding segments on the substrate do not overlap;

[0025] The array substrate further includes N2 second compensation signal lines;

[0026] The N2 second compensation signal lines correspond to the N2 second winding segments, and along the thickness direction of the array substrate, the second compensation signal lines overlap with the orthographic projections of the corresponding second winding segments on the substrate;

[0027] Preferably, the second compensation signal line and the first winding segment are in the same layer.

[0028] Optionally, the N2 second compensation signal lines are connected to a first fixed potential;

[0029] Preferably, the array substrate comprises at least one first power signal line, and the first power signal line is used to provide a first power signal for the pixel driving circuit; the N2 second compensation signal lines are connected to the first power signal line;

[0030] Preferably, the first ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line;

[0031] Preferably, the second ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line.

[0032] Optionally, the array substrate further includes at least one data line, at least one light emitting control signal line and at least one first power signal line;

[0033] The pixel driving circuit further includes a driving module, a first light emitting control module, a second light emitting control module and a first initialization module;

[0034] The first end of the data writing module is electrically connected to the data line, the second end of the data writing module is electrically connected to the first end of the driving module, and the control end of the data writing module is electrically connected to the first signal line or the second signal line;

[0035] The first end of the first light control module is electrically connected to the first power signal line, the second end of the first light control module is electrically connected to the first end of the driving module, and the control end of the first light control module is electrically connected to the light control signal line;

[0036] The first end of the threshold compensation module is electrically connected to the second end of the driving module, the second end of the threshold compensation module is electrically connected to the control end of the driving module, and the control end of the threshold compensation module is electrically connected to the first signal line or the second signal line;

[0037] The first end of the second light emitting control module is electrically connected to the second end of the driving module, the second end of the second light emitting control module is used to connect to the light emitting structure, and the control end of the second light emitting control module is electrically connected to the light emitting control signal line;

[0038] Preferably, the data writing module and the threshold compensation module have transistor types different from each other;

[0039] Preferably, the pixel driving circuit also includes a storage module, a first initialization module, a second initialization module and a third initialization module; the array substrate also includes a first initialization signal line, a first scan signal line, a second initialization signal line, a third initialization signal line and a second scan signal line; the first end of the storage module is electrically connected to the first power signal line, and the second end of the storage module is electrically connected to the control end of the driving module; the first end of the first initialization module is electrically connected to the first initialization signal line, the second end of the first initialization module is electrically connected to the first end of the threshold compensation module, and the control end of the first initialization module is electrically connected to the first scan signal line; the first end of the second initialization module is electrically connected to the second initialization signal line, the second end of the second initialization module is electrically connected to the first end of the light-emitting structure, and the control end of the second initialization module is electrically connected to the second scan signal line; the first end of the third initialization module is electrically connected to the third initialization signal line, the second end of the third initialization module is electrically connected to the second end of the driving module, and the control end of the third initialization module is electrically connected to the second scan signal line.

[0040] Optionally, the array substrate includes a driving circuit layer arranged on the substrate, and the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; wherein the active structure of the data writing module is arranged on the active layer, the gate of the data writing module is arranged on the first conductive layer, and the source and drain of the data writing module are arranged on the fourth conductive layer; the gate of the threshold compensation module is arranged on the third conductive layer, and the source and drain of the threshold compensation module are arranged on the fourth conductive layer;

[0041] Preferably, the first signal line is disposed in the third conductive layer, and the second signal line is disposed in the first conductive layer.

[0042] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate as described above.

[0043] The technical solution of the embodiment of the present invention adopts an array substrate including an array substrate including a winding avoidance area, a wiring area at least partially surrounding the winding avoidance area, and a winding setting area located between the wiring area and the winding avoidance area; the array substrate also includes a substrate and at least one pixel driving circuit arranged on the substrate, the pixel driving circuit includes a data writing module and a threshold compensation module; the array substrate includes at least one first signal line and at least one second signal line extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line includes a first winding segment located in the winding setting area, and the second signal line includes a second winding segment located in the winding setting area; wherein the first winding segment and the second winding segment whose stages of transmission conduction level overlap do not overlap in their orthographic projections on the substrate; the first winding segment and the second winding segment whose stages of partial transmission conduction level do not overlap in their orthographic projections on the substrate partially overlap in their orthographic projections; wherein the first direction intersects with the second direction, and the polarity of the conduction level of the threshold compensation module is opposite to that of the data writing module. By setting the first winding segment and the second winding segment of the pixel driving circuit that overlap in stages corresponding to the conduction level to be non-overlapping, when one of the overlapping first winding segment and the second winding segment is at the conduction level, the other is at the off level, that is, the polarities of the two are the same, thereby avoiding the reduction of signal quality due to coupling of different polarities, and further avoiding the problem of uneven display caused by a decrease in the charging rate.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0047] Figure 2 for Figure 1 A partial enlarged view of

[0048] Figure 3 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention;

[0049] Figure 4 for Figure 3 The corresponding timing diagram;

[0050] Figure 5 for Figure 1 Cross-section of the middle wiring area;

[0051] Figure 6 for Figure 2 Sectional view along direction A1A2;

[0052] Figure 7 for Figure 2 Sectional view along direction A3A4;

[0053] Figure 8 for Figure 2 Sectional view along A5A6 direction;

[0054] Fig. 9 for Figure 2 Sectional view along A7A8 direction;

[0055] Fig.10 for Figure 2 Another cross-sectional view along the A1A2 direction;

[0056] Fig.11 is a circuit connection diagram of a first compensation signal line;

[0057] Fig.12 for Figure 2 Another cross-sectional view along the A7A8 direction;

[0058] Fig.13 is a circuit connection diagram of a second compensation signal line;

[0059] Fig.14 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0060] Fig.15 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] Just as the display panel in the related art has the problem of uneven display, the inventors have found through extensive research that the reason for this technical problem is that when the display panel is provided with a hole-punch area, the signal lines in the display panel need to bypass the hole-punch area, which makes the signal lines near the hole-punch area denser. Some signal lines overlap, and the signals are coupled with each other. This in turn affects the driving of the pixel driving circuit, resulting in the mura phenomenon.

[0064] In view of the above technical problems, the present invention proposes the following solutions:

[0065] Figure 1 A schematic diagram of the structure of an array substrate provided by an embodiment of the present invention, Figure 2 for Figure 1 For a partial enlarged view, see Figure 1 and Figure 2In this embodiment, the array substrate includes a winding avoidance area HO, a wiring area AA1 surrounding the winding avoidance area HO, and a winding setting area AA2 located between the wiring area AA1 and the winding avoidance area HO; the array substrate also includes a substrate and a plurality of pixel driving circuits arranged on the substrate, the pixel driving circuit includes a data writing module and a threshold compensation module; the array substrate includes a plurality of first signal lines SN2 and a plurality of second signal lines SP1 extending along a first direction X and arranged along a second direction Y; one of the first signal line SN2 and the second signal line SP1 is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line SN2 includes The first signal line SP1 includes a first winding segment SN2a located in the winding setting area AA2, and the second signal line SP1 includes a second winding segment SP1a located in the winding setting area AA2; wherein, the first winding segment SN2a and the second winding segment SP1a whose stages of transmission conduction levels overlap do not overlap in their orthographic projections on the substrate; the first winding segment SN2a and the second winding segment SP1a whose stages of partial transmission conduction levels do not overlap in their orthographic projections on the substrate partially overlap; wherein, the first direction X intersects with the second direction Y, and the polarities of the conduction levels of the threshold compensation module and the data writing module are opposite. It should be noted that the overlapping of the transmission conduction level stages recorded in the present application can be understood as overlapping of signals during the transmission conduction level.

[0066] Specifically, the array substrate can be used to form a display panel after the light-emitting structure is evaporated thereon and the packaging layer is made. The winding avoidance area HO of the array substrate is not used to set various signal lines (such as scan lines, data lines, power lines, etc.) for driving pixel circuits. The winding avoidance area HO has a high light transmittance and can be used to set optical devices such as image acquisition and cases or infrared sensor elements. Exemplarily, the winding avoidance area HO can be a hole-digging area; the winding avoidance area HO can also be a part of the light-emitting structure, so that the display panel can achieve a full-screen display effect. The shape of the winding avoidance area HO can be circular, square, triangular or other polygons. The position of the winding avoidance area HO in the array substrate can be above or below. The wiring area AA1 of the array substrate can be understood as the main display area. A plurality of pixel driving circuits and a plurality of signal lines are arranged in the wiring area AA1. The signal lines are used to drive the pixel driving circuits. The signal lines include scan lines, data lines and power lines, etc., wherein the scan lines include first signal lines SN2 and second signal lines SP1. In this embodiment, the first signal line SN2 and the second signal line SP1 refer to the scanning lines whose extension direction intersects with the winding avoidance area HO. It can be understood that, for the convenience of explanation, the scanning lines in the array substrate whose extension direction does not intersect with the winding avoidance area HO are not defined as the first signal line SN2 or the second signal line SP1, and there are multiple scanning lines with the same function as the first signal line SN2 or the second signal line SP1. In this embodiment, the first direction X is, for example, the row direction, and the second direction Y is, for example, the column direction. Each first signal line SN2 is connected to a row of pixel driving circuits, and each second signal line SP1 is connected to a row of pixel driving circuits, and each row of pixel driving circuits is also correspondingly connected to a first signal line SN2 and a second signal line SP1. And the first signal line SN2 bypasses the winding avoidance area HO through the first winding segment SN2a located in the winding setting area AA2, and the second signal line SP1 bypasses the winding avoidance area HO through the second winding segment SP1a located in the winding setting area AA1. The shape of the winding segment can be a broken line; or it can follow the shape of the winding avoidance area HO, that is, when the shape of the winding avoidance area HO is circular, the shape of the winding segment is an arc. It can be understood that the winding setting area AA2 can also be provided with a pixel driving circuit and / or a light emitting structure.

[0067] The data writing module in the pixel driving circuit is used to write the data voltage into the driving module in the pixel driving circuit, and the threshold compensation module is used to compensate the threshold voltage of the driving module. In the charging stage of the pixel driving circuit, the data writing module and the threshold compensation module need to be turned on at the same time to complete the writing of the data voltage and the compensation of the threshold voltage. And the polarity of the on-level of the data writing module and the threshold compensation module is opposite, that is, if the on-level of the data writing module is low, the on-level of the threshold compensation module is high; at the same time, the polarity of the off-level of the data writing module and the threshold compensation module is also opposite, that is, if the off-level of the data writing module is high, the off-level of the threshold compensation module is low.

[0068] There are many signal lines in the winding setting area AA2. In order to reduce the area of ​​the winding setting area AA2, the signal lines can be overlapped, that is, the orthographic projections of the signal lines on the substrate are overlapped. It can be understood that the overlap of two signal lines will form a coupling capacitor, and the closer to the winding avoidance area, the larger the coupling capacitor. For the pixel driving circuit driven simultaneously, if the corresponding first winding segment SN2a overlaps with the corresponding second winding segment SP1a, then when the pixel driving circuit is driven, the first winding segment SN2a and the second winding segment SP1a are both at the on level, and the polarities of the two on levels are opposite. The mutual coupling through the coupling capacitor will affect the quality of the on signal, thereby affecting the on state of the corresponding module, making the data voltage charging rate lower than the corresponding data voltage charging rate of the normal scanning line, and finally causing uneven display, resulting in poor display effect. In this embodiment, the first winding segment SN2a and the second winding segment SP1a, which overlap in the stage of transmitting the on-level, do not overlap. Then, when one of the signal lines is at the on-level, the other signal line is at the off-level. Since the polarities of the on-levels of the data writing module and the threshold compensation module are opposite, the on-level of one of them is the same as the off-level polarity of the other, that is, the level polarity on the overlapping first signal line SN2a and the second signal line SP1a is the same, both are high level or both are low level, thus avoiding the problem of signal quality degradation caused by mutual coupling and improving the display unevenness phenomenon.

[0069] In addition, since the first winding segment SN2a whose stages of partial transmission conduction levels do not overlap with the corresponding second winding segment SP1a in their orthographic projections on the substrate partially overlap, the area of ​​the winding setting area AA2 can be greatly reduced, allowing the array substrate to achieve a higher pixel density.

[0070] The technical solution of this embodiment adopts an array substrate including an array substrate including a winding avoidance area, a wiring area surrounding the winding avoidance area, and a winding setting area located between the wiring area and the winding avoidance area; the array substrate also includes a substrate and a plurality of pixel driving circuits arranged on the substrate, the pixel driving circuit includes a data writing module and a threshold compensation module; the array substrate includes a plurality of first signal lines and a plurality of second signal lines extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line includes a first winding segment located in the winding setting area, and the second signal line includes a second winding segment located in the winding setting area; wherein the first winding segment and the second winding segment whose stages of transmission conduction level overlap do not overlap in their orthographic projections on the substrate; the first winding segment and the second winding segment whose stages of partial transmission conduction level do not overlap in their orthographic projections on the substrate partially overlap in their orthographic projections; wherein the first direction intersects with the second direction, and the polarity of the conduction level of the threshold compensation module is opposite to that of the data writing module. By setting the first winding segment and the second winding segment of the pixel driving circuit that overlap in stages corresponding to the conduction level to be non-overlapping, when one of the overlapping first winding segment and the second winding segment is at the conduction level, the other is at the off level, that is, the polarities of the two are the same, thereby avoiding the reduction of signal quality due to coupling of different polarities, and further avoiding the problem of uneven display caused by a decrease in the charging rate.

[0071] The above is the core idea of ​​the present invention. To facilitate the subsequent description, the structure of the pixel driving circuit and the film layer structure of the array substrate are briefly described below. Figure 3 and Figure 4 As shown, Figure 3 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention, Figure 4 for Figure 3 The corresponding timing diagram is: Figure 5 for Figure 1 Cross-sectional view of the wiring area, see Figures 3 to 5The pixel driving circuit includes a driving module 801, a data writing module 802, a threshold compensation module 803, a first initialization module 804, a first light-emitting control module 805, a second light-emitting control module 806, a second initialization module 807, a third initialization module 808 and a storage module 809; a first end of the data writing module 802 is electrically connected to the data line Data, a second end of the data writing module 802 is electrically connected to a first end of the driving module 801, a control end of the data writing module 802 is electrically connected to a first signal line SN2 or a second signal line SP1, and in this embodiment, the second signal line SP1 is used to control the data writing module, and the first signal line SN2 is used to control the data writing module. Taking the control threshold compensation module as an example, the control end of the data writing module 802 is electrically connected to the second signal line SP2; the first end of the first light-emitting control module 805 is electrically connected to the first power signal line ELVDD, the second end of the first light-emitting control module 805 is electrically connected to the first end of the driving module 801, and the control end of the first light-emitting control module 805 is electrically connected to the light-emitting control signal line EM; the first end of the threshold compensation module 803 is electrically connected to the second end of the driving module 801, the second end of the threshold compensation module 803 is electrically connected to the control end of the driving module 801, and the control end of the threshold compensation module 803 is electrically connected to the first signal line SN2; the second light-emitting control module 805 is electrically connected to the first power signal line ELVDD, the second end of the first light-emitting control module 805 is electrically connected to the first end of the driving module 801, and the control end of the threshold compensation module 803 is electrically connected to the first signal line SN2; The first end of the control module 806 is electrically connected to the second end of the driving module 801, the second end of the second light-emitting control module 806 is used to connect the light-emitting structure 810, and the control end of the second light-emitting control module 806 is electrically connected to the light-emitting control signal line EM; the first end of the storage module 809 is electrically connected to the first power signal line ELVDD, and the second end of the storage module 809 is electrically connected to the control end of the driving module 801; the first end of the first initialization module 804 is electrically connected to the first initialization signal line Vrefn1, the second end of the first initialization module 804 is electrically connected to the first end of the threshold compensation module 803, and the control end of the first initialization module 804 is electrically connected to the first scanning signal line Vrefn1. The signal line SN1 is electrically connected; the first end of the second initialization module 807 is electrically connected to the second initialization signal line Vrefn2, the second end of the second initialization module 807 is electrically connected to the first end of the light-emitting structure 810, and the control end of the second initialization module 807 is electrically connected to the second scanning signal line SP2; the first end of the third initialization module 808 is electrically connected to the third initialization signal line Vrefp, the second end of the third initialization module 808 is electrically connected to the second end of the driving module 801, the control end of the third initialization module 808 is electrically connected to the second scanning signal line SP2, and the second end of the light-emitting structure 810 is electrically connected to the second power supply signal line ELVSS.

[0072] The operation process of the pixel driving circuit may include an initialization phase t1 , a charging phase t2 , and a light emitting phase t3 .

[0073] In the initialization stage t1, the first scanning signal line SN1 controls the first initialization module 804 to be turned on, the first signal line SN2 controls the threshold compensation module 803 to be turned on, and the initialization signal on the first initialization signal line Vrefn1 initializes the control end of the driving module 801. The second scanning signal line SP2 controls the second initialization module 807 and the third initialization module 808 to be turned on, the second initialization signal line Vrefn2 initializes the light-emitting structure, and the third initialization signal line Vrefp initializes the second end of the driving module 801.

[0074] In the charging stage t2, the second signal line SP2 controls the data writing module 802 to be turned on, the first signal line SN2 controls the threshold compensation module 803 to be turned on, and the data voltage on the data line Data is written to the control end of the driving module 801 through the data writing module 802, the driving module 801 and the threshold compensation module 803. When the potential difference between the first end and the control end of the driving module 801 is the threshold voltage of the driving module 801, the driving module 801 is turned off. In this stage, the threshold compensation process of the driving module 801 is completed.

[0075] In the light-emitting stage t3, the light-emitting control signal line EM controls the first light-emitting control module 804 and the second light-emitting control module 805 to be turned on. The driving module 801 generates a driving current, the storage module 809 maintains the potential of the control end of the driving module 801, and the driving current is transmitted to the light-emitting structure 810, and the light-emitting structure 810 emits light in response to the driving current. Optionally, in the light-emitting stage t3, the second scanning signal line SP2 and the light-emitting control signal line EM have opposite polarities and are periodically turned on, so that the light-emitting structure is periodically initialized and emits light, which can further improve the display effect.

[0076] From the above analysis, it can be known that the stages of transmitting the conduction level on the first signal line SN2 are the initialization stage t1 and the charging stage t2. Due to the row scanning driving mode, the initialization stage t1 of the current row is the charging stage t2 of the previous row. Therefore, in this embodiment, the conduction level of the first signal line SN2 overlaps with the conduction level of the second signal line SP1 corresponding to the current row and also overlaps with the conduction level of the second signal line SP1 of the previous row.

[0077] Exemplarily, the driving module 801 includes a first transistor T1 , a first end of the first transistor T1 serves as a first end of the driving module 801 , a second end of the first transistor T1 serves as a second end of the driving module 801 , and a control end of the first transistor T1 serves as a control end of the driving module 801 .

[0078] The data writing module 802 includes a second transistor T2 , a first end of the second transistor T2 serves as the first end of the data writing module 802 , a second end of the second transistor T2 serves as the second end of the data writing module 802 , and a control end of the second transistor T2 serves as the control end of the data writing module 802 .

[0079] The threshold compensation module 803 includes a third transistor T3 , a first end of the third transistor T3 serves as the first end of the threshold compensation module 803 , a second end of the third transistor T3 serves as the second end of the threshold compensation module 803 , and a control end of the third transistor T3 serves as the control end of the threshold compensation module 803 .

[0080] The first initialization module 804 includes a fourth transistor T4, a first end of the fourth transistor T4 serves as the first end of the first initialization module 804, a second end of the fourth transistor T4 serves as the second end of the first initialization module 804, and a control end of the fourth transistor T4 serves as the control end of the first initialization module 804.

[0081] The first light emitting control module 805 includes a fifth transistor T5, a first end of the fifth transistor T5 serves as the first end of the first light emitting control module 805, a second end of the fifth transistor T5 serves as the second end of the first light emitting control module 805, and a control end of the fifth transistor T5 serves as the control end of the first light emitting control module 805.

[0082] The second light emitting control module 806 includes a sixth transistor T6, a first end of the sixth transistor T6 serves as the first end of the second light emitting control module 806, a second end of the sixth transistor T6 serves as the second end of the second light emitting control module 806, and a control end of the sixth transistor T6 serves as the control end of the second light emitting control module 806.

[0083] The second initialization module 807 includes a seventh transistor T7, a first end of the seventh transistor T7 serves as the first end of the second initialization module 807, a second end of the seventh transistor T7 serves as the second end of the second initialization module 807, and a control end of the seventh transistor T7 serves as the control end of the second initialization module 807.

[0084] The third initialization module 808 includes an eighth transistor T8, a first end of the eighth transistor T8 serves as a first end of the third initialization module 808, a second end of the eighth transistor T8 serves as a second end of the third initialization module 808, and a control end of the eighth transistor T8 serves as a control end of the third initialization module 808.

[0085] The storage module 809 includes a storage capacitor Cst, a first end of the storage capacitor Cst serves as a first end of the storage module 809 , and a second end of the storage capacitor Cst serves as a second end of the storage module 809 .

[0086] Among the above transistors, the transistor type of the third transistor T3 is different from the transistor type of the second transistor T2. Further, the third transistor T3 and the fourth transistor T4 can be N-type transistors, such as indium gallium zinc oxide transistors; the remaining transistors can be P-type transistors, such as polysilicon or monocrystalline silicon transistors.

[0087] like Figure 5 As shown, the array substrate includes a substrate Sub, a driving circuit layer and a pixel defining layer PDL stacked in sequence. A first buffer layer Buf1 may also be provided between the substrate Sub and the driving circuit layer. The driving circuit layer specifically includes an active layer Act, a first conductive layer M1, a second conductive layer M2, an indium gallium zinc oxide layer IGZO, a third conductive layer GATO, a fourth conductive layer M3 and a fifth conductive layer M4 stacked in sequence. The active layer Act is used to set the active structure of the P-type transistor, the first conductive layer M1 is used to set the gate of the P-type transistor and the second end of the storage capacitor; the second conductive layer M2 is used to set the first end of the storage capacitor; the indium gallium zinc oxide layer IGZO is used to set the active structure of the N-type transistor; the third conductive layer GATO is used to set the gate of the N-type transistor; the fourth conductive layer M3 is used to set the source and drain of each transistor; the fifth conductive layer M4 can be used to set the data line, etc. A first gate insulating layer GI1 is also provided between the active layer Act and the first conductive layer M1, an interlayer insulating layer CI is provided between the first conductive layer M1 and the second conductive layer M2, a second buffer layer Buf2 is provided between the second conductive layer M2 and the indium gallium zinc oxide layer IGZO, a second gate insulating layer GI2 is provided between the indium gallium zinc oxide layer IGZO and the third conductive layer GATO, an inorganic layer ILD is provided between the third conductive layer GATO and the fourth conductive layer M3, and a first planarization layer PLN1 is provided between the fourth conductive layer M3 and the fifth conductive layer M4. A second planarization layer PLN2 is provided between the fifth conductive layer M4 and the pixel defining layer PDL, the pixel defining layer PDL defines a plurality of openings, a light emitting structure is provided in the opening, and the light emitting structure is connected to the pixel driving circuit through the corresponding anode Ano.

[0088] Optionally, the first signal line SN2 is used to control the conduction state of the threshold compensation module, and the second signal line is used to control the conduction state of the data writing module; the stage in which the first signal line SN2 transmits the conduction level includes N1 stages, and the stage in which the second signal line SP1 transmits the conduction level includes one stage; N1≥2.

[0089] Specifically, the stages described in this embodiment include an initialization stage, a charging stage, and a light-emitting stage. When the threshold compensation module is turned on only in the charging stage, N1 is equal to 2; and when the threshold compensation module is turned on in both the charging stage and the initialization stage, N1 is greater than 2; the data writing module is turned on only in the charging stage.

[0090] Optionally, Figure 6 for Figure 2 The cross-section along the A1A2 direction, Figure 7 for Figure 2 The cross-section along the A3A4 direction, Figure 8 for Figure 2 Cross-sectional view along A5A6 direction, Fig. 9 for Figure 2 Cross-sectional view along A7A8 direction, combined with Figure 2 , Figures 6 to 9 The orthographic projections of the first winding segment SN2a and the corresponding second winding segment SP1a corresponding to the pixel driving circuits in the same row on the substrate Sub do not overlap; the orthographic projections of the first winding segment SN2a corresponding to the pixel driving circuits in the kth row and the second winding segment SP1a corresponding to the pixel driving circuits in the k+N2th row on the substrate Sub partially overlap; N2≥N1, it should be noted that k here can be a positive integer greater than or equal to 1.

[0091] Specifically, in this embodiment, taking N1 as 2 as an example, the pixel driving circuit performs row scanning driving in the order from the first row to the last row. At this time, the stage of the first signal line SN2 transmitting the conduction level not only overlaps with the stage of the second signal line SP1 corresponding to the current row transmitting the conduction level, but also overlaps with the stage of the second signal line SP1 transmitting the conduction level in the previous row. The stage of the first signal line SN2 of the kth row and the stage of the second signal line SP1 transmitting the conduction level of the k+N1th row and before do not overlap. Therefore, the setting of this embodiment makes it possible for the overlapping first signal line SN2 and second signal line SP1 not to transmit the conduction level at the same time, thereby improving the phenomenon of uneven display.

[0092] The arrangement of this embodiment, relative to the overlapping arrangement of the first signal line SN2 and the second signal line SP1 corresponding to the same row of pixel driving circuits, can be understood as moving the first signal line SN2 forward as a whole by N2 rows.

[0093] Optionally, N2 is equal to N1. This configuration makes the overall forward movement distance of the first signal line SN2 smaller, which is convenient for wiring and does not make the area of ​​the winding setting area AA2 too large.

[0094] Alternatively, if Figure 1 As shown, the portion of the first signal line SN2 located in the wiring area AA1 can be understood as a first straight line segment, and the portion of the second signal line SP1 located in the wiring area AA1 can be understood as a second straight line segment.

[0095] It should be noted that Figure 6 In the example, the first winding segment SN2a and the first second winding segment SP1a are numbered M, and Figures 6 to 9Although the signal lines are numbered in ascending order (i.e., SN2a(M)-SN2a(M+9), SP1a(M)-SP1a(M+9)), Figure 6 and Figure 7 , Figure 8 and Fig. 9 Corresponding to Figure 2 A plurality of first signal lines and second signal lines are also arranged between the positions.

[0096] Optionally, in the above embodiment, the first winding segment SN2a is disposed in the third conductive layer GATO, and the second winding segment SP1a is disposed in the first conductive layer M1. The first scan signal line SN1 may be disposed in the second conductive layer M2, and the light emitting control signal line EM and the second scan signal line SP2 may be disposed in the fourth conductive layer M3. The light emitting control signal line EM and the second scan signal line SP2 may be arranged alternately.

[0097] Depend on Figure 6 and Fig. 9 It can be seen that the first winding segment SN2a of this embodiment is moved forward by two rows, and the first first winding segment SN2a(M) and the second first winding segment SN2a(M+1) do not overlap with any second winding segment SP1; while the other first winding segments SN2a overlap with one second winding segment SP1a, that is, there is an overlapping capacitor. When displaying, the first first winding segment SN2a(M) and the second first winding segment SN2a(M+1) have a problem of missing overlapping capacitors, which affects display uniformity. Similarly, the last N2 second winding segments SP1a also have a problem of missing overlapping capacitors, which affects display uniformity.

[0098] Therefore, optionally, Fig.10 for Figure 2 Another cross-sectional view along the A1A2 direction, see Figure 2 and Fig.10 In the winding setting area, the projections of the first N2 first winding segments SN2a and any second winding segment SP1a on the substrate Sub do not overlap; the array substrate further includes N2 first compensation signal lines Comp1; the N2 first compensation signal lines Comp1 correspond to the first N2 first winding segments one by one, and along the thickness direction of the array substrate, the first compensation signal lines Comp1 partially overlap with the orthographic projections of the corresponding first winding segments SN2a on the substrate Sub.

[0099] Specifically, the first compensation signal line Comp1 is used to form an overlapping capacitor with the corresponding first winding segment SN2a to compensate for the problem of missing overlapping capacitors. Each first winding segment SN2a forms an overlapping capacitor with a signal line (the first compensation signal line Comp1 or the second winding segment SP1a), and is affected by the overlapping capacitor during display, so the display uniformity is better. Of course, it can be understood that the overlapping capacitor formed in this embodiment does not reduce the charging rate.

[0100] Optionally, the first compensation signal line Comp1 and the second winding segment SP1a are in the same layer. This arrangement makes the distance between the first compensation signal line Comp1 and the corresponding first winding segment SN1a, and the distance between the second winding segment SP1a and the first winding segment SN1a close, and the size of the overlapped capacitance formed is also close, so that the effect on the display is also similar, which can further improve the display uniformity.

[0101] Optionally, the first compensation signal line Comp1 is connected to a fixed potential, so as to avoid the problem of unstable potential caused by the first compensation signal line Comp1 being suspended in the air, and to avoid the first compensation signal line Comp1 forming an antenna structure and affecting the signal transmission on the corresponding first winding segment SN2a.

[0102] Optionally, the array substrate includes a plurality of first power signal lines, the first power signal lines are used to provide a first power signal for the pixel driving circuit, and N2 first compensation signal lines are connected to one first power signal line.

[0103] Specifically, the first power signal line, namely Figure 3 The first power signal line ELVDD shown in FIG. By connecting the first power signal line to the first compensation signal line, a fixed first power signal can be connected to the first compensation signal line Comp1. Of course, in some other embodiments, the first compensation signal line Comp1 can also be connected to the initialization signal line or the second power signal line. It should be noted that since a fixed potential is connected to the first compensation signal line Comp1, the potential will not jump, and even if the connected potential is opposite to the polarity of the conduction level on the first signal line, the impact on the signal on the first signal line is small.

[0104] Alternatively, if Fig.11 As shown, Fig.11 This is a circuit connection diagram of the first compensation signal line, refer to Fig.11, the first ends of the N2 first compensation signal lines Comp1 are connected in series and connected to the first power signal line ELVDD, and the second ends of the N2 first compensation signal lines Comp1 are connected in series and connected to the first power signal line ELVDD. In this embodiment, the first ends of all the first compensation signal lines are connected in series, and the second ends are connected in series and connected to the first power signal line ELVDD respectively, which can not only reduce the signal voltage drop on the first compensation signal line Comp1, but also reduce the difficulty of connecting with the first power signal line ELVDD.

[0105] Optionally, the first winding segment SN2a is arranged on a side of the second winding segment SP1a away from the substrate; the array substrate also includes a plurality of third signal lines extending along the first direction X and arranged along the second direction Y, the third signal lines are connected to the pixel driving circuit, and the third signal lines include a third winding segment located in the winding setting area AA2; along the thickness direction of the array substrate, the orthographic projections of the first N2 first winding segments SN2a and any third winding segments on the substrate do not overlap.

[0106] Specifically, the third signal line described in this embodiment includes a first scanning signal line SN1, a second scanning signal line SP2, and a light-emitting control signal line EM. The first N2 first winding segments do not overlap with any third winding segment, that is, the first signal line SN2 of this embodiment is N2 rows forward relative to the pixel driving circuit of the corresponding row.

[0107] Optionally, Fig.12 for Figure 2 Another cross-sectional view along the A7A8 direction, see Figure 2 and Fig.11 In the winding setting area, the projections of the last N2 second winding segments SP1a and any first winding segment SN2a on the substrate Sub do not overlap; the array substrate further includes N2 second compensation signal lines Comp2; the N2 second compensation signal lines Comp2 correspond to the last N2 second winding segments one by one, and along the thickness direction of the array substrate, the second compensation signal lines Comp2 partially overlap with the orthographic projections of the corresponding second winding segments SP1a on the substrate Sub.

[0108] Specifically, the second compensation signal line Comp2 is used to form an overlapping capacitor with the corresponding second winding segment SP1a to compensate for the problem of missing overlapping capacitors. Each second winding segment SP1a forms an overlapping capacitor with a signal line (the second compensation signal line Comp2 or the first winding segment SN2a), and is affected by the overlapping capacitor during display, so the display uniformity is better. Of course, it can be understood that the overlapping capacitor formed in this embodiment does not reduce the charging rate.

[0109] Optionally, the second compensation signal line Comp2 is in the same layer as the first winding segment SN2a. This arrangement makes the distance between the second compensation signal line Comp2 and the corresponding second winding segment SP1a, and the distance between the second winding segment SP1a and the first winding segment SN1a close, and the size of the overlapped capacitance formed is also close, so that the effect on the display is also similar, which can further improve the display uniformity.

[0110] Optionally, the second compensation signal line Comp2 is connected to a fixed potential, so as to avoid the problem of unstable potential caused by the second compensation signal line Comp2 being suspended in the air, and to avoid the second compensation signal line Comp2 forming an antenna structure and affecting the signal transmission on the corresponding second winding segment SP1a.

[0111] Optionally, the array substrate includes a plurality of first power signal lines, the first power signal lines are used to provide a first power signal for the pixel driving circuit, and N2 second compensation signal lines are connected to one first power signal line.

[0112] Specifically, the first power signal line, namely Figure 3 The first power signal line ELVDD shown in FIG. By connecting the first power signal line to the second compensation signal line, a fixed first power signal can be connected to the second compensation signal line Comp2. Of course, in some other embodiments, the second compensation signal line Comp2 can also be connected to the initialization signal line or the second power signal line. It should be noted that since a fixed potential is connected to the second compensation signal line Comp2, the potential will not jump, and even if the connected potential is opposite to the polarity of the conduction level on the first signal line, the impact on the signal on the first signal line is small.

[0113] Alternatively, if Fig.13 As shown, Fig.13 This is the circuit connection diagram of the second compensation signal line, refer to Fig.11 , the first ends of N2 second compensation signal lines Comp2 are connected in series and connected to the first power signal line ELVDD, and the second ends of N2 second compensation signal lines Comp2 are connected in series and connected to the first power signal line ELVDD. In this embodiment, the first ends of all second compensation signal lines are connected in series, and the second ends are connected in series and connected to the first power signal line ELVDD respectively, which can not only reduce the signal voltage drop on the second compensation signal line Comp2, but also reduce the difficulty of connecting with the first power signal line ELVDD.

[0114] Optionally, in the above embodiment, although the first winding segment SN2a is moved forward by two rows as a whole, in some other embodiments, the second winding segment SP1a may be moved back by two rows. Alternatively, the first winding segment SN2a may be moved back by at least one row, or the second winding segment SP1a may be moved forward by at least one row to achieve the effect that the orthographic projections of the first winding segment and the second winding segment, which overlap in the stage of the transmission conduction level, on the substrate do not overlap.

[0115] The embodiment of the present invention further provides a display panel, such as Fig.14 As shown, Fig.14 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention, wherein the display panel includes an array substrate provided in any embodiment of the present invention, and the display panel also includes a light-emitting structure. Since the display panel provided in an embodiment of the present invention includes the array substrate provided in an embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0116] The embodiment of the present invention further provides a display device, such as Fig.15 As shown, Fig.15 A schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device includes a display panel provided in any embodiment of the present invention, and the display device may be a mobile phone, a tablet computer, an MP3, an MP4, a smart watch, a smart helmet or other wearable device. Since the display device provided in an embodiment of the present invention includes a display panel provided in an embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0117] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0118] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises a winding avoidance area, a wiring area at least partially surrounding the winding avoidance area, and a winding arrangement area located between the wiring area and the winding avoidance area; The array substrate further comprises a substrate and at least one pixel driving circuit disposed on the substrate, wherein the pixel driving circuit comprises a data writing module and a threshold compensation module; The array substrate comprises at least one first signal line and at least one second signal line extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line comprises a first winding segment located in the winding setting area, and the second signal line comprises a second winding segment located in the winding setting area; The orthographic projections of the first winding segment and the second winding segment, whose transmission conduction level stages overlap, on the substrate do not overlap; the first direction intersects with the second direction, and the polarities of the conduction levels of the threshold compensation module and the data writing module are opposite.

2. The array substrate according to claim 1, characterized in that: The first signal line is used to control the conduction state of the threshold compensation module, and the second signal line is used to control the conduction state of the data writing module; the stage in which the first signal line transmits the conduction level includes N1 stages, and the stage in which the second signal line transmits the conduction level includes one stage; N1≥2; Preferably, the orthographic projections of the first winding segment and the second winding segment corresponding to the pixel driving circuits in the same row on the substrate do not overlap; the orthographic projections of the first winding segment corresponding to the pixel driving circuits in the kth row and the second winding segment corresponding to the pixel driving circuits in the k+N2th row on the substrate partially overlap; N2≥N1; Preferably, N2 is equal to N1; Preferably, the first signal line includes a first straight line segment located in the wiring area, and the second signal line includes a second straight line segment located in the wiring area; Preferably, the orthographic projections of the first winding segment whose stages of partial transmission conduction levels do not overlap with those of the second winding segment on the substrate partially overlap.

3. The array substrate according to claim 2, characterized in that: In the winding setting area, projections of the first N2 first winding segments and any second winding segment on the substrate do not overlap; The array substrate further includes N2 first compensation signal lines; The N2 first compensation signal lines correspond to the first N2 first winding segments, and along the thickness direction of the array substrate, the first compensation signal lines partially overlap with the orthographic projections of the corresponding first winding segments on the substrate; Preferably, the first compensation signal line and the second winding segment are in the same layer.

4. The array substrate according to claim 3, characterized in that: The first compensation signal line is connected to a first fixed potential; Preferably, the array substrate comprises at least one first power signal line, and the first power signal line is used to provide a first power signal for the pixel driving circuit; the N2 first compensation signal lines are connected to the first power signal line; Preferably, the first ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line; Preferably, the second ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line.

5. The array substrate according to claim 3, characterized in that: The first winding segment is arranged on a side of the second winding segment away from the substrate; The array substrate also includes at least one third signal line extending along the first direction and arranged along the second direction, the third signal line is connected to the pixel driving circuit, and the third signal line includes a third winding segment located in the winding setting area; along the thickness direction of the array substrate, the first N2 first winding segments and any of the third winding segments do not overlap in their orthographic projection on the substrate.

6. The array substrate according to claim 2, characterized in that: In the winding arrangement area, the orthographic projections of the last N2 second winding segments and any of the first winding segments on the substrate do not overlap; The array substrate further includes N2 second compensation signal lines; The N2 second compensation signal lines correspond to the N2 second winding segments, and along the thickness direction of the array substrate, the second compensation signal lines overlap with the orthographic projections of the corresponding second winding segments on the substrate; Preferably, the second compensation signal line and the first winding segment are in the same layer.

7. The array substrate according to claim 6, characterized in that: The N2 second compensation signal lines are connected to a first fixed potential; Preferably, the array substrate comprises at least one first power signal line, and the first power signal line is used to provide a first power signal for the pixel driving circuit; the N2 second compensation signal lines are connected to the first power signal line; Preferably, the first ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line; Preferably, the second ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line.

8. The array substrate according to claim 1, characterized in that: The array substrate further comprises at least one data line, at least one light emitting control signal line and at least one first power signal line; The pixel driving circuit further includes a driving module, a first light emitting control module, a second light emitting control module and a first initialization module; The first end of the data writing module is electrically connected to the data line, the second end of the data writing module is electrically connected to the first end of the driving module, and the control end of the data writing module is electrically connected to the first signal line or the second signal line; The first end of the first light control module is electrically connected to the first power signal line, the second end of the first light control module is electrically connected to the first end of the driving module, and the control end of the first light control module is electrically connected to the light control signal line; The first end of the threshold compensation module is electrically connected to the second end of the driving module, the second end of the threshold compensation module is electrically connected to the control end of the driving module, and the control end of the threshold compensation module is electrically connected to the first signal line or the second signal line; The first end of the second light emitting control module is electrically connected to the second end of the driving module, the second end of the second light emitting control module is used to connect to the light emitting structure, and the control end of the second light emitting control module is electrically connected to the light emitting control signal line; Preferably, the data writing module and the threshold compensation module have transistor types different from each other; Preferably, the pixel driving circuit also includes a storage module, a first initialization module, a second initialization module and a third initialization module; the array substrate also includes a first initialization signal line, a first scan signal line, a second initialization signal line, a third initialization signal line and a second scan signal line; the first end of the storage module is electrically connected to the first power signal line, and the second end of the storage module is electrically connected to the control end of the driving module; the first end of the first initialization module is electrically connected to the first initialization signal line, the second end of the first initialization module is electrically connected to the first end of the threshold compensation module, and the control end of the first initialization module is electrically connected to the first scan signal line; the first end of the second initialization module is electrically connected to the second initialization signal line, the second end of the second initialization module is electrically connected to the first end of the light-emitting structure, and the control end of the second initialization module is electrically connected to the second scan signal line; the first end of the third initialization module is electrically connected to the third initialization signal line, the second end of the third initialization module is electrically connected to the second end of the driving module, and the control end of the third initialization module is electrically connected to the second scan signal line.

9. The array substrate according to claim 1, characterized in that: The array substrate comprises a driving circuit layer arranged on the substrate, wherein the driving circuit layer comprises an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; wherein the active structure of the data writing module is arranged on the active layer, the gate of the data writing module is arranged on the first conductive layer, and the source and drain of the data writing module are arranged on the fourth conductive layer; the gate of the threshold compensation module is arranged on the third conductive layer, and the source and drain of the threshold compensation module are arranged on the fourth conductive layer; Preferably, the first signal line is disposed in the third conductive layer, and the second signal line is disposed in the first conductive layer.

10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.

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