Double-sided pixel circuit and writing method

Abstract

The invention discloses a double-sided pixel circuit and a writing method. The double-sided pixel circuit comprises a pre-storage unit and a driving unit, the pre-storage unit is arranged on the upper substrate, and the driving unit is arranged on the lower substrate; the upper substrate and the lower substrate are connected through a conductive material. The array substrate has the advantages that the upper substrate and the lower substrate are connected through the conductive material, so that the first transistor and the second transistor coincide in the vertical direction, the area occupied by the pixel display area is reduced, and the aperture opening ratio is increased.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a double-sided pixel circuit and a writing method. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] While achieving high refresh rate and high brightness, it is also necessary to ensure the aperture ratio of the pixel circuit; therefore, the present invention proposes a double-sided pixel circuit and a writing method to improve the aperture ratio of the pixel circuit. Summary of the invention

[0004] The purpose of the present invention is to provide a double-sided pixel circuit and a writing method, so as to improve the aperture ratio of the pixel circuit.

[0005] The purpose of the present invention is to realize a double-sided pixel circuit through the following technical scheme, including a pre-storage unit and a driving unit; the pre-storage unit is arranged on an upper substrate, and the driving unit is arranged on a lower substrate; the upper substrate and the lower substrate are connected by a conductive material. The lower substrate is arranged vertically in the light emitting direction of the pixel panel, and the upper substrate is arranged parallel to the lower substrate.

[0006] Furthermore, the pre-storage unit includes a first transistor and a pre-storage capacitor; the first source and drain of the first transistor are coupled to the data signal line, the gate of the first transistor is coupled to the row gate signal line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor; the other end of the pre-storage capacitor is coupled to the first common signal line; the second source and drain of the first transistor are coupled to the driving unit through a conductive material.

[0007] Further, the driving unit includes a second transistor, a storage capacitor and a pixel electrode; The first source and drain of the second transistor are coupled to the second source and drain of the first transistor through a conductive material, the gate of the second transistor is coupled to a transfer signal line, the second source and drain of the second transistor are coupled to a storage capacitor and one end of a pixel electrode; the other end of the storage capacitor is coupled to a second common signal line; the other end of the pixel electrode is coupled to a second common signal line.

[0008] Furthermore, the conductive material is one or more of a metal wire, an electrically conductive support column, and a conductive glue.

[0009] Further, the upper substrate includes a first active layer, a first gate layer, a first source and drain layer, and an intermediate metal layer; The first active layer is arranged on the glass substrate, a first insulating layer is arranged on the first active layer, a first gate layer is arranged on the first insulating layer, and the first gate layer constitutes a gate of the first transistor; A second insulating layer is disposed on the first gate layer, a first source-drain layer is disposed on the second insulating layer, the first source-drain layer is connected to the first active layer through a through hole on the second insulating layer, the first source-drain layer and the first active layer constitute a first source-drain electrode and a second source-drain electrode of the first transistor; the second source-drain electrode of the first transistor is connected to the intermediate metal layer through a transfer hole process; A third insulating layer is disposed on the first source-drain layer, an intermediate metal layer is disposed on the third insulating layer, the intermediate metal layer forms a first common signal line, and the intermediate metal layer is connected to the lower substrate through a conductive material; The overlapping area of ​​the intermediate metal layer and the first source and drain layer forms a pre-storage capacitor.

[0010] Further, the lower substrate includes a second active layer, a second gate layer, a second source and drain layer and a transparent conductive layer; The second active layer is arranged on the second glass substrate, the first insulating layer is arranged on the second active layer, the second gate layer is arranged on the first insulating layer, and the second gate layer constitutes the gate of the second transistor; A second insulating layer is disposed on the second gate layer, a second source-drain layer is disposed on the second insulating layer, the second source-drain layer is connected to the second active layer through a through hole on the second insulating layer, the second source-drain layer and the second active layer constitute a first source-drain electrode and a second source-drain electrode of the second transistor; the first source-drain electrode of the second transistor is coupled to the transparent conductive layer through the through hole; A third insulating layer is disposed on the second source-drain layer, a transparent conductive layer is disposed on the third insulating layer, the transparent conductive layer forms a storage capacitor, and the first source-drain of the second transistor is connected to the upper substrate through a conductive material.

[0011] Furthermore, the intermediate metal layer and the transparent conductive layer are placed opposite to each other, and the intermediate metal layer and the transparent conductive layer overlap to form a pixel capacitor.

[0012] Furthermore, a second intermediate metal layer is disposed on the second insulating layer, and the second intermediate metal layer forms a second common signal line; The storage capacitor on the transparent conductive layer is coupled to the second common signal line through a transfer hole process.

[0013] The present invention also provides a double-sided pixel circuit writing method, comprising: Obtain the target pixel voltage at the nth frame; Generate a transfer charge amount based on a pixel voltage of the nth frame, a pixel voltage of the (n-1th) frame, a pixel electrode, and a storage capacitor; Based on the transferred charge amount, the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame and the pre-storage capacitor, the potential of the pre-storage electrode required before the charge transfer is calculated, and the potential is the data signal voltage.

[0014] The present invention has the following advantages: The present invention adopts an upper substrate to prepare a pre-storage unit, and a lower substrate to prepare a driving unit. The upper substrate and the lower substrate connect the second source and drain of the first transistor and the first source and drain of the second transistor through a conductive material, so that the pixel circuit can normally write a target pixel voltage. At the same time, when the layout is prepared, it is ensured that the first transistor and the second transistor overlap in the vertical direction, thereby reducing the area occupied by the pixel display area and improving the aperture ratio.

[0015] The present invention separately arranges the pre-storage unit and the driving unit on different substrates, so only one transistor needs to be made for a single substrate; thereby reducing the difficulty of preparing stable and good gates, sources and drains of transistors during the layout preparation process, thereby improving the yield of the layout and thus improving the stability of the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of the present invention; Figure 2 is a timing diagram of the present invention; Figure 3 It is a schematic diagram of the layout of the TN mode of the present invention; Figure 4 It is a schematic diagram of the layout of the IPS&FFS mode of the present invention. DETAILED DESCRIPTION

[0017] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0018] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0020] The present invention provides a double-sided pixel circuit, comprising a pre-storage unit and a driving unit; the pre-storage unit is arranged on an upper substrate, and the driving unit is arranged on a lower substrate; the upper substrate and the lower substrate are connected by a conductive material.

[0021] See also Figure 1 For example 1, in some specific embodiments, the pre-storage unit includes a first transistor T1 and a pre-storage capacitor Cs1; the first source and drain of the first transistor T1 are coupled to the data signal line Data, the gate of the first transistor T1 is coupled to the row gate signal line Scan, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1; the other end of the pre-storage capacitor Cs1 is coupled to the first common signal line Com1; the second source and drain of the first transistor T1 are coupled to the driving unit through a conductive material.

[0022] The driving unit includes a second transistor T2, a storage capacitor Cs2 and a pixel electrode Clc; the first source and drain of the second transistor T2 are coupled to the second source and drain of the first transistor T1 through a conductive material, the gate of the second transistor T2 is coupled to the transfer signal line Tran, and the second source and drain of the second transistor T2 are coupled to the storage capacitor Cs2 and one end of the pixel electrode Clc; the other end of the storage capacitor Cs2 is coupled to the second common signal line Com2; the other end of the pixel electrode Clc is coupled to the first common signal line Com1, and the voltage signals of the first common signal line Com1 and the second common signal line Com2 are the same.

[0023] At work, if Figure 2 As shown, the timing diagram of the pixel circuit is configured as: Backlight on stage: The row gate signal line Scan jumps to a high level, the first transistor T1 is turned on, so that the data signal line Data writes the data signal voltage of the nth frame into the pre-storage capacitor Cs1; After writing is completed, the row gate signal line Scan jumps to a normal level; the normal level is the common signal level Vcom, and the common signal level Vcom will not turn the transistor on or off; After writing is completed, the row gate signal line Scan and the data signal line Data both jump to normal level; Backlight off stage: The transfer signal line Tran jumps to a high level, the second transistor T2 is turned on, and the data signal voltage Vd1n in the pre-storage capacitor Cs1 is transferred to the storage capacitor Cs2 and the pixel electrode Clc through the second transistor T2; The data voltage transfers charge to the storage capacitor Cs2 and the pixel electrode Cl, and according to the charge conservation principle, the potential of the pixel electrode Clc reaches the target pixel voltage; After the transfer is completed, the transfer signal line Tran jumps to the normal level.

[0024] In this embodiment, the charge conservation principle is used to achieve correct writing of the target pixel voltage according to the input of different data signal voltages under different pixel voltage requirements.

[0025] In this embodiment, when the pixel voltage of the n-1th frame exists in the storage capacitor Cs2 and the pixel electrode Clc, the equations at the pixel electrode Clc are obtained based on charge sharing, and the equations are as follows: (Vdn-Vn)*C1=(V1n-V1n-1)*C2+(V1n-V1n-1)*C; Where: Vn: pixel voltage of the nth frame; V1n-1: pixel voltage of the n-1th frame; Vdn: the pixel voltage of the nth frame corresponds to the data signal voltage; C1: capacitance value of pre-storage capacitor Cs1; C2: Capacitance of storage capacitor Cs2; C: capacitance value of pixel electrode Clc; Referring to the right side of the first equation above, the amount of transfer charge required when the potential of the pixel electrode Clc changes to the target pixel voltage during the charge transfer process is obtained based on the pixel voltage of the nth frame, the pixel voltage of the n-1th frame, the storage capacitor Cs2 and the pixel electrode Clc; Combined with the left side of the first equation, based on the amount of transferred charge, the pixel voltage of the nth frame and the pre-storage capacitor Cs1, the data signal voltage can be calculated. The expression of the data signal voltage corresponding to the nth frame is: Vdn=((Vn - Vn-1)*(C + C2) + C1*Vn) / C1.

[0026] The pixel voltage of the n-1th frame exists in the storage capacitor Cs2 and the pixel electrode Clc, so the data signal line Data needs to pass through Tcon, and Tcon calculates the data signal voltage that needs to be input into the pre-storage capacitor Cs1 for the nth frame according to the principle of charge conservation, thereby ensuring the normal operation and display of the pixel circuit.

[0027] When preparing the layout, Figure 3 As shown, the upper substrate includes a first active layer 1, a first gate layer 2, a first source and drain layer 3 and an intermediate metal layer 4; The first active layer 1 is arranged on a glass substrate, a first insulating layer is arranged on the first active layer 1, a first gate layer 2 is arranged on the first insulating layer, and the first gate layer 2 constitutes a gate of the first transistor T1; A second insulating layer is provided on the first gate layer 2, a first source-drain layer 3 is provided on the second insulating layer, the first source-drain layer 3 is connected to the first active layer 1 through a through hole on the second insulating layer, the first source-drain layer 3 and the first active layer 1 constitute a first source-drain and a second source-drain of the first transistor T1; the second source-drain of the first transistor T1 is coupled to the intermediate metal layer 4 through a transfer hole process; A third insulating layer is provided on the first source-drain layer 3, an intermediate metal layer 4 is provided on the third insulating layer, the intermediate metal layer 4 forms a first common signal line Com1, and the intermediate metal layer 4 is connected to the lower substrate through a conductive material; the conductive material is one or more of a metal wire, an electrically conductive support column, and a conductive glue; The overlapping area of ​​the intermediate metal layer 4 and the first source-drain layer 3 forms a pre-storage capacitor Cs1 .

[0028] Furthermore, the lower substrate includes a second active layer 5, a second gate layer 6, a second source and drain layer 7 and a transparent conductive layer 8; The second active layer 5 is disposed on the second glass substrate, a first insulating layer is disposed on the second active layer 5, a second gate layer 6 is disposed on the first insulating layer, and the second gate layer 6 constitutes a gate of the second transistor T2; A second insulating layer is provided on the second gate layer 6, a second source-drain layer 7 is provided on the second insulating layer, the second source-drain layer 7 is connected to the second active layer 5 through a through hole on the second insulating layer, and the second source-drain layer 7 and the second active layer 5 constitute a first source-drain electrode and a second source-drain electrode of the second transistor T2; the first source-drain electrode of the second transistor T2 is coupled to the transparent conductive layer 8 through a transfer hole process; A third insulating layer is arranged on the second source-drain layer 7, and a transparent conductive layer 8 is arranged on the third insulating layer, and the transparent conductive layer 8 forms a storage capacitor Cs2. The first source and drain of the second transistor T2 are connected to the upper substrate through a conductive material, and the upper substrate and the lower substrate are arranged parallel to each other, and the lower substrate is arranged in the light emitting direction of the pixel panel, wherein the intermediate metal layer 4 of the upper substrate and the transparent conductive layer 8 of the lower substrate are arranged relatively to each other.

[0029] In some specific embodiments, a second intermediate metal layer 9 is further provided on the second insulating layer, and a second common signal line Com2 is formed on the second intermediate metal layer 9, and a voltage signal of the second common signal line Com2 is consistent with the first common signal line Com1; the storage capacitor Cs2 is coupled to the second common signal line Com2 through a through hole.

[0030] In some specific embodiments, the pixel circuit adopts the TN mode, the intermediate metal layer 4 and the transparent conductive layer 8 overlap to form the pixel electrode Clc, and the liquid crystal molecules rotate vertically in the plane.

[0031] like Figure 4 As mentioned above, in some other specific embodiments, when the pixel circuit adopts the IPS or FFS mode, a storage capacitor Cs2 and a pixel capacitor Clc are formed on the transparent conductive layer 8, and at this time, the liquid crystal molecules rotate in the horizontal plane.

[0032] The present invention separately arranges the pre-storage unit and the driving unit on different substrates, and only one transistor needs to be prepared on each substrate; therefore, for the layout preparation of a single substrate, the difficulty of preparing the gate, source and drain of the transistor is reduced, thereby improving the yield of the transistor and increasing the stability of the pixel circuit.

[0033] Furthermore, the present invention uses an upper substrate to prepare a pre-storage unit and a lower substrate to prepare a driving unit. The upper substrate and the lower substrate are connected by a conductive material so that the first transistor T1 and the second transistor T2 overlap in the vertical direction, thereby reducing the area occupied by the pixel display area and improving the aperture ratio. Example

[0034] The present invention also provides a double-sided pixel circuit writing method, which is applied in the first embodiment, including a circuit obtained by a variation of the first embodiment; S1, obtaining the target pixel voltage at the nth frame and the pixel voltage at the n-1th frame; Vn=(Vn-1*(C + C2) + C1*Vdn) / (C + C1 + C2); S2, generating a transfer charge amount based on the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame, the pixel electrode Clc and the storage capacitor Cs2; (Vdn-Vn)*C1=(V1n-V1n-1)*C2+(V1n-V1n-1)*C; Specifically, based on the first pixel voltage and the second pixel voltage, a first data signal voltage required when the potential of the pixel electrode Clc changes to the first pixel voltage during the charge transfer process is calculated according to the charge conservation principle; The method for calculating the first data signal voltage includes: Generate a transfer charge amount based on the pixel voltage, the second pixel voltage, the pixel electrode Clc and the storage capacitor Cs2; Based on the transferred charge amount, the pixel voltage and the pre-storage capacitor Cs1, the potential of the pre-storage electrode required before the charge transfer stage is calculated, and the potential is the data signal voltage; Vdn=((Vn - Vn-1)*(C + C2) + C1*Vn) / C1.

[0035] S3. Write the calculated data signal voltage into the pre-storage capacitor Cs1.

[0036] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A double-sided pixel circuit, characterized in that: It comprises a pre-storage unit and a driving unit; the pre-storage unit is arranged on an upper substrate, and the driving unit is arranged on a lower substrate; the upper substrate and the lower substrate are connected by a conductive material.

2. A double-sided pixel circuit according to claim 1, characterized in that: The pre-storage unit comprises a first transistor (T1) and a pre-storage capacitor (Cs1); a first source and drain of the first transistor (T1) is coupled to a data signal line (Data), a gate of the first transistor (T1) is coupled to a row gate signal line (Scan), a second source and drain of the first transistor (T1) is coupled to one end of the pre-storage capacitor (Cs1); and the other end of the pre-storage capacitor (Cs1) is coupled to a first common signal line (Com1); The second source and drain of the first transistor (T1) are coupled to the driving unit through a conductive material.

3. The double-sided pixel circuit according to claim 1, characterized in that: The driving unit includes a second transistor (T2), a storage capacitor (Cs2) and a pixel electrode (Clc); The first source and drain of the second transistor (T2) are coupled to the second source and drain of the first transistor (T1) through a conductive material, the gate of the second transistor (T2) is coupled to a transfer signal line (Tran), the second source and drain of the second transistor (T2) are coupled to a storage capacitor (Cs2) and one end of a pixel electrode (Clc); the other end of the storage capacitor (Cs2) is coupled to a second common signal line (Com2).

4. The double-sided pixel circuit according to claim 1, characterized in that: The conductive material is one or more of a metal wire, an electrically conductive support column and a conductive glue.

5. The double-sided pixel circuit according to claim 2, characterized in that: The upper substrate comprises a first active layer (1), a first gate layer (2), a first source-drain layer (3) and an intermediate metal layer (4); The first active layer (1) is arranged on a glass substrate, a first insulating layer is arranged on the first active layer (1), a first gate layer (2) is arranged on the first insulating layer, and the first gate layer (2) constitutes a gate of a first transistor (T1); A second insulating layer is arranged on the first gate layer (2), a first source-drain layer (3) is arranged on the second insulating layer, the first source-drain layer (3) is connected to the first active layer (1) via a through hole on the second insulating layer, and the first source-drain layer (3) and the first active layer (1) constitute a first source-drain electrode and a second source-drain electrode of the first transistor (T1); A third insulating layer is arranged on the first source-drain layer (3), an intermediate metal layer (4) is arranged on the third insulating layer, the intermediate metal layer (4) forms a first common signal line (Com1), and the intermediate metal layer (4) is connected to the lower substrate via a conductive material; The overlapping portion of the intermediate metal layer (4) and the first source-drain layer (3) forms a pre-storage capacitor (Cs1).

6. The double-sided pixel circuit according to claim 3, characterized in that: The lower substrate comprises a second active layer (5), a second gate layer (6), a second source-drain layer (7) and a transparent conductive layer (8); The second active layer (5) is arranged on the second glass substrate, a first insulating layer is arranged on the second active layer (5), a second gate layer (6) is arranged on the first insulating layer, and the second gate layer (6) constitutes the gate of the second transistor (T2); A second insulating layer is provided on the second gate layer (6), a second source-drain layer (7) is provided on the second insulating layer, the second source-drain layer (7) is connected to the second active layer (5) via a through hole on the second insulating layer, and the second source-drain layer (7) and the second active layer (5) constitute a first source-drain electrode and a second source-drain electrode of the second transistor (T2); A third insulating layer is arranged on the second source-drain layer (7), and a transparent conductive layer (8) is arranged on the third insulating layer, wherein the transparent conductive layer (8) forms a storage capacitor (Cs2); the transparent conductive layer (8) is connected to the intermediate metal layer (4) of the upper substrate via a conductive material.

7. The double-sided pixel circuit according to claim 6, characterized in that: A second intermediate metal layer (9) is also provided on the second insulating layer, and the second intermediate metal layer (9) forms a second common signal line (Com2); The storage capacitor (Cs2) on the transparent conductive layer (8) is coupled to the second common signal line (Com2) through a transfer hole process.

8. A double-sided pixel circuit writing method, applied to any pixel circuit according to claim 1 to claim 6, characterized in that: include: Obtaining a target pixel voltage at the nth frame and a pixel voltage at the n-1th frame; Generate a transfer charge amount based on a pixel voltage of the nth frame, a pixel voltage of the n-1th frame, a pixel electrode (Clc) and a storage capacitor (Cs2); Based on the transferred charge amount, the pixel voltage of the nth frame, the pixel voltage of the n-1th frame and the pre-storage capacitor (Cs1), the potential of the pre-storage electrode required before charge transfer is calculated, and the potential is the data signal voltage.

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