Optical sensor packaging method and optical sensor

Abstract

The invention discloses an optical sensor packaging method and an optical sensor, and the method comprises the steps: carrying out the punching of an initial crystal based on a preset dot matrix and a preset through hole size, and forming a plurality of contacts; generating a chip circuit layer at the contact based on a multi-layer rewiring method, and generating a salient point on the rewiring layer based on a preset first metal material to obtain a target crystal; segmenting the target crystal based on a preset wafer size to obtain a plurality of sub-wafers; arranging the sub-wafers on a substrate, and connecting the salient points of the sub-wafers with the substrate based on a reflow soldering method to generate a target substrate; and cutting the target substrate to obtain a plurality of packaged optical sensors. By presetting the dot matrix and the sizes of the through holes, the automatic punching process can be achieved, manual intervention is reduced, the punching consistency is improved, and therefore multiple crystals are processed in batches, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of sensor manufacturing, and in particular to an optical sensor packaging method and an optical sensor. Background Art

[0002] Optical sensors are sensors that can detect and measure light. They work based on different characteristics of light, such as its intensity, color (spectrum), direction, etc. The packaging process of optical sensors is a complex and delicate process. The main purpose of packaging is to protect the sensitive components of the sensor, provide mechanical support, and ensure its electrical connection.

[0003] Existing optical sensors are packaged using DM (Die Mount) and WB (Wire Bonding). In order to achieve electrical connection between the chip and the substrate, wire bonding gold fingers need to be arranged on the edge of the package, which will increase the product size and lead to low integration of the optical sensor. In addition, packaging through wire bonding requires precise control of temperature, pressure and time. The process is complex and time-consuming, resulting in a long overall packaging time, affecting production efficiency. Summary of the invention

[0004] The present invention provides an optical sensor packaging method and an optical sensor, so as to improve the production efficiency of the optical sensor.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides an optical sensor packaging method, which is characterized by comprising:

[0006] Punching holes in the initial crystal based on a preset lattice and a preset through-hole size to form a plurality of contacts;

[0007] Generating a chip circuit layer at the contact point based on a multi-layer redistribution method, and generating a bump on the redistribution layer based on a preset first metal material to obtain a target crystal;

[0008] Based on a preset chip size, the target crystal is divided to obtain a plurality of sub-chips;

[0009] Arranging the sub-wafers on a substrate, and connecting the bumps of the sub-wafers and the substrate based on a reflow soldering method to generate a target substrate;

[0010] The target substrate is cut to obtain a plurality of packaged optical sensors.

[0011] The present invention can realize an automated punching process by presetting dot matrix and through-hole size, reduce manual intervention, improve punching consistency, and thus process multiple crystals in batches to improve production efficiency; and extend dense circuits to vacant positions on the chip by a multi-layer rewiring method to form a chip circuit layer, and then generate bumps on the chip circuit layer, and then connect the crystal and the substrate according to the bumps, and fix the sub-chip on the substrate. Since the sub-chip and the substrate are connected by bumps, there is no need to control the packaging temperature, pressure and time, and multiple sub-chips can be processed simultaneously, streamlining the packaging process of optical sensors, reducing packaging complexity, and improving the production efficiency of packaged optical sensors.

[0012] Furthermore, the initial crystal is a silicon wafer; the initial crystal is punched based on a preset lattice to form a plurality of contacts, including:

[0013] Etching the silicon wafer based on a preset dot matrix and a preset through-hole size to generate a plurality of through-holes;

[0014] A second metal material is electroplated on the inner wall of the through hole to generate a plurality of contacts.

[0015] The present invention etches the silicon wafer through a preset dot matrix and a preset through-hole size to form a plurality of through-holes. Since the through-holes are connected to the internal circuit of the silicon wafer, metal material is electroplated on the inner wall of the through-hole to form contacts, thereby realizing electrical connection between the internal circuit of the wafer and the external substrate.

[0016] Furthermore, the generation of a chip circuit layer at the contact point based on a multi-layer rewiring method includes:

[0017] Depositing a first passivation layer and a second passivation layer on a non-contact region of the crystal surface;

[0018] Depositing a second metal material on the second passivation layer and the contact surface to form a first metal seed layer;

[0019] Disposing a first metal deposition mask on the first metal seed layer, and electroplating a third metal material on the first metal seed layer based on the first metal deposition mask to form a metal circuit layer;

[0020] Presetting a bump area on the metal circuit layer, and depositing a third passivation layer on a non-bump area of ​​the metal circuit layer;

[0021] Depositing a second metal material on the third passivation layer and the bump region to form a second metal seed layer;

[0022] A second metal deposition mask is disposed on the second metal seed layer, and a second metal material is electroplated on the second metal seed layer based on the second metal deposition mask to form a metal contact.

[0023] In the present invention, since the through holes formed based on the dot matrix are relatively dense, a chip circuit layer is generated by a multi-layer rewiring method, wherein the first passivation layer and the second passivation layer are used to protect the crystal surface from environmental erosion and physical damage, and at the same time play an insulating role to prevent short circuits between different circuits; the first metal seed layer and the second metal seed layer provide an adhesion basis for the subsequent electroplating process to ensure good bonding between the metal circuit layer and the crystal surface; a first metal deposition mask is set on the first metal seed layer, and a second metal deposition mask is set on the second metal seed layer, so that the metal material is electroplated according to the metal deposition mask, and the metal circuit layer and the metal contacts are accurately formed through mask technology and electroplating process to achieve a preset circuit layout.

[0024] Furthermore, the step of generating bumps on the redistribution layer based on a preset first metal material includes:

[0025] A first metal material is electroplated on the metal contacts to form bumps.

[0026] The present invention generates a convex point by electroplating a first metal material on a metal contact. The convex point serves as an electrical connection point between a wafer and a substrate. The convex structure is formed by electroplating the first metal material, which is convenient for connection with a pad on the substrate.

[0027] Furthermore, the first metal material includes copper metal or tin metal.

[0028] In the present invention, the copper metal has high conductivity, can effectively reduce the resistance and loss in the signal transmission process, and the copper electroplating process is very mature, the production process is easy to control, and can ensure a high yield; the tin metal has excellent solderability, can form reliable solder joints with a variety of metals, and the price of tin metal is relatively low and suitable for large-scale production. Therefore, during the production process, copper metal or tin metal can be selected according to demand to form bumps.

[0029] Furthermore, before cutting the target substrate, the method further includes:

[0030] Epoxy glue is injected into the connection between the substrate and the sub-wafer based on a preset mold to perform a plastic sealing operation on the target substrate.

[0031] The present invention performs a plastic sealing operation on the substrate by using epoxy glue, thereby protecting the sub-chip and the connection circuit inside the epoxy glue from corrosion by moisture, dust and other environmental factors, thereby improving the reliability of the optical sensor.

[0032] Further, after injecting epoxy glue at the connection between the substrate and the sub-wafer based on the preset mold, it also includes:

[0033] The epoxy glue on the target substrate is cut based on the preset segmentation positions to form a plurality of grooves, and protective covers are assembled at the grooves.

[0034] The present invention forms grooves by cutting epoxy resin, and can divide the target substrate into multiple independent units, and then assembles protective covers at the grooves, which can provide additional protection for each independent unit to prevent physical damage and environmental pollution.

[0035] In a second aspect, the present invention provides an optical sensor, comprising: a sub-chip and a substrate; the sub-chip comprises a silicon substrate and a chip circuit layer, the chip circuit layer is electroplated with a plurality of bumps, and the silicon substrate is electrically connected to the substrate based on the bumps.

[0036] In the packaging structure of the present invention, the sub-wafer and the substrate are connected by bumps, thereby connecting the silicon substrate and the circuit of the substrate by the bumps, without arranging wire bonding gold fingers on the edge of the package, thus simplifying the size of the packaging structure and improving the accuracy of the packaging structure.

[0037] Furthermore, the sub-wafer is covered with a layer of epoxy resin.

[0038] The present invention performs plastic sealing on the sub-chip by epoxy glue, thereby protecting the sub-chip and connecting circuits inside the epoxy glue from corrosion by moisture, dust and other environmental factors, thereby improving the reliability of the optical sensor.

[0039] Furthermore, a protective cover is provided on the substrate, an opening is provided above the protective cover, and the sub-wafer is provided inside the protective cover.

[0040] The present invention prevents physical damage and environmental pollution of the optical sensor by means of a protective cover. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a process of an optical sensor packaging method provided by an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of forming a first passivation layer provided by an embodiment of the present invention;

[0043] Figure 3 A schematic diagram of forming a second passivation layer provided by an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of forming a first metal seed layer provided by an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of a first metal deposition mask configuration provided by an embodiment of the present invention;

[0046] Figure 6 A schematic diagram of forming a metal circuit layer provided by an embodiment of the present invention;

[0047] Figure 7 A schematic diagram of forming a third passivation layer provided in an embodiment of the present invention;

[0048] Figure 8 A schematic diagram of line rewiring manufacturing provided by an embodiment of the present invention;

[0049] Fig. 9 A schematic diagram of convex point generation provided by an embodiment of the present invention;

[0050] Fig.10 A schematic diagram of a target crystal provided by an embodiment of the present invention;

[0051] Fig.11 A schematic diagram of a sub-wafer provided by an embodiment of the present invention;

[0052] Fig.12 A schematic diagram of a target substrate provided by an embodiment of the present invention;

[0053] Fig.13 A schematic diagram of a plastic package provided by an embodiment of the present invention;

[0054] Fig.14 A schematic diagram of a cutting groove provided by an embodiment of the present invention;

[0055] Fig.15 A schematic diagram of assembling a protective cover provided by an embodiment of the present invention;

[0056] Fig.16 A schematic diagram of the structure of an optical sensor provided by an embodiment of the present invention.

[0057] The reference numerals of the drawings in the specification are as follows:

[0058] 1. Initial crystal; 2. Contact area; 3. First passivation layer; 4. Second passivation layer; 5. First metal seed layer; 6. First metal deposition mask; 7. Metal circuit layer; 8. Third passivation layer; 9. Second metal seed layer; 10. Second metal deposition mask; 11. Metal contact; 12. Bump; 13. Silicon substrate; 14. Protective cover; 15. Substrate; 16. Sub-wafer; 17 Epoxy glue; 18. Groove. DETAILED DESCRIPTION

[0059] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0060] The terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0061] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0062] Example 1

[0063] See also Figure 1 , Figure 1 The present invention provides a method for restoring fuel cell performance, including steps 101 to 105, as follows:

[0064] Step 101: punching holes in the initial crystal 1 based on a preset lattice and a preset through-hole size to form a plurality of contacts;

[0065] Step 102: generating a chip circuit layer at the contact point based on a multi-layer redistribution method, and generating a bump 12 on the redistribution layer based on a preset first metal material to obtain a target crystal;

[0066] Step 103: dividing the target crystal into a plurality of sub-wafers 16 based on a preset wafer size;

[0067] Step 104: Arrange the sub-wafer 16 on the substrate 15, and connect the bumps 12 of the sub-wafer 16 and the substrate 15 based on a reflow soldering method to generate a target substrate 15;

[0068] Step 105: cutting the target substrate 15 to obtain a plurality of packaged optical sensors.

[0069] In the embodiment of the present invention, by presetting the dot matrix and the through-hole size, the automatic punching process can be realized, manual intervention can be reduced, and the punching consistency can be improved, so that multiple crystals can be processed in batches and production efficiency can be improved; and the dense circuits can be extended to the vacant positions of the chip through the multi-layer rewiring method to form a chip circuit layer, and then the bumps 12 are generated on the chip circuit layer, and then the crystal and the substrate 15 are connected according to the bumps 12, and the sub-chip 16 is fixed on the substrate 15. Since the sub-chip 16 and the substrate 15 are connected through the bumps 12, there is no need to control the packaging temperature, pressure and time, and multiple sub-chips 16 can be processed at the same time, streamlining the packaging process of the optical sensor, reducing the packaging complexity, and improving the production efficiency of the packaged optical sensor.

[0070] In this embodiment, when obtaining the initial crystal 1, the initial crystal 1 needs to be pre-processed, and the initial crystal 1 is ground based on production requirements until the thickness of the initial crystal 1 meets the production requirements.

[0071] In this embodiment, the initial crystal 1 includes a whole silicon substrate 13 .

[0072] In this embodiment, the initial crystal 1 is punched based on a preset lattice and a preset through-hole size to form a plurality of contacts, thereby connecting the internal circuit of the crystal through the through-holes.

[0073] In this embodiment, the initial crystal 1 is a silicon wafer; the initial crystal 1 is punched based on a preset lattice to form a plurality of contacts, including:

[0074] Etching the silicon wafer based on a preset dot matrix and a preset through-hole size to generate a plurality of through-holes;

[0075] A second metal material is electroplated on the inner wall of the through hole to generate a plurality of contacts.

[0076] In this embodiment, the silicon wafer is etched using TGV technology (Through-Glass Vias), a preset dot matrix and a preset through-hole size to form a number of through-holes. Since the through-holes are connected to the internal circuits of the silicon wafer, metal material is electroplated on the inner walls of the through-holes to form contacts, thereby achieving electrical connection between the internal circuits of the wafer and the external substrate 15.

[0077] In this embodiment, the through hole (Vi a) is an important electrical connection channel between the internal circuit of the silicon wafer and the external circuit. The electrical connection between the internal circuit of the wafer and the external substrate 15 is achieved by etching the through hole on the silicon wafer and electroplating metal material on the inner wall of the through hole to form a contact.

[0078] In this embodiment, a second metal material is electroplated on the inner wall of the hollow cavity of the through hole to generate a plurality of contacts. The electroplated metal material not only provides electrical connection, but also enhances the mechanical strength of the through hole area, making the wafer stronger during subsequent processing and reducing the risk of breakage. At the same time, the metal material has good conductivity, ensuring efficient transmission of signals and reducing signal loss and noise interference.

[0079] In this embodiment, by presetting the dot matrix and the through-hole size, the automatic drilling process can be realized, manual intervention can be reduced, and the consistency of the crystal can be improved. At the same time, multiple crystals can be processed in batches, further improving production efficiency.

[0080] In this embodiment, the etching and electroplating processes can be completed through automation, which is suitable for large-scale and batch production, improves the production efficiency and consistency of optical sensors, and ensures the quality of produced products.

[0081] In this embodiment, the first metal material is copper metal. Since copper has very high conductivity, it can effectively reduce resistance and loss during signal transmission and is suitable for high-performance electrical connections. In addition, copper is a widely used and relatively cheap metal material suitable for large-scale production.

[0082] In this embodiment, the step of generating a chip circuit layer at the contact point based on a multi-layer redistribution method includes:

[0083] Depositing a first passivation layer 3 and a second passivation layer 4 on the non-contact area of ​​the crystal surface;

[0084] Depositing a second metal material on the second passivation layer 4 and the contact surface to form a first metal seed layer 5;

[0085] Disposing a first metal deposition mask 6 on the first metal seed layer 5, and electroplating a third metal material on the first metal seed layer 5 based on the first metal deposition mask 6 to form a metal circuit layer 7;

[0086] Preset a bump 12 area on the metal circuit layer 7, and deposit a third passivation layer 8 on a non-bump 12 area of ​​the metal circuit layer 7;

[0087] Depositing a second metal material in the third passivation layer 8 and the bump 12 region to form a second metal seed layer 9;

[0088] A second metal deposition mask 10 is disposed on the second metal seed layer 9 , and a second metal material is electroplated on the second metal seed layer 9 based on the second metal deposition mask 10 to form a metal contact 11 .

[0089] In this embodiment, since the through holes formed based on the dot matrix are relatively dense, the chip circuit layer is generated by a multi-layer redistribution method.

[0090] In this embodiment, the chip circuit layer includes a first passivation layer 3 , a second passivation layer 4 , a first metal seed layer 5 , a metal circuit layer 7 , a third passivation layer 8 , a second metal seed layer 9 and a metal contact 11 in sequence.

[0091] Please refer to Figure 2 , Figure 2 A schematic diagram of forming a first passivation layer provided in an embodiment of the present invention.

[0092] In this embodiment, a first passivation layer 3 is first deposited on the non-contact area of ​​the crystal surface, and the first passivation layer 3 covers the silicon substrate 13 of the sub-wafer 16. Since the contact area 2 is connected to the internal circuit of the crystal, the first passivation layer 3 does not need to cover the contact area 2 to avoid the circuit being unable to connect.

[0093] Please refer to Figure 3 , Figure 3 A schematic diagram of forming a second passivation layer provided in an embodiment of the present invention.

[0094] In this embodiment, a second passivation layer 4 is then deposited on the first passivation layer 3. The second passivation layer 4 is a PI layer (polyimide layer). The PI is deposited on the chip surface to form a passivation layer to protect the crystal surface from environmental erosion and physical damage, and at the same time, it plays an insulating role to prevent short circuits between different circuits. At the same time, the passivation layer can smooth the crystal surface and provide a flat foundation for subsequent metal deposition.

[0095] In this embodiment, the PI layer also serves as an insulating layer to isolate different metal layers and prevent short circuits between different circuits.

[0096] In this embodiment, PI is usually coated on the chip surface by spin coating or spray coating, and then baked and cured.

[0097] Please refer to Figure 4 , Figure 4 A schematic diagram of forming a first metal seed layer provided in an embodiment of the present invention.

[0098] In this embodiment, a second metal material is deposited on the second passivation layer 4 and the contact surface to form a first metal seed layer 5, and a thin metal seed layer (such as a titanium / copper stack) is deposited on the passivation layer and the opening area to provide an adhesion basis for subsequent metal electroplating and ensure good bonding between the metal circuit layer 7 and the crystal surface.

[0099] Please refer to Figure 5 , Figure 5 A schematic diagram of setting a first metal deposition mask provided in an embodiment of the present invention.

[0100] In this embodiment, a first metal deposition mask 6 is set on the first metal seed layer 5, and a third metal material is electroplated on the first metal seed layer 5 based on the first metal deposition mask 6 to form a metal circuit layer 7. The metal circuit layer 7 is precisely formed through mask technology and electroplating process to realize a preset circuit layout, thereby ensuring efficient transmission of signals and power through the metal circuit layer 7.

[0101] Please refer to Figure 6 , Figure 6 A schematic diagram of forming a metal circuit layer provided by an embodiment of the present invention.

[0102] In this embodiment, a first metal deposition mask 6 is set on the first metal seed layer 5 based on the preset circuit layout. The first metal deposition mask 6 is PR (photoresist). The photoresist is coated on the PI layer to expose the designed pattern to the PR, and then developed to form the required PR pattern. Then, according to the PR pattern, a third metal material is electroplated on the first metal seed layer 5 to form a metal circuit layer 7. Through mask technology and electroplating technology, the metal circuit layer 7 and the metal contact 11 are accurately formed to realize the preset circuit layout.

[0103] In this embodiment, after metal deposition or etching is completed, the PR is removed to complete the production of the first layer of line rewiring.

[0104] In this embodiment, by alternately depositing PI and PR and combining metal deposition and etching processes, a complex multi-layer redistribution layout (RDL) structure can be realized to meet the requirements of high-density wiring.

[0105] Please refer to Figure 7 , Figure 8 and Fig. 9 , Figure 7 A schematic diagram of forming a third passivation layer provided in an embodiment of the present invention; Figure 8 A schematic diagram of line rewiring manufacturing provided by an embodiment of the present invention; Fig. 9 A schematic diagram of generating a convex point provided by an embodiment of the present invention.

[0106] In this embodiment, after completing the production of the first layer of circuit rewiring, the production of the second layer of circuit rewiring is started, a bump 12 area is preset on the metal circuit layer 7, and PI is deposited in the non-bump 12 area of ​​the metal circuit layer 7 to form a third passivation layer 8, and then a second metal material is deposited on the third passivation layer 8 and the bump 12 area to form a second metal seed layer 9. Finally, a second metal deposition mask 10 is set on the second metal seed layer 9, and the second metal deposition mask 10 is generated based on PR coating to form a PR pattern. According to the PR image, the second metal material is electroplated on the second metal seed layer 9 to form a metal contact 11, and the metal contact 11 is used to realize the electrical connection between the chip circuit layer of the sub-chip 16 and the outside.

[0107] In this embodiment, the circuit is rearranged through multi-layer rewiring technology to optimize the signal transmission path and improve the integration and performance of the chip.

[0108] In this embodiment, the step of generating the bumps 12 on the redistribution layer based on the preset first metal material includes:

[0109] The first metal material is electroplated on the metal contact 11 to form a bump 12 .

[0110] In this embodiment, the bump 12 is generated by electroplating a first metal material on the metal contact 11. Since the metal contact 11 is connected to the chip circuit layer of the sub-wafer 16, the metal material is electroplated on the metal contact 11 to form the bump 12, and the bump 12 is then used as an electrical connection point between the wafer and the substrate 15. The protruding structure is formed by electroplating the first metal material, which is convenient for connection with the solder pad on the substrate 15.

[0111] In this embodiment, the bumps 12 are used to connect the input and output (I / O) of the chip to the package substrate 15 or an external circuit. At the same time, the bumps 12 provide mechanical support between the chip and the package substrate 15, thereby enhancing the stability of the package.

[0112] In this embodiment, the first metal material includes copper metal or tin metal.

[0113] In the present invention, copper metal has high conductivity, which can effectively reduce the resistance and loss during signal transmission. The copper electroplating process is very mature, the production process is easy to control, and a high yield can be guaranteed. Tin metal has excellent solderability and can form reliable solder joints with a variety of metals. At the same time, the price of tin metal is relatively low and suitable for large-scale production. Therefore, during the production process, copper metal or tin metal can be selected according to demand to form the bump 12.

[0114] In this embodiment, the second metal material includes copper metal, and multi-layer rewiring operation is implemented by copper metal to achieve finer lines and higher density wiring.

[0115] Please refer to Fig.10 and Fig.11 , Fig.10 A schematic diagram of a target crystal provided by an embodiment of the present invention, Fig.11 A schematic diagram of a sub-wafer 16 provided in an embodiment of the present invention.

[0116] In this embodiment, after the target wafer is generated, the target crystal is divided according to a preset size to obtain a plurality of sub-wafers 16 , and then the sub-wafers 16 are attached to the substrate 15 according to a preset arrangement.

[0117] Please refer to Fig.12 , Fig.12 A schematic diagram of a target substrate 15 provided in an embodiment of the present invention.

[0118] In this embodiment, the sub-wafer 16 is arranged on the substrate 15 , and the bumps 12 of the sub-wafer 16 and the substrate 15 are connected based on a reflow soldering method to generate a target substrate 15 .

[0119] In this embodiment, the reflow soldering method is a soldering technology in the electronic manufacturing process, which is mainly used in surface mount technology (SMT) to fix surface mount components on a printed circuit board (PCB).

[0120] In this embodiment, screen printing technology is used to apply solder paste (usually containing tin-lead alloy or lead-free alloy particles) to the pads of the substrate 15, and a placement machine is used to accurately place the sub-chip 16 at the corresponding position on the solder paste. The mounted PCB is then sent to a reflow oven for heating and cooling according to a preset temperature curve to melt and solidify the solder paste, thereby fixing the sub-chip 16 on the substrate 15.

[0121] Please refer to Fig.13 , Fig.13 A schematic diagram of a plastic package provided by an embodiment of the present invention.

[0122] In this embodiment, before cutting the target substrate 15, the method further includes:

[0123] Based on a preset mold, epoxy glue 17 is injected into the connection between the substrate 15 and the sub-wafer 16 to perform a plastic sealing operation on the target substrate 15 .

[0124] In this embodiment, a mold is placed above the substrate 15, and the mold is outside the sub-chip 16. A transparent epoxy glue 17 is injected into the inside of the mold so that the epoxy glue 17 covers the sub-chip 16. After the epoxy glue 17 is cured, the mold is removed to complete the plastic sealing operation of the sub-chip 16 on the substrate 15, thereby protecting the sub-chip 16 and the connecting lines inside the epoxy glue 17 from moisture, dust and other environmental factors, thereby improving the reliability of the optical sensor.

[0125] Please refer to Fig.14 and Fig.15 , Fig.14 A schematic diagram of a cutting groove 18 provided in an embodiment of the present invention; Fig.15 A schematic diagram of assembling a protective cover 14 provided in an embodiment of the present invention.

[0126] In this embodiment, after injecting epoxy glue 17 at the connection between the substrate 15 and the sub-wafer 16 based on the preset mold, the method further includes:

[0127] The epoxy glue 17 on the target substrate 15 is cut based on the preset dividing positions to form a plurality of grooves 18 , and the protection cover 14 is assembled at the grooves 18 .

[0128] The present invention forms a groove 18 on the substrate 15 by cutting the epoxy glue 17 at a preset position, which can divide the target substrate 15 into multiple independent units, and then assemble the protective cover 14 at the groove 18 to provide additional protection for each independent unit to prevent physical damage and environmental pollution.

[0129] In this embodiment, the protective cover 14 is disposed on the periphery of the sub-wafer 16 to block light and protect the internal circuits of the wafer, and is of an open design.

[0130] In this embodiment, the protective cover 14 may be attached to the substrate 15 by an optical grade adhesive.

[0131] In this embodiment, the target substrate 15 is finally cut to obtain a plurality of packaged optical sensors.

[0132] In this embodiment, since each step in the optical sensor packaging method can be automatically completed by the terminal device control device, the time and possible errors of manual operation are reduced. From crystal drilling, generating bumps 12 to the segmentation and welding of sub-chips 16, batch processing is supported, which greatly improves production, shortens the entire packaging cycle, and speeds up production.

[0133] In this embodiment, by presetting the dot matrix and the through-hole size, the punching process can be automated, manual intervention can be reduced, and the punching consistency can be improved, so that multiple crystals can be processed in batches and production efficiency can be improved; and the dense circuits can be extended to the vacant positions of the chip through the multi-layer rewiring method to form a chip circuit layer, and then the bumps 12 are generated on the chip circuit layer, and then the crystal and the substrate 15 are connected according to the bumps 12, and the sub-chip 16 is fixed on the substrate 15. Since the sub-chip 16 and the substrate 15 are connected through the bumps 12, there is no need to control the packaging temperature, pressure and time, and multiple sub-chips 16 can be processed at the same time, streamlining the packaging process of the optical sensor, reducing the packaging complexity, and improving the production efficiency of the packaged optical sensor.

[0134] Please refer to Fig.16 , Fig.16 A schematic diagram of the structure of an optical sensor provided by an embodiment of the present invention.

[0135] An embodiment of the present invention also provides an optical sensor, which is manufactured based on the above-mentioned optical sensor packaging method, and includes: a sub-chip 16 and a substrate 15; the sub-chip 16 includes a silicon substrate 13 and a chip circuit layer, and a plurality of bumps 12 are electroplated and connected on the chip circuit layer, and the silicon substrate 13 is electrically connected to the substrate 15 based on the bumps 12.

[0136] In this embodiment, the sub-wafer 16 is covered with a layer of epoxy glue 17 .

[0137] In this embodiment, the sub-wafer 16 is plastic-sealed by epoxy glue 17, thereby protecting the sub-wafer 16 and the connecting circuits inside the epoxy glue 17 from moisture, dust and other environmental factors, thereby improving the reliability of the optical sensor.

[0138] In this embodiment, a protective cover 14 is disposed on the substrate 15 , an opening is disposed above the protective cover 14 , and the sub-wafer 16 is disposed inside the protective cover 14 .

[0139] In this embodiment, the optical sensor is protected from physical damage and environmental contamination by the protective cover 14 .

[0140] In this embodiment, in the packaging structure of the optical sensor, the sub-chip 16 and the substrate 15 are connected by the bumps 12, thereby connecting the circuits of the silicon base 13 and the substrate 15 through the bumps 12. There is no need to arrange wire bonding gold fingers on the edge of the package, thereby simplifying the size of the packaging structure and improving the accuracy of the optical sensor.

[0141] In an embodiment of the present invention, a terminal device is also provided, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above-mentioned optical sensor packaging method when executing the computer program.

[0142] In an embodiment of the present invention, a computer-readable storage medium is further provided. The computer-readable storage medium includes a stored computer program. When the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned optical sensor packaging method.

[0143] Exemplarily, the computer program may be divided into one or more modules, one or more modules are stored in a memory and executed by a processor to implement the present invention. One or more modules may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in a terminal device.

[0144] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The terminal device may include, but is not limited to, a processor, a memory, and a display. Those skilled in the art will appreciate that the above components are merely examples of the terminal device and do not constitute a limitation on the terminal device. The terminal device may include more or fewer components than the components, or may combine certain components, or different components. For example, the terminal device may also include input and output devices, network access devices, buses, etc.

[0145] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.

[0146] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, a text conversion function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, text message data, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Med i aCard, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0147] Among them, if the module based on the processing of the multi-device access platform is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0148] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. An optical sensor packaging method, characterized in that: include: Punching holes in the initial crystal based on a preset lattice and a preset through-hole size to form a plurality of contacts; Generating a chip circuit layer at the contact point based on a multi-layer redistribution method, and generating a bump on the redistribution layer based on a preset first metal material to obtain a target crystal; Based on a preset chip size, the target crystal is divided to obtain a plurality of sub-chips; Arranging the sub-wafers on a substrate, and connecting the bumps of the sub-wafers and the substrate based on a reflow soldering method to generate a target substrate; The target substrate is cut to obtain a plurality of packaged optical sensors.

2. An optical sensor packaging method as claimed in claim 1, characterized in that: The initial crystal is a silicon wafer; the initial crystal is punched based on a preset lattice to form a plurality of contacts, including: Etching the silicon wafer based on a preset dot matrix and a preset through-hole size to generate a plurality of through-holes; A second metal material is electroplated on the inner wall of the through hole to generate a plurality of contacts.

3. The optical sensor packaging method according to claim 2, characterized in that: The method of generating a chip circuit layer at the contact point based on a multi-layer rewiring method includes: Depositing a first passivation layer and a second passivation layer on a non-contact region of the crystal surface; Depositing a second metal material on the second passivation layer and the contact surface to form a first metal seed layer; Disposing a first metal deposition mask on the first metal seed layer, and electroplating a third metal material on the first metal seed layer based on the first metal deposition mask to form a metal circuit layer; Presetting a bump area on the metal circuit layer, and depositing a third passivation layer on a non-bump area of ​​the metal circuit layer; Depositing a second metal material on the third passivation layer and the bump region to form a second metal seed layer; A second metal deposition mask is disposed on the second metal seed layer, and a second metal material is electroplated on the second metal seed layer based on the second metal deposition mask to form a metal contact.

4. The optical sensor packaging method according to claim 3, characterized in that: The step of generating bumps on the redistribution layer based on a preset first metal material comprises: A first metal material is electroplated on the metal contacts to form bumps.

5. The optical sensor packaging method according to claim 4, characterized in that: The first metal material includes copper metal or tin metal.

6. The optical sensor packaging method according to claim 1, characterized in that: Before cutting the target substrate, the method further includes: Epoxy glue is injected into the connection between the substrate and the sub-wafer based on a preset mold to perform a plastic sealing operation on the target substrate.

7. The optical sensor packaging method according to claim 6, characterized in that: After injecting epoxy glue at the connection between the substrate and the sub-wafer based on the preset mold, the method further includes: The epoxy glue on the target substrate is cut based on the preset segmentation positions to form a plurality of grooves, and protective covers are assembled at the grooves.

8. An optical sensor, characterized in that: include: Sub-wafer and substrate; the sub-wafer includes a silicon substrate and a chip circuit layer, the chip circuit layer is electroplated with a plurality of bumps, and the silicon substrate is electrically connected to the substrate based on the bumps.

9. An optical sensor as claimed in claim 8, characterized in that: The sub-wafer is covered with a layer of epoxy glue.

10. An optical sensor as claimed in claim 9, characterized in that: A protective cover is arranged on the substrate, an opening is arranged above the protective cover, and the sub-wafer is arranged inside the protective cover.

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