Detection device and detection method

Abstract

The invention discloses a detection device and a detection method. The device comprises a substrate; the thin film transistor is arranged on the substrate, and the first insulating layer is arranged on the side, away from the substrate, of the thin film transistor; the photodiode is arranged on one side, far away from the substrate, of the first insulating layer, and the photodiode is electrically connected with the drain electrode through a first via hole in the first insulating layer; the second insulating layer is arranged on one side, far away from the substrate, of the photodiode; the first conductive layer is arranged on the side, away from the substrate, of the second insulating layer, and the first conductive layer is electrically connected with the photodiode through a second via hole in the second insulating layer; the third insulating layer is arranged on the side, away from the substrate, of the first conductive layer, a conductive structure is arranged on the side, away from the substrate, of the third insulating layer, and the conductive structure is electrically connected with the first conductive layer through a third via hole in the third insulating layer. A single TFT can be tested through the conductive structure, the characteristics of the TFT can be effectively identified, and the defect of the panel can be detected.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims patent application No.

[0003] 202411748328.1, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The invention belongs to the field of detection, and in particular relates to a detection device and a detection method. Background Art

[0005] X-ray flat panel detector backplane products (FPXD) can be used in medical testing. They can convert X-rays that penetrate the human body into visible light, and then convert the visible light into electrical signals through the photodiodes on the FPXD for processing by the imaging system. The system then converts the electrical signals into displayed medical images. Various defects will occur during the manufacturing process of the panel, and the performance parameters of the panel need to be tested. In traditional X-ray flat panel detector backplane products (FPXD), Vbias (bias signal) runs through the entire panel. When the voltage is applied to the Vbias photodiode, all pixels on the screen are powered. During the test process, when testing the thin film transistor (TFT) characteristics at a certain position in the display area of ​​the panel, since Vbias runs through the entire screen, it is impossible to test a single TFT at a specific position. Only the characteristics of multiple TFTs in parallel in a certain column can be tested, and it is difficult to analyze and test the characteristics of a single TFT. Summary of the invention

[0006] The purpose of the embodiments of the present invention is to provide a detection device and a detection method to solve the problem that it is difficult to analyze and detect the characteristics of a single TFT in a panel.

[0007] In a first aspect, an embodiment of the present invention provides a detection device, including:

[0008] substrate substrate;

[0009] A thin film transistor, wherein the thin film transistor is disposed on the substrate, and comprises a gate, a source, a drain and an active layer, wherein a surface of the gate is covered with a gate insulating layer, and the source is connected to the drain and the active layer;

[0010] A first insulating layer, wherein the first insulating layer is disposed on a side of the thin film transistor away from the substrate;

[0011] A photodiode, wherein the photodiode is disposed on a side of the first insulating layer away from the base substrate, and the photodiode is electrically connected to the drain through a first via hole on the first insulating layer;

[0012] A second insulating layer, wherein the second insulating layer is disposed on a side of the photodiode away from the substrate;

[0013] a first conductive layer, wherein the first conductive layer is disposed on a side of the second insulating layer away from the base substrate, and the first conductive layer is electrically connected to the photodiode through a second via hole on the second insulating layer;

[0014] A third insulating layer is provided on a side of the first conductive layer away from the base substrate, a conductive structure is provided on the side of the third insulating layer away from the base substrate, and the conductive structure is electrically connected to the first conductive layer through a third via hole on the third insulating layer.

[0015] Optionally, the conductive structure is disposed in contact with a hole wall of a third via hole on the third insulating layer.

[0016] Optionally, part of the conductive structure is disposed in a second via hole on the second insulating layer.

[0017] Optionally, an orthographic projection of the conductive structure on the substrate at least partially overlaps with an orthographic projection of the photodiode on the substrate.

[0018] Optionally, a second conductive layer is provided on a side of the photodiode away from the substrate, the second conductive layer covers the photodiode, and the first conductive layer is electrically connected to the photodiode through the second conductive layer.

[0019] Optionally, the device further comprises:

[0020] A buffer layer is provided on a side of the second conductive layer away from the base substrate, the buffer layer covers the drain and the second conductive layer, a fourth via hole is provided on the buffer layer, and the first conductive layer is electrically connected to the second conductive layer through the fourth via hole.

[0021] Optionally, the device further comprises:

[0022] A planar layer is disposed between the buffer layer and the second insulating layer.

[0023] Optionally, a first connection layer is provided on a side of the first insulating layer away from the base substrate, the first connection layer is electrically connected to the drain through a first via hole on the first insulating layer, and the photodiode is electrically connected to the first connection layer.

[0024] In a second aspect, an embodiment of the present invention provides a detection method of a detection device, which is applied to the detection device described in the above embodiment, and includes:

[0025] A voltage is applied to the gate for scanning, a voltage is applied to the drain through a conductive structure, and current is detected at the source.

[0026] Optionally, the voltage loaded on the gate is -20 to 20 V, and the voltage loaded on the conductive structure is 1 to 7 V.

[0027] In a third aspect, an embodiment of the present invention provides a detection panel, including:

[0028] The devices described in the above embodiments.

[0029] In a fourth aspect, an embodiment of the present invention provides a detection device, including:

[0030] The detection panel described in the above embodiment.

[0031] In the detection device of the embodiment of the present invention, the thin film transistor is arranged on the substrate, the first insulating layer is arranged on the side of the thin film transistor away from the substrate, the photodiode is arranged on the side of the first insulating layer away from the substrate, and the photodiode is electrically connected to the drain through the first via hole on the first insulating layer; the second insulating layer is arranged on the side of the photodiode away from the substrate; the first conductive layer is arranged on the side of the second insulating layer away from the substrate, and the first conductive layer is electrically connected to the photodiode through the second via hole on the second insulating layer; the third insulating layer is arranged on the side of the first conductive layer away from the substrate, and the side of the third insulating layer away from the substrate is provided with a conductive structure, and the conductive structure is electrically connected to the first conductive layer through the third via hole on the third insulating layer. By arranging the photodiode on the side of the first insulating layer away from the substrate, the photodiode is electrically connected to the conductive structure through the via hole on the insulating layer and the first conductive layer, and in the process of TFT testing, a single TFT can be tested through the conductive structure, and a single TFT can be specifically analyzed and detected, and the characteristics of the TFT can be effectively identified, which is conducive to detecting panel defects and improving detection and analysis efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a device according to an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of a pixel structure;

[0034] Figure 3 for Figure 2 A magnified schematic diagram of the local A in the middle;

[0035] Figure 4 A test schematic diagram of TFT in the panel;

[0036] Figure 5 A schematic diagram of the TFT test principle.

[0037] Reference numerals

[0038] Base substrate 10;

[0039] Gate 21; drain 22; source 23; active layer 24; gate insulating layer 25;

[0040] Photodiode 30;

[0041] A first insulating layer 31; a second insulating layer 32; a third insulating layer 33;

[0042] A first conductive layer 41; a second conductive layer 42; a conductive structure 43; a first connecting layer 44;

[0043] Buffer layer 50;

[0044] The planarization layer 60 . DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein. In addition, the term "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0047] like Figure 1 As shown, the detection device of the embodiment of the present invention includes: a substrate 10, a thin film transistor, a first insulating layer 31, a photodiode 30, a second insulating layer 32, a first conductive layer 41, and a third insulating layer 33. The thin film transistor is arranged on the substrate 10. The thin film transistor may include a gate 21, a drain 22, a source 23 and an active layer 24. The surface of the gate 21 is covered with a gate insulating layer 25. The drain 22 is connected to the source 23 and the active layer 24. When a voltage is applied to the gate 21, the active layer 24 can be electrically conductive, and the drain 22 and the source 23 are conductively connected through the active layer 24.

[0048] The first insulating layer 31 may be disposed on a side of the thin film transistor away from the base substrate 10, and the first insulating layer 31 may cover the thin film transistor. The photodiode 30 may be disposed on a side of the first insulating layer 31 away from the base substrate 10, and the photodiode 30 may be electrically connected to the drain 22 through a first via hole on the first insulating layer 31. The orthographic projection of the photodiode 30 on the base substrate 10 and the orthographic projection of the thin film transistor on the base substrate 10 may be spaced apart. The first insulating layer 31 may be SiNx (silicon nitride).

[0049] The second insulating layer 32 may be disposed on a side of the photodiode 30 away from the base substrate 10, the second insulating layer 32 may cover the photodiode 30, and the orthographic projection of the second insulating layer 32 on the base substrate 10 may cover the orthographic projection of the photodiode 30 on the base substrate 10. The second insulating layer 32 may be SiNx (silicon nitride). The first conductive layer 41 may be disposed on a side of the second insulating layer 32 away from the base substrate 10, and the first conductive layer 41 may be electrically connected to the photodiode 30 through a second via hole on the second insulating layer 32. The first conductive layer 41 may be a metal oxide layer, the first conductive layer 41 may extend into the second via hole on the second insulating layer 32, the first conductive layer 41 may be disposed along the hole wall of the second via hole, the portion of the first conductive layer 41 in the second via hole may constitute a groove, and the first conductive layer 41 may extend through the second via hole on the second insulating layer 32 to be electrically connected to the photodiode 30.

[0050] The third insulating layer 33 may be disposed on a side of the first conductive layer 41 away from the base substrate 10, the third insulating layer 33 may cover the first conductive layer 41, and the orthographic projection of the third insulating layer 33 on the base substrate 10 may cover the orthographic projection of the first conductive layer 41 on the base substrate 10. A conductive structure 43 may be disposed on a side of the third insulating layer 33 away from the base substrate 10, and the conductive structure 43 is electrically connected to the first conductive layer 41 through a third via hole on the third insulating layer 33. A portion of the conductive structure 43 may extend into the groove through the third via hole, and a portion of the conductive structure 43 located in the groove may be disposed along the inner wall of the groove, and a portion of the conductive structure 43 in the via hole extends to form a concave cavity, so as to facilitate plugging with the outside during testing.

[0051] In the device of the present invention, a photodiode is arranged on a side of the first insulating layer away from the substrate, and the photodiode is electrically connected to the conductive structure through a via hole on the insulating layer and the first conductive layer, and each TFT can correspond to a conductive structure in a via hole on the third insulating layer of a pixel to be tested. The FPXD product with the device can test the TFT characteristics at any position in the AA area (detection area). During the TFT test, a single TFT can be tested through the conductive structure, and a single TFT can be specifically analyzed and detected, and the characteristics of the TFT can be effectively identified, which is conducive to detecting panel defects and improving the efficiency of detection and analysis.

[0052] In some embodiments, the conductive structure 43 may be disposed in contact with the hole wall of the third via hole on the third insulating layer 33, and the portion of the conductive structure 43 in the third via hole on the third insulating layer 33 may be hollow to facilitate external plugging during testing. A conductive material layer 34 may be disposed on a side surface of the third insulating layer 33 away from the base substrate 10, and the conductive material layer 34 may be a metal oxide layer, and the conductive material layer 34 may be indium tin oxide.

[0053] In an embodiment of the present invention, part of the conductive structure 43 may be disposed in the second via hole on the second insulating layer 32 , and the part of the conductive structure 43 in the second via hole on the second insulating layer 32 may be hollow to facilitate external plugging during testing.

[0054] In the present invention, by designing a via hole on the third insulating layer above the photodiode, the photodiode is electrically connected to the conductive structure through the via hole overlap design, and each TFT can correspond to the conductive structure in the via hole on the third insulating layer of a pixel to be tested. Under the premise of not increasing the cost, a single test of the TFT characteristics in the full screen can be achieved, and a certain TFT can be tested independently, so that the TFT characteristics of the bad position can be effectively identified, and the analysis efficiency can be improved. The relevant graphics can be drawn on the third insulating layer, and the exposure is performed in the exposure machine to form the third via hole on the third insulating layer, such as Figure 2 and Figure 3As shown, the length and width of the third via formed on the third insulating layer 33 can be 9um*9um respectively, and the conductive structure 43 can be electrically connected to the first conductive layer 41 through the third via on the third insulating layer 33, and the depth of the via can be = the thickness of the third insulating layer + the thickness of the second insulating layer + the thickness of the flat layer - the thickness of the photodiode - the thickness of the buffer layer - the thickness of the first conductive layer. In addition, by designing a via on the third insulating layer above the photodiode, the photodiode is electrically connected to the conductive structure through the via overlap design, which does not affect the pixel display area. The third via is opened on the third insulating layer above the photodiode, so as to overlap the first conductive layer, which can save space. The length and width of the conductive structure can be 14.5um*14.5um respectively, the length and width of the via on the flat layer can be 10.5um*10.5um respectively, the length and width of the third via on the third insulating layer can be 9um*9um respectively, and the length and width of the second via on the second insulating layer can be 5.5um*5.5um respectively. The specific size and shape of the via can be selected as needed.

[0055] In some embodiments, the orthographic projection of the conductive structure 43 on the substrate 10 overlaps at least partially with the orthographic projection of the photodiode 30 on the substrate 10, and the orthographic projections of the second via and the third via on the substrate 10 overlap at least partially with the orthographic projections of the photodiode 30 on the substrate 10, so that the orthographic projection of the conductive structure 43 on the substrate 10 overlaps at least partially with the orthographic projection of the photodiode 30 on the substrate 10. For example, the orthographic projection of the conductive structure 43 on the substrate 10 can be located within the orthographic projection of the photodiode 30 on the substrate 10, so as to avoid affecting the area of ​​the photodiode 30 (PIN), thereby avoiding affecting the filling rate. Electrically connecting the first conductive layer 41 through the via of the insulating layer above the photodiode can help save space.

[0056] According to some embodiments, a second conductive layer 42 may be provided on a side of the photodiode 30 away from the base substrate 10, the second conductive layer 42 may cover the photodiode 30, the first conductive layer 41 and the photodiode 30 may be electrically connected through the second conductive layer 42, and the second conductive layer 42 may be a metal oxide layer. For example, the second conductive layer 42 may be indium tin oxide (ITO). The second conductive layer 42 may protect the photodiode and also make the electrical connection between the photodiode 30 and the first conductive layer 41 more stable.

[0057] In some embodiments, the device may further include: a buffer layer 50, which may be disposed on a side of the second conductive layer 42 away from the base substrate 10, and may cover the drain 22 and the second conductive layer 42, and the orthographic projection of the buffer layer 50 on the base substrate 10 may cover the orthographic projection of the thin film transistor on the base substrate 10. A fourth via hole may be disposed on the buffer layer 50, and a portion of the first conductive layer 41 may extend into the fourth via hole, and the first conductive layer 41 is electrically connected to the second conductive layer 42 through the fourth via hole, and the first conductive layer 41 extending into the fourth via hole may be electrically connected to the second conductive layer 42.

[0058] In some other embodiments, the device may further include: a planarizing layer 60, which may be disposed between the buffer layer 50 and the second insulating layer 32, and may be a resin layer. A fifth via may be disposed on the planarizing layer 60, and the first conductive layer 41 may be electrically connected to the photodiode through the fifth via.

[0059] In an embodiment of the present invention, a first connecting layer 44 is provided on the side of the first insulating layer 31 away from the base substrate 10, the first connecting layer 44 is electrically connected to the drain 22 through a first via hole on the first insulating layer 31, the photodiode 30 is electrically connected to the first connecting layer 44, and the photodiode 30 can be arranged on the side of the first connecting layer 44 away from the base substrate 10.

[0060] In a second aspect, an embodiment of the present invention provides a detection method of a detection device, which is applied to the detection device described in the above embodiment, and includes:

[0061] A voltage is applied to the gate for scanning, a voltage is applied to the drain through a conductive structure, and current is detected at the source.

[0062] Optionally, the voltage loaded on the gate is -20 to 20 V, and the voltage loaded on the conductive structure is 1 to 7 V.

[0063] For example, a voltage of -20 to 20 V is applied to the gate for scanning, and the voltage can be scanned every 0.2 V. A voltage is applied to the drain through a conductive structure, and a voltage of 5 V can be applied to the drain, and then a current receiving detection is performed at the source. The above method can be used to test a single TFT, analyze and detect a single TFT, effectively identify the characteristics of the TFT, and is conducive to detecting panel defects and improving detection efficiency.

[0064] During the evaluation and detection of TFT, a photodiode is arranged on the side of the first insulating layer away from the substrate, the photodiode is electrically connected to the conductive structure through the via hole on the insulating layer and the first conductive layer, and the via hole of the insulating layer is overlapped above the photodiode to connect the first conductive layer through the via hole, so as to realize the conduction of the loading signal. For example, Figure 4 As shown, when the TFT characteristics of the product in the fifth row and first column are abnormal, it is necessary to find position D1 (the fifth row gate line pin), use the TFT probe to pierce position D1 (the fifth row gate line pin), position D2 (the conductive structure in the via hole on the third insulating layer of the pixel to be tested on the fifth row and first column TFT) and position D3 (the first column source pin) to test the TFT channel current. The current test result is the channel current of a single TFT. TFT characteristic test method: gate loads -20~20v for scanning, the voltage is scanned every 0.2v, 5v voltage is loaded on the Vbias end, and the source end receives current.

[0065] TFT test mechanism: Figure 5 As shown, when a positive voltage is applied to Vbias, the photodiode is forward-conducted. At this time, the diode is equivalent to a wire. As the gate voltage gradually increases to the threshold voltage, the TFT channel forms an on-current, and the source electrode and the drain electrode are turned on. TFT testing is based on this principle. When the gate terminal is loaded with a scan voltage of -20 to 20v, Vbias is loaded with a 5v voltage (5v can be a universal voltage required by development and design), the probes are respectively inserted into the gate, source, and Vbias terminals to realize the TFT channel current test.

[0066] The detection panel of the embodiment of the present invention includes:

[0067] The detection device described in the above embodiment. The detection panel having the device described in the above embodiment can test a single TFT through the conductive structure during the manufacturing process, can analyze and detect a single TFT, effectively identify the characteristics of the TFT, and is conducive to detecting panel defects and improving detection efficiency.

[0068] The detection device according to the embodiment of the present invention comprises:

[0069] The detection panel described in the above embodiment. The detection device having the detection panel described in the above embodiment is conducive to detecting defects and improving detection efficiency.

[0070] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A detection device, characterized in that: include: substrate substrate; A thin film transistor, wherein the thin film transistor is disposed on the substrate, and comprises a gate, a source, a drain and an active layer, wherein a surface of the gate is covered with a gate insulating layer, and the source is connected to the drain and the active layer; A first insulating layer, wherein the first insulating layer is disposed on a side of the thin film transistor away from the substrate; A photodiode, wherein the photodiode is disposed on a side of the first insulating layer away from the base substrate, and the photodiode is electrically connected to the drain through a first via hole on the first insulating layer; A second insulating layer, wherein the second insulating layer is disposed on a side of the photodiode away from the substrate; a first conductive layer, wherein the first conductive layer is disposed on a side of the second insulating layer away from the base substrate, and the first conductive layer is electrically connected to the photodiode through a second via hole on the second insulating layer; A third insulating layer is provided on a side of the first conductive layer away from the base substrate, a conductive structure is provided on the side of the third insulating layer away from the base substrate, and the conductive structure is electrically connected to the first conductive layer through a third via hole on the third insulating layer.

2. The device according to claim 1, characterized in that The conductive structure is disposed in contact with a hole wall of the third via hole on the third insulating layer.

3. The device according to claim 1, characterized in that A portion of the conductive structure is disposed in a second via hole on the second insulating layer.

4. The device according to claim 3, characterized in that An orthographic projection of the conductive structure on the substrate at least partially overlaps with an orthographic projection of the photodiode on the substrate.

5. The device according to claim 1, characterized in that A second conductive layer is disposed on a side of the photodiode away from the base substrate, the second conductive layer covers the photodiode, and the first conductive layer is electrically connected to the photodiode through the second conductive layer.

6. The device according to claim 5, characterized in that Also includes: A buffer layer is provided on a side of the second conductive layer away from the base substrate, the buffer layer covers the drain and the second conductive layer, a fourth via hole is provided on the buffer layer, and the first conductive layer is electrically connected to the second conductive layer through the fourth via hole.

7. The device according to claim 6, characterized in that Also includes: A planar layer is disposed between the buffer layer and the second insulating layer.

8. The device according to claim 1, characterized in that A first connection layer is provided on a side of the first insulating layer away from the base substrate. The first connection layer is electrically connected to the drain through a first via hole on the first insulating layer, and the photodiode is electrically connected to the first connection layer.

9. A detection method for a detection device, applied to the detection device according to any one of claims 1 to 8, characterized in that: include: A voltage is applied to the gate for scanning, a voltage is applied to the drain through a conductive structure, and current is detected at the source.

10. The detection method according to claim 9, characterized in that: The voltage loaded on the gate is -20~20V, and the voltage loaded on the conductive structure is 1-7V.

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