Switching circuit and switching system

Abstract

The invention discloses a switching circuit and a switching system, and relates to the technical field of circuits. The circuit comprises a charge pump circuit used for processing an input voltage to obtain a first voltage, and the first voltage is used for providing a driving voltage for a gate driving circuit; the gate drive circuit is used for receiving an input signal of the signal input end and processing the input signal based on the first voltage to obtain an output signal, and the output signal is used for providing a switching signal for the cut-off circuit; and the cut-off circuit is used for controlling on or off of the power supply output end according to the output signal and controlling load power supply. The technical problems that in the prior art, a relay is adopted as a switch element to control power supply of a power supply to a load, and reliability and safety are low are solved.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a switch circuit and a switch system. Background Art

[0002] At present, relays are commonly used as switching elements in low-voltage control of high-voltage systems. However, due to their large mechanical structure and size, relays have many design limitations, which may lead to slow switching speeds and waste of space on circuit board layouts. In addition, the mechanical contacts of relays are prone to wear during long-term use, causing problems such as poor contact and arcing, and low reliability and safety.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present invention provide a switch circuit and a switch system to at least solve the technical problem in the prior art of using relays as switch elements to control the power supply of a power supply to a load, which has low reliability and safety.

[0005] According to one aspect of an embodiment of the present invention, a switching circuit is provided, comprising: a charge pump circuit, for processing an input voltage to obtain a first voltage, wherein the first voltage is used to provide a driving voltage for a gate driving circuit; a gate driving circuit, for receiving an input signal from a signal input terminal, and processing the input signal based on the first voltage to obtain an output signal, wherein the output signal is used to provide a switching signal for a cut-off circuit; and a cut-off circuit, for controlling the opening or closing of an output terminal of a power supply according to the output signal, thereby controlling the power supply to a load.

[0006] Furthermore, the charge pump circuit includes: a pulse oscillation circuit for processing the input voltage to obtain a pulse width modulation signal; and a charge pump output circuit for processing the pulse width modulation signal to obtain a first voltage.

[0007] Furthermore, the pulse oscillation circuit includes: a comparator's in-phase input circuit, including a comparator, a first resistor, a second resistor, a third resistor and a fourth resistor; a comparator's inverting input circuit, including a comparator, a fifth resistor, a sixth resistor and a first capacitor; wherein the in-phase input circuit and the inverting input circuit are used to form a hysteresis comparator, and the hysteresis comparator is used to generate a high-level signal and a low-level signal according to an input voltage and a preset period.

[0008] Furthermore, the pulse oscillation circuit also includes: a level inversion circuit, including a first transistor and a second transistor, for inverting a high level signal into a low level signal and inverting a low level signal into a high level signal based on the first transistor and the second transistor to form a pulse width modulation signal.

[0009] Furthermore, the charge pump output circuit includes a seventh resistor, a second capacitor, a first diode, a second diode, a third diode and a third capacitor, wherein the seventh resistor is used to limit the current of the pulse width modulated signal, the second capacitor is used to transfer the pulse width modulated signal after current limiting to the first diode and the second diode, the first diode and the second diode are used to rectify the pulse width modulated signal after current limiting, the third capacitor is used to filter the rectified pulse width modulated signal, and the third diode is used to limit the filtered pulse width modulated signal within a preset range to obtain a first voltage.

[0010] Further, the gate drive circuit includes: a third transistor, wherein the base of the third transistor is connected to the signal input terminal, the emitter of the third transistor is connected to the ground line, and the collector of the third transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor; a fourth transistor, wherein the source of the fourth transistor is connected to the cathode of the fourth diode, and the drain of the fourth transistor is connected to the drain of the fifth transistor; and a fifth transistor, wherein the source of the fifth transistor is connected to the drain of the fifth transistor through the body diode of the fifth transistor.

[0011] Furthermore, when the input signal is a high-level signal, the third transistor is used to convert the high-level signal into a low-level signal, and the fourth transistor and the fifth transistor are used to convert the low-level signal into a high-level signal, and the high-level signal is used as the output signal; when the input signal is a low-level signal, the third transistor is used to convert the low-level signal into a high-level signal, and the fourth transistor and the fifth transistor are used to convert the high-level signal into a low-level signal, and the low-level signal is used as the output signal.

[0012] Further, the cut-off circuit includes: a sixth transistor, wherein the gate of the sixth transistor is connected to the gate of the seventh transistor and then connected to the output end of the gate drive circuit, the source of the sixth transistor is connected to the load through the body diode of the sixth transistor, and the drain of the sixth transistor is connected to the load; a seventh transistor, wherein the source of the seventh transistor is connected to the load through the body diode of the sixth transistor, and the drain of the seventh transistor is connected to the output end of the power supply.

[0013] Further, when the output signal is a high level signal, the sixth transistor and the seventh transistor are turned on to make the power supply output terminal in an on state; when the output signal is a low level signal, the sixth transistor and the seventh transistor are turned off to make the power supply output terminal in an off state.

[0014] According to another aspect of an embodiment of the present invention, a switch system is further provided. The system includes the switch circuit mentioned above.

[0015] In an embodiment of the present invention, a charge pump circuit is used to process an input voltage to obtain a first voltage, wherein the first voltage is used to provide a driving voltage for a gate drive circuit; a gate drive circuit is used to receive an input signal from a signal input terminal, and process the input signal based on the first voltage to obtain an output signal, wherein the output signal is used to provide a switching signal for a cutoff circuit; and a cutoff circuit is used to control the opening or closing of an output terminal of a power supply according to the output signal, thereby controlling the way in which a load is powered, thereby improving the speed and accuracy of the switching operation, optimizing the space utilization rate of the circuit board, ensuring the stability and reliability of long-term operation, and achieving the purpose of better controlling the power supply of the power supply to the load, thereby achieving the technical effect of improving reliability and safety, and further solving the technical problem in the prior art of using relays as switching elements to control the power supply of the power supply to the load, which has low reliability and safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 is a schematic structural diagram of a switch circuit provided according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of a switch circuit provided according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a non-inverting input terminal circuit of a comparator provided according to an embodiment of the present invention;

[0020] Figure 4 Schematic diagram of an equivalent simplified circuit of a non-inverting input terminal circuit of a comparator provided according to an embodiment of the present invention Figure 1 ;

[0021] Figure 5 Schematic diagram of an equivalent simplified circuit of a non-inverting input terminal circuit of a comparator provided according to an embodiment of the present invention Figure 2 ;

[0022] Figure 6 is a schematic diagram of an inverting input terminal circuit of a comparator provided according to an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of a charging path provided according to an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of a discharge path provided according to an embodiment of the present invention;

[0025] Fig. 9 is a schematic diagram of a charge pump output circuit provided according to an embodiment of the present invention;

[0026] Fig.10 is a schematic diagram of a gate driving circuit provided according to an embodiment of the present invention;

[0027] Fig.11 is a schematic diagram of a bidirectional cutoff switch circuit provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] It should be noted that the relevant information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for display, data for analysis, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties. For example, an interface is set between the system and the relevant user or organization. Before obtaining relevant information, it is necessary to send an acquisition request to the aforementioned user or organization through the interface, and obtain relevant information after receiving the consent information fed back by the aforementioned user or organization.

[0031] Example 1

[0032] According to an embodiment of the present invention, a switch circuit is provided.

[0033] Figure 1 is a schematic diagram of the structure of a switch circuit provided according to an embodiment of the present invention. Figure 1 As shown, it includes: a charge pump circuit, which is used to process the input voltage to obtain a first voltage, wherein the first voltage is used to provide a driving voltage for the gate drive circuit; a gate drive circuit, which is used to receive an input signal from a signal input terminal, and process the input signal based on the first voltage to obtain an output signal, wherein the output signal is used to provide a switching signal for a cut-off circuit; and a cut-off circuit, which is used to control the opening or closing of the output terminal of the power supply according to the output signal, thereby controlling the power supply to the load.

[0034] Optionally, the charge pump circuit can also be called a self-excited charge pump generating circuit, the input voltage is the voltage of the OSC_IN terminal, the first voltage is the charge pump voltage Von (max), this voltage is a stable high level output by the charge pump circuit, it provides the required driving voltage for the gate drive circuit.

[0035] Optionally, the signal input terminal is the EN_IN terminal, the input signal is a high level signal or a low level signal, and the output signal is a high level signal or a low level signal output by the EN_OUT output terminal. Specifically, the gate drive circuit provides a switching signal to the cut-off circuit based on the input signal, and provides an operating drive voltage to the cut-off circuit based on the drive voltage (i.e., the first voltage).

[0036] Optionally, the cut-off circuit may also be referred to as a bidirectional cut-off switch circuit, and the power supply may be a variety of voltages such as 12V, 24V and 48V, for example, a DC power supply of 24V.

[0037] Figure 2 is a schematic diagram of a switch circuit provided according to an embodiment of the present invention, such as Figure 2As shown, the gate drive circuit is composed of an NPN transistor Q5, a PMOS tube Q1, an NMOS tube Q2 and peripheral circuits thereof; the self-excited charge pump generating circuit includes a pulse oscillation circuit and a charge pump output circuit, the pulse oscillation circuit is composed of a comparator COMP1 and peripheral circuits of its input and output ends, the charge pump output circuit is composed of a current limiting resistor R1, a coupling capacitor C3, freewheeling diodes D2, D3, a voltage regulator tube D4, and a filter capacitor C2; the bidirectional cutoff switch circuit is composed of NMOS tubes Q6 and Q8.

[0038] Specifically, the non-inverting input terminal of comparator COMP1 and the positive feedback circuit constructed by R4, R5, and R6 form a hysteresis comparator. The input high and low level thresholds of the comparator are V TH and V TL The working process is as follows: When the level of the comparator inverting input terminal is higher than V TH When the comparator outputs a low level, the comparator outputs a low level. When the comparator inverting input level is lower than V TL When , the comparator outputs a high level.

[0039] During system initialization, since the output terminal OSC_OUT is in a floating state, the NMOS tube Q7 is not turned on, and the RC circuit composed of resistor R2 and capacitor C4 starts to work. VCC (the 12V power supply voltage of the circuit) slowly charges C4 through R2. During the charging process, the level value of the OSC_IN terminal gradually increases. When the level value of OSC_IN rises to a value greater than or equal to the threshold V TH , the output of comparator COMP1 will become low level. This low level signal is connected to the gate of PMOS tube Q3 and NMOS tube Q4. Since the gate-source voltage (gate-to-source voltage) Vgs of Q3 is -12V, that is, the gate (g) is 12V lower than the source (s), Q3 is turned on, while the Vgs of Q4 is 0V (the gate and source are at the same level), and Q4 remains in a non-conducting state. Therefore, the voltage of the output terminal OSC_OUT will be pulled up to VCC. The high level signal at the OSC_OUT end is then connected to the gate of NMOS tube Q7, so that the Vgs of Q7 is VCC, and Q7 is therefore turned on.

[0040] As Q7 is turned on, the capacitor C4 at the OSC_IN terminal forms a discharge loop to the ground through the resistor R3. During the discharge process, the voltage at the OSC_IN terminal begins to drop. When the voltage level at the OSC_IN terminal drops below the threshold V TL, the output of comparator COMP1 will become high level. At this time, Vgs of Q3 becomes 0V, Q3 is not turned on, while Vgs of Q4 has a positive voltage, Q4 is turned on, so that the output of OSC_OUT becomes low level, causing Q7 to turn off. Subsequently, the level of OSC_IN rises again, thus forming a cycle. Through this cycle, OSC_OUT will output a regular pulse width modulation (PWM) cycle signal, and the frequency of the PWM waveform is related to the charge and discharge time of capacitor C4. In order to adjust the frequency of the output PWM signal, it can be achieved by changing the capacitance of capacitor C4 and the ratio of voltage divider resistors R2 and R3, so that the output frequency of the system can be accurately controlled according to specific application requirements.

[0041] In the gate drive circuit, when the input terminal EN_IN is high, according to the above driving principle, the output EN_OUT is also high. In this case, the source of Q8 and Q6 connects the load to GND through the body diode of Q6, and the level is clamped at a low potential (GND), so Vgs meets the conduction condition, and Q8 and Q6 are turned on. After turning on, the source voltage of Q8 is the voltage of the DC power supply, that is, 24V. At this time, the anode voltage of diode D3 is 24V, so the positive voltage of coupling capacitor C3 is also charged to 24V (ignore the voltage drop of D3).

[0042] According to the working principle of the charge pump, the negative pole of C3 is connected to a PWM waveform with an amplitude of VCC, which works continuously in the circuit. Therefore, the positive voltage of the coupling capacitor C3 will change with the change of the PWM waveform. When the PWM waveform is at a high level, the positive voltage of C3 is increased to 24V+VCC, and when the PWM waveform is at a low level, the positive voltage of C3 is 24V. After the PWM waveform is rectified by the diode D2, it is filtered by the filter capacitor C2 to generate a smoother high-level voltage Von(max) based on 24V (ignoring the diode voltage drop). This voltage is a stable high level output by the charge pump circuit, which provides the required drive voltage for the gate drive circuit.

[0043] At this time, a high level is input to EN_IN, the CE pole of Q5 is turned on, and the gates of Q1 and Q2 are grounded. Q1 meets the turn-on condition, Q1 is turned on, Q2 does not meet the turn-on condition, Q2 is turned off, and the gate voltage of Q6 and Q8 is Von(max). At this time, the gate-source voltage meets its turn-on condition, Q6 and Q8 are turned on, thereby ensuring that the DC source 24V can continuously power the load.

[0044] On the contrary, when the input terminal EN_IN is at a low level, the CE channel of Q5 is turned off, and the gates of Q1 and Q2 are pulled high, the Vgs of Q1 is 0V, Q1 is turned off, Q2 meets the conduction condition, Q2 is turned on, and Q2 turns on, causing the gate-source of Q6 and Q8 to turn on, Vgs = 0V, and Q6 and Q8 are turned off. Due to the cut-off of Q8 and Q6, the DC power supply 24V stops supplying power to the load.

[0045] It should be noted that this control mechanism turns on or off the power supply output according to the change of the EN_IN terminal signal, thereby achieving precise control of the load power supply.

[0046] In an optional embodiment, the charge pump circuit includes: a pulse oscillation circuit for processing an input voltage to obtain a pulse width modulation signal; and a charge pump output circuit for processing the pulse width modulation signal to obtain a first voltage.

[0047] In an optional embodiment, the pulse oscillation circuit includes: a comparator's in-phase input circuit, including a comparator, a first resistor, a second resistor, a third resistor and a fourth resistor; a comparator's inverting input circuit, including a comparator, a fifth resistor, a sixth resistor and a first capacitor; wherein the in-phase input circuit and the inverting input circuit are used to form a hysteresis comparator, and the hysteresis comparator is used to generate a high-level signal and a low-level signal according to an input voltage and a preset period.

[0048] In an optional embodiment, the pulse oscillation circuit also includes: a level inversion circuit, including a first transistor and a second transistor, used to invert a high-level signal into a low-level signal, and invert a low-level signal into a high-level signal based on the first transistor and the second transistor, to form a pulse width modulation signal.

[0049] Figure 3 is a schematic diagram of a non-inverting input terminal circuit of a comparator provided according to an embodiment of the present invention, such as Figure 3 As shown, it includes a comparator COMP1, a first resistor R4, a second resistor R5, a third resistor R6 and a fourth resistor R7. The reference voltage at the in-phase input terminal is the voltage divided value between R4 and R5. This value changes between the high and low outputs of the comparator, thereby forming a hysteresis comparison with the inverting input voltage. The larger value of this voltage is the input start voltage threshold V TH , the smaller value is the input shutdown voltage threshold V TL The determination of the upper and lower thresholds is related to the voltage divider ratio of resistors R4, R5, R6, and R7. The following describes the input shutdown voltage threshold V TL and input turn-on voltage threshold V TH The specific calculation process.

[0050] Input shutdown threshold voltage V TLThe specific calculation process is as follows:

[0051] When the comparator output is low, Figure 4 Schematic diagram of an equivalent simplified circuit of a non-inverting input terminal circuit of a comparator provided according to an embodiment of the present invention Figure 1 ,like Figure 4 As shown, according to the setting V TL , which satisfies:

[0052]

[0053] Input turn-on threshold voltage V TH The specific calculation process is as follows:

[0054] When the comparator output is high, Figure 5 Schematic diagram of an equivalent simplified circuit of a non-inverting input terminal circuit of a comparator provided according to an embodiment of the present invention Figure 2 ,like Figure 5 As shown, according to the setting V TH , which satisfies:

[0055]

[0056] By setting the values ​​of R4 and R7, the values ​​of R5 and R6 can be calculated according to the formula.

[0057] Figure 6 is a schematic diagram of an inverting input terminal circuit of a comparator provided according to an embodiment of the present invention, such as Figure 6 As shown, it includes a comparator COMP1, a fifth resistor R2, a sixth resistor R3 and a first capacitor C4. R2 and C4 form an RC circuit. VCC slowly charges the capacitor C4 after passing through R2. During the charging process, the level value of the OSC_IN terminal gradually increases. When the level rises to a value greater than or equal to V TH When the comparator reaches the threshold, the comparator outputs a low level, and the output terminal is connected to the gates of Q3 and Q4. The Vgs of Q3 is -12V, Q3 is turned on, the Vgs of Q4 is 0V, Q4 is not turned on, and the voltage of the output terminal OSC_OUT is VCC. OSC_OUT is connected to the gate of the NMOS tube Q8, the Vgs of Q8 is VCC, and Q8 is turned on. At this time, the level of OSC_IN drops after being divided by R3 to the ground. When the level drops below V TL When the comparator outputs a high level, after being inverted by the level inversion circuit composed of the first transistor Q3 and the second transistor Q4, OSC_OUT outputs a low level, so that Q8 is turned off, and the OSC_IN level will rise again, and this cycle will continue.

[0058] After voltage division, the voltage value at the upper end of R3 needs to be less than or equal to the low level threshold of the comparator, that is, the resistance values ​​of resistors R2 and R3 need to meet the following requirements:

[0059]

[0060] By setting the resistance value of R2, the resistance value of R3 can be calculated according to the formula.

[0061] Optionally, the PWM period T of the charge pump is determined by the charge and discharge time, and the charge and discharge are divided into two stages: Figure 7 is a schematic diagram of a charging path according to an embodiment of the present invention. The charging path of capacitor C4 in the charging stage is as follows Figure 7 As shown, according to the capacitor charging formula, the charging state satisfies:

[0062]

[0063] Among them, V0 is the initial voltage value on the capacitor, that is, 0V, and T1 is the charging time of capacitor C4. According to the above formula, T1 can be obtained:

[0064]

[0065] Figure 8 Schematic diagram of a discharge path according to an embodiment of the present invention. The discharge path of capacitor C4 in the discharge phase is as follows: Figure 8 As shown, according to the capacitor discharge formula, the discharge state satisfies:

[0066]

[0067] Where T2 is the discharge time of capacitor C4. According to the above formula, T2 can be obtained:

[0068]

[0069] Assuming that the PWM waveform period T (frequency F=1 / T) of the charge pump is required, according to T=T1+T2, the frequency F of the PWM waveform can be set by adjusting the values ​​of R2, C4, and R3.

[0070] In an optional embodiment, the charge pump output circuit includes a seventh resistor, a second capacitor, a first diode, a second diode, a third diode and a third capacitor, wherein the seventh resistor is used to limit the current of the pulse width modulated signal, the second capacitor is used to transfer the pulse width modulated signal after current limiting to the first diode and the second diode, the first diode and the second diode are used to rectify the pulse width modulated signal after current limiting, the third capacitor is used to filter the rectified pulse width modulated signal, and the third diode is used to limit the filtered pulse width modulated signal within a preset range to obtain a first voltage.

[0071] Fig. 9 is a schematic diagram of a charge pump output circuit provided according to an embodiment of the present invention, such as Fig. 9As shown, it includes a seventh resistor R1, a second capacitor C3, a first diode D2, a second diode D3, a third diode D4 and a third capacitor C2. The value of the coupling capacitor C3 can be determined according to the operating frequency of the charge pump. Optionally, the value of C3 is calculated using the following capacitive reactance formula:

[0072]

[0073] Among them, f is the operating frequency of the charge pump, C is the value of capacitor C3, and the capacitive reactance XC is generally set to be less than 10Ω based on experience. Through this formula, the appropriate value of C3 can be obtained.

[0074] Optionally, R1 is a current limiting resistor, which is used to limit the current. Generally, the value of R1 is about tens of ohms. The freewheeling diodes D2 and D3 can be Schottky diodes, which have the characteristics of small forward voltage drop and short reverse recovery time, which are conducive to improving the efficiency and response speed of the charge pump.

[0075] Specifically, when the EN_OUT output is high, since the source of Q8 is pulled down to the ground through the body diode of Q6 and the load, the source of Q8 is initially at a low level, and Vgs of Q8 = VCC, so the turn-on condition is met. After Q8 is turned on, the source voltage of Q8 will rise to VDC (the input DC voltage of the charge pump), and the source voltage of Q8 passes through the D3 → D2 → Q1 loop to the gates of Q8 and Q6. At this time, Vgs of Q8 = -2*V D (V D =The voltage drop of diodes D2 and D3), Q8 cannot be turned on, so a charge pump voltage needs to be introduced.

[0076] The charge pump starts normally after VCC is powered. Its working principle is as follows: When the PWM signal is low (0V), the negative electrode of C3 is grounded, and the positive electrode voltage of C3 will be charged to VDC-V D Then, when the PWM signal becomes high (VCC), due to the fact that the voltage across the capacitor cannot change instantly, the voltage at the positive electrode of C3 will quickly rise to VCC+(VDC-V D ). Therefore, the voltage of the positive electrode of C3 is VCC+(VDC-V D ), while at low level it is VDC-V D The voltage waveform at the positive electrode of C3 flows to the positive electrode of the filter capacitor C2 through the freewheeling diode, and after being smoothed and filtered by the filter capacitor C2, a stable voltage waveform is output.

[0077] In order to protect Q8 and Q6 and prevent the voltage between their gate and source from exceeding the maximum rated value Vgs(max), a voltage regulator D4 is connected in parallel between the gate and source of Q8. The voltage regulation value can be selected according to the withstand voltage value of Vgs. When the filtered voltage exceeds the Vgs(max) of Q8 and Q6, the voltage regulator D4 will clamp the voltage within the safe operating voltage range, thereby preventing Q8 and Q6 from being damaged due to overvoltage. The voltage clamped by the voltage regulator D4 is output to the gates of Q8 and Q6. When Vgs meets the turn-on voltage requirement, Q8 and Q6 will be turned on, so that the DC voltage source can continuously power the load.

[0078] Optionally, the capacitance value of C2 should satisfy the following conditions:

[0079]

[0080] Wherein, Qg,tota is the sum of the gate input charges of Q8 and Q6, and Vgs(th) is the threshold turn-on voltage of Q8 and Q6.

[0081] In an optional embodiment, the gate drive circuit includes: a third transistor, wherein the base of the third transistor is connected to the signal input terminal, the emitter of the third transistor is connected to the ground line, and the collector of the third transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor; a fourth transistor, wherein the source of the fourth transistor is connected to the cathode of the fourth diode, and the drain of the fourth transistor is connected to the drain of the fifth transistor; and a fifth transistor, wherein the source of the fifth transistor is connected to the drain of the fifth transistor through the body diode of the fifth transistor.

[0082] In an optional embodiment, when the input signal is a high-level signal, the third transistor is used to convert the high-level signal into a low-level signal, the fourth transistor and the fifth transistor are used to convert the low-level signal into a high-level signal, and the high-level signal is used as the output signal; when the input signal is a low-level signal, the third transistor is used to convert the low-level signal into a high-level signal, the fourth transistor and the fifth transistor are used to convert the high-level signal into a low-level signal, and the low-level signal is used as the output signal.

[0083] Fig.10 is a schematic diagram of a gate driving circuit provided according to an embodiment of the present invention, such as Fig.10 As shown, it includes a third transistor (NPN transistor Q5), a fourth transistor (PMOS transistor Q1), and a fifth transistor (NMOS transistor Q2). The circuit is designed to provide efficient and reliable level conversion. The fourth diode is D1.

[0084] When the EN_IN input receives a high-level signal, the CE channel of Q5 is turned on, and its collector outputs a low level. Then, this low-level signal passes through the combination of PMOS tube Q1 and NMOS tube Q2, and after the level logic is reversed, the EN_OUT output terminal finally outputs a high level, and its voltage amplitude is VCC-V D (V D is the conduction voltage drop of diode D1).

[0085] When the EN_IN input receives a low-level signal, the CE channel of Q5 is cut off. At this time, the collector of Q5 is pulled to a high level by the pull-up resistor, Q2 is turned on, Q1 is cut off, and the drain of the NMOS tube Q2 is pulled to a low level due to the conduction of Q5, resulting in the EN_OUT output terminal outputting a low level. Therefore, the gate drive circuit can accurately control the state of the EN_OUT output terminal according to the level of the EN_IN input signal.

[0086] In an optional embodiment, the cut-off circuit includes: a sixth transistor, wherein the gate of the sixth transistor is connected to the gate of the seventh transistor and then connected to the output end of the gate drive circuit, the source of the sixth transistor is connected to the load through the body diode of the sixth transistor, and the drain of the sixth transistor is connected to the load; a seventh transistor, wherein the source of the seventh transistor is connected to the load through the body diode of the sixth transistor, and the drain of the seventh transistor is connected to the output end of the power supply.

[0087] In an optional embodiment, when the output signal is a high-level signal, the sixth transistor and the seventh transistor are turned on to turn on the power supply output terminal; when the output signal is a low-level signal, the sixth transistor and the seventh transistor are turned off to turn off the power supply output terminal.

[0088] Fig.11 is a schematic diagram of a bidirectional cutoff switch circuit provided according to an embodiment of the present invention, such as Fig.11 As shown, it is composed of two identical NMOS tubes Q8 (i.e., the seventh transistor) and Q6 (i.e., the sixth transistor) back to back. Q8 and Q6 are turned on and off at the same time under the control of the output signal of the gate drive circuit, which has the advantages of preventing forward leakage current and reverse connection. It allows the conduction of positive or negative current in the on state, and in the off state, the body diodes inside the two back-to-back MOS tubes will effectively block the flow of current, thereby effectively blocking the positive or negative voltage, whether forward or reverse, thereby ensuring the stability and safety of the switch in the off state.

[0089] Specifically, when the output signal is a high-level signal, Q6 and Q8 are turned on, so that the output end of the power supply is in an on state, and the power supply supplies power to the load; when the output signal is a low-level signal, Q6 and Q8 are turned off, so that the output end of the power supply is in a closed state, and the power supply does not supply power to the load.

[0090] In an embodiment of the present invention, a charge pump circuit is used to process an input voltage to obtain a first voltage, wherein the first voltage is used to provide a driving voltage for a gate drive circuit; a gate drive circuit is used to receive an input signal from a signal input terminal, and process the input signal based on the first voltage to obtain an output signal, wherein the output signal is used to provide a switching signal for a cutoff circuit; and a cutoff circuit is used to control the opening or closing of an output terminal of a power supply according to the output signal, thereby controlling the way in which a load is powered, thereby improving the speed and accuracy of the switching operation, optimizing the space utilization rate of the circuit board, ensuring the stability and reliability of long-term operation, and achieving the purpose of better controlling the power supply of the power supply to the load, thereby achieving the technical effect of improving reliability and safety, and further solving the technical problem in the prior art of using relays as switching elements to control the power supply of the power supply to the load, which has low reliability and safety.

[0091] Example 2

[0092] According to another aspect of an embodiment of the present invention, a switch system is further provided. The system includes the switch circuit mentioned above.

[0093] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0094] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The embodiments described above are only schematic. For example, the division of units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0096] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0097] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A switching circuit, characterized in that: include: A charge pump circuit, used for processing an input voltage to obtain a first voltage, wherein the first voltage is used to provide a driving voltage for a gate driving circuit; The gate driving circuit is used to receive an input signal from a signal input terminal, and process the input signal based on the first voltage to obtain an output signal, wherein the output signal is used to provide a switch signal for the cutoff circuit; The cut-off circuit is used to control the opening or closing of the output end of the power supply according to the output signal, so as to control the power supply to the load.

2. The circuit according to claim 1, characterized in that The charge pump circuit comprises: A pulse oscillation circuit, used for processing the input voltage to obtain a pulse width modulation signal; The charge pump output circuit is used to process the pulse width modulation signal to obtain the first voltage.

3. The circuit according to claim 2, characterized in that The pulse oscillation circuit comprises: A non-inverting input circuit of a comparator, comprising the comparator, a first resistor, a second resistor, a third resistor and a fourth resistor; The inverting input circuit of the comparator comprises the comparator, a fifth resistor, a sixth resistor and a first capacitor; The in-phase input terminal circuit and the inverting input terminal circuit are used to form a hysteresis comparator, and the hysteresis comparator is used to generate a high level signal and a low level signal according to the input voltage and a preset period.

4. The circuit according to claim 3, characterized in that The pulse oscillation circuit also includes: The level inversion circuit includes a first transistor and a second transistor, and is used to invert the high level signal into a low level signal and invert the low level signal into a high level signal according to the first transistor and the second transistor to form the pulse width modulation signal.

5. The circuit according to claim 2, characterized in that The charge pump output circuit includes a seventh resistor, a second capacitor, a first diode, a second diode, a third diode and a third capacitor, wherein the seventh resistor is used to limit the current of the pulse width modulated signal, the second capacitor is used to transfer the pulse width modulated signal after current limiting to the first diode and the second diode, the first diode and the second diode are used to rectify the pulse width modulated signal after current limiting, the third capacitor is used to filter the rectified pulse width modulated signal, and the third diode is used to limit the filtered pulse width modulated signal within a preset range to obtain the first voltage.

6. The circuit according to claim 1, characterized in that The gate drive circuit comprises: a third transistor, wherein a base of the third transistor is connected to the signal input terminal, an emitter of the third transistor is connected to a ground line, and a collector of the third transistor is connected to a gate of the fourth transistor and a gate of the fifth transistor; The fourth transistor, wherein a source of the fourth transistor is connected to a cathode of a fourth diode, and a drain of the fourth transistor is connected to a drain of the fifth transistor; The fifth transistor, wherein the source of the fifth transistor is connected to the drain of the fifth transistor through the body diode of the fifth transistor.

7. The circuit according to claim 6, characterized in that When the input signal is a high-level signal, the third transistor is used to convert the high-level signal into a low-level signal, and the fourth transistor and the fifth transistor are used to convert the low-level signal into a high-level signal, and the high-level signal is used as the output signal; When the input signal is a low level signal, the third transistor is used to convert the low level signal into a high level signal, and the fourth transistor and the fifth transistor are used to convert the high level signal into a low level signal, and the low level signal is used as the output signal.

8. The circuit according to claim 1, characterized in that The cut-off circuit comprises: a sixth transistor, wherein a gate of the sixth transistor is connected to the gate of the seventh transistor and then connected to the output end of the gate driving circuit, a source of the sixth transistor is connected to the load through a body diode of the sixth transistor, and a drain of the sixth transistor is connected to the load; The seventh transistor, wherein the source of the seventh transistor is connected to the load through the body diode of the sixth transistor, and the drain of the seventh transistor is connected to the output end of the power supply.

9. The circuit according to claim 8, characterized in that When the output signal is a high level signal, the sixth transistor and the seventh transistor are turned on, so that the power supply output terminal is in an on state; When the output signal is a low level signal, the sixth transistor and the seventh transistor are turned off, so that the power supply output terminal is in a closed state.

10. A switch system, characterized in that: A switching circuit comprising any one of claims 1 to 9.

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