Airborne stepping motor control system and method based on FPGA
Through the FPGA-based airborne stepper motor control system, the problem of high stepper motor control requirements in airborne aviation equipment systems is solved, and efficient and reliable stepper motor drive and trip protection is achieved, with wide application prospects.
Patent Information
- Application Number
- CN202411801989.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-04-25
AI Technical Summary
The control requirements of stepper motors in airborne aviation equipment systems are high, especially for real-time and safety requirements. It is difficult for the prior art to effectively achieve efficient and reliable stepper motor control.
The onboard stepper motor control system based on FPGA is adopted, including a logic part, a drive part and a two-phase full bridge part. Through the FPGA interface processing module, a motor control module, a drive waveform generation module and a trip detection module, the open-loop driving and tripping protection of the stepper motor is realized.
The continuous pressing and discontinuous rotation of stepper motors is realized, which increases the safety and reliability of motor drives, reduces the use of special driving chips, reduces the development costs, and has a wide range of application prospects.
Smart Images
Figure CN119891833A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of motor control technology, and in particular to an FPGA-based airborne stepper motor control system and method. Background Art
[0002] In airborne aviation equipment systems, there are a large number of control valves and regulating valves, most of which are realized by stepper motors. With the development of airborne control systems, the types of stepper motor equipment in airborne products are becoming more and more abundant, and the control requirements are higher, often with very high requirements for real-time control. Summary of the invention
[0003] In view of this, an embodiment of the present application provides an FPGA-based airborne stepper motor control system and method to implement open-loop drive processing of the airborne system stepper motor.
[0004] In the first aspect, the embodiment of the present application provides an airborne stepper motor control system based on FPGA, the system includes a logic part, a drive part and a two-phase full-bridge part, the logic part includes an FPGA interface processing module, an FPGA motor control module, a drive waveform generation module and a trip detection module; the FPGA interface processing module is used to receive control instructions, and the control instruction input is read and written by the agreed bus address between the DSP and the FPGA; the FPGA motor control module is used to parse the control instruction and issue it, and decide whether to cut off the output according to the trip signal reported by the trip detection module; the drive waveform generation module is used to generate a control signal for controlling the drive circuit according to the analysis result, and when the stepper motor completes the rotation, the completion status is fed back to the DSP; the trip detection module is used to detect the current on the stepper motor line in real time, and decide whether to generate a trip signal according to the current value;
[0005] The driving part is used for control and drive isolation, level conversion of control signals and fast driving of electronic switches; the two-phase full-bridge part directly interacts with the stepper motor and is used for inverting direct current into alternating current for driving the stepper motor.
[0006] According to a specific implementation method of an embodiment of the present application, the two-phase full-bridge part is composed of 8 electronic switches, and each half bridge is divided into an upper bridge arm and a lower bridge arm. According to the control signal of the logic part, the direct current is inverted into alternating current to drive the stepper motor.
[0007] According to a specific implementation of the embodiment of the present application, the stepper motor is a two-phase four-wire hybrid stepper motor, and the A and B phase windings of the stepper motor are radially staggered around the rotor.
[0008] According to a specific implementation method of an embodiment of the present application, the driving mode of the stepper motor adopts dual four-beat drive, and two phases are energized at the same time; each time the input pulse switches, the stepper motor rotates one step angle; when rotating forward, the power-on phase sequence is A+B+, A+B-, AB-, A-B+ cycle, and when rotating reversely, the power-on phase sequence is A-B+, AB-, A+B-, A+B+.
[0009] According to a specific implementation of the embodiment of the present application, the stepper motor is designed to start at 400 Hz for the first 12 steps and then rotate at a frequency of 600 Hz.
[0010] According to a specific implementation of the embodiment of the present application, when the stepper motor changes the power-on phase sequence, a dead time of 400 microseconds is set.
[0011] According to a specific implementation of the embodiment of the present application, the control signal for controlling the driving circuit generated by the driving waveform generating module adopts a three-segment driving waveform method.
[0012] According to a specific implementation of the embodiment of the present application, the completion status fed back to the DSP includes the running status, overcurrent status, locking status and direction information of the stepper motor.
[0013] In a second aspect, an embodiment of the present application further provides an FPGA-based airborne stepper motor control method, which is implemented based on the FPGA-based airborne stepper motor control system described in any embodiment of the first aspect, and the method includes:
[0014] DSP sends control instructions through the data bus, and the control instruction input is read and written by the agreed bus address between DSP and FPGA;
[0015] After receiving the motor rotation direction, rotation step number and speed command configured by DSP, the FPGA logic part starts to generate PWM drive pulse signal to control the rotation of the stepper motor;
[0016] When the stepper motor completes its rotation, the completion status will be fed back to the DSP.
[0017] According to a specific implementation of the embodiment of the present application, the generating of a PWM driving pulse signal to control the rotation of the stepper motor includes:
[0018] Step 1: The current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0019] Step 2: The current flows from AN to AL, and the current gradually decreases. At this time, A+ outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave;
[0020] Step 3: The current flows from AL to AN, and the current gradually increases. At this time, A- outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0021] Step 4: The current flows from AL to AN, and the current gradually decreases. At this time, A- outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave;
[0022] Step 5: The current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0023] Repeat steps 1 to 5 in sequence.
[0024] Beneficial effects:
[0025] The FPGA-based airborne stepper motor control system and method in the embodiment of the present application uses FPGA to implement the stepper motor drive algorithm, which can realize continuous pressing and discontinuous rotation of the stepper motor without adding a feedback loop; in addition, a stepper motor tripping protection mechanism is added, which can cut off the output in time when the stepper motor drive current is too large to avoid damage to the motor and ensure the safety and reliability of the motor drive. The present application has good practicality and wide adaptability in controller products, and has broad application prospects in the field of aviation airborne display. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0027] Figure 1 is a principle block diagram of a driving circuit according to an embodiment of the present invention;
[0028] Figure 2 is a hardware schematic diagram of an H-bridge according to an embodiment of the present invention;
[0029] Figure 3 for Figure 2 The enlarged view of the AN side in FIG.
[0030] Figure 4 for Figure 2The enlarged view of the AL side in;
[0031] Figure 5 is a schematic diagram of a motor driving waveform according to an embodiment of the present invention;
[0032] Figure 6 FIG. 4 is a flow chart of stepper motor fault determination according to an embodiment of the present invention. DETAILED DESCRIPTION
[0033] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0034] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.
[0035] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0036] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0037] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0038] The present application embodiment provides an FPGA-based airborne stepper motor control system and method, as shown below: Figures 1 to 6 Describe in detail.
[0039] First, refer to Figure 1 The embodiment of the present application provides an airborne stepper motor control system based on FPGA, the system includes a logic part, a drive part and a two-phase full-bridge part, the logic part includes an FPGA interface processing module, an FPGA motor control module, a drive waveform generation module and a trip detection module; the FPGA interface processing module is used to receive control instructions, and the control instruction input is read and written by the agreed bus address between the DSP and the FPGA; the FPGA motor control module is used to parse the control instruction and issue it, and decide whether to cut off the output according to the trip signal reported by the trip detection module; the drive waveform generation module is used to generate a control signal for controlling the drive circuit according to the analysis result, and when the stepper motor completes the rotation, the completion status is fed back to the DSP; the trip detection module is used to detect the current on the stepper motor circuit in real time, and decide whether to generate a trip signal according to the current value;
[0040] The driving part is used for control and drive isolation, level conversion of control signals and fast driving of electronic switches; the two-phase full-bridge part directly interacts with the stepper motor and is used for inverting direct current into alternating current for driving the stepper motor.
[0041] In the specific implementation, the construction of the FPGA-based hardware platform mainly includes the following contents:
[0042] The motor control hardware circuit is mainly composed of three parts: logic, drive, and two-phase full bridge. The functions of each part are as follows: Figure 1 shown.
[0043] The FPGA logic part is mainly composed of programmable logic devices, which are used to realize the main task scheduling, data processing and flow control, generate PWM signals to control the drive circuit according to the control instructions, collect and process analog signals such as Hall sensor signals, and monitor the power supply voltage. The internal part is mainly composed of four modules: FPGA interface processing module, FPGA motor control module, drive waveform generation module and trip detection module. The FPGA interface processing module is mainly used to receive control instructions issued by the host computer or DSP, including information such as motor rotation direction, motor rotation steps, and motor rotation frequency. The FPGA motor control module is mainly used to parse instructions. The drive waveform generation module is mainly used to generate the waveform required for motor rotation. The trip detection module is used to detect the current on the stepper motor line in real time, and decide whether to generate a trip signal based on the current value.
[0044] The hardware design functional circuit converts the control signal generated by the logic part into the drive signal of the next-level H-bridge, opens or closes the electronic switch of the H-bridge, connects the DC power supply to the two-phase winding of the stepper motor according to the sequence given by the control end, and isolates the control end from the drive end.
[0045] In one embodiment, the two-phase full-bridge part is composed of 8 electronic switches, and each half bridge is divided into an upper bridge arm and a lower bridge arm, which are complementary and turned on according to the control signal of the logic part to invert DC power into AC power to drive the stepper motor.
[0046] Specifically, the two-phase H full bridge is located at the end of the control system and interacts directly with the motor. The two-phase H full bridge consists of 8 electronic switches, and each half bridge is divided into an upper arm and a lower arm. According to the control signal of the logic part, the DC power is inverted into AC power to drive the motor. The single-phase half H bridge hardware circuit schematic is shown in the figure. Figures 2 to 4 When A+ is valid, the upper tube of the upper bridge arm of the H bridge and the lower tube of the lower bridge arm of the H bridge are turned on, and the current flows from AN through the motor to AL. When A- is valid, the lower tube of the upper bridge arm of the H bridge and the upper tube of the lower bridge arm of the H bridge are turned on, and the current flows from AL through the motor to AN. The current acquisition module is responsible for collecting the current flowing through the motor.
[0047] In one embodiment, the stepper motor is a two-phase four-wire hybrid stepper motor, and the A and B phase windings of the stepper motor are staggered and distributed radially around the rotor.
[0048] In one embodiment, the stepper motor is driven by dual four-beat drive, with two phases energized at the same time; each time the input pulse switches, the stepper motor rotates one step angle; when rotating forward, the power-on phase sequence is A+B+, A+B-, AB-, A-B+ cycle, and when rotating reversely, the power-on phase sequence is A-B+, AB-, A+B-, A+B+.
[0049] In one embodiment, the stepper motor is designed to start at 400 Hz for the first 12 steps and then rotate at 600 Hz.
[0050] In one embodiment, when the stepper motor changes the power-on phase sequence, a dead time of 400 microseconds is set.
[0051] In one embodiment, the control signal for controlling the driving circuit generated by the driving waveform generating module adopts a three-segment driving waveform mode.
[0052] In one embodiment, the completion status fed back to the DSP includes the running status, overcurrent status, locking status and direction information of the stepper motor.
[0053] During the specific implementation, the FPGA logic design solution specifically includes the following contents:
[0054] The control logic of the stepper motor consists of four modules: FPGA interface processing module, FPGA motor control module, drive waveform generation module, and trip detection module. The command input of the FPGA interface processing module is read and written by the agreed bus address between DSP and FPGA; the FPGA motor control module can parse and issue specific motor working instructions, and decide whether to cut off the output based on the trip information reported by the trip detection module; the PWM drive of the drive waveform generation module is completed by FPGA alone. After the FPGA logic receives the motor rotation direction, rotation steps and speed instructions configured by DSP, it starts to generate PWM drive pulse signals to control the motor rotation. When the motor rotation is completed, the completion status will be fed back to DSP. The state feedback logic mainly realizes the feedback of the motor's operating status, overcurrent status, locking status and direction to DSP; the trip detection module is used to detect the current on the stepper motor line in real time, and decide whether to generate a trip signal based on the current value.
[0055] This embodiment adopts a two-phase four-wire hybrid stepper motor, which is divided into two parts: a stator and a rotor. The rotor is a permanent magnet and the stator is a coil. The A and B phase windings of the stepper motor are staggered around the rotor radially. The stepper motor drive is realized by orderly controlling the current in the motor excitation winding. The driving mode of this scheme adopts a double four-beat drive, and two phases are energized at the same time; each time the input pulse is switched, the stepper motor rotates a step angle. Because it is two-phase energized, it has a greater torque than a single four-beat drive. When rotating forward, the energized phase sequence is A+B+, A+B-, AB-, A-B+ cycle, and the reverse rotation energized sequence is A-B+, AB-, A+B-, A+B+. The stepper motor is designed to start at 400Hz for the first 12 steps and then rotate at a frequency of 600Hz. In order to avoid the upper and lower tubes of the MOS tube from being turned on at the same time and causing burning when the energized phase sequence is changed, a dead time of 400 microseconds is set when the energized phase sequence is changed.
[0056] According to the mechanism analysis, the driving current is increased to increase the current torque. The motor driver is open-loop drive before and after the program is changed. The power supply sequence is A+B+ to A+B- to AB- to A-B+. Taking phase A as an example, the four steps of motor rotation can be divided into:
[0057] In the first step, the current flows from AN to AL, and the current gradually increases;
[0058] In the second step, the current flows from AN to AL, and the current gradually decreases;
[0059] In the third step, the current flows from AL to AN, and the current gradually increases;
[0060] In the fourth step, the current flows from AL to AN, and the current gradually decreases;
[0061] In the fifth step, the current flows from AN to AL, and the current gradually increases;
[0062] Cycle in sequence.
[0063] The FPGA motor driver adds a current acceleration process to speed up the current growth and reduce the speed. The drive waveform generation module outputs a three-stage drive waveform. First, turn on the two-phase full-bridge MOS tube to quickly reach the rated current, then use a PWM square wave to maintain the current, and then turn it off. That is:
[0064] In the first step, the current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0065] In the second step, the current flows from AN to AL, and the current gradually decreases. At this time, A+ outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave;
[0066] In the third step, the current flows from AL to AN, and the current gradually increases. At this time, A- outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0067] In the fourth step, the current flows from AL to AN, and the current gradually decreases. At this time, A- outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave;
[0068] In the fifth step, the current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0069] Cycle in sequence.
[0070] After the drive is improved, the electric drive waveform is as follows Figure 5 shown.
[0071] As can be seen from the figure, when the driving MOS tube is turned on in the first stage, the current quickly climbs to the rated current, and then the current can be maintained or slowly decreased when the higher frequency PWM square wave is output. In the off state, the current decreases rapidly. After the change, the peak current can fully reach the rated current, ensuring that the electromagnetic driving force is sufficient, and due to the existence of high-frequency PWM, the current can be maintained in a fixed range for a certain period of time, further increasing the electromagnetic driving force.
[0072] Before the improvement, the voltage drive was PWM square wave drive in a certain drive, so the climbing mode was step-up. At 600Hz frequency, the current did not climb to the rated current, and entered the next phase rotation state. At this time, the current of this phase entered the attenuation state. Therefore, the driving force was insufficient.
[0073] After the improvement, the voltage drive is normally open in a certain drive, so the climbing mode is a linear rise. At a frequency of 600Hz, the current can normally climb to the rated current, and the driving force is sufficient.
[0074] At the same time, a tripping function is added to realize motor overcurrent protection.
[0075] Principle of stepper motor trip detection: When the output signal of the stepper motor is valid, detect A+, A-, B+, B-current. When the current meets the trip condition, the trip condition is shown in Table 1. Its trip curve conforms to the I 2t curve, that is, the larger the overcurrent, the faster the reaction time. For example, when the current is greater than 3 times the rated current and the duration is greater than 206ms, or when the current is greater than 8 times the rated current and the duration is greater than 20us, the corresponding stepper motor drive channel trip command is generated, and all stepper motor outputs are cut off at the same time. That is: the motor current recovery method of the FPGA program is realized by FPGA accessing the analog acquisition chip. When the hardware circuit is designed, the output load current is processed by recovery, conditioning and amplification, and then connected to the analog acquisition chip. The FPGA periodically reads the current value, and the update cycle is less than 5us. When the collected motor drive current meets the trip condition, the Trip trip action is generated.
[0076] Reference Figure 6 , the specific stepper motor fault judgment process includes:
[0077] RI U is powered on and enters normal working mode;
[0078] Read back the FPGA motor rotation flag. If it is rotating, RI U determines the current of the motor at this time. If not, it ends.
[0079] If the current is less than 1A, a circuit breaker occurs and the motor reports EXT FALL;
[0080] If the current meets the tripping condition, TRIP is generated and the motor reports RI U FALL;
[0081] End the judgment process.
[0082] Table 1 Tripping multiple time correspondence table
[0083]
[0084]
[0085] In a second aspect, an embodiment of the present application further provides an FPGA-based airborne stepper motor control method, which is implemented based on the FPGA-based airborne stepper motor control system described in any embodiment of the first aspect, and the method includes:
[0086] DSP sends control instructions through the data bus, and the control instruction input is read and written by the agreed bus address between DSP and FPGA;
[0087] After receiving the motor rotation direction, rotation step number and speed command configured by DSP, the FPGA logic part starts to generate PWM drive pulse signal to control the rotation of the stepper motor;
[0088] When the stepper motor completes its rotation, the completion status will be fed back to the DSP.
[0089] Furthermore, the generating of the PWM driving pulse signal to control the rotation of the stepping motor includes:
[0090] Step 1: The current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0091] Step 2: The current flows from AN to AL, and the current gradually decreases. At this time, A+ outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave;
[0092] Step 3: The current flows from AL to AN, and the current gradually increases. At this time, A- outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0093] Step 4: The current flows from AL to AN, and the current gradually decreases. At this time, A- outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave;
[0094] Step 5: The current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave;
[0095] Repeat steps 1 to 5 in sequence.
[0096] The FPGA-based airborne stepper motor drive control method of the present application is as follows: first, the system is powered on, and the DSP sends instructions through the data bus. The instruction input is read and written by the agreed bus address between the DSP and the FPGA. The PWM drive is completed by the FPGA alone. After the FPGA logic receives the motor rotation direction, rotation step number and speed instructions configured by the DSP, it starts to generate a PWM drive pulse signal to control the motor rotation. When the motor rotation is completed, the completion status will be fed back to the DSP. The state feedback logic mainly realizes the feedback of information such as the motor's operating status, overcurrent status, locking status and direction to the DSP.
[0097] The embodiment provided by the present invention can realize the open-loop drive of the stepper motor; support the rotation of the motor with any number of step instructions, and have a trip protection function. The driving reliability and safety of the stepper motor are increased, the use of dedicated drive chips is reduced, and the development cost is reduced. In airborne equipment, this FPGA-based open-loop drive and trip detection of stepper motors has potential application value.
[0098] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. An airborne stepper motor control system based on FPGA, characterized in that: The system includes a logic part, a drive part and a two-phase full-bridge part. The logic part includes an FPGA interface processing module, an FPGA motor control module, a drive waveform generation module and a trip detection module; the FPGA interface processing module is used to receive control instructions, and the control instruction input is read and written by the agreed bus address between the DSP and the FPGA; the FPGA motor control module is used to parse the control instructions and issue them, and decide whether to cut off the output according to the trip signal reported by the trip detection module; the drive waveform generation module is used to generate a control signal for controlling the drive circuit according to the analysis result, and feedback the completion status to the DSP when the stepper motor completes rotation; The trip detection module is used to detect the current on the stepper motor circuit in real time and decide whether to generate a trip signal according to the current value; The driving part is used for control and drive isolation, level conversion of control signals and fast driving of electronic switches; the two-phase full-bridge part directly interacts with the stepper motor and is used for inverting direct current into alternating current for driving the stepper motor.
2. The FPGA-based airborne stepper motor control system according to claim 1, characterized in that: The two-phase full-bridge part is composed of 8 electronic switches, and each half bridge is divided into an upper bridge arm and a lower bridge arm, which are complementary and turned on according to the control signal of the logic part to invert DC power into AC power to drive the stepper motor.
3. The FPGA-based airborne stepper motor control system according to claim 1, characterized in that: The stepper motor is a two-phase four-wire hybrid stepper motor, and the A and B phase windings of the stepper motor are staggered and distributed radially around the rotor.
4. The FPGA-based airborne stepper motor control system according to claim 3, characterized in that: The stepper motor is driven by dual four-beat drive, with two phases energized at the same time; each time the input pulse is switched, the stepper motor rotates a step angle; when rotating forward, the energized phase sequence is A+B+, A+B-, AB-, A-B+ cycle, and when rotating reversely, the energized phase sequence is A-B+, AB-, A+B-, A+B+.
5. The FPGA-based airborne stepper motor control system according to claim 4, characterized in that: The stepper motor is designed to start at 400 Hz for the first 12 steps and then rotate at 600 Hz.
6. The FPGA-based airborne stepper motor control system according to claim 4, characterized in that: When the stepper motor changes the energized phase sequence, a dead time of 400 microseconds is set.
7. The FPGA-based airborne stepper motor control system according to claim 1, characterized in that: The control signal for controlling the driving circuit generated by the driving waveform generating module adopts a three-stage driving waveform mode.
8. The FPGA-based airborne stepper motor control system according to claim 1, characterized in that: The completion status fed back to the DSP includes the running status, overcurrent status, locking status and direction information of the stepper motor.
9. An airborne stepper motor control method based on FPGA, characterized in that: Based on the implementation of the FPGA-based airborne stepper motor control system according to any one of claims 1 to 8, the method comprises: DSP sends control instructions through the data bus, and the control instruction input is read and written by the agreed bus address between DSP and FPGA; After receiving the motor rotation direction, rotation step number and speed command configured by DSP, the FPGA logic part starts to generate PWM drive pulse signal to control the rotation of the stepper motor; When the stepper motor completes its rotation, the completion status will be fed back to the DSP.
10. The FPGA-based airborne stepper motor control method according to claim 9, characterized in that: The generating of the PWM driving pulse signal to control the rotation of the stepper motor comprises: Step 1: The current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave; Step 2: The current flows from AN to AL, and the current gradually decreases. At this time, A+ outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave; Step 3: The current flows from AL to AN, and the current gradually increases. At this time, A- outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave; Step 4: The current flows from AL to AN, and the current gradually decreases. At this time, A- outputs a 70% duty cycle PWM square wave with a duration of 1.6ms, and then turns to a 0% duty cycle square wave; Step 5: The current flows from AN to AL, and the current gradually increases. At this time, A+ outputs a 100% duty cycle PWM square wave with a duration of 1.6ms, and then changes to a 70% duty cycle square wave; Repeat steps 1 to 5 in sequence.