Chip circuit of high-gain high-broadband fully differential operational amplifier
By introducing a combination of the main op amp circuit and the auxiliary op amp circuit A1 and A2 into the op amp circuit, and adopting a common bias circuit and a simple three-input tube structure, the existing op amp circuit has been solved, and the high gain, high bandwidth and low power consumption operational amplifier design is realized.
Patent Information
- Application Number
- CN202411971819.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
While the existing op amp circuits pursue high gain and high bandwidth, they have problems of large power consumption and poor stability.
A chip circuit of a high-gain high-wideband fully differential operational amplifier is designed, using a combination of the main op amp circuit and the auxiliary op amp circuit A1 and A2. By increasing the input transconductance and output impedance of the main op amp circuit, the gain and bandwidth are improved, and circuit power consumption is saved through the common bias circuit and the simple three-input tube structure.
A high gain and high bandwidth operational amplifier is realized, while significantly reducing power consumption and improving circuit stability.
Smart Images
Figure CN119891983A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of operational amplifier design, and in particular relates to a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier. Background Art
[0002] With the rapid development of wireless communications, communication protocols have been derived for use in different fields. In order to meet the requirements of multi-standard communication protocols, the ADC in the system needs to work at different sampling rates while providing sufficiently high accuracy and efficiency. In order to solve these problems, many ADC structures with reduced power consumption have been proposed. Generally, when the sampling frequency of the ADC is relatively high, a larger unit gain bandwidth is generated through the operational amplifier circuit to meet the settling time requirements.
[0003] However, the existing operational amplifier circuit has the following problems: 1. The existing operational amplifier circuit improves the gain of the operational amplifier by cascading, but due to the increase in the number of cascades and parasitic capacitance, there are problems of high power consumption and poor stability; 2. The auxiliary operational amplifier requires a different bias circuit, which further increases the power consumption. It can be seen that while pursuing high gain and high bandwidth, requiring the operational amplifier to have good performance such as power consumption and output voltage swing is a technical problem that needs to be solved urgently.
[0004] Therefore, the present invention provides a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier to solve the above technical problems. Summary of the invention
[0005] In view of the above problems, an object of the present invention is to provide a chip circuit of a high-gain and high-bandwidth fully differential operational amplifier, which has the characteristics of high gain and high bandwidth.
[0006] The present invention provides a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier, comprising: an operational amplifier circuit and a bias circuit connected to the operational amplifier circuit, wherein the operational amplifier circuit comprises a main operational amplifier circuit and a first auxiliary operational amplifier circuit A1 and a second auxiliary operational amplifier circuit A2 connected to the main operational amplifier circuit, and the bias circuit is used to output a bias voltage to power the main operational amplifier circuit, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2.
[0007] Preferably, the bias circuit includes a power supply terminal VDD for outputting a bias voltage, PMOS tubes MP1-MP9 and NMOS tubes MN1-MN7, the drain of the PMOS tube MP1 is simultaneously connected to the drain of the PMOS tube MP3, the drain of the PMOS tube MP5, the drain of the PMOS tube MP7 and the drain of the PMOS tube MP9, and then connected to the power supply terminal VDD, the gate of the PMOS tube MP1 is simultaneously connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP5, the gate of the PMOS tube MP7, the gate of the The source of the PMOS tube MP2, the drain of the NMOS tube MN1, the source of the NMOS tube MN4, the source of the NMOS tube MN5 and the source of the NMOS tube MN7 are connected to the ground terminal VSS, the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2, and the gate of the PMOS tube MP2 is connected to the gate of the PMOS tube MP4, the gate of the PMOS tube MP6, the gate of the PMOS tube MP8, the gate of the PMOS tube MP9, the source of the PMOS tube MP9 and the NMOS tube MN7. The drain of the OS transistor MN6 is connected to the Vb1 terminal, the source of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP4, the source of the PMOS transistor MP4 is simultaneously connected to the source of the NMOS transistor MN2, the gate of the NMOS transistor MN1, the gate of the NMOS transistor MN4 and the gate of the NMOS transistor MN7, the source of the PMOS transistor MP5 is connected to the drain of the PMOS transistor MP6, the source of the PMOS transistor MP6 is connected to the drain of the NMOS transistor MN3, the source of the PMOS transistor MP7 is connected to the The drain of the PMOS tube MP8 is connected, the source of the PMOS tube MP8 is connected to the drain of the NMOS tube MN5, the gate of the NMOS tube MN5, the gate of the NMOS tube MN3, the gate of the NMOS tube MN2 and the gate of the NMOS tube MN6, and then connected to the Vb2 terminal, the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2, the source of the NMOS tube MN3 is connected to the drain of the NMOS tube MN4, and the source of the NMOS tube MN6 is connected to the drain of the NMOS tube MN7.
[0008] Preferably, the main operational amplifier circuit includes PMOS tubes P1-P5, NMOS tubes N1-N5, switch tubes MAP1-MAP2 and switch tubes MBN1-MBN2, the gate of the PMOS tube P1 is connected to the gate of the NMOS tube N1 and then connected to the Vin- terminal, the drain of the PMOS tube P1 is simultaneously connected to the source of the PMOS tube P4, the source of the PMOS tube P5, the drain of the switch tube MBN1, the drain of the switch tube MBN2, the drain of the PMOS tube P2, the positive input terminal of the second auxiliary operational amplifier circuit A2 and the negative input terminal of the second auxiliary operational amplifier circuit A2, the PMOS tube P The source of the PMOS tube P1 is connected to the drain of the NMOS tube N3 and the source of the PMOS tube P2 at the same time, the drain of the PMOS tube P4 is connected to the drain of the PMOS tube P3 and the drain of the PMOS tube P5 at the same time, and then connected to the ground terminal VSS, the gate of the PMOS tube P4 is connected to the gate of the PMOS tube P5 and then connected to the VCMFB terminal, the gate of the PMOS tube P3 is connected to the Vb2 terminal, the source of the PMOS tube P3 is connected to the drain of the NMOS tube N1 and the drain of the NMOS tube N2 at the same time, the source of the NMOS tube N1 is connected to the drain of the NMOS tube N5, the switch The source of the NMOS tube MAP2 is connected to the positive input terminal of the first auxiliary operational amplifier circuit A1, the gate of the NMOS tube N3 is connected to the Vb1 terminal, the source of the NMOS tube N3 is simultaneously connected to the source of the NMOS tube N4 and the source of the NMOS tube N5, and then connected to the power supply terminal VDD, the gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2, and then connected to the Vin+ terminal, the source of the NMOS tube N2 is simultaneously connected to the drain of the NMOS tube N4, the source of the switch tube MAP1, and the negative input terminal of the first auxiliary operational amplifier circuit A1, the gate of the NMOS tube N4 is connected to the NMOS The gate of the switch tube N5 is connected to the Vb1 terminal, the drain of the switch tube MAP1 is connected to the source of the switch tube MBN1 and then connected to the V0- terminal, the gate of the switch tube MAP1 is connected to the positive output terminal of the first auxiliary operational amplifier circuit A1, the drain of the switch tube MAP2 is connected to the source of the switch tube MBN2 and then connected to the V0+ terminal, the gate of the switch tube MAP2 is connected to the negative output terminal of the first auxiliary operational amplifier circuit A1, the gate of the switch tube MBN1 is connected to the positive output terminal of the second auxiliary operational amplifier circuit A2, and the gate of the switch tube MBN2 is connected to the negative output terminal of the second auxiliary operational amplifier circuit A2.
[0009] Preferably, the first auxiliary operational amplifier circuit A1 includes a switch tube MA1, an NMOS tube N10, an NMOS tube N20, a PMOS tube P10, a capacitor C1, a capacitor C2, NMOS tubes M4-M7 and PMOS tubes M8-M11, the gate of the switch tube MA1 is connected to the VPC terminal, the source of the switch tube MA1 is connected to the power supply terminal VDD, the drain of the switch tube MA1 is simultaneously connected to the drain of the NMOS tube N10, the drain of the NMOS tube N20 and the source of the PMOS tube P10, and the NMOS tube N The gate of the NMOS tube N10 is connected to the Vin+ terminal, the source of the NMOS tube N10 is simultaneously connected to the source of the NMOS tube M7 and the drain of the NMOS tube M5 and then connected to the Vb1 terminal, the gate of the NMOS tube N20 is connected to the Vin- terminal, the source of the NMOS tube N20 is simultaneously connected to the drain of the NMOS tube M4 and the source of the NMOS tube M6, the gate of the PMOS tube P10 is connected to the Vb2 terminal, the drain of the PMOS tube P10 is simultaneously connected to the drain of the PMOS tube M10 and the drain of the PMOS tube M11 The drain of the NMOS tube M6 is connected to the source of the PMOS tube M8 and the first end of the capacitor C1 and then connected to the V0- terminal. The second end of the capacitor C1 is connected to the ground terminal VSS. The gate of the NMOS tube M4 is connected to the gate of the NMOS tube M5. The source of the NMOS tube M4 is connected to the source of the NMOS tube M5 and then connected to the power supply terminal VDD. The gate of the NMOS tube M6 is connected to the gate of the NMOS tube M7 and then connected to the Vb1 terminal. The drain of the NMOS tube M6 is simultaneously connected to the source of the PMOS tube M8 and the first end of the capacitor C1 and then connected to the V0- terminal. The second end of the capacitor C1 is connected to the ground terminal VSS. The drain of M7 is connected to the source of the PMOS tube M9 and the first end of the capacitor C2 at the same time, and then connected to the V0+ end. The second end of the capacitor C2 is connected to the ground end VSS. The gate of the PMOS tube M8 is connected to the gate of the PMOS tube M9 and then connected to the Vb2 end. The drain of the PMOS tube M8 is connected to the source of the PMOS tube M10. The drain of the PMOS tube M9 is connected to the source of the PMOS tube M11. The gate of the PMOS tube M10 is connected to the gate of the PMOS tube M11 and then connected to the Vb2 end.
[0010] Preferably, the second auxiliary operational amplifier circuit A2 includes a switch tube MB1, NMOS tubes BN1-BN2, NMOS tubes BM3-BM7, capacitors C3, capacitors C4 and PMOS tubes BM8-BM11, the gate of the switch tube MB1 is connected to the VNC terminal, the drain of the switch tube MB1 is connected to the ground terminal VSS, the source of the switch tube MB1 is simultaneously connected to the source of the NMOS tube BN1, the source of the NMOS tube BN2 and the drain of the NMOS tube BM3, the gate of the NMOS tube BN1 is connected to the Vin2+ terminal, and the The drain of the NMOS tube BN1 is connected to the drain of the PMOS tube BM9 and the source of the PMOS tube BM11, the gate of the NMOS tube BN2 is connected to the Vin2- terminal, the drain of the NMOS tube BN2 is connected to the drain of the PMOS tube BM8 and the source of the PMOS tube BM10, the gate of the NMOS tube BM3 is connected to the Vb1 terminal, the source of the NMOS tube BM3 is connected to the source of the NMOS tube BM4 and the source of the NMOS tube BM5, and then connected to the power supply terminal VDD, the N The gate of the MOS tube BM4 is connected to the gate of the NMOS tube BM5 and then connected to the Vb1 terminal. The drain of the NMOS tube BM4 is connected to the source of the NMOS tube BM6. The drain of the NMOS tube BM5 is connected to the source of the NMOS tube BM7. The gate of the NMOS tube BM6 is connected to the gate of the NMOS tube BM7 and then connected to the Vb1 terminal. The drain of the NMOS tube BM6 is simultaneously connected to the source of the PMOS tube BM8 and the first terminal of the capacitor C3 and then connected to the V0- terminal. The second terminal of the capacitor C3 is connected to the ground terminal. The drain of the NMOS tube BM7 is connected to the source of the PMOS tube BM9 and the first end of the capacitor C4, and then connected to the V0+ end. The second end of the capacitor C4 is connected to the ground terminal VSS. The gate of the PMOS tube BM8 is connected to the gate of the PMOS tube BM9 and then connected to the Vb2 end. The gate of the PMOS tube BM10 is connected to the gate of the PMOS tube BM11 and then connected to the Vb2 end. The drain of the PMOS tube BM10 is connected to the drain of the PMOS tube BM11 and then connected to the ground terminal VSS.
[0011] Preferably, the gate length of the PMOS transistor MP9 is 4 to 5 times the gate length of the PMOS transistor MP4, and the gate length of the NMOS transistor MN5 is 4 to 5 times the gate length of the NMOS transistor MN3.
[0012] Compared with the related art, the present invention provides a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier, including an operational amplifier circuit and a bias circuit connected to the operational amplifier circuit, wherein the operational amplifier circuit includes a main operational amplifier circuit and a first auxiliary operational amplifier circuit A1 and a second auxiliary operational amplifier circuit A2 connected to the main operational amplifier circuit, and the bias circuit is used to output a bias voltage to power the main operational amplifier circuit, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2. The above-mentioned structure improves the input transconductance of the main operational amplifier circuit, thereby improving the gain and bandwidth of the main operational amplifier circuit; and the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2 use a simpler three-input tube structure, and share a bias circuit with the main operational amplifier circuit, which greatly saves the power consumption of the circuit; in addition, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2 will not change the bandwidth of the main operational amplifier circuit, and increase the output impedance by reducing the main pole of the main operational amplifier circuit, thereby further improving the gain of the main operational amplifier circuit, thereby achieving the purpose of high gain and high bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 A schematic structural diagram of a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier provided by the present invention;
[0014] Figure 2 Schematic diagram of the circuit structure of the operational amplifier circuit in the present invention;
[0015] Figure 3 is a schematic diagram of the circuit structure of the bias circuit in the present invention;
[0016] Figure 4 is a schematic diagram of the circuit structure of the first auxiliary operational amplifier circuit A1 in the present invention;
[0017] Figure 5 Schematic diagram of the circuit structure of the second auxiliary operational amplifier circuit A2 in the present invention;
[0018] Figure 6 The present invention provides a design principle diagram of a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier. DETAILED DESCRIPTION
[0019] The present invention provides a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier, aiming to solve the problems of high power consumption and poor stability of existing operational amplifier circuits.
[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0021] Please see attached Figure 1-6 As shown, the present invention provides a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier, comprising an operational amplifier circuit 1 and a bias circuit 2 connected to the operational amplifier circuit 1, wherein the operational amplifier circuit 1 comprises a main operational amplifier circuit 11 and a first auxiliary operational amplifier circuit A1 and a second auxiliary operational amplifier circuit A2 connected to the main operational amplifier circuit, and the bias circuit 2 is used to output a bias voltage to power the main operational amplifier circuit 11, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2.
[0022] In this embodiment, in order to increase the range of the output voltage, the bias circuit 2 selects a wide swing low-voltage common source common gate structure, which includes a power supply terminal VDD for outputting the bias voltage, PMOS tubes MP1-MP9 and NMOS tubes MN1-MN7, the drain of the PMOS tube MP1 is simultaneously connected to the drain of the PMOS tube MP3, the drain of the PMOS tube MP5, the drain of the PMOS tube MP7 and the drain of the PMOS tube MP9, and then connected to the power supply terminal VDD, the gate of the PMOS tube MP1 is simultaneously connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP5, the gate of the PMOS tube MP7 and the gate of the PMOS tube MP9, and the gate of the PMOS tube MP1 is simultaneously connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP5, the gate of the PMOS tube MP7 and the gate of the PMOS tube MP9. The gate of the PMOS tube MP5, the gate of the PMOS tube MP7, the source of the PMOS tube MP2, the drain of the NMOS tube MN1, the source of the NMOS tube MN4, the source of the NMOS tube MN5 and the source of the NMOS tube MN7 are connected to the ground terminal VSS, the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2, and the gate of the PMOS tube MP2 is connected to the gate of the PMOS tube MP4, the gate of the PMOS tube MP6, the gate of the PMOS tube MP8, the gate of the PMOS tube MP9, ... The source of the PMOS tube MP9 is connected to the drain of the NMOS tube MN6 and then connected to the Vb1 terminal. The source of the PMOS tube MP3 is connected to the drain of the PMOS tube MP4. The source of the PMOS tube MP4 is simultaneously connected to the source of the NMOS tube MN2, the gate of the NMOS tube MN1, the gate of the NMOS tube MN4 and the gate of the NMOS tube MN7. The source of the PMOS tube MP5 is connected to the drain of the PMOS tube MP6. The source of the PMOS tube MP6 is connected to the drain of the NMOS tube MN3. The source of P7 is connected to the drain of the PMOS tube MP8, the source of the PMOS tube MP8 is simultaneously connected to the drain of the NMOS tube MN5, the gate of the NMOS tube MN5, the gate of the NMOS tube MN3, the gate of the NMOS tube MN2 and the gate of the NMOS tube MN6, and then connected to the Vb2 terminal, the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2, the source of the NMOS tube MN3 is connected to the drain of the NMOS tube MN4, and the source of the NMOS tube MN6 is connected to the drain of the NMOS tube MN7.
[0023] In the above structure, the gate length of the PMOS tube MP9 is 4 to 5 times the gate length of the PMOS tube MP4, and the gate length of the NMOS tube MN5 is 4 to 5 times the gate length of the NMOS tube MN3. The purpose of this design is to provide a suitable voltage, reduce the voltage drop on the MOS tube, and thus expand the output voltage swing. In addition, the width-to-length ratio of the PMOS tubes P1-P4 and the NMOS tubes N1-N4 is the same as the width-to-length ratio of the main operational amplifier circuit 11, the first auxiliary operational amplifier circuit A1, and the second auxiliary operational amplifier circuit A2, but the value of the parallel number (Multiplier) is different. This design can proportionally reduce the Multiplier of the bias circuit 2 and the corresponding tubes of the auxiliary operational amplifier, and minimize the power consumption of the bias circuit and the auxiliary operational amplifier circuit.
[0024] Specifically, the main operational amplifier circuit 1 includes PMOS tubes P1-P5, NMOS tubes N1-N5, switch tubes MAP1-MAP2 and switch tubes MBN1-MBN2. The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N1 and then connected to the Vin- terminal. The drain of the PMOS tube P1 is simultaneously connected to the source of the PMOS tube P4, the source of the PMOS tube P5, the drain of the switch tube MBN1, the drain of the switch tube MBN2, the drain of the PMOS tube P2, the positive input terminal of the second auxiliary operational amplifier circuit A2 and the negative input terminal of the second auxiliary operational amplifier circuit A2. The source of the PMOS tube P1 is connected to the drain of the NMOS tube N3 and the source of the PMOS tube P2 at the same time, the drain of the PMOS tube P4 is connected to the drain of the PMOS tube P3 and the drain of the PMOS tube P5 at the same time, and then connected to the ground terminal VSS, the gate of the PMOS tube P4 is connected to the gate of the PMOS tube P5 and then connected to the VCMFB terminal, the gate of the PMOS tube P3 is connected to the Vb2 terminal, the source of the PMOS tube P3 is connected to the drain of the NMOS tube N1 and the drain of the NMOS tube N2 at the same time, the source of the NMOS tube N1 is connected to the drain of the NMOS tube N5, the switch The source of the NMOS tube MAP2 is connected to the positive input terminal of the first auxiliary operational amplifier circuit A1, the gate of the NMOS tube N3 is connected to the Vb1 terminal, the source of the NMOS tube N3 is simultaneously connected to the source of the NMOS tube N4 and the source of the NMOS tube N5, and then connected to the power supply terminal VDD, the gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2, and then connected to the Vin+ terminal, the source of the NMOS tube N2 is simultaneously connected to the drain of the NMOS tube N4, the source of the switch tube MAP1, and the negative input terminal of the first auxiliary operational amplifier circuit A1, the gate of the NMOS tube N4 is connected to the NMOS The gate of the switch tube N5 is connected to the Vb1 terminal, the drain of the switch tube MAP1 is connected to the source of the switch tube MBN1 and then connected to the V0- terminal, the gate of the switch tube MAP1 is connected to the positive output terminal of the first auxiliary operational amplifier circuit A1, the drain of the switch tube MAP2 is connected to the source of the switch tube MBN2 and then connected to the V0+ terminal, the gate of the switch tube MAP2 is connected to the negative output terminal of the first auxiliary operational amplifier circuit A1, the gate of the switch tube MBN1 is connected to the positive output terminal of the second auxiliary operational amplifier circuit A2, and the gate of the switch tube MBN2 is connected to the negative output terminal of the second auxiliary operational amplifier circuit A2.
[0025] In the above structure, the main operational amplifier circuit 11 adopts a wide input common mode range fully differential folded common source common gate operational amplifier structure, the input pair of tubes is composed of NMOS tubes and PMOS tubes, when the input potential is low, PMOS tubes P1 and PMOS tubes P2 are turned on, when the input voltage is high, NMOS tubes N1 and NMOS tubes N2 are turned on, this structure expands the input common mode range and increases the input transconductance to twice that of the traditional operational amplifier structure. In order to avoid the influence of parasitic capacitance on the operational amplifier frequency when using the gain boost technology, the size of PMOS tubes P1 and PMOS tubes P2 (NMOS tubes N1 and NMOS tubes N2) is designed to be smaller when the main operational amplifier circuit is designed.
[0026] Further, the first auxiliary operational amplifier circuit A1 includes a switch tube MA1, an NMOS tube N10, an NMOS tube N20, a PMOS tube P10, a capacitor C1, a capacitor C2, NMOS tubes M4-M7 and PMOS tubes M8-M11, the gate of the switch tube MA1 is connected to the VPC terminal, the source of the switch tube MA1 is connected to the power supply terminal VDD, the drain of the switch tube MA1 is simultaneously connected to the drain of the NMOS tube N10, the drain of the NMOS tube N20 and the source of the PMOS tube P10, the NMOS tube The gate of N10 is connected to Vin+ terminal, the source of the NMOS tube N10 is connected to the source of the NMOS tube M7 and the drain of the NMOS tube M5 and then connected to Vb1 terminal, the gate of the NMOS tube N20 is connected to Vin- terminal, the source of the NMOS tube N20 is connected to the drain of the NMOS tube M4 and the source of the NMOS tube M6, the gate of the PMOS tube P10 is connected to Vb2 terminal, the drain of the PMOS tube P10 is connected to the drain of the PMOS tube M10 and the drain of the PMOS tube M11 at the same time. The drain of the NMOS tube M4 is connected to the drain of the PMOS tube M8 and then connected to the ground terminal VSS, the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M5, the source of the NMOS tube M4 is connected to the source of the NMOS tube M5 and then connected to the power supply terminal VDD, the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M7 and then connected to the Vb1 terminal, the drain of the NMOS tube M6 is simultaneously connected to the source of the PMOS tube M8 and the first end of the capacitor C1 and then connected to the V0- terminal, the second end of the capacitor C1 is connected to the ground terminal VSS, the NMOS tube The drain of M7 is connected to the source of the PMOS tube M9 and the first end of the capacitor C2 at the same time, and then connected to the V0+ end. The second end of the capacitor C2 is connected to the ground end VSS. The gate of the PMOS tube M8 is connected to the gate of the PMOS tube M9 and then connected to the Vb2 end. The drain of the PMOS tube M8 is connected to the source of the PMOS tube M10. The drain of the PMOS tube M9 is connected to the source of the PMOS tube M11. The gate of the PMOS tube M10 is connected to the gate of the PMOS tube M11 and then connected to the Vb2 end.
[0027] Furthermore, the second auxiliary operational amplifier circuit A2 includes a switch tube MB1, NMOS tubes BN1-BN2, NMOS tubes BM3-BM7, capacitors C3, capacitors C4 and PMOS tubes BM8-BM11, the gate of the switch tube MB1 is connected to the VNC terminal, the drain of the switch tube MB1 is connected to the ground terminal VSS, the source of the switch tube MB1 is simultaneously connected to the source of the NMOS tube BN1, the source of the NMOS tube BN2 and the drain of the NMOS tube BM3, the gate of the NMOS tube BN1 is connected to the Vin2+ terminal, and the The drain of the NMOS tube BN1 is connected to the drain of the PMOS tube BM9 and the source of the PMOS tube BM11 at the same time, the gate of the NMOS tube BN2 is connected to the Vin2- terminal, the drain of the NMOS tube BN2 is connected to the drain of the PMOS tube BM8 and the source of the PMOS tube BM10 at the same time, the gate of the NMOS tube BM3 is connected to the Vb1 terminal, the source of the NMOS tube BM3 is connected to the source of the NMOS tube BM4 and the source of the NMOS tube BM5 at the same time, and then connected to the power supply terminal VDD, the The gate of the NMOS tube BM4 is connected to the gate of the NMOS tube BM5 and then connected to the Vb1 terminal. The drain of the NMOS tube BM4 is connected to the source of the NMOS tube BM6. The drain of the NMOS tube BM5 is connected to the source of the NMOS tube BM7. The gate of the NMOS tube BM6 is connected to the gate of the NMOS tube BM7 and then connected to the Vb1 terminal. The drain of the NMOS tube BM6 is simultaneously connected to the source of the PMOS tube BM8 and the first terminal of the capacitor C3 and then connected to the V0- terminal. The second terminal of the capacitor C3 is connected to the ground terminal. The drain of the NMOS tube BM7 is connected to the source of the PMOS tube BM9 and the first end of the capacitor C4, and then connected to the V0+ end. The second end of the capacitor C4 is connected to the ground terminal VSS. The gate of the PMOS tube BM8 is connected to the gate of the PMOS tube BM9 and then connected to the Vb2 end. The gate of the PMOS tube BM10 is connected to the gate of the PMOS tube BM11 and then connected to the Vb2 end. The drain of the PMOS tube BM10 is connected to the drain of the PMOS tube BM11 and then connected to the ground terminal VSS.
[0028] It is worth mentioning that the first auxiliary op amp circuit A1 and the second auxiliary op amp circuit A2 also select folded common source and common gate operational amplifiers with more flexible input and output, and add a tube to the input end of both, eliminating the common mode feedback circuit of the auxiliary op amp, and the circuit structure is simpler and more efficient. Among them, VPC and VNC are the potentials of points A and B when the main op amp circuit is not equipped with an auxiliary op amp, and the capacitors C1-C4 are set to prevent the zero poles introduced by the auxiliary op amp from affecting the stability of the system.
[0029] In addition, in order to further explain how the auxiliary operational amplifier circuit uses the current common-mode feedback to stabilize the output common-mode voltage, the first auxiliary operational amplifier circuit A1 is taken as an example for explanation (the principle of the second auxiliary operational amplifier circuit A2 is similar to that of the first auxiliary operational amplifier circuit A1, which will not be repeated here): Assuming that due to transistor mismatch, process manufacturing and other reasons, the common-mode voltages Vin1- and Vin1+ increase, and the gate voltages of the NMOS tubes N10 and NMOS tubes N20 increase, resulting in a slight increase in a unit current I that originally flows through, while the current 2I of the NMOS tube M4 remains unchanged, and the current flowing through the NMOS tube M6 branch decreases. , the output common-mode levels Vo- and Vo+ decrease, and the output common-mode level of the first auxiliary operational amplifier circuit A1 increases, causing the potential of point A in the main operational amplifier circuit, i.e., the input terminal of the first auxiliary operational amplifier circuit A1, to decrease, offsetting the trend of the voltage increase of Vin1- and Vin1+, thereby achieving the purpose of stabilizing the common mode of the auxiliary operational amplifier. The main operational amplifier circuit adopts a switched capacitor CMFB. Compared with the continuous-time CMFB structure, the switched capacitor CMFB has the advantages of no restriction on the output voltage range, high linearity (only passive devices are used in the circuit), no introduction of new parasitic zeros and poles in the CMFB loop, and low power consumption.
[0030] It should be noted that the chip circuit of a high-gain, high-bandwidth fully differential operational amplifier provided by the present invention is to add an operational amplifier circuit A on the basis of the traditional common source and common gate to improve the gain and bandwidth. Figure 6 As shown, attached Figure 6 In the example, Vref is the reference voltage, Vin is the input signal, Vout is the output signal, and the output impedance rout is r out ≈g m2 r o2 r o1 (A+1), where gm2 is the transconductance of the two MOS tubes, ro2 and ro1 are the output impedances of the two MOS tubes, and A is the DC gain of the auxiliary operational amplifier.
[0031] Compared with the related art, the present invention provides a chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier, including an operational amplifier circuit and a bias circuit connected to the operational amplifier circuit, wherein the operational amplifier circuit includes a main operational amplifier circuit and a first auxiliary operational amplifier circuit A1 and a second auxiliary operational amplifier circuit A2 connected to the main operational amplifier circuit, and the bias circuit is used to output a bias voltage to power the main operational amplifier circuit, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2. The above-mentioned structure improves the input transconductance of the main operational amplifier circuit, thereby improving the gain and bandwidth of the main operational amplifier circuit; and the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2 use a simpler three-input tube structure, and share a bias circuit with the main operational amplifier circuit, which greatly saves the power consumption of the circuit; in addition, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2 will not change the bandwidth of the main operational amplifier circuit, and increase the output impedance by reducing the main pole of the main operational amplifier circuit, thereby further improving the gain of the main operational amplifier circuit, thereby achieving the purpose of high gain and high bandwidth.
[0032] The above-described embodiments should be understood as illustrative rather than limiting the scope of protection of the present invention, which is subject to the claims. For those skilled in the art, some non-essential improvements and adjustments made to the present invention still fall within the scope of protection of the present invention without departing from the essence and scope of the present invention.
Claims
1. A chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier, characterized in that: The chip circuit includes an operational amplifier circuit and a bias circuit connected to the operational amplifier circuit, wherein the operational amplifier circuit includes a main operational amplifier circuit and a first auxiliary operational amplifier circuit A1 and a second auxiliary operational amplifier circuit A2 connected to the main operational amplifier circuit, and the bias circuit is used to output a bias voltage to power the main operational amplifier circuit, the first auxiliary operational amplifier circuit A1 and the second auxiliary operational amplifier circuit A2.
2. The chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier according to claim 1, characterized in that: The bias circuit includes a power supply terminal VDD for outputting a bias voltage, PMOS tubes MP1-MP9 and NMOS tubes MN1-MN7, the drain of the PMOS tube MP1 is simultaneously connected to the drain of the PMOS tube MP3, the drain of the PMOS tube MP5, the drain of the PMOS tube MP7 and the drain of the PMOS tube MP9, and then connected to the power supply terminal VDD, the gate of the PMOS tube MP1 is simultaneously connected to the gate of the PMOS tube MP3, the gate of the PMOS tube MP5, the gate of the PMOS tube MP7, the gate of the PMOS tube MP9 The source of the S transistor MP2, the drain of the NMOS transistor MN1, the source of the NMOS transistor MN4, the source of the NMOS transistor MN5 and the source of the NMOS transistor MN7 are connected to the ground terminal VSS, the source of the PMOS transistor MP1 is connected to the drain of the PMOS transistor MP2, and the gate of the PMOS transistor MP2 is connected to the gate of the PMOS transistor MP4, the gate of the PMOS transistor MP6, the gate of the PMOS transistor MP8, the gate of the PMOS transistor MP9, the source of the PMOS transistor MP9 and the NMOS transistor MP7. The drain of the PMOS tube MN6 is connected to the Vb1 terminal, the source of the PMOS tube MP3 is connected to the drain of the PMOS tube MP4, the source of the PMOS tube MP4 is simultaneously connected to the source of the NMOS tube MN2, the gate of the NMOS tube MN1, the gate of the NMOS tube MN4 and the gate of the NMOS tube MN7, the source of the PMOS tube MP5 is connected to the drain of the PMOS tube MP6, the source of the PMOS tube MP6 is connected to the drain of the NMOS tube MN3, the source of the PMOS tube MP7 is connected to the PMOS tube MN2, the gate of the NMOS tube MN1, the gate of the NMOS tube MN4 and the gate of the NMOS tube MN7, the source of the PMOS tube MP5 is connected to the drain of the PMOS tube MP6, the source of the PMOS tube MP6 is connected to the drain of the NMOS tube MN3, the source of the PMOS tube MP7 is connected to the PMOS tube MN2. The source of the PMOS tube MP8 is connected to the drain of the NMOS tube MN5, the gate of the NMOS tube MN5, the gate of the NMOS tube MN3, the gate of the NMOS tube MN2 and the gate of the NMOS tube MN6, and then connected to the Vb2 terminal. The source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2, the source of the NMOS tube MN3 is connected to the drain of the NMOS tube MN4, and the source of the NMOS tube MN6 is connected to the drain of the NMOS tube MN7.
3. The chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier according to claim 2, characterized in that: The main operational amplifier circuit includes PMOS tubes P1-P5, NMOS tubes N1-N5, switch tubes MAP1-MAP2 and switch tubes MBN1-MBN2. The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N1 and then connected to the Vin- terminal. The drain of the PMOS tube P1 is simultaneously connected to the source of the PMOS tube P4, the source of the PMOS tube P5, the drain of the switch tube MBN1, the drain of the switch tube MBN2, the drain of the PMOS tube P2, the positive input terminal of the second auxiliary operational amplifier circuit A2 and the negative input terminal of the second auxiliary operational amplifier circuit A2. The source of the PMOS tube P1 is connected to the negative input terminal of the second auxiliary operational amplifier circuit A2. The gate of the PMOS tube P4 is connected to the drain of the NMOS tube N3 and the source of the PMOS tube P2 at the same time, the drain of the PMOS tube P4 is connected to the drain of the PMOS tube P3 and the drain of the PMOS tube P5 at the same time, and then connected to the ground terminal VSS, the gate of the PMOS tube P4 is connected to the gate of the PMOS tube P5 and then connected to the VCMFB terminal, the gate of the PMOS tube P3 is connected to the Vb2 terminal, the source of the PMOS tube P3 is connected to the drain of the NMOS tube N1 and the drain of the NMOS tube N2 at the same time, the source of the NMOS tube N1 is connected to the drain of the NMOS tube N5, the switch tube M The source of the NMOS tube AP2 is connected to the positive input terminal of the first auxiliary operational amplifier circuit A1, the gate of the NMOS tube N3 is connected to the Vb1 terminal, the source of the NMOS tube N3 is simultaneously connected to the source of the NMOS tube N4 and the source of the NMOS tube N5 and then connected to the power supply terminal VDD, the gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2 and then connected to the Vin+ terminal, the source of the NMOS tube N2 is simultaneously connected to the drain of the NMOS tube N4, the source of the switch tube MAP1 and the negative input terminal of the first auxiliary operational amplifier circuit A1, the gate of the NMOS tube N4 is connected to the NMOS tube The gate of the switch tube N5 is connected to the Vb1 terminal, the drain of the switch tube MAP1 is connected to the source of the switch tube MBN1 and then connected to the V0- terminal, the gate of the switch tube MAP1 is connected to the positive output terminal of the first auxiliary operational amplifier circuit A1, the drain of the switch tube MAP2 is connected to the source of the switch tube MBN2 and then connected to the V0+ terminal, the gate of the switch tube MAP2 is connected to the negative output terminal of the first auxiliary operational amplifier circuit A1, the gate of the switch tube MBN1 is connected to the positive output terminal of the second auxiliary operational amplifier circuit A2, and the gate of the switch tube MBN2 is connected to the negative output terminal of the second auxiliary operational amplifier circuit A2.
4. The chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier according to claim 3, characterized in that: The first auxiliary operational amplifier circuit A1 includes a switch tube MA1, an NMOS tube N10, an NMOS tube N20, a PMOS tube P10, a capacitor C1, a capacitor C2, NMOS tubes M4-M7 and PMOS tubes M8-M11, the gate of the switch tube MA1 is connected to the VPC terminal, the source of the switch tube MA1 is connected to the power supply terminal VDD, the drain of the switch tube MA1 is simultaneously connected to the drain of the NMOS tube N10, the drain of the NMOS tube N20 and the source of the PMOS tube P10, the gate of the NMOS tube N10 is connected to the VPC terminal, the source of the switch tube MA1 is connected to the power supply terminal VDD, the drain of the switch tube MA1 is simultaneously connected to the drain of the NMOS tube N10, the drain of the NMOS tube N20 and the source of the PMOS tube P10, and the gate of the NMOS tube N10 is connected to the VPC terminal. The gate is connected to the Vin+ terminal, the source of the NMOS tube N10 is simultaneously connected to the source of the NMOS tube M7 and the drain of the NMOS tube M5 and then connected to the Vb1 terminal, the gate of the NMOS tube N20 is connected to the Vin- terminal, the source of the NMOS tube N20 is simultaneously connected to the drain of the NMOS tube M4 and the source of the NMOS tube M6, the gate of the PMOS tube P10 is connected to the Vb2 terminal, the drain of the PMOS tube P10 is simultaneously connected to the drain of the PMOS tube M10 and the drain of the PMOS tube M11 The gate of the NMOS tube M4 is connected to the gate of the NMOS tube M5, the source of the NMOS tube M4 is connected to the source of the NMOS tube M5 and then connected to the power supply terminal VDD, the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M7 and then connected to the Vb1 terminal, the drain of the NMOS tube M6 is simultaneously connected to the source of the PMOS tube M8 and the first end of the capacitor C1 and then connected to the V0- terminal, the second end of the capacitor C1 is connected to the ground terminal VSS, the NMOS tube M The drain of the PMOS tube M7 is connected to the source of the PMOS tube M9 and the first end of the capacitor C2 at the same time, and then connected to the V0+ end. The second end of the capacitor C2 is connected to the ground end VSS. The gate of the PMOS tube M8 is connected to the gate of the PMOS tube M9 and then connected to the Vb2 end. The drain of the PMOS tube M8 is connected to the source of the PMOS tube M10. The drain of the PMOS tube M9 is connected to the source of the PMOS tube M11. The gate of the PMOS tube M10 is connected to the gate of the PMOS tube M11 and then connected to the Vb2 end.
5. The chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier according to claim 3, characterized in that: The second auxiliary operational amplifier circuit A2 includes a switch tube MB1, NMOS tubes BN1-BN2, NMOS tubes BM3-BM7, capacitors C3, capacitors C4 and PMOS tubes BM8-BM11, the gate of the switch tube MB1 is connected to the VNC terminal, the drain of the switch tube MB1 is connected to the ground terminal VSS, the source of the switch tube MB1 is simultaneously connected to the source of the NMOS tube BN1, the source of the NMOS tube BN2 and the drain of the NMOS tube BM3, the gate of the NMOS tube BN1 is connected to the Vin2+ terminal, and the NMOS The drain of the S transistor BN1 is connected to the drain of the PMOS transistor BM9 and the source of the PMOS transistor BM11, the gate of the NMOS transistor BN2 is connected to the Vin2- terminal, the drain of the NMOS transistor BN2 is connected to the drain of the PMOS transistor BM8 and the source of the PMOS transistor BM10, the gate of the NMOS transistor BM3 is connected to the Vb1 terminal, the source of the NMOS transistor BM3 is connected to the source of the NMOS transistor BM4 and the source of the NMOS transistor BM5, and then connected to the power supply terminal VDD, the NMOS The gate of the S transistor BM4 is connected to the gate of the NMOS transistor BM5 and then connected to the Vb1 terminal. The drain of the NMOS transistor BM4 is connected to the source of the NMOS transistor BM6. The drain of the NMOS transistor BM5 is connected to the source of the NMOS transistor BM7. The gate of the NMOS transistor BM6 is connected to the gate of the NMOS transistor BM7 and then connected to the Vb1 terminal. The drain of the NMOS transistor BM6 is simultaneously connected to the source of the PMOS transistor BM8 and the first terminal of the capacitor C3 and then connected to the V0- terminal. The second terminal of the capacitor C3 is connected to the ground terminal V SS, the drain of the NMOS tube BM7 is connected to the source of the PMOS tube BM9 and the first end of the capacitor C4 at the same time, and then connected to the V0+ end, the second end of the capacitor C4 is connected to the ground terminal VSS, the gate of the PMOS tube BM8 is connected to the gate of the PMOS tube BM9, and then connected to the Vb2 end, the gate of the PMOS tube BM10 is connected to the gate of the PMOS tube BM11, and then connected to the Vb2 end, the drain of the PMOS tube BM10 is connected to the drain of the PMOS tube BM11, and then connected to the ground terminal VSS.
6. The chip circuit of a high-gain, high-bandwidth, fully differential operational amplifier according to claim 2, characterized in that: The gate length of the PMOS transistor MP9 is 4 to 5 times the gate length of the PMOS transistor MP4 , and the gate length of the NMOS transistor MN5 is 4 to 5 times the gate length of the NMOS transistor MN3 .