Time delay circuit, circuit board assembly and electronic equipment
By setting the first inverter in the delay circuit, delay is achieved by using the charging and discharging process of its gate capacitor, the existing RC delay circuit cannot meet the requirements of miniaturization and cost reduction, and the effect of volume reduction, cost reduction and controllable delay time is achieved.
Patent Information
- Application Number
- CN202411781930.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-05
- Publication Date
- 2025-04-25
AI Technical Summary
The existing RC delay circuit cannot meet the high requirements for miniaturization and low cost of delay circuits.
A delay circuit without capacitance and resistor is designed, and the delay of the initial clock signal is achieved by setting a first inverter in the delay circuit using the charging and discharging process of its gate capacitance.
The delay circuit is greatly reduced in size and cost reduction. At the same time, the delay time of the rising and falling edges of the delay circuit is controllable, and the reliability of the delay circuit is high.
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Figure CN119892023A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of circuit technology, and in particular to a delay circuit, a circuit board assembly, and an electronic device. Background Art
[0002] With the development of high-speed mixed-signal circuits, signal timing is becoming increasingly crucial to the overall system. Therefore, delay circuits are often added to circuit configurations to generate or compensate for delay differences between paths to achieve specific performance requirements. With the continuous advancement of integrated circuit technology, the demand for miniaturization and cost-effectiveness of delay circuits is increasing. Therefore, the need for small, low-cost delay circuits is becoming increasingly important.
[0003] RC (Resistance-Capacitance) delay circuits are often used in related technologies. However, current RC delay circuits still cannot meet the increasingly high requirements for miniaturization and low cost of delay circuits. Summary of the Invention
[0004] The purpose of the embodiments of the present application is to provide a delay circuit, a circuit board assembly, and an electronic device, thereby reducing the volume occupied by the delay circuit in the chip and reducing costs.
[0005] To solve the above technical problems, an embodiment of the present application provides a delay circuit, including: a first switch module, a second switch module, a first inverter, and a power module; the control end of the first switch module is configured to receive an initial clock signal, and the control end of the second switch module is configured to receive an enable signal; the input end of the first switch module is connected to a power supply, the output end of the first switch module is connected to the input end of the second switch module, and the output end of the second switch module is grounded; the output end of the first switch module is also connected to the input end of the first inverter; the input end of the first inverter is also connected to the input end of the power module; the output end of the first inverter is configured to output a first delayed clock signal.
[0006] An embodiment of the present application further provides a circuit board assembly, comprising: the above-mentioned delay circuit.
[0007] An embodiment of the present application further provides an electronic device, including: the above-mentioned circuit board assembly.
[0008] In some embodiments, the delay circuit further includes a first shaping module; the input end of the first shaping module is connected to the output end of the first inverter, and the first shaping module is configured to perform shaping processing on the first delayed clock signal to obtain a target delayed clock signal, and output the target delayed clock signal.
[0009] In some embodiments, the first shaping module includes a second inverter and a third inverter; the input end of the second inverter serves as the input end of the first shaping module, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter serves as the output end of the first shaping module.
[0010] In some embodiments, the delay circuit further includes a second shaping module; the control end of the second shaping module is connected to the output end of the first inverter, the input end of the second shaping module is connected to the input end of the first inverter, and the output end of the second shaping module is grounded.
[0011] In some embodiments, the second shaping module is an NMOS tube, the gate of the NMOS tube serves as the control end of the second shaping module, the drain of the NMOS tube serves as the input end of the second shaping module, and the source of the NMOS tube serves as the output end of the second shaping module.
[0012] In some embodiments, the power module includes: a current source, a fourth switch module, and a fifth switch module;
[0013] The input end of the current source is connected to a power supply, the output end of the current source is connected to the input end of the fourth switch module, the output end of the current source is also connected to the control end of the fourth switch module, and the control end of the fourth switch module is also connected to the control end of the fifth switch module; the output end of the fourth switch module is grounded, the input end of the fifth switch module serves as the input end of the power module, and the output end of the fifth switch module is grounded.
[0014] In some embodiments, the first switch module is a PMOS inverse ratio transistor.
[0015] In some embodiments, the second switch module and the third switch module are both NMOS transistors.
[0016] The embodiments of the present disclosure have at least the following advantages:
[0017] In this embodiment, a first inverter is provided in the delay circuit. When the initial clock signal received by the delay circuit switches from a high level to a low level or from a low level to a high level, the charging and discharging process of the gate capacitance of the first inverter is utilized to delay the initial clock signal. The entire circuit does not require capacitors and resistors. Compared with the RC delay circuit in the related art, the volume occupied by the entire circuit in the chip is greatly reduced, which also reduces the cost. In addition, the delay time of the rising edge and the falling edge of the delay circuit of this embodiment are both controllable, and the delay circuit has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0019] Figure 1 1 is a schematic diagram of a circuit structure of a delay circuit according to an embodiment of the present application;
[0020] Figure 2 is a schematic diagram of the circuit structure of a first inverter according to an embodiment of the present application;
[0021] Figure 3 is a schematic diagram of the circuit structure of a power consumption unit according to an embodiment of the present application;
[0022] Figure 4 1 is a schematic diagram of the circuit structure of a delay circuit according to an embodiment of the present application. DETAILED DESCRIPTION
[0023] As can be seen from the background technology, the current RC delay circuit cannot meet the increasingly high requirements for miniaturization and low cost of the delay circuit.
[0024] Through analysis, the inventors found that the RC delay circuit is formed by a combination of capacitors and resistors, and a single capacitor or a single resistor occupies a large area in the chip, which results in a larger volume occupied by the RC delay circuit on the chip, resulting in increased chip cost.
[0025] The present application improves a delay circuit including: a first switch module, a second switch module, a first inverter, and a power module; the control end of the first switch module is configured to receive an initial clock signal, and the control end of the second switch module is configured to receive an enable signal; the input end of the first switch module is connected to a power supply, the output end of the first switch module is connected to the input end of the second switch module, and the output end of the second switch module is grounded; the output end of the first switch module is also connected to the input end of the first inverter; the input end of the first inverter is also connected to the input end of the power module; the output end of the first inverter is configured to output a first delayed clock signal.
[0026] In an embodiment of the present application, a first inverter is provided in the delay circuit. When the initial clock signal received by the delay circuit switches from a high level to a low level or from a low level to a high level, the charging and discharging process of the gate capacitance of the first inverter is utilized to delay the initial clock signal. The entire circuit does not require capacitors and resistors. Compared with the RC delay circuit in the related art, the volume occupied by the entire circuit in the chip is greatly reduced, which also reduces the cost. Moreover, the delay time of the rising edge and the falling edge of the delay circuit of this embodiment are controllable, and the reliability of the delay circuit is high.
[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined and referenced with each other under the premise of no contradiction.
[0028] An embodiment of the present application relates to a delay circuit, and a specific circuit structure diagram is shown in FIG. Figure 1 As shown, the delay circuit includes: a first switch module 101 , a second switch module 102 , a first inverter INV1 , and a power module 103 .
[0029] Specifically, the control end of the first switch module 101 is configured to receive the initial clock signal CLK0, and the control end of the second switch module 102 is configured to receive an enable signal; the input end of the first switch module 101 is connected to the power supply, the output end of the first switch module 101 is connected to the input end of the second switch module 102, and the output end of the second switch module 102 is grounded; the output end of the first switch module 101 is also connected to the input end of the first inverter INV1; the input end of the first inverter INV1 is also connected to the input end of the power module 103; the output end of the first inverter INV1 is configured to output the first delayed clock signal CLK1.
[0030] Specifically, the first switch module 101 of this embodiment is configured to be turned on when the voltage is low and turned off when the voltage is high. The second switch module 102 can be configured to be turned on when receiving an enable signal. The enable signal can be a high-level signal or a low-level signal, and this embodiment does not impose any specific limitations. In one embodiment, the second switch module 102 is an NMOS transistor N1. The second switch module 102, i.e., the NMOS transistor N1, is turned on when the enable signal is high.
[0031] Specifically, the initial clock signal CLK0 is a square wave signal. When the initial clock signal CLK0 is at a low level, the second switch module 102 is turned on under the control of the enable signal, and the control end of the first switch module 101 is at a low level. The first switch module 101 is turned on, so that the input voltage of the first inverter INV1 is at a high level. The first inverter INV1 inverts the high level to obtain a low-level first delayed clock signal CLK1. When the initial clock signal CLK0 is at a high level, the control end of the first switch module 101 is at a high level. The first switch module 101 is turned off, so that the input voltage of the first inverter INV1 is at a low level. The first inverter INV1 inverts the low level to obtain a high-level first delayed clock signal CLK1. In this way, the first delayed clock signal CLK1 output by the first inverter INV1 is synchronized with the initial clock signal CLK0.
[0032] Specifically, the structural diagram of the first inverter of this embodiment is as follows: Figure 2 As shown, it includes a PMOS tube M P 、NMOS tube M N , PMOS tube M P The gate of NMOS tube M N The gates of the two transistors serve as the input of the first inverter INV1. P The source of the PMOS tube M is connected to the power supply. P The drain of the NMOS tube M N The drain of NMOS tube M N The source of the PMOS tube M is grounded. P The drain of NMOS tube M N There is a node A between the drain of , and the node A serves as the output end of the first inverter INV1 to output the first delayed clock signal CLK1.
[0033] Since the PMOS tube M P The gate of NMOS tube M N A capacitor-like structure, namely, a gate capacitor, is formed between the gates. Therefore, when the initial clock signal CLK0 changes from a low level to a high level, that is, when the voltage at the input end of the first inverter INV1 changes from a high level to a low level, the voltage will not drop suddenly due to the presence of the gate capacitor. Therefore, in this embodiment, a power module 103 is connected to the input end of the first inverter INV1. The power module 103 consumes the charge of the gate capacitor, and finally the first inverter INV1 realizes signal inversion and implements the delay function.
[0034] Specifically, when the initial clock signal CLK0 input to the first switch module 101 is converted from a low level to a high level, the first switch module 101 is turned off, and the input end of the first inverter INV1 is a low-level signal; due to the existence of the gate capacitance of the first inverter INV1, the voltage at the input end of the first inverter INV1 will not drop suddenly, and the charge stored in the gate capacitance is controlled by the power-consuming unit (such as the current mirror circuit) to be discharged, and the discharge speed is controlled by the current source in the current mirror. The current of the current source is related to the amount of charge stored in the gate capacitance. When the charge of the gate capacitance at the Ready position drops below the threshold voltage, the first inverter INV1 works to invert the low-level signal into the first delayed clock signal CLK1 of a high level. Refer to the formula CV=It, where C is the charge of the gate capacitance of the first inverter INV1, V is the voltage value at the input terminal of the first inverter INV1, I is the discharge current value of the current source, and t is the discharge time, i.e., the delay time. C and V are both constant values after the various circuit components in the delay circuit are determined, and can be obtained based on the configuration information of the delay circuit. It can be seen that the delay time of the rising edge of the first delayed clock signal CLK1 output by the first inverter INV1 is inversely proportional to the current of the current source. Therefore, this embodiment can control the delay time of the rising edge of the delay circuit by controlling the current of the current source.
[0035] Specifically, when the initial clock signal CLK0 input to the first switch module 101 changes from a high level to a low level, the first switch module 101 is turned on, and the input end of the first inverter INV1 is a high-level signal. Due to the gate capacitance of the first inverter INV1, the voltage at Ready will not suddenly increase, and the charge at Ready is charged by the current flowing through the first switch module 101. In this embodiment, the first switch module 101 is a PMOS inverse proportional transistor P1. The current flowing through the first switch module 101, i.e., the PMOS inverse proportional transistor P1, is controlled by the aspect ratio of the PMOS inverse proportional transistor P1, see formula I=1 / 2μCoxW / L(Vgs-Vth)2, where Cox is the oxide layer thickness of the PMOS inverse proportional transistor P1, W / L is the aspect ratio of the PMOS inverse proportional transistor P1, Vgs is the gate-source voltage of the PMOS inverse proportional transistor P1, and Vth is the turn-on voltage threshold. When the charge at the Ready position rises above the threshold voltage of the gate capacitor, the first inverter INV1 operates to invert the high-level signal into a low-level signal. Therefore, by controlling the width-to-length ratio of the PMOS inverted ratio transistor P1, the current of the PMOS inverted ratio transistor P1 can be controlled, thereby controlling the delay time of the falling edge of the first delayed clock signal CLK1 output by the first inverter INV1.
[0036] Specifically, the gate of the PMOS inverse ratio transistor P1 is the control terminal of the first switch module 101, the source of P1 is the input terminal of the first switch module 101, and the drain of P1 is the output terminal of the first switch module 101. In this embodiment, by setting the first switch module 101 as the PMOS inverse ratio transistor P1, due to the characteristic of the inverse ratio transistor being a small current, when the charge amount of the gate capacitance is the same, the smaller the current, the longer the delay time, so that the delay circuit can achieve a better delay effect.
[0037] like Figure 3 2 is a schematic diagram of the circuit structure of the power-consuming unit. This embodiment is described by taking the power-consuming unit as a current mirror as an example. The power-consuming module 103 includes: a current source I, a fourth switch module 1031, and a fifth switch module 1032. The input end of the current source I is connected to the power supply, the output end of the current source I is connected to the input end of the fourth switch module 1031, the output end of the current source I is also connected to the control end of the fourth switch module 1031, and the control end of the fourth switch module 1031 is also connected to the control end of the fifth switch module. The output end of the fourth switch module 1031 is grounded, the input end of the fifth switch module 1032 serves as the input end of the power-consuming module 103, and receives the first delayed clock signal CLK1 through the Ready point. The output end of the fifth switch module 1032 is grounded.
[0038] Among them, the fourth switch module 1031 is an NMOS transistor N2, and the fifth switch module 1032 is an NMOS transistor N3. The gate of the NMOS transistor N2 is the control end of the fourth switch module 1031, the drain of the NMOS transistor N2 is the input end of the fourth switch module 1031, and the source of the NMOS transistor N2 is the output end of the fourth switch module 1031. The gate of the NMOS transistor N3 is the control end of the fifth switch module 1032, the drain of the NMOS transistor N3 is the input end of the fifth switch module 1032, and the source of the NMOS transistor N3 is the output end of the fifth switch module 1032.
[0039] In this embodiment, the fifth switch module 1032 in the current mirror, namely the NMOS transistor N3, consumes the charge in the gate capacitor. The consumption speed can be controlled by controlling the current of the current source I, so that the delay time of the rising edge of the delay circuit is controllable.
[0040] In this embodiment, a first inverter INV1 is provided in the delay circuit. When the initial clock signal CLK0 received by the delay circuit switches from a high level to a low level or from a low level to a high level, the charging and discharging process of the gate capacitance of the first inverter INV1 is utilized to delay the initial clock signal CLK0. The entire circuit does not require capacitors and resistors. Compared with the RC delay circuit in the related art, the volume occupied by the entire circuit in the chip is greatly reduced, which also reduces the cost. In addition, the delay time of the rising edge and the falling edge of the delay circuit of this embodiment are controllable, and the delay circuit has high reliability.
[0041] Another embodiment of the present application relates to a delay circuit. The difference between this embodiment and the previous embodiment is that the delay circuit of this embodiment further includes a first shaping module and a second shaping module. The specific circuit structure diagram of the delay circuit of this embodiment is shown in FIG. Figure 4 As shown, the delay circuit includes: a first switch module 101 , a second switch module 102 , a first inverter INV1 , a power module 103 , a first shaping module 104 , and a second shaping module 105 .
[0042] Specifically, the control end of the first switch module 101 is configured to receive the initial clock signal CLK0, and the control end of the second switch module 102 is configured to receive an enable signal; the input end of the first switch module 101 is connected to the power supply, the output end of the first switch module 101 is connected to the input end of the second switch module 102, and the output end of the second switch module 102 is grounded; the output end of the first switch module 101 is also connected to the input end of the first inverter INV1; the input end of the first inverter INV1 is also connected to the input end of the power module 103; the output end of the first inverter INV1 is configured to output the first delayed clock signal CLK1.
[0043] Specifically, the input end of the first shaping module 104 is connected to the output end of the first inverter INV1 . The first shaping module 104 is configured to shape the first delayed clock signal CLK1 to obtain a target delayed clock signal CLK, and output the target delayed clock signal CLK.
[0044] like Figure 4 As shown, the first shaping module 104 of this embodiment includes a second inverter INV2 and a third inverter INV3. The input of the second inverter INV2 serves as the input of the first shaping module 104, the output of the second inverter INV2 is connected to the input of the third inverter INV3, and the output of the third inverter INV3 serves as the output of the first shaping module 104. The circuit structures of the second inverter INV2 and the third inverter INV3 are substantially the same as those of the first inverter INV1, and are not further described here to avoid repetition.
[0045] Specifically, the initial clock signal CLK0 is a square wave signal. The initial clock signal CLK0 may encounter problems such as attenuation, amplitude reduction or capacitive load during transmission. These problems will cause the leading edge of the pulse signal to become irregular and no longer an ideal rectangular pulse; therefore, the present application sets a first shaping module 104, namely the second inverter INV2 and the third inverter INV3, at the output end of the first inverter INV1, and shapes the first delayed clock signal CLK1 output by the first inverter INV1 through the second inverter INV2 and the third inverter INV3, and adjusts the amplitude, frequency and phase and other characteristics of the first delayed clock signal CLK1, so that the target delayed clock signal CLK output by the first shaping module 104 is restored to a regular square wave signal, thereby improving the quality and accuracy of the signal.
[0046] Specifically, the second inverter INV2 receives the first delayed clock signal CLK1, inverts the first delayed clock signal CLK1 to obtain the second delayed clock signal CLK2, and the third inverter INV3 receives the second delayed clock signal CLK2, inverts the second delayed clock signal CLK2 to obtain the target delayed clock signal CLK. After two inversions, the phase of the target delayed clock signal CLK is consistent with that of the first delayed clock signal CLK1. For example, when the first delayed clock signal CLK1 is at a high level, it is inverted into the second delayed clock signal CLK2 at a low level by the second inverter INV2, and then inverted into the target delayed clock signal CLK at a high level by the third inverter INV3. When the first delayed clock signal CLK1 is at a low level, it is inverted into the second delayed clock signal CLK2 at a high level by the second inverter INV2, and then inverted into the target delayed clock signal CLK at a low level by the third inverter INV3, thereby ensuring that the phase of the target delayed clock signal CLK is consistent with that of the first delayed clock signal CLK1. Furthermore, the time taken by the second inverter INV2 and the third inverter INV3 in the signal inversion process can be neglected, thus achieving signal shaping for the delay circuit while ensuring the accuracy of the rising and falling edge delay times of the delay circuit.
[0047] Specifically, the control end of the second shaping module 105 is connected to the output end of the first inverter INV1 , the input end of the second shaping module 105 is connected to the input end of the first inverter INV1 , and the output end of the second shaping module 105 is grounded.
[0048] like Figure 4As shown, the second shaping module 105 of this embodiment is an NMOS transistor N4. The gate of the NMOS transistor N4 serves as the control terminal of the second shaping module 105 and is used to connect to the output terminal of the first inverter INV1. The drain of the NMOS transistor N4 serves as the input terminal of the second shaping module 105 and is used to connect to the input terminal of the first inverter INV1, i.e., the Ready point. The source of the NMOS transistor N4 serves as the output terminal of the second shaping module 105 and is used to be grounded.
[0049] Specifically, when the first delayed clock signal CLK1 is at a high level, NMOS transistor N4 is turned on, pulling the signal at the input of the first inverter INV1 low. This causes the initial clock signal CLK0 input to the first inverter INV1 to be closer to 0. The first delayed clock signal CLK1, obtained by the first inverter INV1 after inverting the initial clock signal CLK0, is closer to 1, thereby improving the accuracy of the obtained first delayed clock signal CLK1. It should be noted that when the first delayed clock signal CLK1 is at a low level, NMOS transistor N4 is turned off and does not operate.
[0050] This embodiment shapes the first delayed clock signal CLK1 to make the waveform of the final output target delayed clock signal CLK more regular, thereby improving the quality and accuracy of the output signal of the delay circuit and ensuring the accuracy of the rising and falling edge delay times.
[0051] On the other hand, an embodiment of the present application further provides a circuit board assembly, including: a delay circuit as described in any of the above embodiments.
[0052] It is not difficult to find that this embodiment is a circuit board assembly embodiment corresponding to the circuit embodiment, and this embodiment can be implemented in conjunction with the circuit embodiment. The relevant technical details mentioned in the circuit embodiment are still valid in this embodiment and are not repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the circuit embodiment.
[0053] In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems raised by this application, but this does not mean that there are no other units in this embodiment.
[0054] Another aspect of the present application embodiment provides an electronic device, including: a circuit board assembly as described in the above embodiment.
[0055] The above division of various components is only for clear description. During implementation, they can be combined into one component or some components can be split and decomposed into multiple components. As long as they include the same logical relationship, they are all within the scope of protection of the present invention.
[0056] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.
Claims
1. A delay circuit, characterized in that: include: A first switch module, a second switch module, a first inverter, and a power module; The control end of the first switch module is configured to receive an initial clock signal, and the control end of the second switch module is configured to receive an enable signal; the input end of the first switch module is connected to a power supply, the output end of the first switch module is connected to the input end of the second switch module, and the output end of the second switch module is grounded; The output end of the first switch module is also connected to the input end of the first inverter; the input end of the first inverter is also connected to the input end of the power module; the output end of the first inverter is configured to output a first delayed clock signal.
2. The delay circuit according to claim 1, characterized in that: The delay circuit also includes a first shaping module; the input end of the first shaping module is connected to the output end of the first inverter, and the first shaping module is configured to perform shaping processing on the first delayed clock signal to obtain a target delayed clock signal, and output the target delayed clock signal.
3. The delay circuit according to claim 2, characterized in that: The first shaping module includes a second inverter and a third inverter; The input end of the second inverter serves as the input end of the first shaping module, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter serves as the output end of the first shaping module.
4. The delay circuit according to any one of claims 1 to 3, characterized in that: The delay circuit also includes a second shaping module; The control end of the second shaping module is connected to the output end of the first inverter, the input end of the second shaping module is connected to the input end of the first inverter, and the output end of the second shaping module is grounded.
5. The delay circuit according to claim 4, characterized in that: The second shaping module is an NMOS tube, the gate of the NMOS tube serves as the control end of the second shaping module, the drain of the NMOS tube serves as the input end of the second shaping module, and the source of the NMOS tube serves as the output end of the second shaping module.
6. The delay circuit according to any one of claims 1 to 3, characterized in that: The power module includes: a current source, a fourth switch module, and a fifth switch module; The input end of the current source is connected to a power supply, the output end of the current source is connected to the input end of the fourth switch module, the output end of the current source is also connected to the control end of the fourth switch module, and the control end of the fourth switch module is also connected to the control end of the fifth switch module; the output end of the fourth switch module is grounded, the input end of the fifth switch module serves as the input end of the power consumption module, and the output end of the fifth switch module is grounded.
7. The delay circuit according to claim 1, characterized in that: The first switch module is a PMOS inverse ratio tube.
8. The delay circuit according to claim 4, characterized in that: The second switch module and the third switch module are both NMOS tubes.
9. A circuit board assembly, characterized in that: A delay circuit comprising any one of claims 1 to 8.
10. An electronic device, characterized in that: include: The circuit board assembly of claim 9.