Differential input buffer circuit and device

Abstract

The embodiment of the invention discloses a differential input buffer circuit and device. The circuit comprises two differential units, wherein each differential unit comprises a first signal input end, a second signal input end, a third signal input end, a first switch module, a second switch module, a third switch module and a coupling module; the coupling module is used for coupling an input signal of a second signal input end to the first node and the second node; the first switch module is used for controlling the conduction state of the first node and the power supply end according to a signal of the first signal input end; the second switch module is used for controlling the conduction state of the second node and the grounding end according to the signal of the second signal input end; and the third switch module is used for controlling the conduction state of the power supply end and the output end of the differential unit and controlling the conduction state of the grounding end and the output end of the differential unit according to the signals of the first node and the second node. According to the technical scheme, the area and power consumption of the buffer circuit can be reduced, and the conversion efficiency of the circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a differential input buffer circuit and device. Background Art

[0002] The original output signals of existing oscillator circuits are all non-full-swing sine waves, while the circuit system requires a full-swing square wave for the clock, so the sine wave needs to be converted through a buffer circuit.

[0003] Existing buffer circuits usually use two schemes for signal conversion. One scheme is to directly use an inverter for signal conversion. This scheme consumes large power and there is overlap in the output signals after conversion. The other scheme is to isolate the DC through a capacitor and then convert it through a resistor and an inverter. However, the resistor will generate a lot of energy loss and occupy a large circuit area. Summary of the invention

[0004] The present invention provides a differential input buffer circuit and device to reduce the area and power consumption of the buffer circuit and improve conversion efficiency.

[0005] According to one aspect of the present invention, a differential input buffer circuit is provided, comprising: two differential units, the differential units comprising a first signal input terminal, a second signal input terminal, a third signal input terminal, a first switch module, a second switch module, a third switch module and a coupling module;

[0006] The first signal input terminal and the second signal input terminal are connected to input signals that are differential signals, and the first signal input terminal and the third signal input terminal are connected to the same input signal;

[0007] The coupling module is connected to the second signal input terminal, the coupling module and the first switch module are connected to a first node, the coupling module and the second switch module are connected to a second node, and the coupling module is used to couple the input signal of the second signal input terminal to the first node and the second node;

[0008] The first switch module is used to control the conduction state between the first node and the power supply terminal according to the signal of the first signal input terminal; the second switch module is used to control the conduction state between the second node and the ground terminal according to the signal of the second signal input terminal;

[0009] The third switch module is used to control the conduction state between the power supply terminal and the output terminal of the differential unit, and to control the conduction state between the ground terminal and the output terminal of the differential unit according to the signals of the first node and the second node.

[0010] Optionally, the two differential modules include a first differential module and a second differential module, and a first signal input terminal of the first differential module and a first signal input terminal of the second differential module are connected to input signals that are differential signals of each other.

[0011] Optionally, the coupling module includes: a first coupling unit and a second coupling unit;

[0012] A first end of the first coupling unit is connected to the first node, and a second end of the first coupling unit is connected to the second signal input end;

[0013] A first end of the second coupling unit is connected to the second signal input end, and a second end of the second coupling unit is connected to the second node.

[0014] Optionally, the first coupling unit includes a capacitor, and the second coupling unit includes a capacitor.

[0015] Optionally, the first switch module includes a first transistor, and the second switch module includes a second transistor;

[0016] The control terminal of the first transistor is connected to the first signal input terminal, the first electrode of the first transistor is connected to the power supply terminal, and the second electrode of the first transistor is connected to the first node;

[0017] The control terminal of the second transistor is connected to the third signal input terminal, the first electrode of the second transistor is connected to the second node, and the second electrode of the second transistor is connected to the ground terminal;

[0018] The first transistor and the second transistor are of different types.

[0019] Optionally, the third switch module includes a third transistor and a fourth transistor;

[0020] The control terminal of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the power supply terminal, and the second electrode of the third transistor is connected to the output terminal of the differential unit;

[0021] The control terminal of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the output terminal of the differential unit, and the second electrode of the fourth transistor is connected to the ground terminal;

[0022] The third transistor and the fourth transistor are of different types.

[0023] Optionally, the differential unit further includes a fourth switch module;

[0024] A first end of the fourth switch module is connected to the power supply end, a second end of the fourth switch module is connected to the ground end, and a third end of the fourth switch module is connected to the output end of the differential unit;

[0025] The fourth switch module is used to shape the signal output from the output end of the differential unit.

[0026] Optionally, the fourth switch module includes a fifth transistor and a sixth transistor;

[0027] The control terminal of the fifth transistor is connected to the output terminal of the differential unit, the first electrode of the fifth transistor is connected to the power supply terminal, and the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor;

[0028] The control terminal of the sixth transistor is connected to the output terminal of the differential unit, and the second electrode of the sixth transistor is connected to the ground terminal;

[0029] The fifth transistor and the sixth transistor are of different types.

[0030] Optionally, the input signal includes a sinusoidal AC signal, and the voltage at the power supply end is greater than the amplitude of the sinusoidal AC signal.

[0031] According to another aspect of the present invention, a differential input buffer device is provided, comprising the differential input buffer circuit provided by any embodiment of the present invention.

[0032] The technical solution of the embodiment of the present invention couples the input signal of the second input terminal to the first node through the coupling module, so that the conduction strength between the third switch module and the power supply terminal is greater than the conduction strength between the third switch module and the ground terminal, and reduces the time for the third switch module to be connected to the power supply terminal through the first node and the first switch module for the next time; the input signal of the second input terminal is coupled to the second node through the coupling module, so that the conduction strength between the third switch module and the power supply terminal is less than the conduction strength between the third switch module and the ground terminal, and reduces the time for the third switch module to be connected to the ground terminal through the second node and the second switch module for the next time. The technical solution provided by the embodiment of the present invention reduces the time required for the third switch unit to be connected to the power supply terminal and the ground terminal through the coupling effect of the coupling module, thereby adapting to the changing strength of the high-frequency sinusoidal signal at the input terminal and avoiding the overlap of the output signal; at the same time, the circuit structure is simple, no additional resistor is required, the circuit area is significantly reduced, and the influence of excessive loss of the resistor under high-frequency input signals is avoided, thereby improving the conversion efficiency of the circuit.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of the structure of a differential input buffer circuit provided by an embodiment of the present invention;

[0036] Figure 2 A signal timing diagram of a differential input buffer circuit provided by an embodiment of the present invention;

[0037] Figure 3 A schematic structural diagram of yet another differential input buffer circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] Figure 1 A schematic diagram of a differential input buffer circuit provided by an embodiment of the present invention is provided. Figure 2A signal timing diagram of a differential input buffer circuit provided by an embodiment of the present invention. Figure 1 and Figure 2 The differential input buffer circuit includes: two differential units 10, the differential unit 10 includes a first signal input terminal 11, a second signal input terminal 12, a third signal input terminal 13, a first switch module 100, a second switch module 200, a third switch module 300 and a coupling module 400; the first signal input terminal 11 and the second signal input terminal 12 are connected to input signals that are differential signals, and the first signal input terminal 11 and the third signal input terminal 13 are connected to the same input signal; the coupling module 400 is connected to the second signal input terminal 12, the coupling module 400 and the first switch module 100 are connected to the first node A, and the coupling module 400 and the second switch module 200 are connected to Connected to the second node B, the coupling module 400 is used to couple the input signal of the second signal input terminal 12 to the first node A and the second node B; the first switch module 100 is used to control the conduction state of the first node A and the power supply terminal VDD according to the signal of the first signal input terminal 11; the second switch module 200 is used to control the conduction state of the second node B and the ground terminal GND according to the signal of the second signal input terminal 12; the third switch module 300 is used to control the conduction state of the power supply terminal VDD and the output terminal 14 of the differential unit 10 according to the signals of the first node A and the second node B, and control the conduction state of the ground terminal GND and the output terminal 14 of the differential unit 10.

[0041] Specifically, the first signal input terminal 11, the second signal input terminal 12 and the third signal input terminal 13 are three input signal interfaces of the differential buffer circuit. Figure 2 As shown, the input signal can be a high-frequency sine wave signal of 2.4 GHZ. Among them, the first signal input terminal 11 and the third signal input terminal 13 are connected to the OSCP signal, and the second signal input terminal 12 is connected to the OSCN signal. The OSCP signal and the OSCN signal are differential signals. In the same time period, the voltage change direction of the OSCP signal is opposite to the voltage change direction of the OSCN signal. When the voltage of the OSCP signal gradually increases, the voltage of the OSCN signal gradually decreases; when the voltage of the OSCP signal gradually decreases, the voltage of the OSCN signal gradually increases. There are many ways to set the first switch module 100 and the second switch module 200. See Figure 1In one embodiment, the control end of the first switch module 100 can be connected to the first signal input end 11, the first end of the first switch module 100 is connected to the power supply end VDD, and the second end of the first switch module 100 is connected to the coupling module 400 at the first node A; the control end of the second switch module 200 can be connected to the third signal input end 12, the first end of the second switch module 200 can be connected to the second node B of the coupling module 400, and the second end of the second switch module 200 can be connected to the ground end GND. The switch type of the first switch module 100 can be opposite to that of the second switch module 200, so that when the first signal input end 11 and the third signal input end 13 are input with the same signal, the first switch module 100 and the second switch module 200 maintain opposite switch states at the same time.

[0042] The following description is made with the input signal OSCP of the first signal input terminal 11 controlling the first switch module 100 to be in the on state as the starting state. For example, curve LA is a schematic diagram of the voltage waveform change at the first node A, and curve LB is a schematic diagram of the voltage waveform change at the second node B. When the input signal OSCP of the first signal input terminal 11 controls the first switch module 100 to be turned on, the input signal OSCP of the third signal input terminal 13 controls the second switch module 200 to be turned off. At this time, the signal at the first node A is the voltage signal of the power supply terminal VDD. The third switch module 300 controls the conduction strength between the power supply terminal VDD and the output terminal 14 of the differential unit 10 to be greater than the conduction strength between the ground terminal GND and the output terminal 14 of the differential unit 10, and the output terminal 14 of the differential unit 10 outputs the level signal of the power supply terminal VDD. When the input signal OSCP of the first signal input terminal 11 gradually rises from low to high and controls the first switch module 100 to change from the on state to the off state, the input signal OSCP of the third signal input terminal 13 controls the second switch module 200 to change from the off state to the on state. At this time, the signal at the second node B is a voltage signal of the ground terminal GND. Since the change direction of the input signal OSCN of the second signal input terminal 12 is gradually decreasing from high to low, which is opposite to the change direction of the input signal OSCP of the first signal input terminal 11, the coupling module 400 couples the input signal OSCN of the second signal input terminal 12 to the first node A, and the voltage signal at the first node A is a signal that gradually decreases from the signal of the power supply terminal VDD as a reference. The third switch module 300 controls the conduction strength between the power supply terminal VDD and the output terminal 14 of the differential unit 10 to be less than the conduction strength between the ground terminal GND and the output terminal 14 of the differential unit 10, and the output terminal 14 of the differential unit 10 outputs a level signal of the ground terminal GND. Since the voltage signal at the first node A is a signal derived from the signal at the power supply terminal VDD, the voltage signal at the first node A can be quickly changed to the signal at the power supply terminal VDD when the first switch module 100 is turned on next time, thereby reducing the time required for the third switch module 300 to be connected to the power supply terminal VDD through the first node A and the first switch module 100 next time, so as to adapt to the changing intensity of the high-frequency sinusoidal signal and avoid overlapping of the signal output from the output terminal 14 of the differential unit 10.

[0043] The technical solution provided by the embodiment of the present invention couples the input signal of the second input terminal to the first node through a coupling module, so that the conduction strength between the third switch module and the power supply terminal is greater than the conduction strength between the third switch module and the ground terminal, and reduces the time for the third switch module to be connected to the power supply terminal through the first node and the first switch module for the next time; the input signal of the second input terminal is coupled to the second node through a coupling module, so that the conduction strength between the third switch module and the power supply terminal is less than the conduction strength between the third switch module and the ground terminal, and reduces the time for the third switch module to be connected to the ground terminal through the second node and the second switch module for the next time. The technical solution provided by the embodiment of the present invention reduces the time required for the third switch unit to be connected to the power supply terminal and the ground terminal through the coupling effect of the coupling module, thereby adapting to the changing strength of the high-frequency sinusoidal signal at the input terminal and avoiding the overlap of the output signal; at the same time, the circuit structure is simple, no additional resistor is required, the circuit area is significantly reduced, and the influence of excessive loss of the resistor under high-frequency input signals is avoided, thereby improving the conversion efficiency of the circuit.

[0044] Optionally, based on the above embodiment, Figure 1 and Figure 2 The two differential modules include a first differential module 101 and a second differential module 102 , and the first signal input terminal 11 of the first differential module 101 and the first signal input terminal 11 of the second differential module 102 are connected to input signals that are differential signals.

[0045] Specifically, the first signal input terminal 11 of the first differential module 101 and the first signal input terminal 11 of the second differential module 102 are connected to the input signals which are differential signals to each other, so that the first differential module 101 and the second differential module form a bilaterally symmetrical differential buffer circuit. Such a setting can make the output terminal 14 of the first differential module 101 output the power supply terminal VDD level signal, and the output terminal 14 of the second differential module 102 can output the ground terminal GND level signal, thereby improving the conversion efficiency of the circuit to the input signal.

[0046] Exemplarily, when the input signal of the first signal input terminal 11 of the first differential module 101 is an OSCP signal, the input signal of the first signal input terminal 11 of the second differential module 102 may be an OSCN signal which is a differential signal with the OSCP signal.

[0047] Correspondingly, when the input signal OSCN of the first signal input terminal 11 of the second differential module 102 controls the first switch module 100 to be turned off, the input signal OSCN of the third signal input terminal 13 controls the second switch module 200 of the second differential module 102 to be turned on. At this time, the signal at the second node B of the second differential module 102 is a voltage signal of the ground terminal GND. The third switch module 300 of the second differential module 102 controls the conduction strength between the ground terminal GND and the output terminal 14 of the second differential module 102 to be greater than the conduction strength between the power supply terminal VDD and the output terminal 14 of the second differential module 102, and the output terminal 14 of the second differential module 102 outputs a level signal of the power supply terminal VDD. When the input signal OSCN of the first signal input terminal 11 of the second differential module 102 controls the first switch module 100 of the second differential module 102 to change from the off state to the on state, the input signal OSCN of the third signal input terminal 13 of the second differential module 102 controls the second switch module 200 of the second differential module 102 to change from the on state to the off state. At this time, the signal at the first node A of the second differential module 102 is a voltage signal of the power supply terminal VDD. Since the voltage change direction of the input signal OSCP of the second signal input terminal 12 of the second differential module 102 is opposite to the voltage change direction of the input signal OSCN of the first signal input terminal 11 of the second differential module 102, the coupling module 400 of the second differential module 102 will couple the input signal OSCP of the second signal input terminal 12 of the second differential module 102 to the second node B, and the voltage signal at the second node B is a signal that gradually changes based on the signal of the ground terminal GND. The third switch module 300 of the second differential module 102 controls the conduction strength between the power supply terminal VDD and the output terminal 14 of the second differential module 102 to be greater than the conduction strength between the ground terminal GND and the output terminal 14 of the second differential module 102, and the output terminal 14 of the second differential module 102 outputs the level signal of the power supply terminal VDD.

[0048] The technical solution provided by the embodiment of the present invention is as follows: from the input end of the differential input buffer circuit: when the first signal input end 11 and the third signal input end 13 of the first differential module 101 are connected to the OSCP signal, and the second signal input end 12 of the first differential module 101 is connected to the OSCN signal; the first signal input end 11 and the third signal input end 13 of the second differential module 102 are connected to the OSCN signal, and the second signal input end 12 of the second differential module 102 is connected to the OSCP signal; from the output end of the differential input buffer circuit: when the output end 14 of the first differential module 101 outputs the power supply end VDD signal, the output end 14 of the second differential module 102 outputs the ground end GND signal; when the output end 14 of the first differential module 101 outputs the ground end GND signal, the output end 14 of the second differential module 102 outputs the power supply end VDD signal.

[0049] Optionally, Figure 3 A schematic diagram of a differential input buffer circuit according to an embodiment of the present invention. Figure 3 The coupling module 400 includes: a first coupling unit C1 and a second coupling unit C2; a first end of the first coupling unit C1 is connected to the first node A, and a second end of the first coupling unit C1 is connected to the second signal input terminal 12; a first end of the second coupling unit C2 is connected to the second signal input terminal 12, and a second end of the second coupling unit C2 is connected to the second node B.

[0050] Specifically, the first coupling unit C1 and the second coupling unit C2 can both be set as capacitors. In one embodiment, the second end of the first coupling unit C1 and the first end of the second coupling unit C2 are set as the second signal input terminal 12. The first differential module 101 is used as an example for explanation below. Exemplarily, when the input signal of the first signal input terminal 11 controls the first switch module 100 from the on state to the off state, the input signal of the third signal input terminal 13 controls the second switch module 200 from the off state to the on state. At this time, the signal at the second node B is a voltage signal of the ground terminal GND, and the second coupling unit C2 cannot couple the input signal of the second signal input terminal 12 to the second node B. Since the change direction of the input signal of the second signal input terminal 12 is opposite to the change direction of the input signal of the first signal input terminal 11, the first coupling unit C1 will couple the input signal of the second signal input terminal 12 to the first node A. The voltage signal at the first node A is a signal that gradually changes based on the signal of the power supply terminal VDD. The final voltage signal that changes at the first node A is the voltage signal after the first coupling unit C1 can couple the input signal of the second signal input terminal 12 after the first switch module 100 is turned off.

[0051] When the input signal of the third signal input terminal 13 controls the second switch module 200 to change from the on state to the off state, the input signal of the first signal input terminal 11 controls the first switch module 200 to change from the off state to the on state. At this time, the signal at the first node A is the voltage signal of the power supply terminal VDD, and the first coupling unit C1 cannot couple the input signal of the second signal input terminal 12 to the first node A. Since the change direction of the input signal of the second signal input terminal 12 is opposite to the change direction of the input signal of the third signal input terminal 13, the second coupling unit C2 will couple the input signal of the second signal input terminal 12 to the second node B. The voltage signal at the second node B is a signal that gradually changes based on the voltage signal of the ground terminal GND. The final voltage signal at the second node B is the voltage signal after the second coupling unit C2 can couple the input signal of the second signal input terminal 12 after the second switch module 200 is turned off.

[0052] Optionally, based on the above embodiment, continue to refer to Figure 2 and Figure 3 The first switch module 100 includes a first transistor P1, and the second switch module 200 includes a second transistor N1; the control end of the first transistor P1 is connected to the first signal input end 11, the first electrode of the first transistor P1 is connected to the power supply end VDD, and the second electrode of the first transistor P1 is connected to the first node A; the control end of the second transistor N1 is connected to the third signal input end 13, the first electrode of the second transistor N1 is connected to the second node B, and the second electrode of the second transistor N1 is connected to the ground end GND; the first transistor P1 and the second transistor N1 are of different types.

[0053] Specifically, in one embodiment, the first switch module 100 and the second switch module 200 can be set as metal-oxide semiconductor field effect transistors. Exemplarily, the following is an example of the first transistor P1 being a P-type transistor and the second transistor N1 being an N-type transistor. The control terminal of the first transistor P1 can be a gate connected to the first signal input terminal 11; the first electrode of the first transistor P1 can be a source connected to the power supply terminal VDD; the second electrode of the first transistor P1 can be a drain connected to the first node A. The control terminal of the second transistor N1 can be a gate connected to the third signal input terminal 13; the first electrode of the second transistor N1 can be a drain connected to the second node B; the second electrode of the second transistor N1 can be a source connected to the ground terminal GND.

[0054] The following description is made by taking the first differential module 101 as an example. Figure 2 The middle curve LA may be a schematic diagram of the voltage waveform at the first node A of the first differential module 101, and the curve LB may be a schematic diagram of the voltage waveform at the second node B of the first differential module 101. When the signal OSCP inputted from the first signal input terminal 11 and the third signal input terminal 13 gradually rises from low to high, and the signal OSCN inputted from the second signal input terminal 12 gradually decreases from high to low, the first transistor P1 gradually changes from the on state to the off state, and the second transistor N1 gradually changes from the off state to the on state. When the second transistor N1 is turned on, the voltage of the second node B is rapidly reduced to 0V, and the signal OSCN inputted from the second signal input terminal 12 cannot be coupled to the second node B through the second coupling unit C2; the voltage signal of the first node A will start to change from VDD, and at this time, the signal OSCN inputted from the second signal input terminal 12 can be coupled to the first node A through the first coupling unit C1, so the voltage signal of the first node A is reduced from VDD by the coupling effect of the first coupling unit C1, and the reduced voltage depends on the reduced voltage coupled to the first coupling unit C1 after the first transistor P1 is turned off.

[0055] When the signal OSCP inputted from the first signal input terminal 11 and the third signal input terminal 13 gradually decreases from high to low, and the signal OSCN inputted from the second signal input terminal 12 gradually increases from low to high, the first transistor P1 gradually changes from the off state to the on state, and the second transistor N1 gradually changes from the on state to the off state. When the first transistor P1 is turned on, the voltage of the first node A is quickly pulled up to VDD, and the signal OSCN inputted from the second signal input terminal 12 cannot be coupled to the second node A through the first coupling unit C1; the voltage signal of the second node B will start to change from 0V, and at this time, the signal OSCN inputted from the second signal input terminal 12 can be coupled to the second node B through the second coupling unit C2, so the voltage signal of the second node B can be coupled from 0V by the coupling effect of the second coupling unit C2, and the voltage after the increase depends on the rising voltage coupled to the second coupling unit C2 after the second transistor N1 is turned off.

[0056] Optionally, based on the above embodiment, continue to refer to Figure 2 and Figure 3 The third switch module 300 includes a third transistor P2 and a fourth transistor N2; the control end of the third transistor P2 is connected to the second node B, the first electrode of the third transistor P2 is connected to the power supply end VDD, and the second electrode of the third transistor P2 is connected to the output end 14 of the differential unit 10; the control end of the fourth transistor N2 is connected to the first node A, the first electrode of the fourth transistor N2 is connected to the output end 14 of the differential unit 10, and the second electrode of the fourth transistor N2 is connected to the ground end GND; the third transistor P2 and the fourth transistor N2 are of different types.

[0057] Specifically, in one embodiment, the third transistor P2 and the fourth transistor N2 may be set as metal-oxide semiconductor field effect transistors. Exemplarily, the third transistor P2 is a P-type transistor and the fourth transistor N2 is an N-type transistor. The control terminal of the third transistor P2 may be a gate connected to the second node B; the first electrode of the third transistor P2 may be a source connected to the power supply terminal VDD; the second electrode of the third transistor P2 may be a drain connected to the output terminal 14. The control terminal of the fourth transistor N2 may be a gate connected to the first node A; the first electrode of the fourth transistor N2 may be a drain connected to the output terminal 14; the second electrode of the fourth transistor N2 may be a source connected to the ground terminal GND.

[0058] The following description is made by taking the first differential module 101 as an example. Figure 2The middle curve L141 may be a schematic diagram of a voltage waveform output at the output terminal 14 of the first differential module 101, and the curve L142 may be a schematic diagram of a voltage waveform output at the output terminal 14 of the second differential module 102. When the signal OSCP inputted from the first signal input terminal 11 and the third signal input terminal 13 gradually rises from low to high, and the signal OSCN inputted from the second signal input terminal 12 gradually decreases from high to low, the first transistor P1 gradually changes from the on state to the off state, and the second transistor N1 gradually changes from the off state to the on state. When the second transistor N1 is turned on, the voltage signal of the second node B is rapidly reduced to 0V, and the third transistor P2 can enter a linear on state. After the first transistor P1 is turned off, the voltage of the first node A is a voltage that gradually decreases from VDD, so the fourth transistor N2 changes from a linear on state to a saturated state. At this time, the conduction state between the third switch module 300 and the power supply terminal VDD through the third transistor P2 is stronger than the conduction state between the third switch module 300 and the ground terminal GND through the fourth transistor N2, and the output terminal 14 of the first differential module 101 outputs a high level signal of the power supply terminal VDD. At this time, the output terminal 14 of the second differential module 102 outputs a low level signal of the ground terminal GND.

[0059] When the signal OSCP inputted by the first signal input terminal 11 and the third signal input terminal 13 gradually decreases from high to low, and the signal OSCN inputted by the second signal input terminal 12 gradually increases from low to high, the first transistor P1 gradually changes from the off state to the on state, and the second transistor N1 gradually changes from the on state to the off state. When the first transistor P1 is turned on, the voltage of the first node A is quickly pulled up to VDD, and the fourth transistor N2 enters the linear on state from the saturation state. After the second transistor N1 is turned off, the voltage of the second node B is a voltage that gradually increases from 0V, so the third transistor P2 changes from the linear on state to the saturation state. At this time, the on state of the third switch module 300 through the fourth transistor N2 and the ground terminal GND is stronger than the on state of the third transistor P2 through the third transistor P2 and the power supply terminal VDD, and the output terminal 14 of the first differential module 101 outputs a low-level signal of the ground terminal GND. At this time, the output terminal 14 of the second differential module 102 outputs a high-level signal of the ground terminal GND.

[0060] The technical solution of this embodiment uses the voltage signals of the first node A and the second node B as the input of the second stage amplification, which can make the third transistor P2 and the fourth transistor N2 in a high gain state, and the voltage signals of the first node A and the second node B change at the same time, becoming high at the same time and becoming low at the same time; so that when the pull-down ability of the fourth transistor N2 is enhanced, the pull-up ability of the third transistor P2 is weakened, and when the pull-down ability of the fourth transistor N2 is weakened, the pull-up ability of the third transistor P2 is enhanced, and finally a waveform that quickly changes from VDD to 0V and quickly changes from 0V to VDD is obtained at the output end 14, completing the conversion from sine wave to square wave. The technical solution of this embodiment does not set a resistor in the circuit design, simplifies the circuit structure, and reduces the overall area and power consumption of the circuit; when the coupling unit is set by a capacitor, the required capacitance of the capacitor is small, and the loss and influence on the input sine wave signal are extremely small; and the transistor can also be of a smaller size, further reducing the circuit area. Exemplarily, taking the input sine wave as 2.4 GHZ frequency, the power supply voltage VDD=800 mV, and the first coupling unit C1 and the second coupling unit C2 as 10 fF capacitors as an example for calculation, the overall power consumption of the circuit is 77.9 uA.

[0061] Optionally, based on the above embodiment, continue to refer to Figure 3 The differential unit 10 further includes a fourth switch module 500; a first end of the fourth switch module 500 is connected to the power supply terminal VDD, a second end of the fourth switch module 500 is connected to the ground terminal GND, and a third end of the fourth switch module 500 is connected to the output terminal 14 of the differential unit 10; the fourth switch module 500 is used to shape the signal output from the output terminal 14 of the differential unit 10.

[0062] Specifically, the first end of the fourth switch module 500 is connected to the power supply terminal VDD, and when the conduction state between the third switch module 300 and the ground terminal GND is stronger than the conduction state between the third switch module 300 and the power supply terminal VDD, the first end of the fourth switch module 500 and the power supply terminal VDD are in a connected state, the driving capability of the output terminal 14 is enhanced, and the low-level signal outputted by the output terminal 14 is shaped. The second end of the fourth switch module 500 is connected to the ground terminal GND, and when the conduction state between the third switch module 300 and the power supply terminal VDD is stronger than the conduction state between the third switch module 300 and the ground terminal GND, the second end of the fourth switch module 500 and the ground terminal GND are in a connected state, the driving capability of the output terminal 14 is enhanced, and the high-level signal outputted by the output terminal 14 is shaped.

[0063] Optionally, based on the above embodiment, continue to refer to Figure 2 and Figure 3The fourth switch module 500 includes a fifth transistor P3 and a sixth transistor N3; the control terminal P3 of the fifth transistor is connected to the output terminal 14 of the differential unit 10, the first electrode of the fifth transistor P3 is connected to the power supply terminal VDD, and the second electrode of the fifth transistor P3 is connected to the first electrode of the sixth transistor N3; the control terminal of the sixth transistor N3 is connected to the output terminal 14 of the differential unit 10, and the second electrode of the sixth transistor N3 is connected to the ground terminal GND; the fifth transistor P3 and the sixth transistor N3 are of different types.

[0064] Specifically, in one embodiment, the fifth transistor P3 and the sixth transistor N3 may be set as metal-oxide semiconductor field effect transistors. Exemplarily, the fifth transistor P3 is a P-type transistor and the sixth transistor N3 is an N-type transistor. The control terminal of the fifth transistor P3 may be a gate connected to the output terminal 14; the first electrode of the fifth transistor P3 may be a source electrode connected to the power supply terminal VDD; the second electrode of the fifth transistor P3 may be a drain electrode connected to the first electrode of the sixth transistor N3. The control terminal of the sixth transistor N3 may be a gate electrode connected to the output terminal 14; the first electrode of the sixth transistor N3 may be a drain electrode connected to the second electrode of the fifth transistor P3; the second electrode of the sixth transistor N3 may be a source electrode connected to the ground terminal GND.

[0065] The following is explained by taking the first differential module 101 as an example. When the output terminal 14 of the first differential module 101 outputs a VDD high-level signal, the sixth transistor N3 can be turned on, so that the power supply terminal VDD can form a conduction loop through the linearly conductive third transistor P2 and the linearly conductive sixth transistor N3 and the ground terminal GND to shape the high-level signal output by the output terminal 14. When the output terminal 14 of the first differential module 101 outputs a 0V low-level signal, the fifth transistor P3 can be turned on, so that the power supply terminal VDD can form a conduction loop through the linearly conductive fifth transistor P3 and the linearly conductive fourth transistor N2 to shape the low-level signal output by the output terminal 14. Exemplarily, Figure 2 The middle curve L1411 may be a schematic diagram of a voltage waveform outputted from the output terminal 14 of the first differential module 101 after being shaped by the fourth switch module 500. Compared with the waveform outputted from the output terminal 14 of the first differential module 101 when the fourth switch module 500 is not provided, the square wave outputted by the curve L1411 has a higher quality. The curve L1422 may be a schematic diagram of a voltage waveform outputted from the output terminal 14 of the second differential module 102 after being shaped by the fourth switch module 500. Compared with the waveform outputted from the output terminal 14 of the second differential module 102 when the fourth switch module 500 is not provided, the square wave outputted by the curve L1422 has a higher quality.

[0066] Optionally, the input signal includes a sinusoidal AC signal, and the voltage of the power supply terminal VDD is greater than the amplitude of the sinusoidal AC signal.

[0067] Specifically, if the voltage of the power supply terminal VDD is less than the amplitude of the sinusoidal AC signal, then after the signal at the first signal input terminal 11 turns off the first transistor P1, due to the coupling effect of the first coupling unit C1, the voltage signal at the first node A will be pulled up from VDD to the amplitude of the sinusoidal AC signal at the second signal input terminal 12, thereby causing the fourth transistor N2 and the third transistor P2 to be in a linear conduction state at the same time, thereby affecting the signal output by the output terminal 14 and affecting the conversion effect of the circuit.

[0068] An embodiment of the present invention further provides a differential input buffer device, including the differential input buffer circuit provided by any embodiment of the present invention, and having the same beneficial effects as the differential input buffer circuit provided by any embodiment of the present invention, which will not be elaborated here.

[0069] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0070] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A differential input buffer circuit, characterized in that: include: Two differential units, each of which comprises a first signal input terminal, a second signal input terminal, a third signal input terminal, a first switch module, a second switch module, a third switch module and a coupling module; The first signal input terminal and the second signal input terminal are connected to input signals that are differential signals, and the first signal input terminal and the third signal input terminal are connected to the same input signal; The coupling module is connected to the second signal input terminal, the coupling module and the first switch module are connected to a first node, the coupling module and the second switch module are connected to a second node, and the coupling module is used to couple the input signal of the second signal input terminal to the first node and the second node; The first switch module is used to control the conduction state between the first node and the power supply terminal according to the signal of the first signal input terminal; the second switch module is used to control the conduction state between the second node and the ground terminal according to the signal of the second signal input terminal; The third switch module is used to control the conduction state between the power supply terminal and the output terminal of the differential unit, and to control the conduction state between the ground terminal and the output terminal of the differential unit according to the signals of the first node and the second node.

2. The differential input buffer circuit according to claim 1, wherein: The two differential modules include a first differential module and a second differential module. The first signal input terminal of the first differential module and the first signal input terminal of the second differential module are connected to input signals that are differential signals of each other.

3. The differential input buffer circuit according to claim 2, wherein: The coupling module comprises: a first coupling unit and a second coupling unit; A first end of the first coupling unit is connected to the first node, and a second end of the first coupling unit is connected to the second signal input end; A first end of the second coupling unit is connected to the second signal input end, and a second end of the second coupling unit is connected to the second node.

4. The differential input buffer circuit according to claim 3, characterized in that: The first coupling unit includes a capacitor, and the second coupling unit includes a capacitor.

5. The differential input buffer circuit according to claim 2, wherein: The first switch module includes a first transistor, and the second switch module includes a second transistor; The control terminal of the first transistor is connected to the first signal input terminal, the first electrode of the first transistor is connected to the power supply terminal, and the second electrode of the first transistor is connected to the first node; The control terminal of the second transistor is connected to the third signal input terminal, the first electrode of the second transistor is connected to the second node, and the second electrode of the second transistor is connected to the ground terminal; The first transistor and the second transistor are of different types.

6. The differential input buffer circuit according to claim 2, wherein: The third switch module includes a third transistor and a fourth transistor; The control terminal of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the power supply terminal, and the second electrode of the third transistor is connected to the output terminal of the differential unit; The control terminal of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the output terminal of the differential unit, and the second electrode of the fourth transistor is connected to the ground terminal; The third transistor and the fourth transistor are of different types.

7. The differential input buffer circuit according to claim 1, wherein: The differential unit further includes a fourth switch module; A first end of the fourth switch module is connected to the power supply end, a second end of the fourth switch module is connected to the ground end, and a third end of the fourth switch module is connected to the output end of the differential unit; The fourth switch module is used to shape the signal output from the output end of the differential unit.

8. The differential input buffer circuit according to claim 7, characterized in that: The fourth switch module includes a fifth transistor and a sixth transistor; The control terminal of the fifth transistor is connected to the output terminal of the differential unit, the first electrode of the fifth transistor is connected to the power supply terminal, and the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor; The control terminal of the sixth transistor is connected to the output terminal of the differential unit, and the second electrode of the sixth transistor is connected to the ground terminal; The fifth transistor and the sixth transistor are of different types.

9. The differential input buffer circuit according to claim 1, wherein: The input signal includes a sinusoidal AC signal, and the voltage at the power supply terminal is greater than the amplitude of the sinusoidal AC signal.

10. A differential input buffer device, characterized in that: The differential input buffer circuit comprises any one of claims 1 to 9.

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