Bias temperature instability recovery circuit and method of inverter
By designing a bias temperature instability recovery circuit for the inverter, the bias temperature instability of PMOS and NMOS transistors is restored by the first and second recovery units, the problem that the prior art cannot recover both transistors at the same time is solved, and more efficient electrical performance improvement and aging delay are achieved.
Patent Information
- Application Number
- CN202311396931.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-25
- Publication Date
- 2025-04-25
AI Technical Summary
The prior art cannot simultaneously restore bias temperature instability to the gate-sharing PMOS and NMOS transistors in the inverter, resulting in degradation of electrical performance and aging acceleration.
A bias temperature instability recovery circuit of an inverter is designed, including a first and a second recovery unit, coupled to PMOS and NMOS transistors, respectively, and applying a recovery voltage signal to the well region of the transistor during each recovery state to achieve bias temperature instability recovery.
This solution can simultaneously restore bias temperature instability of PMOS and NMOS transistors in the inverter, improve the electrical performance of the inverter and delay the aging speed.
Smart Images
Figure CN119892050A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of circuits, and in particular to a bias temperature instability recovery circuit and recovery method for an inverter. Background Art
[0002] Bias Temperature Instability (BTI) refers to the degradation effects of threshold voltage drift and saturation current on the electrical characteristics of a transistor when a bias voltage is applied to the transistor gate under certain temperature conditions. Bias temperature instability includes negative bias temperature instability (NBTI) occurring in PMOS transistors and positive bias temperature instability (PBTI) occurring in NMOS transistors.
[0003] As gate lengths continue to shrink and oxide thicknesses continue to decrease, the impact of bias temperature instability on semiconductor devices becomes more and more significant and has become one of the main factors in device degradation. Therefore, performing bias temperature instability recovery on transistors has become critical.
[0004] In standard cells such as ring oscillators, inverters are used as basic functional units, which usually include gate-sharing PMOS transistors and NMOS transistors. However, current bias temperature instability solutions cannot simultaneously perform bias temperature instability recovery on gate-sharing PMOS transistors and NMOS transistors. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a bias temperature instability recovery circuit and a semiconductor structure of an inverter, which can simultaneously realize bias temperature instability recovery for the first transistor and the second transistor in the inverter, which correspondingly helps to improve the electrical performance of the inverter.
[0006] To solve the above problem, an embodiment of the present invention provides a bias temperature instability recovery circuit of an inverter, wherein the inverter includes a first transistor and a second transistor, and the bias temperature instability recovery circuit of the inverter includes:
[0007] a first recovery unit, coupled to the first transistor, adapted to apply a first recovery voltage signal to a well region of the first transistor when the first transistor is in a recovery state, so as to perform first bias temperature instability recovery on the first transistor;
[0008] The second recovery unit is coupled to the second transistor and is adapted to apply a second recovery voltage signal to the well region of the second transistor when the second transistor is in a recovery state, so as to perform a second bias temperature instability recovery on the second transistor.
[0009] Optionally, the first transistor is an enhancement type PMOS transistor, and the first bias temperature instability recovery is negative bias temperature instability recovery;
[0010] The second transistor is an enhancement type NMOS transistor, and the second bias temperature instability recovery is a positive bias temperature instability recovery.
[0011] Optionally, the first recovery unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the first transistor when the first transistor is in an operating state.
[0012] Optionally, the first recovery unit includes a third transistor, and the third transistor is an enhancement type NMOS transistor;
[0013] The gate terminal of the third transistor is used to receive a ground voltage signal, the source terminal and the body terminal of the third transistor are used to receive the first recovery voltage signal when the first transistor is in a recovery state, and are used to receive the ground voltage signal when the first transistor is in a working state, and the drain terminal of the third transistor is coupled to the source terminal and the body terminal of the first transistor.
[0014] Optionally, the second recovery unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the second transistor when the second transistor is in an operating state.
[0015] Optionally, the second recovery unit includes a fourth transistor, and the fourth transistor is an enhancement type PMOS transistor;
[0016] The gate terminal of the fourth transistor is used to receive a power supply voltage signal, the source terminal and the body terminal of the fourth transistor are used to receive the second recovery voltage signal when the second transistor is in a recovery state, and are used to receive the power supply voltage signal when the second transistor is in an operating state, and the drain terminal of the fourth transistor is coupled to the source terminal and the body terminal of the second transistor.
[0017] Optionally, the second recovery unit includes a first diode;
[0018] The cathode of the first diode is coupled to the source and body of the second transistor, and the anode of the first diode is used to receive the second recovery voltage signal when the second transistor is in a recovery state, and to receive the power supply voltage signal when the second transistor is in an operating state.
[0019] Optionally, the inverter bias temperature instability recovery circuit further includes at least one of the following:
[0020] a first switch unit, adapted to cut off a leakage current path between a drain terminal of the first transistor and an output terminal of the inverter when the first transistor is in a recovery state;
[0021] The second switch unit is adapted to cut off a leakage current path between a drain terminal of the second transistor and an output terminal of the inverter when the second transistor is in a recovery state.
[0022] Optionally, the first switch unit includes a second diode;
[0023] A cathode of the second diode is coupled to the output terminal of the inverter, and an anode of the second diode is coupled to the drain terminal of the first transistor.
[0024] Optionally, the second switch unit includes a third diode;
[0025] A cathode of the third diode is coupled to the drain terminal of the second transistor, and an anode of the third diode is coupled to the output terminal of the inverter.
[0026] Optionally, the inverter bias temperature instability recovery circuit further includes at least one of the following:
[0027] a third switch unit, coupled to the first transistor, and adapted to apply a power supply voltage signal to a source terminal and a body terminal of the first transistor when the first transistor is in an operating state;
[0028] The fourth switch unit is coupled to the second transistor and is adapted to apply a ground voltage signal to a source terminal and a body terminal of the second transistor when the second transistor is in an operating state.
[0029] Optionally, the third switch unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the first transistor when the first transistor is in a recovery state.
[0030] Optionally, the third switch unit includes a fifth transistor, and the fifth transistor is an enhancement type PMOS transistor;
[0031] The gate terminal of the fifth transistor is used to receive the ground voltage signal, the source terminal and the body terminal of the fifth transistor are used to receive the power supply voltage signal, and the drain terminal of the fifth transistor is coupled to the source terminal and the body terminal of the first transistor.
[0032] Optionally, the fourth switch unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the second transistor when the second transistor is in a recovery state.
[0033] Optionally, the fourth switch unit includes a sixth transistor, and the sixth transistor is an enhancement type NMOS transistor;
[0034] The gate terminal of the sixth transistor is used to receive a power supply voltage signal, the source terminal and the body terminal of the sixth transistor are used to receive a ground voltage signal, and the drain terminal of the sixth transistor is coupled to the source terminal and the body terminal of the first transistor.
[0035] Optionally, the voltage of the first restored voltage signal is -5V to 0V, and the voltage of the second restored voltage signal is 0V to 5V.
[0036] Accordingly, an embodiment of the present invention further provides a method for recovering bias temperature instability of an inverter, wherein the inverter includes a first transistor and a second transistor, including:
[0037] When the first transistor is in a recovery state, applying a first recovery voltage signal to a well region of the first transistor to perform first bias temperature instability recovery on the first transistor;
[0038] When the second transistor is in a recovery state, a second recovery voltage signal is applied to a well region of the second transistor to perform a second bias temperature instability recovery on the second transistor.
[0039] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0040] In the bias temperature instability recovery circuit of the inverter in the embodiment of the present invention, a first recovery unit is used to apply a first recovery voltage signal to the well region of the first transistor when the first transistor is in a recovery state, so as to perform a first bias temperature instability recovery on the first transistor, and a second recovery unit is used to apply a second recovery voltage signal to the well region of the second transistor when the second transistor is in a recovery state, so as to perform a second bias temperature instability recovery on the second transistor. The first recovery voltage signal is applied to the well region of the first transistor, and the second recovery voltage signal is applied to the well region of the second transistor. Compared with the method of applying the recovery voltage signal to the gate terminal of the transistor for bias instability recovery, it can avoid the aggravation of the bias temperature instability of the other transistor when the bias temperature instability recovery is performed on either of the first transistor and the second transistor whose gate terminal is shared in the inverter, and the bias temperature instability recovery can be realized for the first transistor and the second transistor in the inverter at the same time, which is correspondingly helpful to improve the electrical performance of the inverter and slow down the aging speed of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1It is a schematic diagram of the frame structure and connection relationship of an inverter and an inverter bias temperature instability recovery circuit according to an embodiment of the present invention;
[0042] Figure 2 It is a schematic diagram of the circuit structure and connection relationship of an inverter and an inverter bias temperature instability recovery circuit according to an embodiment of the present invention;
[0043] Figure 3 It is a schematic diagram of the circuit structure and connection relationship of another embodiment of the inverter and the bias temperature instability recovery circuit of the inverter provided by the technical solution of the present invention;
[0044] Figure 4 It is a flow chart of an embodiment of a method for recovering from bias temperature instability of an inverter provided by the technical solution of the present invention. DETAILED DESCRIPTION
[0045] Currently, the bias temperature instability recovery circuit cannot simultaneously perform bias temperature instability recovery on two transistors sharing a gate terminal in an inverter.
[0046] In order to solve the above technical problems, an embodiment of the present invention provides a bias temperature instability recovery circuit of an inverter, including: a first recovery unit, coupled to the first transistor, when the first transistor is in a recovery state, applying a first recovery voltage signal to the well region of the first transistor to perform a first bias temperature instability recovery on the first transistor; a second recovery unit, coupled to the second transistor, when the second transistor is in a recovery state, applying a second recovery voltage signal to the well region of the second transistor to perform a second bias temperature instability recovery on the second transistor.
[0047] The bias temperature instability recovery circuit of the inverter in the embodiment of the present invention adopts a first recovery unit to apply a first recovery voltage signal to the well region of the first transistor when the first transistor is in a recovery state, so as to perform a first bias temperature instability recovery on the first transistor, and adopts a second recovery unit to apply a second recovery voltage signal to the well region of the second transistor when the second transistor is in a recovery state, so as to perform a second bias temperature instability recovery on the second transistor. The first recovery voltage signal is applied to the well region of the first transistor, and the second recovery voltage signal is applied to the well region of the second transistor, so as to avoid the aggravation of the bias temperature instability of the other transistor when the bias temperature instability recovery is performed on either of the first transistor and the second transistor shared by the gate terminal in the inverter, and the bias temperature instability recovery can be realized for the first transistor and the second transistor in the inverter at the same time, which is correspondingly helpful to improve the electrical performance of the inverter and slow down the aging speed of the inverter.
[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0049] First of all, it should be pointed out that in the embodiment of the present invention, the recovery state refers to the state of the transistor when the bias instability recovery is performed on the transistor; the working state refers to the state of the transistor when different voltage signals are applied to the gate and source terminals of the transistor, so that the transistor is turned on when the voltage difference between its gate and source terminals meets the threshold voltage, and the transistor is turned off when the voltage difference between its gate and source terminals does not meet the threshold voltage.
[0050] Figure 1 1 is a schematic diagram of the framework structure of an embodiment of a bias temperature instability recovery circuit for an inverter provided by the technical solution of the present invention. Figure 2 The invention is a schematic diagram of the circuit structure of an inverter and an inverter bias temperature instability recovery circuit according to an embodiment of the present invention.
[0051] Combined with reference Figure 1 and Figure 2 , a bias temperature instability recovery circuit of an inverter, the inverter 200 includes a first transistor M1 and a second transistor M2, the bias temperature instability recovery circuit of the inverter includes: a first recovery unit 110, coupled to the first transistor M1, suitable for applying a first recovery voltage signal Vpr to a well region of the first transistor M1 when the first transistor M1 is in a recovery state, so as to perform a first bias temperature instability recovery on the first transistor M1; a second recovery unit 120, coupled to the second transistor M2, suitable for applying a second recovery voltage signal Vnr to the well region of the second transistor M2 when the second transistor M2 is in a recovery state, so as to perform a second bias temperature instability recovery on the second transistor M2.
[0052] In this embodiment, the first recovery unit 110 has a control end, a first conduction end, a second conduction end, and a third conduction end, wherein the control end of the first recovery unit 110 is used to receive the ground voltage signal VSS, the first conduction end and the second conduction end of the first recovery unit 110 are used to receive the first recovery voltage signal Vpr when the first transistor M1 is in a recovery state, and the third conduction end of the first recovery unit 110 is coupled to the source end and the body end of the first transistor M1.
[0053] The first recovery unit 110 is used for applying a first recovery voltage signal Vpr to a well region of the first transistor M1 when the first transistor M1 is in a recovery state, so as to perform first bias temperature instability recovery on the first transistor M1.
[0054] In this embodiment, the first transistor M1 is an enhancement type PMOS transistor. Accordingly, the first recovery unit 110 is used to apply a first recovery voltage signal Vpr to the well region of the first transistor M1 when the first transistor M1 is in a recovery state, so as to recover the first transistor M1 from negative bias temperature instability.
[0055] In this embodiment, the first recovery unit 110 includes a third transistor M3. Specifically, the third transistor M3 is an enhancement type NMOS transistor. The gate terminal of the third transistor M3 is used to receive the ground voltage signal VSS, the source terminal and the body terminal of the third transistor M3 are used to receive the first recovery voltage signal Vpr when the first transistor M1 is in the recovery state, and the drain terminal of the third transistor M3 is coupled to the source terminal and the body terminal of the first transistor M1.
[0056] In this embodiment, the voltage difference between the ground voltage signal VSS and the first recovery voltage signal Vpr satisfies the threshold voltage of the third transistor M3, so that the third transistor M3 is turned on when the first transistor M1 is in the recovery state, thereby applying the first recovery voltage signal Vpr received by its source terminal and body terminal to the source terminal and body terminal of the first transistor M1. Since the body terminal of the first transistor M1 is electrically connected to the well region, the first recovery voltage signal Vpr is applied to the well region of the first transistor M1 through the body terminal of the first transistor M1, thereby recovering the first transistor M1 from negative bias temperature instability.
[0057] In this embodiment, the first transistor M1 is an enhancement type PMOS transistor. Accordingly, the voltage value of the first recovery voltage signal Vpr is less than or equal to 0V.
[0058] Specifically, the voltage value of the first recovery voltage signal Vpr is related to the device size of the first transistor M1. Specifically, when the device size of the first transistor M1 is larger, the absolute value of the voltage value of the first recovery voltage signal Vpr is relatively larger; when the device size of the first transistor M1 is smaller, the absolute value of the voltage value of the first recovery voltage signal Vpr is relatively smaller. As an example, the voltage value of the first recovery voltage signal Vpr is -5V to 0V.
[0059] In this embodiment, the first recovery unit 110 is further configured to cut off a leakage current path between a source terminal and a body terminal of the first transistor M1 when the first transistor M1 is in a state of being in a state of being in a state of being.
[0060] Specifically, the first recovery unit 110 includes a third transistor M3, and the third transistor M3 is an enhancement type NMOS transistor. Accordingly, the source terminal and the body terminal of the third transistor M3 are also used to receive the ground voltage signal VSS when the first transistor M1 is in the working state.
[0061] At this time, the signals received by the source and body of the third transistor M3 and the gate of the third transistor M3 are all the ground voltage signal VSS, so that the third transistor M3 is turned off when the first transistor M1 is in an operating state, so that the leakage current path of the source and body of the first transistor M1 is cut off, and then when the first transistor M1 is in an operating state, the source and body of the first transistor M1 are prevented from leaking current, which is beneficial to reducing power consumption and correspondingly helps to improve the electrical performance of the bias temperature instability recovery circuit of the inverter 200 in the implementation of the present invention.
[0062] In other embodiments, the first recovery unit can also be implemented by other structures with the same functions, and those skilled in the art can select them according to actual needs, and no limitation is made here.
[0063] In this embodiment, the second recovery unit 120 has a control end, a first conduction end, a second conduction end and a third conduction end, wherein the control end of the second recovery unit 120 is used to receive the power supply voltage signal VDD, the first conduction end and the second conduction end of the second recovery unit 120 are used to receive the second recovery voltage signal Vnr when the second transistor M2 is in a recovery state, and the third conduction end of the second recovery unit 120 is coupled to the source end and the body end of the second transistor M2.
[0064] The second recovery unit 120 is used for applying a second recovery voltage signal Vnr to a well region of the second transistor M2 when the second transistor M2 is in a recovery state, so as to perform a second bias temperature instability recovery on the second transistor M2.
[0065] In this embodiment, the second transistor M2 is an enhancement type PMOS transistor. Accordingly, the second recovery unit 120 is used to apply a second recovery voltage signal Vnr to the well region of the second transistor M2 when the second transistor M2 is in a recovery state, so as to recover the second transistor M2 from the forward bias temperature instability.
[0066] In this embodiment, the second recovery unit 120 includes a fourth transistor M4. Specifically, the fourth transistor M4 is an enhancement type PMOS transistor. The gate terminal of the fourth transistor M4 is used to receive the power supply voltage signal VDD, the source terminal and the body terminal of the fourth transistor M4 are used to receive the second recovery voltage signal Vnr when the second transistor M2 is in the recovery state, and the drain terminal of the fourth transistor M4 is coupled to the source terminal and the body terminal of the second transistor M2.
[0067] In this embodiment, the voltage difference between the power supply voltage signal VDD and the second recovery voltage signal Vnr satisfies the threshold voltage of the fourth transistor M4, so that the fourth transistor M4 is turned on when the second transistor M2 is in the recovery state, thereby applying the second recovery voltage signal Vnr received by its source terminal and body terminal to the source terminal and body terminal of the second transistor M2. Since the body terminal of the second transistor M2 is electrically connected to the well region, the second recovery voltage signal Vnr is applied to the well region of the second transistor M2 through the body terminal of the second transistor M2, thereby recovering the second transistor M2 from negative bias temperature instability.
[0068] In this embodiment, the second transistor M2 is an enhancement type NMOS transistor. Accordingly, the voltage value of the second recovery voltage signal Vnr is greater than or equal to 0V.
[0069] Specifically, the voltage value of the second recovery voltage signal Vnr is related to the device size of the second transistor M2. Specifically, when the device size of the second transistor M2 is larger, the voltage value of the second recovery voltage signal Vnr is larger; when the device size of the second transistor M2 is smaller, the voltage value of the second recovery voltage signal Vnr is smaller. As an example, the voltage value of the second recovery voltage signal Vnr is 0V to 5V.
[0070] In this embodiment, the second recovery unit 120 is further configured to cut off a leakage current path between a source terminal and a body terminal of the second transistor M2 when the second transistor M2 is in a working state.
[0071] The second recovery unit 120 is further used to cut off the leakage current path of the source and body of the second transistor M2 when the second transistor M2 is in the working state, thereby preventing leakage current from appearing at the source and body of the second transistor M2 when the second transistor M2 is in the working state, which is beneficial to reducing power consumption and correspondingly helps to improve the electrical performance of the bias temperature instability recovery circuit of the inverter 200 in the implementation of the present invention.
[0072] In this embodiment, the second recovery unit 120 includes a fourth transistor M4. Specifically, the fourth transistor M4 is an enhancement type PMOS transistor. Accordingly, the source terminal and the body terminal of the fourth transistor M4 are also used to receive the power supply voltage signal VDD when the second transistor M2 is in the working state.
[0073] At this time, the signals received by the source and body of the fourth transistor M4 and the gate of the fourth transistor M4 are all the power supply voltage signal VDD, so that the fourth transistor M4 is turned off when the second transistor M2 is in an operating state, so that the leakage current path of the source and body of the second transistor M2 is cut off, and then when the second transistor M2 is in an operating state, the source and body of the second transistor M2 are prevented from leaking current, which is beneficial to reducing power consumption and correspondingly helps to improve the electrical performance of the bias temperature instability recovery circuit of the inverter 200 in the implementation of the present invention.
[0074] Please continue to see Figure 1 and Figure 2 In this embodiment, the bias temperature instability recovery circuit of the inverter 200 further includes: a first switch unit 130, adapted to cut off a leakage current path between the drain terminal of the first transistor M1 and the output terminal OUT of the inverter 200 when the first transistor M1 is in a recovery state; and a second switch unit 140, adapted to cut off a leakage current path between the drain terminal of the second transistor M2 and the output terminal OUT of the inverter 200 when the second transistor M2 is in a recovery state.
[0075] In this embodiment, the first switch unit 130 has a first conduction end and a second conduction end, wherein the first conduction end of the first switch unit 130 is coupled to the output end OUT of the inverter 200, and the second conduction end of the first switch unit 130 is coupled to the drain end of the first transistor M1. The first switch unit 130 is used to cut off the leakage current path between the drain end of the first transistor M1 and the output end OUT of the inverter 200 when the first transistor M1 is in the recovery state, so as to prevent leakage current from occurring between the drain end of the first transistor M1 and the output end OUT of the inverter 200 when the first transistor M1 is in the recovery state, which is beneficial to reducing power consumption and correspondingly helps to improve the electrical performance of the bias temperature instability recovery circuit of the inverter 200 in the embodiment of the present invention.
[0076] In this embodiment, the first switch unit 130 includes a second diode D2 , wherein a cathode of the second diode D2 is coupled to the output terminal OUT of the inverter 200 , and an anode of the second diode D2 is coupled to the drain terminal of the first transistor M1 .
[0077] In this embodiment, when the first transistor M1 is in the recovery state, the voltage difference between the positive electrode and the negative electrode of the second diode D2 is a negative value, so that the second diode D2 is cut off, thereby cutting off the leakage current path between the first transistor M1 and the output terminal OUT of the inverter 200, thereby preventing leakage current from occurring between the drain terminal of the first transistor M1 and the output terminal OUT of the inverter 200 when the first transistor M1 is in the recovery state.
[0078] In other embodiments, the first switch unit can also be implemented by other structures with the same functions, and those skilled in the art can select them according to actual needs, and no limitation is made here.
[0079] In this embodiment, the second switch unit 140 has a first conduction end and a second conduction end, wherein the first conduction end of the second switch unit 140 is coupled to the drain end of the second transistor M2, and the second conduction end of the second switch unit 140 is coupled to the output end OUT of the inverter 200. The second switch unit 140 is used to cut off the leakage current path between the drain end of the second transistor M2 and the output end OUT of the inverter 200 when the second transistor M2 is in the recovery state, so as to prevent leakage current from occurring between the drain end of the second transistor M2 and the output end OUT of the inverter 200 when the second transistor M2 is in the recovery state, which is beneficial to reducing power consumption and improving the electrical performance of the bias temperature instability recovery circuit of the inverter 200 in the embodiment of the present invention.
[0080] In this embodiment, the second switch unit 140 includes a third diode D3 , wherein a cathode of the third diode D3 is coupled to the drain terminal of the second transistor M2 , and an anode of the third diode D3 is coupled to the output terminal OUT of the inverter 200 .
[0081] In this embodiment, when the second transistor M2 is in the recovery state, the voltage difference between the positive electrode and the negative electrode of the third diode D3 is negative, so that the third diode D3 is cut off, thereby cutting off the leakage current path between the second transistor M2 and the output terminal OUT of the inverter 200, thereby preventing leakage current from occurring between the drain terminal of the second transistor M2 and the output terminal OUT of the inverter 200 when the second transistor M2 is in the recovery state, which is beneficial to reducing power consumption and correspondingly helps to improve the electrical performance of the bias temperature instability recovery circuit of the inverter 200 implemented in the present invention.
[0082] In other embodiments, the second switch unit can also be implemented by other structures with the same functions, and those skilled in the art can select them according to actual needs, and no limitation is made here.
[0083] In other embodiments, the bias temperature instability recovery circuit of the inverter 200 may also include only the first switch unit or the second switch unit. Those skilled in the art may select one according to actual needs, and no limitation is made here.
[0084] In this embodiment, the bias temperature instability recovery circuit of the inverter 200 also includes: a third switch unit 150, coupled to the first transistor M1, suitable for applying the power supply voltage signal VDD to the source terminal and the body terminal of the first transistor M1 when the first transistor M1 is in a working state; a fourth switch unit 160, coupled to the second transistor M2, suitable for applying the ground voltage signal to the source terminal and the body terminal of the second transistor M2 when the second transistor M2 is in a working state.
[0085] In this embodiment, the third switch unit 150 has a control end, a first conduction end, a second conduction end and a third conduction end, wherein the control end of the third switch unit 150 is used to receive the ground voltage signal VSS, the first conduction end and the second conduction end of the third switch unit 150 are used to receive the power supply voltage signal VDD, and the third conduction end of the third switch unit 150 is coupled to the source end and the body end of the first transistor M1.
[0086] In this embodiment, the third switch unit 150 is further configured to cut off a leakage current path between a source terminal and a body terminal of the first transistor M1 when the first transistor M1 is in a recovery state.
[0087] In this embodiment, the third switch unit 130 includes a fifth transistor M5. Specifically, the fifth transistor M5 is an enhancement type PMOS transistor. The gate terminal of the fifth transistor M5 is used to receive the ground voltage signal VSS when the first transistor M1 is in the working state, the source terminal and the body terminal of the fifth transistor M5 are used to receive the power supply voltage signal VDD when the first transistor M1 is in the working state, and the drain terminal of the fifth transistor M5 is coupled to the source terminal and the body terminal of the first transistor M1.
[0088] At this time, the voltage difference between the ground voltage signal VSS received by the gate terminal of the fifth transistor M5 and the power supply voltage signal VDD received by the source terminal and the body terminal of the fifth transistor M5 meets the threshold voltage of the fifth transistor M5, so that the fifth transistor M5 is turned on, thereby applying the power supply voltage signal VDD to the source terminal and the body terminal of the first transistor M1.
[0089] At the same time, the gate terminal of the first transistor M1 serves as the input terminal IN of the inverter 200 or is coupled to the input terminal IN of the inverter 200, and the voltage difference between the voltage of the input signal received by it and the power supply voltage signal VDD applied to the source terminal and the body terminal of the first transistor M1 satisfies the threshold voltage of the first transistor M1, so that the first transistor M1 is turned on, so that the output terminal OUT of the inverter 200 is pulled up to the power supply voltage signal VDD by the first transistor M1.
[0090] When the first transistor M1 is in the recovery state, the power supply voltage signal VDD received by the source and body terminals of the fifth transistor M5 is the same as the ground voltage signal VSS received by the gate terminal of the fifth transistor M5, so that the voltage difference between the source and gate terminals of the fifth transistor M5 does not meet the threshold voltage of the fifth transistor M5, so that the fifth transistor M5 is turned off, thereby cutting off the leakage current path of the source and body terminals of the first transistor M1.
[0091] In this embodiment, the fourth switch unit 160 has a control end, a first conduction end, a second conduction end and a third conduction end, wherein the control end of the fourth switch unit 160 is used to receive the power supply voltage signal VDD when the second transistor M2 is in an operating state, the first conduction end and the second conduction end of the fourth switch unit 160 are used to receive the ground voltage signal VSS when the second transistor M2 is in an operating state, and the third conduction end of the fourth switch unit 160 is coupled to the source end and the body end of the second transistor M2.
[0092] In this embodiment, the fourth switch unit 160 is further configured to cut off a leakage current path between the source terminal and the body terminal of the second transistor M2 when the second transistor M2 is in the recovery state.
[0093] In this embodiment, the fourth switch unit 160 includes a sixth transistor M6. Specifically, the sixth transistor M6 is an enhancement type NMOS transistor. The gate terminal of the sixth transistor M6 is used to receive the power supply voltage signal VDD when the second transistor M2 is in the working state, the source terminal and the body terminal of the sixth transistor M6 are used to receive the ground voltage signal VSS when the second transistor M2 is in the working state, and the drain terminal of the sixth transistor M6 is coupled to the source terminal and the body terminal of the second transistor M2.
[0094] At this time, when the second transistor M2 is in the working state, the voltage difference between the power supply voltage signal received by the gate terminal of the sixth transistor M6 and the ground voltage signal VSS received by the source terminal and the gate terminal of the sixth transistor M6 satisfies the threshold voltage of the sixth transistor M6, so that the sixth transistor M6 is turned on, thereby applying the ground voltage signal VSS received by the source terminal and the body terminal of the sixth transistor M6 to the source terminal and the body terminal of the second transistor M2.
[0095] At the same time, the gate terminal of the second transistor M2 serves as the input terminal IN of the inverter 200 or is coupled to the input terminal IN of the inverter 200. The voltage difference between the voltage of the input signal received by the gate terminal and the ground voltage signal VSS applied to the source terminal and the body terminal of the second transistor M2 satisfies the threshold voltage of the second transistor M2, so that the second transistor M2 is turned on, so that the output terminal OUT of the inverter 200 is pulled down to the voltage of the ground voltage signal VSS by the second transistor M2.
[0096] When the second transistor M2 is in the recovery state, the ground voltage signal VSS received by the source and body terminals of the sixth transistor M6 is the same as the power supply voltage signal VDD received by the gate terminal of the sixth transistor M6, so that the voltage difference between the source and gate terminals of the sixth transistor M6 does not meet the threshold voltage of the sixth transistor M6, so that the sixth transistor M6 is turned off, thereby cutting off the leakage current path of the source and body terminals of the second transistor M2.
[0097] It should be pointed out that the bias temperature instability recovery circuit of the inverter 200 in the embodiment of the present invention can simultaneously realize the bias temperature instability recovery of the first transistor M1 and the second transistor M2 in the inverter 200, and can also realize the bias temperature instability recovery of the first transistor M1 and the second transistor M2 in the inverter 200 separately. Those skilled in the art can set it according to actual needs and no limitation is made here.
[0098] Figure 3 A schematic diagram showing the circuit structure and connection relationship of another embodiment of an inverter and a bias temperature instability recovery circuit of the inverter 200 provided by the technical solution of the present invention is shown.
[0099] See also Figure 3 The similarities between this embodiment and the above embodiment are not repeated here. The difference between this embodiment and the above embodiment is that the second recovery unit 120 includes a first diode D1. The cathode of the first diode D1 is coupled to the source terminal and the body terminal of the second transistor M2, and the anode of the first diode D1 is used to receive the second recovery voltage signal Vnr.
[0100] Correspondingly, an embodiment of the present invention further provides a method for recovering from bias temperature instability of an inverter.
[0101] Figure 4 FIG. 1 is a flow chart showing a method for recovering from bias temperature instability of an inverter according to an embodiment of the present invention. Figure 4 A method for recovering bias temperature instability of an inverter in an embodiment of the present invention may specifically include the following steps:
[0102] Step S410: When the first transistor is in a recovery state, applying a first recovery voltage signal to a well region of the first transistor to perform first bias temperature instability recovery on the first transistor;
[0103] Step S420: When the second transistor is in a recovery state, applying a second recovery voltage signal to a well region of the second transistor to perform a second bias temperature instability recovery on the second transistor.
[0104] Regarding the method for recovering the bias temperature instability of the inverter, please refer to the aforementioned description of the circuit for recovering the bias temperature instability of the inverter, which will not be repeated here.
[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A bias temperature instability recovery circuit for an inverter, the inverter comprising a first transistor and a second transistor, characterized in that: include: a first recovery unit, coupled to the first transistor, adapted to apply a first recovery voltage signal to a well region of the first transistor when the first transistor is in a recovery state, so as to perform first bias temperature instability recovery on the first transistor; The second recovery unit is coupled to the second transistor and is adapted to apply a second recovery voltage signal to the well region of the second transistor when the second transistor is in a recovery state, so as to perform a second bias temperature instability recovery on the second transistor.
2. The inverter bias temperature instability recovery circuit as claimed in claim 1, characterized in that: The first transistor is an enhancement type PMOS transistor, and the first bias temperature instability recovery is negative bias temperature instability recovery; The second transistor is an enhancement type NMOS transistor, and the second bias temperature instability recovery is a positive bias temperature instability recovery.
3. The inverter bias temperature instability recovery circuit as claimed in claim 2, characterized in that: The first recovery unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the first transistor when the first transistor is in an operating state.
4. The inverter bias temperature instability recovery circuit as claimed in claim 3, characterized in that: The first recovery unit includes a third transistor, and the third transistor is an enhancement type NMOS transistor; The gate terminal of the third transistor is used to receive a ground voltage signal, the source terminal and the body terminal of the third transistor are used to receive the first recovery voltage signal when the first transistor is in a recovery state, and are used to receive the ground voltage signal when the first transistor is in a working state, and the drain terminal of the third transistor is coupled to the source terminal and the body terminal of the first transistor.
5. The inverter bias temperature instability recovery circuit as claimed in claim 2, characterized in that: The second recovery unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the second transistor when the second transistor is in an operating state.
6. The inverter bias temperature instability recovery circuit as claimed in claim 5, characterized in that: The second recovery unit includes a fourth transistor, and the fourth transistor is an enhancement type PMOS transistor; The gate terminal of the fourth transistor is used to receive a power supply voltage signal, the source terminal and the body terminal of the fourth transistor are used to receive the second recovery voltage signal when the second transistor is in a recovery state, and are used to receive the power supply voltage signal when the second transistor is in an operating state, and the drain terminal of the fourth transistor is coupled to the source terminal and the body terminal of the second transistor.
7. The inverter bias temperature instability recovery circuit as claimed in claim 5, characterized in that: The second recovery unit includes a first diode; The cathode of the first diode is coupled to the source and body of the second transistor, and the anode of the first diode is used to receive the second recovery voltage signal when the second transistor is in a recovery state, and to receive the power supply voltage signal when the second transistor is in an operating state.
8. The inverter bias temperature instability recovery circuit as claimed in claim 1, characterized in that: Also includes at least one of the following: a first switch unit, adapted to cut off a leakage current path between a drain terminal of the first transistor and an output terminal of the inverter when the first transistor is in a recovery state; The second switch unit is adapted to cut off a leakage current path between a drain terminal of the second transistor and an output terminal of the inverter when the second transistor is in a recovery state.
9. The inverter bias temperature instability recovery circuit as claimed in claim 8, characterized in that: The first switch unit includes a second diode; A cathode of the second diode is coupled to the output terminal of the inverter, and an anode of the second diode is coupled to the drain terminal of the first transistor.
10. The inverter bias temperature instability recovery circuit as claimed in claim 8, characterized in that: The second switch unit includes a third diode; A cathode of the third diode is coupled to the drain terminal of the second transistor, and an anode of the third diode is coupled to the output terminal of the inverter.
11. The inverter bias temperature instability recovery circuit according to any one of claims 2 to 10, characterized in that: Also includes at least one of the following: a third switch unit, coupled to the first transistor, and adapted to apply a power supply voltage signal to a source terminal and a body terminal of the first transistor when the first transistor is in an operating state; The fourth switch unit is coupled to the second transistor and is adapted to apply a ground voltage signal to a source terminal and a body terminal of the second transistor when the second transistor is in an operating state.
12. The inverter bias temperature instability recovery circuit according to claim 11, characterized in that: The third switch unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the first transistor when the first transistor is in a recovery state.
13. The inverter bias temperature instability recovery circuit according to claim 12, characterized in that: The third switch unit includes a fifth transistor, and the fifth transistor is an enhancement type PMOS transistor; The gate terminal of the fifth transistor is used to receive the ground voltage signal, the source terminal and the body terminal of the fifth transistor are used to receive the power supply voltage signal, and the drain terminal of the fifth transistor is coupled to the source terminal and the body terminal of the first transistor.
14. The inverter bias temperature instability recovery circuit according to claim 13, characterized in that: The fourth switch unit is further adapted to cut off a leakage current path between a source terminal and a body terminal of the second transistor when the second transistor is in a recovery state.
15. The inverter bias temperature instability recovery circuit as claimed in claim 14, characterized in that: The fourth switch unit includes a sixth transistor, and the sixth transistor is an enhancement type NMOS transistor; The gate terminal of the sixth transistor is used to receive a power supply voltage signal, the source terminal and the body terminal of the sixth transistor are used to receive a ground voltage signal, and the drain terminal of the sixth transistor is coupled to the source terminal and the body terminal of the first transistor.
16. The inverter bias temperature instability recovery circuit as claimed in claim 1, characterized in that: The voltage of the first restoration voltage signal is between -5V and 0V, and the voltage of the second restoration voltage signal is between 0V and 5V.
17. A method for recovering bias temperature instability of an inverter, the inverter comprising a first transistor and a second transistor, characterized in that: include: When the first transistor is in a recovery state, applying a first recovery voltage signal to a well region of the first transistor to perform first bias temperature instability recovery on the first transistor; When the second transistor is in a recovery state, a second recovery voltage signal is applied to a well region of the second transistor to perform a second bias temperature instability recovery on the second transistor.