Low-delay capacitance isolation driving circuit
By designing a low-latency capacitive isolation driving circuit, using fewer logic circuits and specific circuit structures, the delay and signal distortion problems of traditional capacitive isolation driving circuits when transmitting logic high-level signals are solved, and low-latency and high-quality signal transmission is achieved.
Patent Information
- Application Number
- CN202411865256.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-04-25
AI Technical Summary
Traditional capacitive isolation driving circuits have delays and signal distortions when transmitting logic high-level signals, resulting in delays and distortions received on the low-voltage side.
By using fewer logic circuits, a low-latency capacitive isolation drive circuit is designed, including an inverter, a delay buffer, an AND gate, an NAND gate and an enhanced PMOS tube, to achieve width compensation of high-frequency carrier signals and reduce signal delay and distortion.
It realizes low-latency signal transmission, reduces signal distortion, and ensures high-quality signal transmission.
Smart Images
Figure CN119892057A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of analog integrated circuits, and in particular relates to a low-delay capacitor isolation drive circuit. Background Art
[0002] In the application of isolation devices, it is necessary to modulate the input signal onto a high-frequency carrier on the high-voltage side. The high-frequency carrier carries the signal across the isolation band to the low-voltage side, and then demodulates the low-voltage side to restore the original signal. Capacitor isolation drive circuits often use on-off keying (OOK) to modulate digital signals. When the input digital signal is at a logic level of "1", it is modulated into a high-frequency signal and the carrier is transmitted. When the input digital signal is at a logic level of "0", the signal is not modulated and the carrier is not transmitted. At the receiving end on the low-voltage side, it can be determined whether the received logic signal is high or low by whether the carrier is received. Through OOK modulation, binary signals can be transmitted with a simple circuit and low power consumption.
[0003] Common capacitor isolation drive circuit structures such as Figure 1 As shown in the figure, it consists of an oscillator module (Oscillator), a NAND gate (NAND), and a class AB amplifier. When the input signal is at a logic level "1", the oscillator is turned on to generate a high-frequency carrier, and the high-frequency carrier signal is coupled with the logic signal "1" through the NAND gate, and the carrier is output through the amplifier; when the input signal is at a logic level "0", the oscillator is not started, and the NAND gate outputs a high level, so that the output is continuously at a low level and no carrier is output. The timing diagram of the traditional capacitor isolation drive circuit is shown in the figure. Figure 2 As shown, this method restarts the oscillator each time a logic high level is transmitted, and there is a certain delay ΔT from the start-up to the stabilization of the oscillator. During this startup time, the drive circuit does not output a carrier, which will cause a delay in the logic high level signal received by the low-voltage side; in addition, within a certain high-level gate width, the transmitted high-level signal will also be smaller than the actual high-level signal width, causing signal distortion.
[0004] Based on the above problems, the present invention proposes a novel circuit structure with a simple structure to realize a low-delay capacitor isolation driving circuit. Summary of the invention
[0005] The purpose of the present invention is to propose a low-delay capacitor isolation driving circuit to solve the problems existing in the above-mentioned traditional circuits.
[0006] The technical solution of the present invention is a low-delay capacitor isolation driving circuit, characterized in that less logic circuits can be used to compensate for the capacitor isolation delay time and reduce the delay and distortion of the transmission signal. It includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a delay buffer, an AND gate, an OR gate, a first NAND gate, a second NAND gate, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, and a first NMOS tube; wherein the source end of the first PMOS tube is connected to an external power supply, and its drain end is connected to the drain end of the first NMOS tube as the output end of the driving circuit, and the source end of the first NMOS tube is grounded; the output of the first NAND gate is connected to the gate of the first PMOS tube, one input end of the first NAND gate is connected to the output of the OR gate, and the other input end of the first NAND gate is connected to the external data input; the output of the second NAND gate is connected to the gate of the first NMOS tube, one input end of the second NAND gate is connected to the output of the OR gate, and the other input end of the second NAND gate is connected to the external data input; one input end of the OR gate is connected to the output of the fourth inverter, and the other input end of the OR gate is connected to the AND gate. The output of the AND gate; one input end of the AND gate is connected to the output of the delay buffer, and the other input end of the AND gate is connected to the external data input; the input of the delay buffer is connected to the output of the first inverter, and the input of the first inverter is connected to the external data input; the input of the fourth inverter is connected to the output of the third inverter, the power supply end of the fourth inverter is connected to the drain end of the fourth PMOS tube, and the source end of the fourth PMOS tube is connected to the external power supply; the input of the third inverter is connected to the output of the second inverter, the power supply end of the third inverter is connected to the drain end of the third PMOS tube, and the source end of the third PMOS tube is connected to the external power supply; the input of the second inverter is connected to the output of the fourth inverter, the power supply end of the second inverter is connected to the drain end of the second PMOS tube, and the source end of the second PMOS tube is connected to the external power supply; the gate of the second PMOS tube, the gate of the third PMOS tube, and the gate of the fourth PMOS tube are connected to the output of the fifth inverter, and the input of the fifth inverter is connected to the external data input.
[0007] According to the present invention, the capacitive isolation driving circuit can use fewer gate circuits, achieve low-delay signal transmission, and reduce signal distortion. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 It is a structural schematic diagram of a traditional capacitive isolation drive circuit;
[0009] Figure 2 This is the timing diagram of the traditional capacitor isolation drive circuit;
[0010] Figure 3 It is a structural schematic diagram of a low-delay capacitor isolation driving circuit of the present invention;
[0011] Figure 4 It is a timing diagram of the low-delay capacitor isolation driving circuit of the present invention;
[0012] Figure 5 This is a transient simulation waveform diagram of the circuit of the present invention. DETAILED DESCRIPTION
[0013] The specific implementation of the present invention is described below in conjunction with the accompanying drawings:
[0014] like Figure 3 As shown, the specific circuit structure of the present invention is composed of inverters INV, INV1, INV2, INV3, INV4, a delay buffer delay, an AND gate AND, an OR gate OR, NAND gates NAND1, NAND2, enhanced PMOS tubes M1, M3, M4, M5, and an enhanced PMOS tube M2. Among them, the source terminal of M1 is connected to the external power supply, the drain terminal of M1 is connected to the drain terminal of M2, and the source terminal of M2 is grounded; the output of NAND1 is connected to the gate of M1, and the input of NAND1 is connected to the output and data input of OR; the output of NAND2 is connected to the gate of M2, and the input of NAND2 is connected to the output and data input of OR, and the input of OR is connected to the output of INV3 and the output of AND; the input of AND is connected to the output and data input of delay, the input of delay is connected to the output of INV, and the input of INV is connected to the data input; the input of INV3 is connected to the output of INV2, the power terminal of M5 is connected to the drain terminal, and the source terminal of M5 is connected to the external power supply; the input of INV2 is connected to the output of INV1, the power terminal of M4 is connected to the drain terminal, and the source terminal of M4 is connected to the external power supply; the input of INV1 is connected to the output of INV3, the power terminal of M3 is connected to the drain terminal, and the source terminal of M3 is connected to the external power supply; the gates of M3, M4, and M5 are connected to the output of INV4, and the input of INV4 is connected to the data input.
[0015] The working principle of the present invention is:
[0016] Enhanced PMOS tubes M3, M4, M5, inverters INV1, INV2, INV3, INV4 form a ring oscillator that can be started and closed by input data; inverter INV, delay buffer delay, and AND gate AND form a monostable circuit; NAND gates NAND1, NAND2, and OR gate OR form a carrier control circuit; enhanced PMOS tube M1 and enhanced NMOS tube M2 form a class AB amplifier. The output of the ring oscillator is coupled with the output of the monostable circuit through OR, and the output of OR is coupled with the input data signal Vin through NAND1 and NAND2 for gate width control. The outputs of NAND1 and NAND2 are connected to the gate input of the class AB amplifier to generate the output signal Vout.
[0017] like Figure 4As shown in the figure, when the input signal Vin is at logic level "1", INV4 inverts the high level to low level, thereby turning on M3, M4, and M5, so that INV1, INV2, and INV3 are powered on. At this time, the ring oscillator composed of the three-stage inverter will start to oscillate, and after a start-up time of ΔT, a high-frequency carrier signal will be formed; when the logic level "1" is input to the monostable circuit, one input end of AND changes from low level to high level almost immediately, while the other input end, because the logic "1" is inverted to low level by INV and is transmitted to AND after a delay, its output is set to logic "0", and it will remain at a high level before that, so AND The output will be set to logic "1" immediately when the input high level comes, and will become logic "0" after the three-level gate delay of INV, delay, and AND, thereby generating a narrow pulse with a three-level gate delay width; when the narrow pulse output by the monostable circuit is coupled with the output signal of the oscillator through OR, the narrow pulse will appear during the startup of the oscillator and end after the oscillator starts and stabilizes, thereby compensating the width of the high-frequency carrier signal that originally lost the ΔT width; the compensated high-frequency carrier signal is input to NAND1 and NAND2 for gate width control, and only within the gate width range of Vin being high level will it be transmitted to the subsequent class AB amplifier, and finally the compensated high-frequency carrier is output, thereby reducing the delay of the output signal and reducing signal distortion. When the input signal Vin is at logic level "0", INV4 inverts the low level to a high level, thereby turning off M3, M4, and M5, so that the ring oscillator does not oscillate and does not generate a high-frequency carrier. At the same time, the logic level "0" is input to the monostable circuit, and one end of AND will almost immediately input a low level, so that its output remains at logic "0" and no narrow pulse is generated. NAND1 and NAND2 also input a high level to the class AB amplifier because of the input logic "0", so that the output Vout always remains at a low level and does not transmit a high-frequency carrier.
[0018] The transient simulation results of the input signal VIN after passing through the traditional capacitor isolation driving circuit and the low-latency capacitor isolation driving circuit of the present invention are as follows: Figure 5 As shown. Wherein, VOUT_OLD is the output signal of the traditional capacitor isolation driving circuit, and VOUT is the output signal of the low-delay capacitor isolation driving circuit of the present invention. Through simulation output comparison, the present invention can insert a narrow pulse signal before the high-frequency carrier signal stabilizes, thereby realizing compensation for the high-frequency carrier signal, and the signal delay is reduced by Δt, solving the problem of signal quality degradation caused by oscillator delay in the traditional capacitor isolation driving circuit.
[0019] It can be seen from the working principle description and simulation waveform that the present invention successfully implements a low-latency capacitor isolation drive circuit. Compared with the traditional capacitor isolation drive circuit, it can effectively reduce the delay and distortion of the signal while performing the OOK modulation function normally, ensuring high-quality signal transmission.
Claims
1. A low-delay capacitor isolation drive circuit, characterized in that: The invention comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a delay buffer, an AND gate, an OR gate, a first NAND gate, a second NAND gate, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first NMOS tube; wherein the source end of the first PMOS tube is connected to an external power supply, the drain end thereof is connected to the drain end of the first NMOS tube as the output end of the driving circuit, and the source end of the first NMOS tube is grounded; the output of the first NAND gate is connected to the gate of the first PMOS tube, one input end of the first NAND gate is connected to the output of the OR gate, and the other input end of the first NAND gate is connected to the external data input; the output of the second NAND gate is connected to the gate of the first NMOS tube, one input end of the second NAND gate is connected to the output of the OR gate, and the other input end of the second NAND gate is connected to the external data input; one input end of the OR gate is connected to the output of the fourth inverter, and the other input end of the OR gate is connected to the AND gate. The output of the AND gate; one input end of the AND gate is connected to the output of the delay buffer, and the other input end of the AND gate is connected to the external data input; the input of the delay buffer is connected to the output of the first inverter, and the input of the first inverter is connected to the external data input; the input of the fourth inverter is connected to the output of the third inverter, the power supply end of the fourth inverter is connected to the drain end of the fourth PMOS tube, and the source end of the fourth PMOS tube is connected to the external power supply; the input of the third inverter is connected to the output of the second inverter, the power supply end of the third inverter is connected to the drain end of the third PMOS tube, and the source end of the third PMOS tube is connected to the external power supply; the input of the second inverter is connected to the output of the fourth inverter, the power supply end of the second inverter is connected to the drain end of the second PMOS tube, and the source end of the second PMOS tube is connected to the external power supply; the gate of the second PMOS tube, the gate of the third PMOS tube, and the gate of the fourth PMOS tube are connected to the output of the fifth inverter, and the input of the fifth inverter is connected to the external data input.