Level shift chip and circuit thereof
By adding and adjusting the connection mode of the field effect tube in the level displacement chip circuit, a cross-coupled adjustment module is formed, which solves the problems of high dynamic power loss and low level switching rate in the prior art, and achieves lower power loss and faster level switching rate.
Patent Information
- Application Number
- CN202411971823.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
The existing level shift chip circuit has high dynamic power consumption and low level slewing rate, which cannot meet the needs of level shift chips.
By adding the fifth field effect tube, the sixth field effect tube, the seventh field effect tube, the eighth field effect tube, the ninth field effect tube and the tenth field effect tube are defined, so that they act as a cross-coupling adjustment module to adjust the strength of the pull-up network and reduce the charge and discharge time of the nodes inside the joint.
It reduces the dynamic power consumption of the level shift chip circuit and improves its level slewing rate, meeting the needs of the level shift chip.
Smart Images
Figure CN119892059A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chips, and in particular to a level shift chip and a circuit thereof. Background Art
[0002] The main function of the level shift chip circuit is to realize level conversion between different voltage domains. In electronic systems, different modules or chips need to work at different voltages, so level conversion is required to ensure the correct transmission of signals.
[0003] like Figure 1 As shown, the level shift chip circuit in the prior art mainly includes four field effect transistors, namely M1, M2, M3 and M4, wherein the source of M1 and M2 is used to connect the working voltage, the gate of M3 is used to connect the first input terminal IN, and the gate of M4 is used to connect the second input terminal INB.
[0004] Assume that at the beginning, connection point A in the circuit is at a high level and connection point B is at a low level, then M1 is turned on and M2 is turned off. When the input signal changes from low to high, M3 is turned on and M1 is turned off. At this time, the left branch of the circuit will be turned on. The current in the left branch is determined by the competition between M3 and M1. If M3 can pull the current down and reduce the voltage at connection point A to below VDDH-Vthp, M2 will be turned on at this time. When the potential of connection point B gradually rises to exceed VDDH-Vthp, M1 will be turned off. Then the potential of connection point A will continue to decrease until it reaches GND, and the potential of connection point B will eventually reach the power supply voltage, thus completing the level conversion. The same is true for the other side.
[0005] The falling delay of the A connection point consists of the following three stages: in the initial state, the voltage of the A connection point is the power supply voltage, the voltage of the B connection point is the ground, M1 is turned on, and M2 is turned off. As the input signal increases, M3 changes from the closed state to the open state, and M4 changes from the open state to the closed state.
[0006] In the first stage, the voltage level of connection point B remains unchanged, and parasitic capacitance exists at connection point A and begins to discharge outward, that is, the voltage of connection point A decreases from VDDH to VDDH-Vthp. The duration of this process segment is as follows:
[0007]
[0008] in,
[0009]
[0010] In the second stage, the voltage at the A connection point decreases to below VDDH-Vthp, M2 is turned on, and the voltage at the B connection point rises to VDDH-Vthp. During this period, the voltage at the A connection point drops to VA. During this process, the voltage at the B connection point is:
[0011]
[0012] The charging current Icharge2(t) at the B connection point satisfies the following two equations, which are the linear region and saturation region current expressions respectively:
[0013]
[0014]
[0015] The voltage at the A connection point is as follows:
[0016]
[0017] The current flowing through M1 is as follows:
[0018]
[0019] Therefore, the fall delay time of the second stage satisfies the following formula:
[0020]
[0021] In the third stage, the voltage at the B connection point rises to VDDH, M1 is turned off, and the voltage at the A connection point continues to drop from VA to the ground level. In this process, the duration is as follows:
[0022]
[0023] The total falling delay time is the sum of the above three times, that is, tf=tf1+tf2+tf3.
[0024] The voltage rise delay time of the A connection point is composed of two parts. That is, when the input changes from high to low, in the first stage, M3 is turned off and M4 is turned on. At this time, M1 is still in the off state and M2 is still in the on state. The parasitic capacitance of the B connection point is discharged, and the discharge current is as follows:
[0025] I dischage2 =I4-I2;
[0026] At this time, the voltage at A can still remain unchanged. The delay time of this process is:
[0027]
[0028] in,
[0029]
[0030] In the second stage, when the voltage at the B connection point drops below VDDH-Vthp, M1 turns on and starts charging the parasitic capacitance at the A connection point. The charging current is as follows:
[0031] I discharge2 =I1;
[0032] The delay time of this process is:
[0033]
[0034] in,
[0035]
[0036] Therefore, the total rise delay is tr=tr1+tr2.
[0037] In summary, it can be seen that the level shift chip circuit in the prior art not only has high dynamic power consumption, but also has a low level conversion rate, which can no longer meet the requirements of the level shift chip. Summary of the invention
[0038] The present invention provides a new level shift chip and a circuit thereof, aiming to solve the problem that the level shift chip circuit in the prior art has not only high dynamic power consumption but also low level conversion rate.
[0039] The present invention provides a level shift chip circuit, which includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor;
[0040] The gate of the first field effect transistor is used to connect to the first signal input terminal, and the source of the first field effect transistor is grounded;
[0041] The gate of the second field effect transistor is used to connect to the second signal input terminal, and the source of the second field effect transistor is grounded;
[0042] The gate of the third field effect transistor is connected to the drain of the third field effect transistor, and the drain of the third field effect transistor is connected to the drain of the first field effect transistor;
[0043] The gate of the fourth field effect transistor is connected to the drain of the fourth field effect transistor, and the drain of the fourth field effect transistor is connected to the drain of the second field effect transistor;
[0044] The drain of the fifth field effect transistor is connected to the source of the third field effect transistor;
[0045] The drain of the sixth field effect transistor is connected to the source of the fourth field effect transistor;
[0046] The gate of the seventh field effect transistor is connected to the gate of the sixth field effect transistor, and the drain of the seventh field effect transistor is connected to the source of the fifth field effect transistor;
[0047] The gate of the eighth field effect transistor is connected to the gate of the fifth field effect transistor, the drain of the eighth field effect transistor is connected to the source of the sixth field effect transistor, and the source of the eighth field effect transistor is connected to the source of the seventh field effect transistor for connecting to the working voltage;
[0048] The gate of the ninth field effect tube is connected to the source of the third field effect tube, and the source of the ninth field effect tube is used to connect to the working voltage;
[0049] The gate of the tenth field effect tube is connected to the source of the first field effect tube, the source of the tenth field effect tube is grounded, and the drain of the tenth field effect tube is connected to the drain of the ninth field effect tube and they serve together as the output end of the level shift circuit.
[0050] Preferably, the first field effect transistor, the second field effect transistor and the tenth field effect transistor are all P-type field effect transistors; the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are all N-type field effect transistors.
[0051] Preferably, the ninth field effect transistor and the tenth field effect transistor have different sizes.
[0052] The present invention also provides a level shift chip, which comprises the level shift chip circuit as described above.
[0053] Compared with the prior art, the level shift chip circuit in the present invention adds a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor, and limits the connection method of the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor to make it a cross-coupling adjustment module. The introduced part can reduce the charging and discharging time of the internal nodes of the joint by adjusting the strength of the pull-up network, thereby reducing the dynamic power consumption of the level shift chip circuit and improving its level conversion rate so that it meets the requirements of the level shift chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:
[0055] Figure 1 It is a schematic diagram of a level shift chip circuit provided by the prior art;
[0056] Figure 2 It is a schematic diagram of a level shift chip circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0057] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0058] The embodiment of the present invention provides a level shift chip circuit 100, combined with Figure 2 As shown, it includes a first field effect transistor M11, a second field effect transistor M12, a third field effect transistor M13, a fourth field effect transistor M14, a fifth field effect transistor M15, a sixth field effect transistor M16, an eighth field effect transistor M18, a ninth field effect transistor M19 and a tenth field effect transistor M20.
[0059] The gate of the first field effect transistor M11 is used to connect to the first signal input terminal In, and the source of the first field effect transistor M11 is grounded.
[0060] The gate of the second field effect transistor M12 is used to connect to the second signal input terminal Inb, and the source of the second field effect transistor M12 is grounded.
[0061] The gate of the third field effect transistor M13 is connected to the drain of the third field effect transistor M13 , and the drain of the third field effect transistor M13 is connected to the drain of the first field effect transistor M11 .
[0062] The gate of the fourth field effect transistor M14 is connected to the drain of the fourth field effect transistor M14 , and the drain of the fourth field effect transistor M14 is connected to the drain of the second field effect transistor M12 .
[0063] The drain of the fifth field effect transistor M15 is connected to the source of the third field effect transistor M13.
[0064] The drain of the sixth field effect transistor M16 is connected to the source of the fourth field effect transistor M14.
[0065] The gate of the seventh field effect transistor M17 is connected to the gate of the sixth field effect transistor M16 , and the drain of the seventh field effect transistor M17 is connected to the source of the fifth field effect transistor M15 .
[0066] The gate of the eighth field effect transistor M18 is connected to the gate of the fifth field effect transistor M15, the drain of the eighth field effect transistor M18 is connected to the source of the sixth field effect transistor M16, and the source of the eighth field effect transistor M18 is connected to the source of the seventh field effect transistor M17 and is used to connect to the operating voltage VDD.
[0067] The gate of the ninth field effect transistor M19 is connected to the source of the third field effect transistor M13 , and the source of the ninth field effect transistor M19 is used to connect to the operating voltage VDD.
[0068] The gate of the tenth field effect transistor M20 is connected to the source of the first field effect transistor M11, the source of the tenth field effect transistor M20 is grounded, and the drain of the tenth field effect transistor M20 is connected to the drain of the ninth field effect transistor M19 and serves as the output terminal Out of the level shift circuit.
[0069] The first FET M11, the second FET M12 and the tenth FET M20 are all P-type FETs; the third FET M13, the fourth FET M14, the fifth FET M15, the sixth FET M16, the seventh FET M17 and the eighth FET M18 are all N-type FETs.
[0070] The ninth field effect transistor M19 and the tenth field effect transistor M20 have different sizes. This design can avoid the situation where the ninth field effect transistor M19 and the tenth field effect transistor M20 are turned on or off at the same time.
[0071] The third field effect transistor M13 and the fourth field effect transistor M14 of the level shift chip circuit 100 in this embodiment constitute a limiting circuit module; the fifth field effect transistor M15, the sixth field effect transistor M16, the seventh field effect transistor M17 and the eighth field effect transistor M18 constitute a pull-up module and serve as a cross-coupling adjustment module; the ninth field effect transistor M19 and the tenth field effect transistor M20 constitute an inverter, and the gate potentials of the ninth field effect transistor M19 and the tenth field effect transistor M20 are different.
[0072] In the level shift chip circuit 100 of this embodiment, assuming that the first signal input terminal In is at a low level in the initial stage, the first field effect transistor M11 is turned off, the second field effect transistor M12 is turned on, the C connection point will be pulled to a high level, the VA value is slightly lower than the power supply voltage (also called the working voltage VDD), and the D connection point is at a low level. The fifth field effect transistor M15 and the eighth field effect transistor M18 are turned on, and the sixth field effect transistor M16 and the seventh field effect transistor M17 are turned off.
[0073] In the second stage, when the first signal input terminal In jumps from low to high, the first field effect tube M11 starts to conduct, and the second field effect tube M12 will be turned off. At this time, the parasitic capacitance of the C connection point begins to discharge, but because the seventh field effect tube M17 has not yet been turned on, the pull-up current of the left branch is small, so the voltage of the C connection point can be quickly reduced. When VA is reduced to VDDH-Vth, the sixth field effect tube M16 and the seventh field effect tube M17 start to conduct. After the sixth field effect tube M16 is turned on, the voltage of the D connection point is quickly pulled up, causing the fifth field effect tube M15 and the eighth field effect tube M18 to be turned off.
[0074] In the above-mentioned working process, the pull-up current of the C connection point is always small, so compared with the cross-coupled level shift circuit in the prior art, the level shift chip circuit 100 in this embodiment can achieve fast pull-down of the C connection point; similarly, when the first signal input terminal In changes from high to low, the working condition of the circuit is just the opposite. The advantage of this structure is that it can reduce the static power consumption of the circuit and the output voltage pull-down time, but the output voltage pull-up time may be prolonged.
[0075] In order to further reduce some of the losses, a third field effect transistor M13 and a fourth field effect transistor M14 with two diode connections are added on the basis of the level shift chip circuit of the prior art to play a current limiting role and convert the output stage into a branch input inverter. The gate potentials of the P-type field effect transistor and the N-type field effect transistor of the branch input inverter are different, so the size of the field effect transistor needs to be selected to avoid the situation where the two field effect transistors are turned on at the same time.
[0076] Compared with the prior art, the level shift chip circuit 100 in this embodiment adds a fifth field effect transistor M15, a sixth field effect transistor M16, a seventh field effect transistor M17, an eighth field effect transistor M18, a ninth field effect transistor M19 and a tenth field effect transistor M20, and limits the connection method of the fifth field effect transistor M15, the sixth field effect transistor M16, the seventh field effect transistor M17 and the eighth field effect transistor M18 to make it a cross-coupling adjustment module. The introduced part can reduce the charging and discharging time of the internal nodes of the joint by adjusting the strength of the pull-up network, thereby reducing the dynamic power consumption of the level shift chip circuit 100 and improving its level conversion rate so that it meets the requirements of the level shift chip.
[0077] The present invention further provides an embodiment of a level shift chip, which includes the level shift chip circuit 100 in the above embodiment. Since the level shift chip in this embodiment includes the level shift chip circuit 100 in the above embodiment, it can also achieve the technical effect achieved by the level shift chip circuit 100 in the above embodiment, which will not be described in detail here.
[0078] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0079] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.
Claims
1. A level shift chip circuit, characterized in that: The level shift chip circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor; The gate of the first field effect transistor is used to connect to the first signal input terminal, and the source of the first field effect transistor is grounded; The gate of the second field effect transistor is used to connect to the second signal input terminal, and the source of the second field effect transistor is grounded; The gate of the third field effect transistor is connected to the drain of the third field effect transistor, and the drain of the third field effect transistor is connected to the drain of the first field effect transistor; The gate of the fourth field effect transistor is connected to the drain of the fourth field effect transistor, and the drain of the fourth field effect transistor is connected to the drain of the second field effect transistor; The drain of the fifth field effect transistor is connected to the source of the third field effect transistor; The drain of the sixth field effect transistor is connected to the source of the fourth field effect transistor; The gate of the seventh field effect transistor is connected to the gate of the sixth field effect transistor, and the drain of the seventh field effect transistor is connected to the source of the fifth field effect transistor; The gate of the eighth field effect transistor is connected to the gate of the fifth field effect transistor, the drain of the eighth field effect transistor is connected to the source of the sixth field effect transistor, and the source of the eighth field effect transistor is connected to the source of the seventh field effect transistor for connecting to the working voltage; The gate of the ninth field effect tube is connected to the source of the third field effect tube, and the source of the ninth field effect tube is used to connect to the working voltage; The gate of the tenth field effect tube is connected to the source of the first field effect tube, the source of the tenth field effect tube is grounded, and the drain of the tenth field effect tube is connected to the drain of the ninth field effect tube and they serve together as the output end of the level shift circuit.
2. The level shift chip circuit according to claim 1, characterized in that: The first field effect transistor, the second field effect transistor and the tenth field effect transistor are all P-type field effect transistors; the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are all N-type field effect transistors.
3. The level shift chip circuit according to claim 1, characterized in that: The ninth field effect transistor and the tenth field effect transistor have different sizes.
4. A level shift chip, characterized in that: The level shift chip comprises the level shift chip circuit as claimed in any one of claims 1 to 3.