Signal generation circuit and memory

Abstract

The invention relates to the technical field of semiconductors, in particular to a signal generation circuit and a memory, and the signal generation circuit comprises a ring oscillator which is configured to form an oscillation circuit and output an oscillation signal; the controller is connected with the ring oscillator, accesses a frequency selection signal, and is configured to provide the switch control signal for the ring oscillator according to a preset level of the oscillation signal and the frequency selection signal; the switch control signal is used for configuring the number of phase inverters connected to the oscillating circuit in the ring oscillator. The signal generation circuit provided by the invention aims to improve the stability of the ring oscillator when the oscillation frequency is changed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a signal generating circuit and a memory. Background Art

[0002] Ring oscillators can generate oscillation signals with stable frequencies, and are often used to generate synchronous clocks for digital circuits in system-on-chips. Variable-frequency ring oscillators are more adaptable and widely used, and are an indispensable circuit module for system-on-chips.

[0003] The classic ring oscillator is realized by connecting an odd number of inverters into a loop. By increasing or decreasing the number of inverting delay units in the loop through switches, the oscillation frequency can be reduced or increased.

[0004] However, when the ring oscillator changes the oscillation frequency by increasing or decreasing the number of inverting delay units in the loop, pulse waveform interference is easily generated, which in turn leads to abnormal oscillation signals and frequency confusion. Summary of the invention

[0005] The main purpose of the present application is to provide a signal generating circuit and a memory, aiming to improve the stability of a ring oscillator when changing the oscillation frequency.

[0006] To achieve the above-mentioned purpose, the present application proposes a signal generating circuit, comprising: a ring oscillator, configured to: form an oscillation circuit and output an oscillation signal; a controller, connected to the ring oscillator and connected to a frequency selection signal, configured to: provide a switch control signal to the ring oscillator according to a preset level of the oscillation signal and the frequency selection signal; the switch control signal is used to configure the number of inverters in the ring oscillator connected to the oscillation circuit.

[0007] In some embodiments, the ring oscillator includes: a plurality of cascaded delay units, configured to: configure the number of the delay units connected to the oscillation circuit based on the switch control signal; a delay inverter, whose input end is connected to the output end of the first-stage delay unit, and whose output end is connected to the input end of the first-stage delay unit, and which constitutes the oscillation circuit with the delay unit connected to the oscillation circuit; the first input end of the controller is connected to the output end of the delay inverter, the second input end is connected to the frequency selection signal, and the output end is respectively connected to each of the delay units.

[0008] In some embodiments, the controller includes: a trigger, wherein the input end of the trigger is used to receive the frequency selection signal, and the clock end of the trigger is connected to the output end of the ring oscillator; a decoder, wherein the input end of the decoder is connected to the output end of the trigger, and the output end of the decoder is connected to the ring oscillator to output the switch control signal.

[0009] In some embodiments, each of the delay units is further configured to: configure the number of the inverters connected to the oscillation circuit based on the switch control signal.

[0010] In some embodiments, each of the delay units is further configured to: configure the number of the inverters connected to the oscillation circuit based on the adjustment signal.

[0011] In some embodiments, each of the delay units includes: a first input terminal, a first output terminal, a second input terminal, and a second output terminal; the first input terminal is connected to the first output terminal of the previous delay unit, the first output terminal is connected to the first input terminal of the next delay unit, the second input terminal is connected to the second output terminal of the next delay unit, and the second output terminal is connected to the second input terminal of the previous delay unit; the second output terminal of the first delay unit is connected to the input terminal of the delay inverter, and the output terminal of the delay inverter is connected to the first input terminal of the first delay unit.

[0012] In some embodiments, if the preset level is a low level, the first output end of the last delay unit is vacant and the second input end is connected to a low level; if the preset level is a high level, the first output end of the last delay unit is vacant and the second input end is connected to a high level.

[0013] In some embodiments, each of the delay units includes: a first inverter, whose input end is connected to the first input end of the delay unit; a first switch, whose first selection end is connected to the output end of the first inverter; a second inverter, whose input end is connected to the control end of the first switch; a second switch, whose first selection end is connected to the output end of the second inverter, and whose control end is connected to the first output end of the delay unit; a third switch, whose first selection end is connected to the second input end of the delay unit, and whose second selection end is connected to the output end of the second inverter; a third inverter, whose input end is connected to the control end of the third switch; a fourth switch, whose first selection end is connected to the output end of the third inverter, and whose second selection end is connected to the output end of the first inverter; a fourth inverter, whose input end is connected to the control end of the fourth switch, and whose output end is connected to the second output end of the delay unit.

[0014] In some embodiments, the first switch further includes a third selection terminal, and the second switch further includes a fourth selection terminal; if the preset level is a low level, the third selection terminal is connected to a high level, and the fourth selection terminal is connected to a low level; if the preset level is a high level, the third selection terminal is connected to a low level, and the fourth selection terminal is connected to a high level.

[0015] In some embodiments, the delay unit is configured to be in a first closed-loop state. When the delay unit is in the first closed-loop state, the adjustment signal configures the first switch to be placed at the third selection end, the second switch to be placed at the first selection end, the third switch to be placed at the first selection end, and the fourth switch to be placed at the second selection end; when the delay unit is in a second closed-loop state, the adjustment signal configures the first switch to be placed at the first selection end, the second switch to be placed at the fourth selection end, the third switch to be placed at the second selection end, and the fourth switch to be placed at the first selection end; when the delay unit is in an open-loop state, the adjustment signal configures the first switch to be placed at the first selection end, the second switch to be placed at the first selection end, the third switch to be placed at the first selection end, and the fourth switch to be placed at the first selection end.

[0016] The present application also proposes a memory, comprising: a clock circuit, comprising the signal generating circuit provided in the above embodiment, to generate a clock signal based on the oscillation signal; an execution circuit, connected to the clock circuit, to drive the clock signal based on the clock signal

[0017] The technical solution of this application has the following beneficial effects:

[0018] When the oscillation signal output by the ring oscillator is at a preset level, the number of inverters connected to the oscillation circuit in the ring oscillator is changed through a switch control signal, thereby effectively avoiding pulse waveform interference when the ring oscillator frequency changes and improving the stability of the ring oscillator when changing the oscillation frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of the structure of the frequency switching of the ring oscillator circuit provided in an embodiment of the present application;

[0021] Figure 2 Provided in the embodiments of this application Figure 1 A schematic diagram of the timing of signals at each node of the ring oscillator circuit during the frequency switching process;

[0022] Figure 3 A schematic diagram of the structure of a signal generating circuit provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of the structure of a controller provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the structure of a ring oscillator provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of a delay unit provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of the structure of a delay unit in a first closed-loop state provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of the structure of a delay unit in a second closed-loop state provided in an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of the structure of a delay unit in an open-loop state provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of the structure of the signal generating circuit provided in an embodiment of the present application before the frequency switching process;

[0030] Fig.11 A schematic diagram of the structure of the signal generating circuit provided in an embodiment of the present application after the frequency switching process;

[0031] Fig.12 A schematic diagram of the structure of a memory provided in an embodiment of the present application.

[0032] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0033] As known from the background technology, when a ring oscillator changes the oscillation frequency by increasing or decreasing the number of inverting delay units in the loop, pulse waveform interference is easily generated, which leads to abnormal oscillation signal and frequency disorder.

[0034] In one example, refer to Figure 1 , Figure 1 The schematic diagram is a structural diagram of the frequency switching of the ring oscillator circuit. The ring oscillator includes: a plurality of inverters connected in series to form an oscillation loop, and the number of inverters connected in series in the ring oscillator is adjustable. When the ring oscillator switches from a high frequency to a low frequency, that is, the ring oscillator changes from a small loop 20 to a large loop 10, the number of inverters in the oscillation loop increases; when the ring oscillator switches from a low frequency to a high frequency, that is, the ring oscillator changes from a large loop 10 to a small loop 20, the number of inverters in the oscillation loop decreases.

[0035] If the ring oscillator switches from high frequency to low frequency, in one example, refer to Figure 2 , Figure 2 for Figure 1The timing diagram of each node signal of the ring oscillation circuit during the frequency switching process is shown. When the ring oscillator switches from high frequency to low frequency, that is, the level change time of the switching signal (which can be a change from high level to low level or a change from low level to high level), the connection relationship of node B changes. At this time, the voltage of node C will immediately change to the reverse voltage of node B (there are an odd number of inverters between node B and node C). Referring to the indication of arrow 31, a falling edge is formed at node C at this time. At the same time, at the switching moment, the voltage of node A will immediately change from the original voltage to the same as the voltage of node D (there are an even number of inverters between node D and node A). Referring to the indication of arrow 32, a rising edge is formed at node A at this time. The voltage of node A is transmitted to node C through node B, and the voltage of node C changes according to the voltage change of node B and then according to the voltage change of node A. At this time, the voltage of node C introduces the waveform interference 34 of signal switching into the oscillation signal 33 generated by the large loop 10, that is, the ring oscillator has voltage jitter at node C, and the jitter will be circulated in the ring oscillator, resulting in an error in the oscillation signal output by the ring oscillator and abnormal frequency.

[0036] In order to solve the above problems, this embodiment proposes a signal generating circuit, including: a ring oscillator, configured to: form an oscillation circuit and output an oscillation signal; a controller, connected to the ring oscillator and connected to a frequency selection signal, configured to: provide the switch control signal to the ring oscillator according to a preset level of the oscillation signal and the frequency selection signal; the switch control signal is used to configure the number of inverters in the ring oscillator connected to the oscillation circuit.

[0037] The signal generating circuit provided in the embodiment of the present application, when the oscillation signal output by the ring oscillator is at a preset level, changes the number of inverters connected to the oscillation circuit in the ring oscillator through a switch control signal, thereby effectively avoiding pulse waveform interference when the ring oscillator frequency changes and improving the stability of the ring oscillator when changing the oscillation frequency.

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0040] refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of a signal generating circuit provided in this embodiment. The signal generating circuit 100 includes a ring oscillator 101 and a controller 102 .

[0041] The ring oscillator 101 is configured to form an oscillation circuit and output an oscillation signal.

[0042] In one example, multiple inverters in the ring oscillator 101 are connected in series to form an oscillation circuit and output an oscillation signal; wherein the oscillation frequency of the oscillation signal output by the ring oscillator 101 is related to the number of inverters connected to the oscillation circuit, and the more inverters connected to the ring oscillator 101, the smaller the oscillation frequency of the oscillation signal; the fewer inverters connected to the ring oscillator 101, the larger the oscillation frequency of the oscillation signal.

[0043] The controller 102 is configured to provide a switch control signal to the ring oscillator 101 according to a preset level of the oscillation signal and a frequency selection signal, and the switch control signal is used to configure the number of inverters connected to the oscillation circuit in the ring oscillator 101 .

[0044] In one example, a frequency selection signal is generated by an external input signal generating circuit 100, which is decoded by a controller 102 to generate a switch control signal. The controller 102 transmits the switch control signal to the ring oscillator 101. The switch control signal adjusts the oscillation frequency of the oscillation signal output by the ring oscillator 101 by adjusting the number of inverters connected to the oscillation circuit in the ring oscillator 101.

[0045] Specifically, the controller 102 controls based on a preset level of the oscillation signal to transmit the switch control signal to the ring oscillator 101 .

[0046] By adjusting the frequency when the oscillation circuit outputs a preset level, pulse waveform interference when the ring oscillator frequency changes can be effectively avoided, thereby improving the stability of the ring oscillator when the oscillation frequency changes.

[0047] In one example, the switch control signal is used to configure the on / off state of the switch in the ring oscillator, thereby changing the number of inverters connected to the oscillation circuit.

[0048] refer to Figure 4 , Figure 4 A schematic diagram of the structure of the controller provided in this embodiment; in some embodiments, the controller includes a trigger 103 and a decoder 104. The input end of the trigger 103 is used to receive the frequency selection signal, and the clock end of the trigger is connected to the output end of the ring oscillator 101; the input end of the decoder 104 is connected to the output end of the trigger 103, and the output end of the decoder 104 is connected to the ring oscillator 101 to output a switch control signal.

[0049] In some embodiments, the control order logic of the trigger 103 and the decoder 104 can be exchanged, that is, the controller 102 first obtains the switch control signal based on the decoder 104, and then outputs it to the ring oscillator 101 via the trigger 103. At this time, the input end of the decoder is used to receive the frequency selection signal, the output end of the decoder is connected to the input end of the trigger, the clock end of the trigger is connected to the output end of the ring oscillator, and the output end of the trigger is connected to the ring oscillator to output the switch control signal.

[0050] Regarding the preset level, in a specific application, the preset level may be set to a high level or a low level.

[0051] Specifically, the clock end of the trigger is connected to the output end of the ring oscillator 101 so that the trigger is enabled based on the valid edge of the oscillation signal. After the trigger is enabled based on the valid edge of the oscillation signal, the level received at the input end at this moment is output and latched at the output end.

[0052] In one example, if the preset level of the oscillation signal is a low level and if the effective edge of the trigger is a falling edge, that is, when the oscillation signal changes from a high level to a low level, the controller 102 provides a switch control signal to the ring oscillator 101 .

[0053] In one example, if the preset level of the oscillation signal is a low level and if the effective edge of the trigger is a falling edge, an inverter needs to be connected in series to the input end of the trigger. That is, when the oscillation signal changes from a high level to a low level, the input end of the trigger changes from a low level to a high level, and the controller 102 provides a switch control signal to the ring oscillator 101.

[0054] In one example, if the preset level of the oscillation signal is a high level and if the effective edge of the trigger is a rising edge, that is, when the oscillation signal changes from a low level to a high level, the controller 102 provides a switch control signal to the ring oscillator 101 .

[0055] In one example, if the preset level of the oscillation signal is a high level and if the effective edge of the trigger is a falling edge, the input end of the trigger needs to be connected in series with an inverter, that is, when the oscillation signal changes from a low level to a high level, the input end of the trigger changes from a high level to a low level, and the controller 102 provides a switch control signal to the ring oscillator 101.

[0056] It should be noted that in the above description of the trigger, the trigger is based on edge triggering; in some embodiments, the trigger can also be set as a level trigger, a pulse trigger, etc.

[0057] In some embodiments, the controller 102 may also be based on latch settings.

[0058] It should be noted that, in the subsequent description of this embodiment, the preset level of the oscillation signal is taken as a low level for exemplary description, which does not constitute a limitation on this embodiment.

[0059] In some embodiments, reference Figure 5 , Figure 5 The ring oscillator 101 is a schematic diagram of the structure of the ring oscillator provided in this embodiment. The ring oscillator 101 includes: a plurality of cascaded delay units 301 and a delay inverter 302 .

[0060] The cascaded multiple delay units are configured to configure the number of delay units connected to the oscillation circuit based on the switch control signal; the delay inverter 302, the input end is connected to the output end of the first-stage delay unit, the output end is connected to the input end of the first-stage delay unit, the delay inverter 302 and the delay unit 301 connected to the oscillation circuit constitute an oscillation circuit; the first input end of the controller 102 is connected to the output end of the delay inverter 302, the second input end is connected to the frequency selection signal, and the output end is connected to each delay unit 301 respectively.

[0061] Specifically, the cascaded delay units 301 change the number of connected delay units 301 through a switch control signal, thereby changing the number of connected inverters in the oscillation circuit to change the oscillation frequency of the oscillation signal output by the ring oscillator 101 .

[0062] Based on the working principle of the ring oscillator 101 , it can be known that an odd number of inverters need to be connected to form an oscillation circuit of the ring oscillator 101 .

[0063] In an example, if each delay unit 301 includes an odd number of inverters, and the number of delay units 301 connected to the oscillation circuit is an odd number, then the number of delay inverters 302 is an even number.

[0064] In an example, if each delay unit 301 includes an odd number of inverters, and the number of delay units 301 connected to the oscillation circuit is an even number, then the number of delay inverters 302 is an odd number.

[0065] In one example, if each delay unit 301 includes an even number of inverters, the number of the delay inverters 302 is an odd number.

[0066] In some embodiments, the signal generating circuit 100 further includes an adjustment module, which is connected to the ring oscillator 101 and the controller 102 . The adjustment module is configured to adjust the oscillation signal and transmit it to the controller 102 .

[0067] Taking the controller 102 composed of a trigger as an example, if the controller 102 needs to be configured to output a switch control signal based on a low-level oscillation signal, but the trigger constituting the controller 102 is a high-level trigger, then based on the working principle of the controller 102, the controller 102 actually needs to output a switch control signal based on a high-level signal; the ring oscillator 101 and the controller 102 are connected through the adjustment module to adjust the oscillation signal and transmit it to the controller 102, thereby realizing the control logic of the controller 102.

[0068] Based on the above example, in some embodiments, the adjustment module is configured based on an inverter to invert the oscillation signal and then transmit it to the controller 102 .

[0069] In some embodiments, the adjustment module is configured based on the delay inverter 302. By multiplexing the delay inverter 302 to realize the function of the adjustment module, the circuit structure is simple and the cost is low.

[0070] In some embodiments, each delay unit 301 is further configured to configure the number of inverters connected to the oscillation circuit based on the switch control signal.

[0071] Specifically, each delay unit 301 in the cascaded plurality of delay units 301 changes the number of inverters connected to the oscillation circuit in the delay unit 301 through a switch control signal, so as to change the oscillation frequency of the oscillation signal output by the ring oscillator 101 .

[0072] In combination with the above two examples, in some embodiments, the switch control signal can adjust the number of inverters in the oscillation circuit by adjusting the number of delay units 301 connected to the oscillation circuit. The switch control signal can also adjust the number of inverters in the oscillation circuit by adjusting the number of inverters connected to the delay unit 301, thereby improving the flexibility of the switch control signal in adjusting the oscillation frequency of the ring oscillator 101.

[0073] In some embodiments, each delay unit 301 includes: a first input terminal IN1, a first output terminal OUT1, a second input terminal IN2, and a second output terminal OUT2. The first input terminal IN1 is connected to the first output terminal OUT1 of the previous delay unit, the first output terminal OUT1 is connected to the first input terminal IN1 of the next delay unit, the second input terminal IN2 is connected to the second output terminal OUT2 of the next delay unit, and the second output terminal OUT2 is connected to the second input terminal IN2 of the previous delay unit; the second output terminal OUT2 of the first delay unit is connected to the input terminal of the delay inverter 302, and the output terminal of the delay inverter 302 is connected to the first input terminal IN1 of the first delay unit.

[0074] In some embodiments, reference Figure 6 , Figure 6 The structural diagram of the delay unit provided in this embodiment, each delay unit 301 includes: a first inverter F1, whose input end is connected to the first input end IN1 of the delay unit 301; a first switch K1, whose first selection end 1 is connected to the output end of the first inverter F1; a second inverter F2, whose input end is connected to the control end 0 of the first switch K1; a second switch K2, whose first selection end 1 is connected to the output end of the second inverter F2, and whose control end 0 is connected to the first output end OUT1 of the delay unit 301; a third switch K3, whose first selection end 1 is connected to the second input end IN2 of the delay unit 301, and whose second selection end 2 is connected to the output end of the second inverter F2; a third inverter F3, whose input end is connected to the control end 0 of the third switch K3; a fourth switch K4, whose first selection end 1 is connected to the output end of the third inverter F3, and whose second selection end 2 is connected to the output end of the first inverter F1; a fourth inverter F4, whose input end is connected to the control end 0 of the fourth switch K4, and whose output end is connected to the second output end OUT2 of the delay unit 301.

[0075] The first switch K1 , the second switch K2 , the third switch K3 and the fourth switch K4 are controlled by a switch control signal to adjust the delay unit 301 , thereby adjusting the number of inverters connected to the oscillation circuit.

[0076] exist Figure 6 In the example, the first switch K1 and the second switch K2 are three-terminal switches. At this time, the first switch K1 also includes a third selection terminal 3, and the third selection terminal 3 is vacant; if the preset level is a low level, the third selection terminal 3 is connected to a high level, and the fourth selection terminal 4 is connected to a low level; if the preset level is a high level, the third selection terminal 3 is connected to a low level, and the fourth selection terminal 4 is connected to a high level.

[0077] In some embodiments, the first switch K1 and the second switch K2 can also be set based on a two-terminal switch. The control terminal 0 of the first switch K1 is connected to the first selection terminal 1, which indicates that the first switch K1 is closed, and the control terminal 0 of the first switch K1 is not connected to the first selection terminal 1, which indicates that the first switch K1 is disconnected; the control terminal 0 of the second switch K2 is connected to the first selection terminal 1, which indicates that the second switch K2 is closed, and the control terminal 0 of the second switch K2 is not connected to the first selection terminal 1, which indicates that the second switch K2 is disconnected.

[0078] for Figure 6 The delay unit 301 shown can operate in different states based on the switching states of the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4. In some embodiments, the delay unit 301 includes a first closed-loop state, a second closed-loop state and a switch state.

[0079] refer to Figure 7 , Figure 7 It is a structural diagram of the delay unit in the first closed-loop state. When the delay unit 301 is in the first closed-loop state, the switch control signal configures the first switch K1 to be placed at the third selection end 3, the second switch K2 to be placed at the first selection end 1, the third switch K3 to be placed at the first selection end 1, and the fourth switch K4 to be placed at the second selection end 2. At this time, the delay unit 301 is connected to two inverters, namely the first inverter F1 and the fourth inverter F4; the signal is input from the first input end IN1 of the delay unit 301 and output from the second output end OUT2.

[0080] For the delay unit 301 in the first closed-loop state, the first inverter F1 and the fourth inverter F4 are connected to the oscillation circuit. At this time, the signals of the first input terminal IN1 and the second output terminal OUT2 are in phase, that is, the input of the first input terminal IN1 is "0", and the output of the second output terminal OUT2 is "0".

[0081] refer to Figure 8 , Figure 8 It is a structural diagram of the delay unit in the second closed-loop state. When the delay unit 301 is in the second closed-loop state, the switch control signal configures the first switch K1 to be placed at the first selection end 1, the second switch K2 to be placed at the fourth selection end 4, the third switch K3 to be placed at the second selection end 2, and the fourth switch K4 to be placed at the first selection end 1. At this time, the delay unit 301 is connected to four inverters, namely the first inverter F1, the second inverter F2, the third inverter F3 and the fourth inverter F4; the signal is input from the first input end IN1 of the delay unit 301 and output from the second output end OUT2.

[0082] For the delay unit 301 in the second closed-loop state, the first inverter F1, the second inverter F2, the third inverter F3 and the fourth inverter F4 are connected to the oscillation circuit. At this time, the signals of the first input terminal IN1 and the second output terminal OUT2 are in phase, that is, the input of the first input terminal IN1 is "0", and the output of the second output terminal OUT2 is "0".

[0083] refer to Fig. 9 , Fig. 9 It is a structural diagram of a delay unit in an open-loop state. When the delay unit 301 is in an open-loop state, the switch control signal configures the first switch K1 to be placed at the first selection end 1, the second switch K2 to be placed at the first selection end 1, the third switch K3 to be placed at the first selection end 1, and the fourth switch K4 to be placed at the first selection end 1. At this time, the delay unit 301 is connected to four inverters, namely the first inverter F1, the second inverter F2, the third inverter F3 and the fourth inverter F4; the signal is input from the first input end IN1 of the delay unit 301, output from the first output end OUT1, and input from the second input end IN2, and output from the second output end OUT2.

[0084] The delay unit 301 in an open-loop state includes two open-loop paths, each of which includes two inverters. At this time, the signals of the first input terminal IN1 and the first output terminal OUT1 are in phase, and the signals of the second input terminal IN2 and the second output terminal OUT2 are in phase, that is, the input of the first input terminal IN1 is "0", and the output of the first output terminal OUT2 is "0"; the input of the second input terminal IN2 is "0", and the output of the second output terminal OUT2 is "0".

[0085] It should be noted that, among the cascaded multiple delay units 301, only one delay unit 301 is in the first closed-loop state or the second closed-loop state (collectively referred to as the closed-loop state), and the other delay units 301 are all in the open-loop state; the delay unit 301 in the closed-loop state, the multiple delay units 301 in the previous stage in the open-loop state and the delay inverter 302 form an oscillation circuit.

[0086] The access adjustment of two inverters is achieved by placing the closed-loop state delay unit 301 in the first closed-loop state or the second closed-loop state, and the access adjustment of four inverters is achieved by adjusting the number of open-loop state delay units 301. At this time, the number of inverters accessed in the oscillation circuit = 1 (the number of delay inverters 302) + the number of open-loop state delay units 301 * 4 + 2 / 4 (wherein, the number of delay units 301 accessed to the first closed-loop state is 2, and the number of delay units 301 accessed to the second closed-loop state is 4).

[0087] In some embodiments, the first input terminal IN1 , the first output terminal OUT1 , the second input terminal IN2 , and the second output terminal OUT2 of the delay unit 301 that is not connected to the oscillation circuit all maintain a low level.

[0088] In some embodiments, if the preset level is a low level, the first output terminal OUT1 of the last-stage delay unit is vacant, and the second input terminal IN2 is connected to a low level to ensure that the levels of the first input terminal IN1, the first output terminal OUT1, the second input terminal IN2, and the second output terminal OUT2 of the delay unit 301 that is not connected to the oscillation circuit are consistent with the preset level and are all low levels; if the preset level is a high level, the first output terminal OUT1 of the last-stage delay unit is vacant, and the second input terminal IN2 is connected to a high level to ensure that the levels of the first input terminal IN1, the first output terminal OUT1, the second input terminal IN2, and the second output terminal OUT2 of the delay unit 301 that is not connected to the oscillation circuit are consistent with the preset level and are all high levels.

[0089] In one example, refer to Fig.10 and Fig.11 , Fig.10 This is a schematic diagram of the structure of the signal generating circuit provided in this embodiment before the frequency switching process. Fig.11 A schematic diagram of the structure of the signal generating circuit provided in this embodiment after the frequency switching process, based on Figure 6 to Figure 9 The delay unit 301 shown, the delay unit in the open-loop state is hereinafter referred to as the open-loop unit 311, and the delay unit in the closed-loop state is hereinafter referred to as the closed-loop unit 312. When the oscillation frequency of the oscillation circuit decreases, that is, more inverters need to be connected to the oscillation circuit, the closed-loop unit 312 needs to be moved back in the cascaded delay unit. Similarly, in other examples, when the oscillation frequency of the oscillation circuit increases, that is, more inverters need to be connected to the oscillation circuit, the closed-loop unit 312 needs to be moved forward in the cascaded delay unit.

[0090] Taking the case where the preset level of the oscillation signal is a low level and the effective edge of the trigger is a rising edge as an example, for the open-loop unit 311 and the closed-loop unit 312 connected to the oscillation circuit, at the moment of switch switching, the oscillation signal is converted from a high level to a low level, the upper branch of the open-loop unit 311 is connected to two inverters, and as the front stage of the oscillation signal, the level conversion has been completed, that is, at this time, all input terminals and output terminals are low levels, and the output of the delay inverter 302 is converted from a low level to a high level at this time, the lower branch of the open-loop unit 311 is connected to two inverters, and as the rear stage of the delay inverter 302, the level conversion has not yet started, that is, at this time, all input terminals and output terminals are low levels; and the closed-loop unit 312 is connected to an even-numbered inverter regardless of whether it is the first closed-loop state or the second closed-loop state, and the input terminal and output terminal of the closed-loop unit 312 are both low levels. At this time, the levels of the first input terminal IN1, the second input terminal IN2, the first output terminal OUT1, and the second output terminal OUT2 of the delay unit 301 connected to the oscillation circuit are all low levels.

[0091] For the open-loop unit 311 and the closed-loop unit 312 not connected to the oscillation circuit, the first-stage delay unit 301 is the closed-loop unit 312, the subsequent cascaded delay unit 301 is the open-loop unit 311, and the first output terminal OUT1 of the last-stage delay unit is vacant, and the second input terminal IN2 is connected to a low level.

[0092] For the lower branch, if the closed-loop unit 312 is in the first closed-loop state, refer to Figure 7 , the first switch K1 is placed at the third selection end 3, and the second switch K2 is placed at the first selection end 1. At this time, the high level connected to the third selection end 3 is inverted by the second inverter F2 and output at the first output end OUT1. The first output end OUT1 of the closed-loop unit 312 is at a low level. The lower branch of the open-loop unit 311 is connected to two inverters, and the input end level is the same as the output end level, until the first output end OUT1 of the last-stage open-loop unit 311 is grounded. At this time, the first input end IN1 and the first output end OUT1 of the open-loop unit 311 and the closed-loop unit 312 on the lower branch that are not connected to the oscillation circuit are both at a low level.

[0093] For the lower branch, if the closed-loop unit 312 is in the second closed-loop state, refer to Figure 8 , the second switch is placed at the fourth selection terminal 4. At this time, the low level connected to the fourth selection terminal is output at the first output terminal OUT1, the first output terminal OUT1 of the closed-loop unit 312 is at a low level, and the lower branch of the open-loop unit 311 is connected to two inverters, and the input terminal level is the same as the output terminal level, until the first output terminal OUT1 of the last-stage open-loop unit 311 is grounded. At this time, the first input terminal IN1 and the first output terminal OUT1 of the open-loop unit 311 and the closed-loop unit 312 on the lower branch that are not connected to the oscillation circuit are both at a low level.

[0094] For the upper branch, the second input terminal IN2 of the last-stage delay unit is connected to a low level, the upper branch of the open-loop unit 311 is connected to two inverters, and the input terminal level is the same as the output terminal level. At this time, the second input terminal IN2 and the second output terminal OUT2 of the open-loop unit 311 on the upper branch that is not connected to the oscillation circuit are both low levels.

[0095] In summary, before and after the frequency of the signal generating circuit 100 is changed, the levels of the first input terminal IN1, the second input terminal, the first output terminal OUT1 and the second output terminal OUT2 of the delay unit are all low levels, which is consistent with the output of the oscillation signal, avoiding the voltage mutation. Since the circuit structure avoids the node voltage mutation when switching from high frequency to low frequency, it avoids voltage jitter, and will not cause oscillation signal errors and frequency abnormalities.

[0096] Similarly, taking the case where the preset level of the oscillation signal is a high level and the effective edge of the trigger is a falling edge as an example, for the open-loop unit 311 and the closed-loop unit 312 connected to the oscillation circuit, at the moment of switch switching, the oscillation signal is converted from a low level to a high level, the upper branch of the open-loop unit 311 is connected to two inverters, and as the front stage of the oscillation signal, the level conversion has been completed, that is, at this time, all input terminals and output terminals are high levels, and the output of the delay inverter 302 is converted from a high level to a low level at this time, the lower branch of the open-loop unit 311 is connected to two inverters, and the rear stage of the delay inverter 302 has not yet started the level conversion, that is, at this time, all input terminals and output terminals are high levels; and the closed-loop unit 312 is connected to an even-numbered inverter regardless of whether it is the first closed-loop state or the second closed-loop state, and the input terminal and output terminal of the closed-loop unit 312 are both high levels. At this time, the levels of the first input terminal IN1, the second input terminal IN2, the first output terminal OUT1, and the second output terminal OUT2 of the delay unit 301 connected to the oscillation circuit are all high levels.

[0097] For the open-loop unit 311 and the closed-loop unit 312 not connected to the oscillation circuit, the first-stage delay unit 301 is the closed-loop unit 312, the subsequent cascaded delay unit 301 is the open-loop unit 311, and the first output terminal OUT1 of the last-stage delay unit is vacant, and the second input terminal IN2 is connected to a high level.

[0098] For the lower branch, if the closed-loop unit 312 is in the first closed-loop state, the first switch K1 is placed at the third selection terminal 3, and the second switch K2 is placed at the first selection terminal 1. At this time, the high level connected to the third selection terminal 3 is inverted by the second inverter F2 and output at the first output terminal OUT1. The first output terminal OUT1 of the closed-loop unit 312 is a high level. The lower branch of the open-loop unit 311 is connected to two inverters, and the input terminal level is the same as the output terminal level until the first output terminal OUT1 of the last-stage open-loop unit 311 is grounded. At this time, the first input terminal IN1 and the first output terminal OUT1 of the open-loop unit 311 and the closed-loop unit 312 on the lower branch that are not connected to the oscillation circuit are both high levels.

[0099] For the lower branch, if the closed-loop unit 312 is in the second closed-loop state, the second switch is placed at the fourth selection terminal 4. At this time, the high level connected to the fourth selection terminal is output at the first output terminal OUT1, and the first output terminal OUT1 of the closed-loop unit 312 is at a high level. The lower branch of the open-loop unit 311 is connected to two inverters, and the input terminal level is the same as the output terminal level until the first output terminal OUT1 of the last-stage open-loop unit 311 is grounded. At this time, the first input terminal IN1 and the first output terminal OUT1 of the open-loop unit 311 and the closed-loop unit 312 on the lower branch that are not connected to the oscillation circuit are both at a high level.

[0100] For the upper branch, the second input terminal IN2 of the last-stage delay unit is connected to a high level, the upper branch of the open-loop unit 311 is connected to two inverters, and the input terminal level is the same as the output terminal level. At this time, the second input terminal IN2 and the second output terminal OUT2 of the open-loop unit 311 on the upper branch that is not connected to the oscillation circuit are both high levels.

[0101] In summary, before and after the frequency of the signal generating circuit 100 is changed, the levels of the first input terminal IN1, the second input terminal, the first output terminal OUT1 and the second output terminal OUT2 of the delay unit are all high levels, which are consistent with the output of the oscillation signal, avoiding the voltage mutation. Since the circuit structure avoids the node voltage mutation when switching from high frequency to low frequency, it avoids voltage jitter, and will not cause oscillation signal errors and frequency abnormalities.

[0102] In some embodiments, the time from when the switch control signal is input into the delay unit 301 to when the states of the first switch K1 , the second switch K2 , the third switch K3 and the fourth switch K4 in the delay unit 301 are switched does not exceed half the oscillation period of the oscillation signal.

[0103] The signal generating circuit provided in the embodiment of the present application, when the oscillation signal output by the ring oscillator is at a preset level, changes the number of inverters connected to the oscillation circuit in the ring oscillator through a switch control signal, thereby effectively avoiding pulse waveform interference when the ring oscillator frequency changes and improving the stability of the ring oscillator when changing the oscillation frequency.

[0104] It should be noted that, in the absence of conflict, the features applied for in the signal generating circuit provided in the above embodiments can be randomly combined to obtain a new memory embodiment.

[0105] This embodiment also provides a memory to effectively avoid pulse waveform interference when the frequency of the ring oscillator changes.

[0106] refer to Fig.12 , Fig.12 The schematic diagram of the structure of the memory provided in this embodiment is as follows: the memory 400 includes a clock circuit 401 and an execution circuit 402, wherein the clock circuit 401 includes the signal generating circuit provided in the above embodiment to generate a clock signal based on an oscillation signal. The execution circuit 402 is connected to the clock circuit to be driven based on the clock signal.

[0107] For the clock circuit 401, the clock circuit 401 includes a phase-locked loop (PLL), which generates a clock signal based on an oscillation signal as a reference clock to achieve a large adjustment of the clock signal frequency. The signal generating circuit is used to achieve a small adjustment of the clock signal frequency, thereby achieving flexibility in adjusting the clock signal frequency in the memory.

[0108] Regarding the execution circuit 402, the execution circuit 402 may be a component of a related functional circuit in a memory, or an entire circuit of a related functional circuit.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0110] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0111] The above is a detailed introduction to a signal generating circuit and a memory provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A signal generating circuit, characterized in that: include: The ring oscillator is configured to: form an oscillation circuit and output an oscillation signal; A controller connected to the ring oscillator and receiving a frequency selection signal, configured to: provide a switch control signal to the ring oscillator according to a preset level of the oscillation signal and the frequency selection signal; The switch control signal is used to configure the number of inverters in the ring oscillator connected to the oscillation circuit.

2. The signal generating circuit according to claim 1, characterized in that: The ring oscillator comprises: The plurality of delay units connected in cascade are configured to: configure the number of the delay units connected to the oscillation circuit based on the switch control signal; A delay inverter, whose input end is connected to the output end of the first-stage delay unit, whose output end is connected to the input end of the first-stage delay unit, and which forms the oscillation circuit with the delay unit connected to the oscillation circuit; The first input terminal of the controller is connected to the output terminal of the delay inverter, the second input terminal is connected to the frequency selection signal, and the output terminal is respectively connected to each of the delay units.

3. The signal generating circuit according to claim 1 or 2, characterized in that: The controller comprises: A trigger, wherein the input end of the trigger is used to receive the frequency selection signal, and the clock end of the trigger is connected to the output end of the ring oscillator; A decoder, wherein the input end of the decoder is connected to the output end of the trigger, and the output end of the decoder is connected to the ring oscillator to output the switch control signal.

4. The signal generating circuit according to claim 2, wherein: Each of the delay units is further configured to: configure the number of the inverters connected to the oscillation circuit based on the switch control signal.

5. The signal generating circuit according to claim 4, characterized in that: Each of the delay units comprises: a first input end, a first output end, a second input end, and a second output end; The first input end is connected to the first output end of the previous delay unit, the first output end is connected to the first input end of the next delay unit, the second input end is connected to the second output end of the next delay unit, and the second output end is connected to the second input end of the previous delay unit; The second output end of the first-stage delay unit is connected to the input end of the delay inverter, and the output end of the delay inverter is connected to the first input end of the first-stage delay unit.

6. The signal generating circuit according to claim 5, characterized in that: If the preset level is a low level, the first output end of the last delay unit is vacant, and the second input end is connected to a low level; if the preset level is a high level, the first output end of the last delay unit is vacant, and the second input end is connected to a high level.

7. The signal generating circuit according to claim 5, characterized in that: Each of the delay units comprises: A first inverter, an input end of which is connected to a first input end of the delay unit; A first switch, a first selection end connected to an output end of the first inverter; a second inverter, an input end of which is connected to the control end of the first switch; A second switch, a first selection end connected to the output end of the second inverter, and a control end connected to the first output end of the delay unit; A third switch, a first selection end connected to the second input end of the delay unit, and a second selection end connected to the output end of the second inverter; a third inverter, an input end of which is connected to the control end of the third switch; a fourth switch, wherein a first selection end is connected to the output end of the third inverter, and a second selection end is connected to the output end of the first inverter; A fourth inverter has an input end connected to the control end of the fourth switch, and an output end connected to the second output end of the delay unit.

8. The signal generating circuit according to claim 7, characterized in that: The first switch further includes a third selection terminal, and the second switch further includes a fourth selection terminal; if the preset level is a low level, the third selection terminal is connected to a high level, and the fourth selection terminal is connected to a low level; if the preset level is a high level, the third selection terminal is connected to a low level, and the fourth selection terminal is connected to a high level.

9. The signal generating circuit according to claim 7, characterized in that: When the delay unit is in the first closed-loop state, the adjustment signal configures the first switch to be placed at the third selection end, the second switch to be placed at the first selection end, the third switch to be placed at the first selection end, and the fourth switch to be placed at the second selection end; When the delay unit is in the second closed-loop state, the adjustment signal configures the first switch to be placed at the first selection end, the second switch to be placed at the fourth selection end, the third switch to be placed at the second selection end, and the fourth switch to be placed at the first selection end; When the delay unit is in an open-loop state, the adjustment signal configures the first switch to be placed at the first selection end, the second switch to be placed at the first selection end, the third switch to be placed at the first selection end, and the fourth switch to be placed at the first selection end.

10. A memory, characterized in that: include: A clock circuit, comprising the signal generating circuit according to any one of claims 1 to 9, for generating a clock signal based on the oscillation signal; The execution circuit is connected to the clock circuit so as to be driven based on the clock signal.

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