MIPI-CPHY port clock generation circuit
By using counters and digital oscillators in MIPI-CPHY devices, the problem of long and high power consumption of phase-locked loop recovery clocks is solved, and fast recovery and low-power clock generation is achieved.
Patent Information
- Application Number
- CN202411923618.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-25
AI Technical Summary
In existing MIPI-CPHY devices, the process of phase-locked loop recovery clocks takes a long time and consumes a lot of power.
A MIPI-CPHY port clock generation circuit is designed, and the clock signal is analyzed and generated using counters and digital oscillators to quickly restore the clock signal consistent with the own clock in the transmitted data.
Shorten the clock generation time and reduce circuit power consumption.
Smart Images
Figure CN119892069A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of communication technology, relates to a clock processing technology for signal transmission, and specifically relates to a MIPI-CPHY port clock generation circuit. Background Art
[0002] MIPI protocol is a general term for a series of protocols initiated by the Mobile Industry Processor Interface Alliance. The protocol has established open standards and a unified specification for mobile application processors. Interfaces manufactured using MIPI protocol can optimize their performance, simplify the design process of intermediate links, and reduce overall development costs, creating economies of scale for interface design, while shortening product time to market.
[0003] CPHY is a high-speed interface specification for mobile devices that can provide high data throughput on bandwidth-constrained channels. The C-PHY protocol defines a high-speed and efficient interface physical layer, which is suitable for mobile devices whose channel rates are limited due to electromagnetic radiation and other reasons. By using three-phase symbol encoding, the effect of sending one symbol is equivalent to 2.28 bits of data in the signal channel of each group of three transmission lines, and the data transmission speed is improved by improving efficiency under limited signal rate constraints. CPHY is mainly used in mobile devices with limited bandwidth. Many product manufacturers use the CPHY specification to design products that comply with the MIPI mobile device interface specification, which is used to connect to peripheral devices including displays and cameras. The unified protocol interface standardizes the interface between products of different manufacturers through protocol specifications, shortens the time to market for mobile devices, and reduces design costs.
[0004] At the RX end of the mipi-cphy device that receives data, when receiving data from the mipi-cphy-tx module that sends data, it is necessary to parse the clock signal from the data. The existing technology is to use the transmission data to pass through the clock recovery module and the phase-locked loop to recover the clock signal of the transmission data, and pass it to the protocol layer for application data processing. Due to the presence of the loop filter in the phase-locked loop, it takes a long time to wait for the clock to stabilize when using the phase-locked loop to recover the clock, and the power consumption required for the phase-locked loop to work is relatively large. Summary of the invention
[0005] In view of the defects of the above-mentioned prior art, the present invention discloses a MIPI-CPHY port clock generation circuit.
[0006] The MIPI-CPHY port clock generation circuit of the present invention includes a clock recovery module and a clock analysis module connected to the output end of the clock recovery module, wherein the function of the clock analysis module is to analyze the frequency and duty cycle of the input clock signal; the clock generation circuit also includes a clock generation module connected to the output end of the clock analysis module, wherein the clock generation module includes a clock comparison control module and a digital oscillator connected to the output end of the clock comparison control module, wherein the output end of the digital oscillator is connected to the clock comparison control module and the clock analysis module; The function of the clock comparison control module is to compare the input clock signal and output the frequency word and the phase word to the digital oscillator.
[0007] Preferably, the clock analysis module is a counter, which counts the time between adjacent rising edges and falling edges, and adjacent falling edges and rising edges in the input clock signal in chronological order, and the counting adopts the system global clock signal to obtain the number of periods between adjacent rising edges and falling edges as N1, and the number of periods between adjacent falling edges and rising edges as N2. Then the period of the clock signal is (N1+N2)*T1, and the duty cycle is N1 / (N1+N2), where T1 is the period of the system global clock.
[0008] Preferably, the digital oscillator includes a first register, a second register and a phase accumulator, the second register is connected to an adder in the phase accumulator, the adder is connected to a third register in the phase accumulator, the third register and the second register are connected to a phase modulator, the phase modulator is connected to a memory, the memory is also connected to a clock sampling module and a digital-to-analog converter, the phase word and the frequency word are respectively input to the first register and the second register, the output end of the clock recovery module is also connected to the clock sampling module, and each register is an accumulator register.
[0009] Preferably, the memory is a ROM memory.
[0010] Preferably, the phase modulator is an adder.
[0011] The present invention uses a counter and a digital oscillator to analyze and generate a clock signal, and can quickly recover and generate a clock signal that is consistent with the clock contained in the transmitted data, thereby shortening the clock generation time and reducing the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 FIG. 1 is a schematic diagram of a specific implementation of the MIPI-CPHY port clock generation circuit of the present invention; Figure 2A schematic diagram of a specific method for calculating frequency and duty cycle by the clock analysis module of the present invention; Figure 3 It is a schematic diagram of a specific implementation of the clock generation module of the present invention;. DETAILED DESCRIPTION
[0013] In order to more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be given below in conjunction with specific embodiments and example drawings.
[0014] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0015] like Figure 1 As shown, data is transmitted between two different mipi-cphy devices, from the TX port of a mipi-cphy device to the RX port of another mipi-cphy device through a set of three data lines A, B, and C. After the TX module sends the data on the line, since the mipi-cphy interface transmission belongs to an embedded clock, the data on the three lines A, B, and C in the RX module are simultaneously transmitted to the clock recovery module.
[0016] In the clock recovery module, the incoming data is parsed and its embedded clock information is recovered. The obtained clock signal follows the data. When no data is transmitted, the clock signal does not exist. The clock signal can only be obtained when data is transmitted. Therefore, the obtained clock signal is unstable.
[0017] The obtained clock signal is passed to the clock analysis module (Analysis clk). In the clock analysis module, the incoming clock is analyzed, the frequency and other parameters of the clock are calculated, and the information is transmitted to the clock generation module (Generateclk). After receiving the data from the clock analysis module, the clock generation module can quickly generate a stable output clock signal that meets the requirements, and finally output it to the data processing module for subsequent data optimization.
[0018] First, the clock analysis module analyzes the original clock signal recovered by the clock recovery module to obtain the frequency and duty cycle of the original clock signal. The specific implementation method is to use a counter circuit to count the time between adjacent rising edges and falling edges, and adjacent falling edges and rising edges in the original clock signal in chronological order. The counting uses the system global clock signal and calculates the number of cycles of the system global clock, such as Figure 2 As shown, the number of periods between adjacent rising edges and falling edges is N1, and the number of periods between adjacent falling edges and rising edges is N2. The period of the original clock signal is (N1+N2)*T1, and the duty cycle is N1 / (N1+N2), where T1 is the period of the system global clock.
[0019] The clock analysis module adopts the above principle and analyzes the output clock signal output by the clock generation module to obtain the frequency and duty cycle of the current output clock signal.
[0020] The clock analysis module outputs the counter values representing the frequencies and duty cycles of the two clock signals to the clock generation module. The clock generation module includes a clock comparison control module and a digital oscillator. The clock comparison control module compares the counter values representing the frequencies and duty cycles of the two clock signals, and generates a calibrated phase word and frequency word to the digital oscillator based on the current output clock signal. The digital oscillator calibrates the phase and frequency of the output clock signal so that the frequency and phase of the output clock signal are consistent with those of the original clock signal.
[0021] like Figure 2 As shown, the original clock signal obtained from the clock recovery module and the output clock signal obtained from the clock generation module are input into the clock analysis module, and the frequency and duty cycle of the clock signal are obtained by identifying the rising edge and falling edge of the clock signal, and a counter value representing this information is output.
[0022] like Figure 3 A specific implementation of the clock generation module is shown in the figure. The counter value and the original clock signal and the output clock signal are simultaneously input into the clock comparison control module. The clock comparison control module compares the frequencies of the two clock signals and outputs the frequency word and the phase word according to the comparison result. If the frequencies of the original clock signal and the output clock signal are inconsistent, the value of the frequency word is adjusted. If the phases of the original clock signal and the output clock signal are inconsistent, the value of the phase word is adjusted. If the frequencies are consistent, the frequency word maintains a constant value. If the phases are consistent, the phase word maintains a constant value. The clock comparison control module can be implemented by programming in a computer software programming language.
[0023] The clock comparison control module outputs a phase word and a frequency word to the digital oscillator according to the comparison result. The digital oscillator changes the frequency and phase of the signal through the frequency word and the phase word.
[0024] like Figure 3 As shown, the digital oscillator includes a first register, a second register and a phase accumulator, the second register is connected to the adder in the phase accumulator, the adder is connected to the third register in the phase accumulator, the third register and the second register are connected to the phase modulator, the phase modulator is connected to the memory, the memory is also connected to a clock sampling module and a digital-to-analog converter, the phase word and the frequency word are respectively input to the first register and the second register, the output end of the clock recovery module is also connected to the clock sampling module, and each register is an accumulator register.
[0025] The digital oscillator uses the system global clock as the working clock, and the working principle is as follows: the phase word input is transmitted to the first register. The frequency word is input to the second register, and the phase accumulator connected to the second register is composed of an adder and a third register.
[0026] At each system global clock, the adder in the accumulator adds the frequency word stored in the second register to the accumulated phase data output by the third register, and the result of the addition is fed back to the data input of the third register so that the adder continues to add to the frequency word under the action of the next clock pulse. In this way, the phase accumulator continuously linearly accumulates the frequency word and stores the data in the third register of the phase accumulator.
[0027] The phase word is input into the first register, the phase modulator adds the phase word stored in the first register and the data in the third register and inputs them into a memory such as a ROM, the original clock signal is input into the clock sampling module for sampling, and the sampling value is digitized and stored in the memory in the form of a lookup table; the data output by the phase modulator is used as the phase sampling address in the lookup table, the waveform sampling value stored in the memory is looked up through the lookup table, and then converted into an output clock signal through the analog-to-digital converter DAC, the output clock signal is returned to the clock analysis module and the clock comparison control signal for feedback adjustment until the frequency and phase of the original clock signal and the output clock signal are consistent, and the frequency word and the phase word maintain constant values.
[0028] Compared with using a phase-locked loop to generate a clock, a digital oscillator can generate a clock in the data domain, which is fast, while a phase-locked loop needs to lock for a period of time when generating a clock. In addition, there are a large number of analog circuits in the phase-locked loop, such as amplifiers, oscillators and other high-power circuit modules, while a digital oscillator basically does not require analog circuits, and has lower power consumption than the phase-locked loop method of generating clocks.
[0029] The present invention uses a counter and a digital oscillator to analyze and generate a clock signal, and can quickly recover and generate a clock signal that is consistent with the clock contained in the transmitted data, thereby shortening the clock generation time and reducing the power consumption of the circuit.
[0030] The foregoing describes various preferred embodiments of the present invention. Unless the preferred implementation modes in various preferred embodiments are obviously self-contradictory or based on a certain preferred implementation mode, various preferred implementation modes can be arbitrarily superimposed and used in combination. The embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. All equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.
Claims
1. A MIPI-CPHY port clock generation circuit, comprising a clock recovery module, characterized in that , also includes a clock analysis module connected to the output end of the clock recovery module, the function of the clock analysis module is to analyze the frequency and duty cycle of the input clock signal; the clock generation circuit also includes a clock generation module connected to the output end of the clock analysis module, the clock generation module includes a clock comparison control module and a digital oscillator connected to the output end of the clock comparison control module, the output end of the digital oscillator is connected to the clock comparison control module and the clock analysis module; The function of the clock comparison control module is to compare the input clock signal and output the frequency word and the phase word to the digital oscillator.
2. The MIPI-CPHY port clock generation circuit according to claim 1, characterized in that: The clock analysis module is a counter, which counts the time between adjacent rising edges and falling edges, and adjacent falling edges and rising edges in the input clock signal in chronological order. The counting adopts the system global clock signal, and the number of cycles between adjacent rising edges and falling edges is N1, and the number of cycles between adjacent falling edges and rising edges is N2. Then the period of the clock signal is (N1+N2)*T1, and the duty cycle is N1 / (N1+N2), where T1 is the period of the system global clock.
3. The MIPI-CPHY port clock generation circuit according to claim 1, characterized in that: The digital oscillator includes a first register, a second register and a phase accumulator, the second register is connected to an adder in the phase accumulator, the adder is connected to a third register in the phase accumulator, the third register and the second register are connected to a phase modulator, the phase modulator is connected to a memory, the memory is also connected to a clock sampling module and a digital-to-analog converter, the phase word and the frequency word are respectively input to the first register and the second register, the output end of the clock recovery module is also connected to the clock sampling module, and each register is an accumulator register.
4. The MIPI-CPHY port clock generation circuit as claimed in claim 3, characterized in that: The memory is a ROM memory.
5. The MIPI-CPHY port clock generation circuit as claimed in claim 3, characterized in that: The phase modulator is an adder.