Clock synchronization method and system based on clock frequency multiplication and programmable phase-locked loop
By using clock frequency multiplication and programmable phase-locking loop technology in the closed-circuit guidance simulation system of the launch vehicle, the problem of mismatch between the clock frequency of the inertial measurement unit and the real-time simulation machine is solved, and high-precision clock synchronization is achieved, and simulation accuracy and stability are improved.
Patent Information
- Application Number
- CN202411962963.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-29
- Publication Date
- 2025-04-25
AI Technical Summary
In the semi-physical simulation experiment of closed-circuit guidance of launch vehicles, the clock frequency of the inertial measurement unit and the real-time simulation machine did not match, resulting in a synchronous offset of the clock, seriously affecting the simulation accuracy.
The clock synchronization system based on clock frequency multiplication and programmable phase-locking loop is adopted. The 100Hz differential clock signal output by the inertial measurement unit is doubled to 10000Hz, and the CDCE913 programmable phase-locking loop chip is used to achieve high-precision clock synchronization.
It realizes high-precision clock synchronization between the inertial measurement unit and the real-time simulation machine, and the clock deviation is controlled within 10 microseconds, which is suitable for complex power supply environments, significantly improving the clock synchronization performance of closed-circuit guidance simulation experiments.
Smart Images
Figure CN119892070A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of rockets, and in particular, to a clock synchronization method and system based on clock multiplication and a programmable phase-locked loop. Background Art
[0002] In the closed-loop guidance semi-physical simulation experiment of the launch vehicle, the clock synchronization between the flight control computer, the real-time simulator and the inertial unit (IMU) is a key link. The clock signal output by the inertial unit is usually a 100Hz RS422 differential signal, which is input to the flight control computer to achieve clock synchronization. However, in the actual closed-loop guidance simulation experiment, the system also includes a real-time simulator, whose model scheduling frequency requirement is 1000Hz, which is much higher than the output frequency of the inertial unit. Since the clock frequencies of the inertial unit and the simulator do not match, direct clock synchronization cannot be performed. Long-term operation will cause clock synchronization deviation. It is estimated that the clock deviation may be as high as 90ms within 1 hour, which seriously affects the simulation accuracy. The existing clock synchronization scheme is out of sync with the inertial measurement unit clock because the output frequency of the inertial measurement unit is lower than the execution frequency of the simulation model. The clock accuracy is improved by the high-precision timing card of the real-time simulator to reduce the clock drift caused by long-term operation. However, these traditional schemes usually have a decrease in clock stability with the long-term use of the high-precision timing card, resulting in serious clock drift, which is difficult to meet the synchronization requirements of high-precision simulation.
[0003] Therefore, this application proposes a system architecture design based on the output clock signal of the inertial navigation unit, which realizes clock synchronization and real-time scheduling of multiple core devices through hardware circuits and scheduling strategies, thereby improving the overall performance of the system. Summary of the invention
[0004] The present application proposes a clock synchronization system based on clock multiplication and programmable phase-locked loop, comprising: an inertial measurement unit, a flight control computer, a differential clock signal conversion unit, a clock multiplication and phase-locked processing unit and a real-time simulator; the inertial measurement unit is used to output a stable differential clock signal and input the signal to the flight control computer and the differential clock signal conversion unit; the flight control computer is used to receive the differential clock signal output by the inertial measurement unit and complete the clock synchronization between the flight control computer and the inertial measurement unit; the differential clock signal conversion unit is used to receive the differential clock signal output by the inertial measurement unit for conversion and send the converted clock signal to the clock multiplication and phase-locked processing unit; the clock multiplication and phase-locked processing unit is used to multiply the converted clock signal and send it to the real-time simulator; the real-time simulator is used to collect, count and divide the multiplied clock signal, schedule the calculation task of the real-time simulation model according to the set execution frequency, and complete the clock synchronization with the inertial measurement unit.
[0005] In the clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, the inertial measurement unit includes a high-precision clock source, and the high-precision clock source generates a 100 Hz differential clock signal.
[0006] In the clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, the differential clock signal conversion unit includes a SN65HVD30 chip.
[0007] The clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, wherein the R pin and RE pin of the SN65HVD30 chip are connected to the clock multiplication and phase-locked processing unit; the VCC pin is connected to the 3.3V power supply; the GND pin is grounded; pin A is connected to one end of the first resistor, and the other end of the first resistor is connected to the RX+ line; pin B is connected to one end of the second resistor, and the other end of the second resistor is connected to the RX- line.
[0008] In the clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, the SN65HVD30 chip also includes a first differential amplifier and a second differential amplifier.
[0009] In the clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, the differential clock signal conversion unit converts the differential clock signal into a 100 Hz TTL clock signal.
[0010] In the clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, the clock multiplication and phase-locked processing unit includes a CDCE913 phase-locked loop multiplication chip.
[0011] The clock synchronization system based on clock multiplication and programmable phase-locked loop as described above, wherein the Xin / Clk pin of the CDCE913 phase-locked loop multiplication chip is connected to the R pin of the SN65HVD30 chip; the S0 pin is grounded; the Vdd pin is connected to a 1.8V power supply, the Vctr pin is connected to one end of a resistor R27, and the other end of the resistor R27 is connected to a 1.8V power supply; one end of the resistor R27 is also connected to one end of a capacitor C6, and the other end of the capacitor C6 is grounded; both GND pins of the chip are grounded; both Vddout pins are connected to a 3.3V power supply; the S1 / SDA and S2 / SCL pins are brought out through connectors; and the Y1 pin is connected to an implementation simulation machine.
[0012] In the clock synchronization system based on clock frequency multiplication and programmable phase-locked loop as described above, the clock frequency multiplication and phase-locked processing unit multiplies the converted 100 Hz TTL clock signal into a 10000 Hz TTL clock signal.
[0013] A clock synchronization method based on clock multiplication and a programmable phase-locked loop comprises the following steps: generating a differential clock signal; sending the generated differential clock signal to a flight control computer to complete clock synchronization; performing signal conversion on the generated differential clock signal; multiplying the converted clock signal; collecting, counting and dividing the multiplied clock signal, scheduling the computing task of a real-time simulation model according to a set execution frequency to complete clock synchronization.
[0014] This application has the following beneficial effects:
[0015] This application realizes high-precision clock synchronization between the inertial measurement unit and the real-time simulator through a programmable phase-locked loop and a high-precision clock multiplication circuit. Through the programmable characteristics of CDCE913, the clock frequency can be flexibly adjusted according to the requirements of different simulation tasks to ensure that the clock deviation is controlled within 10 microseconds, and it is insensitive to power supply noise, suitable for applications in complex power supply environments. The clock synchronization performance of the system in closed-loop guidance simulation experiments has been significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0017] Figure 1 It is a schematic diagram of the internal structure of a clock synchronization system based on clock multiplication and a programmable phase-locked loop provided according to an embodiment of the present application;
[0018] Figure 2 is a schematic diagram of the principle of a differential clock signal conversion unit provided according to an embodiment of the present application;
[0019] Figure 3 It is a schematic diagram of the principle of a clock multiplication and phase locking processing unit provided according to an embodiment of the present application;
[0020] Figure 4 It is a flow chart of a clock synchronization method based on clock multiplication and a programmable phase-locked loop provided according to an embodiment of the present application. DETAILED DESCRIPTION
[0021] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0022] The present application provides a clock synchronization method and system based on clock multiplication and programmable phase-locked loop, which converts and multiplies the 100Hz differential clock signal of the inertial measurement unit to 10000Hz to meet the high-frequency scheduling requirements of the real-time simulator. The present invention particularly uses the programmable phase-locked loop chip CDCE913, which makes the clock multiplication scheme highly flexible and ensures high-precision synchronization in a complex power supply environment, with a clock deviation of no more than 10 microseconds.
[0023] Embodiment 1
[0024] like Figure 1 As shown, the internal structure diagram of the clock synchronization system based on clock multiplication and programmable phase-locked loop provided in this embodiment specifically includes: an inertial measurement unit 110, a flight control computer 120, a differential clock signal conversion unit 130, a clock multiplication and phase-locked processing unit 140 and a real-time simulator 150.
[0025] The inertial measurement unit 110 is used to output a stable differential clock signal, and input the signal to the flight control computer 120 and the differential clock signal conversion unit 130 .
[0026] Specifically, the inertial measurement unit 110 contains a high-precision clock source that can generate a stable 100Hz RS422 differential clock signal. The differential clock signal is also used for the clock synchronization output of the onboard control device to ensure that the clock of the inertial measurement unit itself and other onboard devices (such as the flight control computer) are consistent.
[0027] The flight control computer 120 is connected to the inertial measurement unit 110 and is used to receive the differential clock signal output by the inertial measurement unit 110 to complete the clock synchronization between the flight control computer and the inertial measurement unit.
[0028] The aircraft control computer 120 internally supports the conversion process between the differential clock signal and the TTL clock signal. The execution frequency of the flight control computer is 100 Hz, which is consistent with the output clock of the inertial measurement unit.
[0029] The differential clock signal conversion unit 130 is connected to the inertial measurement unit 110 , and is used to receive the differential clock signal output by the inertial measurement unit 110 , perform conversion, and send the converted clock signal to the clock multiplication and phase locking processing unit 140 .
[0030] The differential clock signal conversion unit is the SN65HVD30 chip. The SN65HVD30 is a high-performance differential signal conversion chip that requires a 3.3V power supply and converts the clock signal into a 3.3V TTL output. It has strong power supply noise immunity and is suitable for subsequent frequency multiplication circuit processing.
[0031] Specifically, the 100Hz RS422 differential clock signal output by the inertial measurement unit is converted into a 100Hz 3.3V TTL clock signal by the SN65HVD30 chip.
[0032] like Figure 2 As shown, it is the circuit schematic diagram of the SN65HVD30 chip. The R pin and RE pin of the SN65HVD30 chip are connected to the clock multiplication and phase-locked processing unit; the VCC pin is connected to the 3.3V power supply; the GND pin is grounded; the pin A is connected to one end of the first resistor, and the other end of the first resistor is connected to the RX+ line; the pin B is connected to one end of the second resistor, and the other end of the second resistor is connected to the RX- line.
[0033] The clock frequency multiplication and phase locking processing unit 140 is connected to the differential clock signal conversion unit 130 , and is used to multiply the converted clock signal and send it to the real-time simulator 150 .
[0034] The clock multiplication and phase-locked processing unit is a CDCE913 phase-locked loop multiplication chip. CDCE913 is a programmable phase-locked loop chip, and users can flexibly configure its output frequency according to system requirements. Through programming, it can ensure that the system adjusts the clock frequency and phase-locked loop settings under different simulation tasks to meet the needs of various scenarios. This chip supports 3.3V power supply, is insensitive to power supply noise, and ensures the stability of the clock signal. Its design ensures that the multiplication output can be maintained stably even when the power supply ripple is large. At the same time, the power supply design of the chip is simple, avoiding the additional power management burden on the system.
[0035] Specifically, the converted 100Hz 3.3V TTL clock signal passes through a CDCE913 phase-locked loop frequency multiplication chip and is multiplied to a 10000Hz TTL clock signal.
[0036] like Figure 3As shown in the figure, it is the circuit schematic diagram of CDCE913 chip. The Xin / Clk pin of the chip is connected to the R pin of SN65HVD30; the S0 pin needs to be grounded, and the chip is configured as phase-locked loop output working mode. The Vdd pin is connected to the 1.8V power supply, the Vctr pin is connected to one end of the resistor R27, and the other end of the resistor R27 is connected to the 1.8V power supply; one end of the resistor R27 is also connected to one end of the capacitor C6, and the other end of the capacitor C6 is grounded; the two GND pins of the chip are grounded; the two Vddout pins are connected to the 3.3V power supply; the Xout pin is left floating and not used. The S1 / SDA and S2 / SCL pins need to be brought out through the connector for clock multiplication multiple control. The Y1 pin is connected to the implementation simulator; the Y2 and Y3 pins will also output the same square wave as the Y1 pin in practice, and are left floating and not used in practice.
[0037] The CDCE913 chip is connected to the SN65HVD30 chip to form a differential clock signal frequency multiplication circuit. When the 100Hz differential clock is multiplied to 10000Hz, the clock jitter is mainly affected by the jitter introduced by the PLL of the CDCE913. The CDCE913 has a low phase noise level, and its clock output jitter after frequency multiplication can be maintained below 50ps. At the same time, the chip is less sensitive to power supply noise and can maintain a stable clock output in a more complex power supply environment. In actual use, the reference clock jitter when the 100Hz frequency is multiplied to 10kHz can be controlled within 1 microsecond, while the clock jitter generated by the real-time operating system installed in the real-time simulator during its scheduling process ranges from 0 to 10 microseconds. Therefore, the clock jitter generated by the frequency multiplication circuit does not have much impact on the real-time performance of the real-time simulation system.
[0038] In addition, there is a propagation delay from the input to the output of the SN65HVD30, which is usually between 15ns and 50ns (typical value is about 30ns), and the phase delay introduced by the CDCE913 phase-locked loop is between 100ps and 500ps, so the total delay time generated by the synchronization system does not exceed 50ns.
[0039] The real-time simulation machine 150 is connected to the clock multiplication and phase-locked processing unit 140, and is used to receive the 10000 Hz square wave (i.e., 10000 Hz clock signal) or other frequency square waves generated by the clock multiplication and phase-locked processing unit 140, collect and count the received square waves and perform frequency division, and schedule the computing tasks of the real-time simulation model according to the set execution frequency to complete the clock synchronization with the inertial measurement unit 110.
[0040] The received square wave signal is collected, counted and divided by the timing counter board of the real-time simulator, and the calculation task of the real-time simulation model is scheduled according to the set execution frequency to complete the clock synchronization with the inertial measurement unit 110.
[0041] In the actual closed-loop guidance semi-physical simulation experiment, this system was used to synchronize the clocks of the inertial measurement unit and the simulator. Through the combination of SN65HVD30 and CDCE913, the 100Hz clock signal of the inertial measurement unit was successfully multiplied to 10kHz and synchronized to the simulator. The long-term running experiment (24 hours) showed that the clock synchronization error was controlled within 10 microseconds, which significantly improved the accuracy and stability of the simulation system.
[0042] Embodiment 2
[0043] like Figure 4 As shown, the clock synchronization method based on clock multiplication and programmable phase-locked loop provided in this embodiment specifically includes the following steps:
[0044] Step S410: Generate a differential clock signal.
[0045] The IMU contains a high-precision clock source that can generate a stable 100Hz RS422 differential clock signal. This differential clock signal is also used for the clock synchronization output of the onboard control device to ensure that the clocks of the IMU itself and other onboard devices (such as the flight control computer) are consistent.
[0046] Step S420: Send the generated differential clock signal to the flight control computer to complete clock synchronization.
[0047] The clock signal output by the inertial measurement unit is directly input into the flight control computer to complete the clock synchronization between the flight control computer and the inertial measurement unit. The aircraft control computer supports the conversion process between differential clock signals and TTL clock signals. The execution frequency of the flight control computer is 100Hz, which is consistent with the output clock of the inertial measurement unit.
[0048] Step S430: performing signal conversion on the generated differential clock signal.
[0049] The differential clock signal conversion unit receives the differential clock signal output by the inertial measurement unit for conversion.
[0050] The differential clock signal conversion unit is the SN65HVD30 chip. The SN65HVD30 is a high-performance differential signal conversion chip that requires a 3.3V power supply and converts the clock signal into a 3.3V TTL output. It has strong power supply noise immunity and is suitable for subsequent frequency multiplication circuit processing.
[0051] Specifically, the converted clock signal is a 100 Hz 3.3V TTL clock signal.
[0052] like Figure 2 As shown, it is the circuit schematic diagram of the SN65HVD30 chip. The R pin and RE pin of the SN65HVD30 chip are connected to the clock multiplication and phase-locked processing unit; the VCC pin is connected to the 3.3V power supply; the GND pin is grounded; the pin A is connected to one end of the first resistor, and the other end of the first resistor is connected to the RX+ line; the pin B is connected to one end of the second resistor, and the other end of the second resistor is connected to the RX- line.
[0053] Step S440: multiplying the converted clock signal.
[0054] The clock multiplication and phase-locked processing unit multiplies the converted clock signal, and the clock multiplication and phase-locked processing unit is a CDCE913 phase-locked loop multiplication chip. CDCE913 is a phase-locked loop chip with programmable functions, and users can flexibly configure its output frequency according to system requirements. Through programming, it can be ensured that the system adjusts the clock frequency and phase-locked loop settings under different simulation tasks to meet the needs of various scenarios. This chip supports 3.3V power supply, is insensitive to power supply noise, and ensures the stability of the clock signal. Its design ensures that stable multiplication output can be maintained even when the power supply ripple is large. At the same time, the power supply design of the chip is simple, avoiding the additional power management burden on the system.
[0055] Specifically, the converted 100Hz 3.3V TTL clock signal passes through the CDCE913 phase-locked loop frequency multiplication chip, multiplies it to a 10000Hz TTL clock signal and sends it to the real-time simulator.
[0056] like Figure 3 As shown in the figure, it is the circuit schematic diagram of CDCE913 chip. The Xin / Clk pin of the chip is connected to the R pin of SN65HVD30; the S0 pin needs to be grounded, and the chip is configured as phase-locked loop output working mode. The Vdd pin is connected to the 1.8V power supply, the Vctr pin is connected to one end of the resistor R27, and the other end of the resistor R27 is connected to the 1.8V power supply; one end of the resistor R27 is also connected to one end of the capacitor C6, and the other end of the capacitor C6 is grounded; the two GND pins of the chip are grounded; the two Vddout pins are connected to the 3.3V power supply; the Xout pin is left floating and not used. The S1 / SDA and S2 / SCL pins need to be brought out through the connector for clock multiplication multiple control. The Y1 pin is connected to the implementation simulator; the Y2 and Y3 pins will also output the same square wave as the Y1 pin in practice, and are left floating and not used in practice.
[0057] Step S450: collect, count and divide the multiplied clock signal, schedule the computing task of the real-time simulation model according to the set execution frequency, and complete clock synchronization.
[0058] The real-time simulator receives the TTL clock signal multiplied to 10000Hz for collection, counting and frequency division, and schedules the calculation tasks of the real-time simulation model according to the set execution frequency to complete the clock synchronization with the inertial measurement unit.
[0059] This application has the following beneficial effects:
[0060] This application realizes high-precision clock synchronization between the inertial measurement unit and the real-time simulator through a programmable phase-locked loop and a high-precision clock multiplication circuit. Through the programmable characteristics of CDCE913, the clock frequency can be flexibly adjusted according to the requirements of different simulation tasks to ensure that the clock deviation is controlled within 10 microseconds, and it is insensitive to power supply noise, suitable for applications in complex power supply environments. The clock synchronization performance of the system in closed-loop guidance simulation experiments has been significantly improved.
[0061] Although the present application is described with reference to examples, this is for illustrative purposes only and is not intended to limit the present application, and changes, additions and / or deletions to the embodiments may be made without departing from the scope of the present application.
[0062] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A clock synchronization system based on clock multiplication and programmable phase-locked loop, characterized in that: include: Inertial measurement unit, flight control computer, differential clock signal conversion unit, clock multiplication and phase-locked processing unit, and real-time simulator; An inertial measurement unit, used to output a stable differential clock signal and input the signal to a flight control computer and a differential clock signal conversion unit; The flight control computer is used to receive the differential clock signal output by the inertial measurement unit and complete the clock synchronization between the flight control computer and the inertial measurement unit; A differential clock signal conversion unit, used for receiving the differential clock signal output by the inertial measurement unit for conversion, and sending the converted clock signal to the clock multiplication and phase locking processing unit; A clock frequency multiplication and phase-locking processing unit, used for multiplying the converted clock signal and sending it to the real-time simulation machine; The real-time simulation machine is used to collect, count and divide the multiplied clock signal, schedule the calculation tasks of the real-time simulation model according to the set execution frequency, and complete the clock synchronization with the inertial measurement unit.
2. The clock synchronization system based on clock multiplication and programmable phase-locked loop according to claim 1, characterized in that: The inertial measurement unit contains a high-precision clock source that generates a 100Hz differential clock signal.
3. The clock synchronization method based on clock multiplication and programmable phase-locked loop according to claim 1, characterized in that: The differential clock signal conversion unit includes a SN65HVD30 chip.
4. The clock synchronization method based on clock multiplication and programmable phase-locked loop according to claim 3, characterized in that: The R pin and RE pin of the SN65HVD30 chip are connected to the clock multiplication and phase-locked processing unit; the VCC pin is connected to the 3.3V power supply; the GND pin is grounded; pin A is connected to one end of the first resistor, and the other end of the first resistor is connected to the RX+ line; pin B is connected to one end of the second resistor, and the other end of the second resistor is connected to the RX- line.
5. The clock synchronization method based on clock multiplication and programmable phase-locked loop according to claim 3, characterized in that: The SN65HVD30 chip also includes a first differential amplifier and a second differential amplifier.
6. The clock synchronization system based on clock multiplication and programmable phase-locked loop according to any one of claims 3 to 5, characterized in that: The differential clock signal conversion unit converts the differential clock signal into a 100 Hz TTL clock signal.
7. The clock synchronization system based on clock multiplication and programmable phase-locked loop according to claim 1, characterized in that: The clock frequency multiplication and phase-locked processing unit includes a CDCE913 phase-locked loop frequency multiplication chip.
8. The clock synchronization system based on clock multiplication and programmable phase-locked loop according to claim 6, characterized in that: The Xin / Clk pin of the CDCE913 phase-locked loop multiplier chip is connected to the R pin of the SN65HVD30 chip; the S0 pin is grounded; the Vdd pin is connected to a 1.8V power supply, the Vctr pin is connected to one end of a resistor R27, and the other end of the resistor R27 is connected to a 1.8V power supply; one end of the resistor R27 is also connected to one end of a capacitor C6, and the other end of the capacitor C6 is grounded; both GND pins of the chip are grounded; both Vddout pins are connected to a 3.3V power supply; the S1 / SDA and S2 / SCL pins are brought out through connectors; and the Y1 pin is connected to the implementation simulation machine.
9. The clock synchronization system based on clock multiplication and programmable phase-locked loop according to any one of claims 7 to 8, characterized in that: The clock frequency multiplication and phase-locked processing unit multiplies the converted 100 Hz TTL clock signal into a 10000 Hz TTL clock signal.
10. A clock synchronization method based on clock multiplication and programmable phase-locked loop, characterized in that: The following steps are involved: generating a differential clock signal; Send the generated differential clock signal to the flight control computer to complete clock synchronization; Performing signal conversion on the generated differential clock signal; Multiplying the converted clock signal; The multiplied clock signal is collected, counted and divided, and the computing tasks of the real-time simulation model are scheduled according to the set execution frequency to complete clock synchronization.