High-precision dynamic comparator with offset voltage automatic calibration circuit

Abstract

The invention relates to a high-precision dynamic comparator with an offset voltage automatic calibration circuit, which adopts a switched capacitor preamplifier, so that the comparator applied to a FLASH ADC (Analog to Digital Converter) does not cause different DC (Direct Current) parameters due to different common-mode voltages, thereby reducing the offset voltage between different comparators; and a substrate voltage bias technology is adopted, so that the resistance of the sampling switch is smaller when the sampling switch is switched on, and the resistance is larger when the sampling switch is switched off. And an offset voltage automatic calibration circuit ACC is adopted, so that the circuit can adaptively adjust the offset voltage according to a process error in a manufacturing process. Compared with a traditional comparator, the comparator adopts a design form of a switched capacitor comparator, so that an input signal of the comparator is close to a common-mode voltage VCM, it is ensured that each comparator does not have an offset voltage error caused by different DC parameters due to different common-mode voltages, and the offset voltage automatic calibration circuit ACC enables the offset voltage of the comparator to be smaller.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuit design and relates to a high-precision dynamic comparator with an offset voltage automatic calibration circuit. Background Art

[0002] Dynamic high-precision comparators are key components in modern electronic technology, especially in ADC (analog-to-digital converter). Dynamic comparators are a circuit that compares voltages. They use different input signals to make the output stage circuit discharge at different speeds, and introduce a positive feedback to further accelerate the discharge speed to achieve the comparison effect. However, due to the mismatch in the manufacturing process, the comparator comparison threshold will inevitably deviate, which is unacceptable in high-precision comparators. Therefore, how to achieve a high-precision dynamic comparator with offset voltage self-calibration function has become a technical problem to be solved. Summary of the invention

[0003] In view of the problems existing in the above-mentioned conventional technology, the present invention proposes a high-precision dynamic comparator with an offset voltage automatic calibration circuit, which can realize a high-precision dynamic comparator with an offset voltage self-calibration function.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: Provided is a high-precision dynamic comparator with an offset voltage automatic calibration circuit, comprising a signal sampling circuit, a preamplifier and a dynamic latch, wherein the signal sampling circuit is based on a gate voltage bootstrap circuit BTSP and is designed using a substrate voltage bias technology, and the dynamic latch comprises a latch LAT, an offset voltage automatic calibration circuit ACC and a dynamic comparator; The sampling input end of the signal sampling circuit is used to access the input signal to be sampled and the reference signal, the output end of the signal sampling circuit is connected to the input end of the preamplifier, the output end of the preamplifier is connected to the input end of the dynamic comparator, the output end of the dynamic comparator is respectively connected to the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC, and the output end of the offset voltage automatic calibration circuit ACC is connected to the calibration input end of the dynamic comparator; The signal sampling circuit is used to sample the input signal and the reference signal, the preamplifier is used to preamplify the sampled output of the signal sampling circuit, the offset voltage automatic calibration circuit ACC is used to adaptively reduce the offset voltage of the dynamic comparator according to the process error in the manufacturing process, the dynamic comparator is used to perform data comparison, and the latch LAT is used to control whether the output signal of the dynamic comparator changes with the change of the input signal.

[0005] In one embodiment, the signal sampling circuit includes an inverter INV0, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a gate voltage bootstrap circuit BTSP, a transistor NMOS0, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor NMOS4, a transistor NMOS5, a transistor NMOS6, a transistor NMOS7, a transistor PMOS0, a capacitor C0 and a capacitor C1; The PHI terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP through the inverter INV0, the PHIB terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP, the VIN terminal of the gate voltage bootstrap circuit BTSP is used to access the input signal VSIG, and the OUT terminal of the gate voltage bootstrap circuit BTSP is connected to the gate of the transistor NMOS0 and the gate of the transistor NMOS1 respectively; The drain of transistor NMOS0 is connected to the drain of transistor NMOS1 and is used to access the input signal VSIG, the substrate of transistor NMOS0 is respectively connected to the source of transistor NMOS1 and the drain of transistor NMOS2, the source of transistor NMOS0 is connected to one end of capacitor C0, the gate of transistor NMOS2 is used to access the control signal VSAMP, the source of transistor NMOS2 is grounded, the drain of transistor NMOS3 is connected to the drain of transistor PMOS0 and is used to access the reference signal VREF, the source of transistor NMOS3 is connected to the source of transistor PMOS0 and connected to one end of capacitor C0, the other end of capacitor C0 is connected to the first input end of the preamplifier, inverter INV1, inverter INV2 and inverter INV3 are connected in series in sequence, the input end of inverter INV1 is used to access the input signal PHIB, the output end of inverter INV3 is connected to the gate of transistor PMOS0, and the gate of transistor NMOS3 is connected to the output end of inverter INV2; Inverter INV4 and inverter INV5 are connected in series, the input end of inverter INV4 is used to access the input signal NCON2, the output end of inverter INV5 is connected to the gate of transistor NMOS5, the drain of transistor NMOS4 and the drain of transistor NMOS5 are both connected to one end of capacitor C1, the drain of transistor NMOS6 is connected to the other end of capacitor C1, the other end of capacitor C1 is connected to the second input end of the preamplifier, the gate of transistor NMOS4 is connected to the output end of inverter INV0, the source of transistor NMOS4 is used to access the signal VSS, the source of transistor NMOS5 is used to access the reference signal VREFN, the gate of transistor NMOS6 is used to access the input signal PHIB, the substrate of transistor NMOS6 is used to access the signal VSS, the source of transistor NMOS6 and the source of transistor NMOS7 are both used to access the signal VCM, the drain of transistor NMOS7 is connected to the other end of capacitor C0, the substrate of transistor NMOS7 is used to access the signal VSS, and the gate of transistor NMOS7 is used to access the input signal NCON2.

[0006] In one embodiment, the preamplifier includes a transistor NMOS8, a transistor NMOS9, a transistor NMOS10, a transistor NMOS11, and a transistor NMOS12; The gate of transistor NMOS8 is used to access the bias voltage VBIAS, the source of transistor NMOS8 is grounded, the drain of transistor NMOS8 is respectively connected to the source of transistor NMOS9 and the source of transistor NMOS10, the substrate of transistor NMOS9 is connected to the substrate of transistor NMOS10 and is used to access the signal VSS, the gate of transistor NMOS9 is connected to the first output end of the signal sampling circuit, the gate of transistor NMOS10 is connected to the second output end of the signal sampling circuit, the drain of transistor NMOS9 is connected to the drain of transistor NMOS11 and is connected to the first input end of the dynamic comparator, the drain of transistor NMOS10 is connected to the drain of transistor NMOS12 and is connected to the second input end of the dynamic comparator, the source of transistor NMOS11 is connected to the source of transistor NMOS12 and is used to access the power supply voltage VDD, and the gate of transistor NMOS11 is connected to the gate of transistor NMOS12 and is used to access the power supply voltage VDD.

[0007] In one embodiment, the dynamic comparator in the dynamic latch includes an inverter INV6, an inverter INV7, a NOR gate NOR1, a NOR gate NOR2, a transistor NMOS13, a transistor NMOS14, a transistor NMOS15, a transistor NMOS16, a transistor NMOS17, a transistor PMOS1, a transistor PMOS2, a transistor PMOS3, a transistor PMOS4, a transistor PMOS5, a transistor PMOS6, a transistor PMOS7, a transistor PMOS8, a transistor PMOS9, a transistor PMOS10, a transistor PMOS11, a transistor PMOS12, a transistor PMOS13 and a transistor PMOS14; The gate of transistor NMOS17 is used to access the clock signal CLK, the source of transistor NMOS17 is grounded, the drain of transistor NMOS17 is respectively connected to the source of transistor NMOS13 and the source of transistor NMOS14, the gate of transistor NMOS13 is connected to the second output terminal of the preamplifier, the gate of transistor NMOS14 is connected to the first output terminal of the preamplifier, the substrate of transistor NMOS13 and the substrate of transistor NMOS14 are both used to access the signal VSS, the drain of transistor NMOS13 is connected to the drain of transistor NMOS15, the drain of transistor NMOS14 is connected to the drain of transistor NMOS16, and the substrate of transistor NMOS15 and the substrate of transistor NMOS16 are both used to access the signal VSS; The source of transistor NMOS15, the drain of transistor PMOS2, the drain of transistor PMOS1, the gate of transistor PMOS3 and the gate of transistor NMOS16 are connected, the source of transistor NMOS16, the drain of transistor PMOS3, the drain of transistor PMOS4, the gate of transistor PMOS2 and the gate of transistor NMOS15 are connected, the source of transistor PMOS1, the source of transistor PMOS2, the source of transistor PMOS3 and the source of transistor PMOS4 are all used to access the power supply voltage VDD, the gate of transistor PMOS1 and the gate of transistor PMOS4 are connected. The gate of S4 is used to access the clock signal CLK, the input end of the inverter INV6 is connected to the drain of the transistor PMOS2, the input end of the inverter INV7 is connected to the drain of the transistor PMOS3, the output end of the inverter INV6 is connected to the first input end of the NOR gate NOR1, the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR2, the output end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR2, and the output end of the NOR gate NOR2 is respectively connected to the second input end of the NOR gate NOR1, the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC; The gates of transistors PMOS5 to PMOS9 are connected and connected to the drain of transistor NMOS15, the gates of transistors PMOS10 to PMOS14 are connected and connected to the drain of transistor NMOS16, the substrates of transistors PMOS5 to PMOS14 are used to access the power supply voltage VDD, the source and drain of transistor PMOS5 are connected, the source and drain of transistor PMOS6 are connected, the source and drain of transistor PMOS7 are connected, the source and drain of transistor PMOS9 are connected, the sources of transistors PMOS5 to PMOS9 are respectively connected to the right output end of the offset voltage automatic calibration circuit ACC, the source and drain of transistor PMOS10 are connected, the source and drain of transistor PMOS11 are connected, the source and drain of transistor PMOS12 are connected, the source and drain of transistor PMOS13 are connected, the source and drain of transistor PMOS14 are connected, and the sources of transistors PMOS10 to PMOS14 are respectively connected to the left output end of the offset voltage automatic calibration circuit ACC.

[0008] In one embodiment, the offset voltage automatic calibration circuit ACC includes INCNDEC units 0 to INCNDEC units 9, D flip-flops 0 to D flip-flops 9, a left output gate circuit and a right output gate circuit, and the INCNDEC units correspond to the D flip-flops 9 one by one; The clock end of each D flip-flop is used to access the offset voltage calibration clock signal, the reset end of each D flip-flop is used to access the offset voltage automatic calibration reset signal, the D end of each D flip-flop is connected to the S end of the corresponding INCNDEC unit, the Q end of each D flip-flop is connected to the B end of the corresponding INCNDEC unit, the DEC end of INCNDEC unit 0 to INCNDEC unit 4 is connected to the output end of the NOR gate NOR2, INCNDEC unit 0 to INCNDEC unit 4 are cascaded with the Cin end through the CB end in turn, and the CB end of INCNDEC unit 4 is left floating; The DEC terminals of INCNDEC units 5 to INCNDEC units 9 are all connected to the output terminal of NOR gate NOR2 through inverter INV12, and INCNDEC units 5 to INCNDEC units 9 are cascaded with Cin terminals through CB terminals in sequence, and the CB terminal of INCNDEC unit 9 is suspended; The output end of the left output gate circuit is connected to the Cin end of INCNDEC unit 0, and the input end of the left output gate circuit is respectively connected to the source of transistor PMOS10, transistor PMOS11, transistor PMOS12, transistor PMOS13 and transistor PMOS14. The output end of the right output gate circuit is connected to the Cin end of INCNDEC unit 5, and the input end of the right output gate circuit is respectively connected to the drain of transistor PMOS5, transistor PMOS6, transistor PMOS7, transistor PMOS8 and transistor PMOS9.

[0009] In one embodiment, the right output gate circuit includes an inverter INV8, an inverter INV9, a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, a NAND gate NAND4, a NAND gate NAND5, a NAND gate NAND6, a NOR gate NOR3, a NOR gate NOR4, a NOR gate NOR5 and a NOR gate NOR6, and the left output gate circuit includes an inverter INV10, an inverter INV11, a NAND gate NAND7, a NAND gate NAND8, a NAND gate NAND9, a NAND gate NAND10, a NAND gate NAND11, a NAND gate NAND12, a NOR gate NOR7, a NOR gate NOR8, a NOR gate NOR9 and a NOR gate NOR10; The input ends of the NAND gate NAND1, the NAND gate NAND2, the NOR gate NOR3 and the NOR gate NOR4 serve as the input ends of the right output gate circuit, the two input ends of the NOR gate NOR5 are respectively connected to the output end of the NAND gate NAND1 and the output end of the NAND gate NAND2, the output end of the NOR gate NOR5 is connected to the first input end of the NAND gate NAND4, the two input ends of the NAND gate NAND3 are respectively connected to the output ends of the NOR gate NOR3 and the NOR gate NOR4, the other input end of the NAND gate NAND3 is connected to the Q inverting end of the D flip-flop 9, the output end of the NAND gate NAND3 is respectively connected to one input end of the NOR gate NOR6 and one input end of the NAND gate NAND11, and the other input end of the NOR gate NOR6 is connected to the Q inverting end of the D flip-flop 9. The input end is connected to the output end of the NOR gate NOR2, the output end of the NOR gate NOR6 is connected to the input end of the inverter INV8, one input end of the NAND gate NAND5 is connected to the output end of the NOR gate NOR2, the other input end of the NAND gate NAND5 is connected to the output end of the NAND gate NAND9, the second input end of the NAND gate NAND4 is connected to the Q end of the D flip-flop 9, the third input end of the NAND gate NAND4 is connected to the output end of the NOR gate NOR2, the three input ends of the NAND gate NAND6 are respectively connected to the output ends of the NAND gate NAND4, the NAND gate NAND5 and the inverter INV8, and the output end of the NAND gate NAND6 is connected to the Cin end of the INCNDEC unit 5 through the inverter INV9; The input ends of the NAND gate NAND7, the NAND gate NAND8, the NOR gate NOR7 and the NOR gate NOR8 serve as the input ends of the left output gate circuit, the two input ends of the NOR gate NOR9 are respectively connected to the output ends of the NAND gate NAND7 and the output end of the NAND gate NAND8, the output end of the NOR gate NOR9 is connected to the first input end of the NAND gate NAND10, the two input ends of the NAND gate NAND9 are respectively connected to the output ends of the NOR gate NOR7 and the NOR gate NOR8, the other input end of the NAND gate NAND9 is connected to the Q inverting end of the D flip-flop 4, the output ends of the NAND gate NAND9 are respectively connected to one input end of the NOR gate NOR10 and the other input end of the NOR gate NOR10 An input end is connected to the output end of the inverter INV12, the output end of the NOR gate NOR10 is connected to the input end of the inverter INV10, another input end of the NAND gate NAND11 is connected to the output end of the inverter INV12, the second input end of the NAND gate NAND10 is connected to the Q end of the D flip-flop 4, the third input end of the NAND gate NAND10 is connected to the output end of the inverter INV12, the three input ends of the NAND gate NAND12 are respectively connected to the output ends of the NAND gate NAND10, the NAND gate NAND11 and the inverter INV10, and the output end of the NAND gate NAND12 is connected to the Cin end of the INCNDEC unit 0 through the inverter INV11.

[0010] In one embodiment, the INCNDEC unit includes an XOR gate XOR0, an XOR gate XOR1, a NAND gate NAND13, and an inverter INV13. The first input end of the XOR gate XOR0 is used as a DEC end, the second input end of the XOR gate XOR0 is connected to the second input end of the XOR gate XOR1 as a B end, the output end of the XOR gate XOR0 is connected to the first input end of the NAND gate NAND13, the second input end of the NAND gate NAND13 is connected to the first input end of the XOR gate XOR1 as a Cin end, the output end of the NAND gate NAND13 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is used as a CB end, and the output end of the XOR gate XOR1 is used as an S end.

[0011] One of the above technical solutions has the following advantages and beneficial effects: The high-precision dynamic comparator with automatic offset voltage calibration circuit adopts a switched capacitor preamplifier, so that the comparator applied to the FLASH (flash memory) ADC will not have different DC parameters due to different common mode voltages, thereby reducing the offset voltage between different comparators; and adopts substrate voltage bias technology, so that the sampling switch has a smaller resistance when it is turned on and a larger resistance when it is turned off. The offset voltage automatic calibration circuit ACC is adopted so that the circuit can adaptively adjust the offset voltage according to the process error in the manufacturing process. Compared with the traditional comparator, the design form of the switched capacitor comparator is adopted, so that the comparator input signal is near the common mode voltage VCM, ensuring that each comparator will not have an offset voltage error caused by different DC parameters due to different common mode voltages, and the offset voltage automatic calibration circuit ACC is adopted to make the offset voltage of the comparator smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of the module structure of a high-precision dynamic comparator with an automatic offset voltage calibration circuit in one embodiment; Figure 2 A schematic diagram of the first circuit structure of a high-precision dynamic comparator with an automatic offset voltage calibration circuit in one embodiment; Figure 3 A schematic diagram of the second circuit structure of a high-precision dynamic comparator with an automatic offset voltage calibration circuit in one embodiment; Figure 4 A schematic diagram of the third circuit structure of a high-precision dynamic comparator with an automatic offset voltage calibration circuit in one embodiment; Figure 5 It is a schematic diagram of the structure of the first part of an automatic offset voltage calibration circuit ACC in one embodiment; Figure 6 It is a schematic diagram of the structure of the second part of the automatic offset voltage calibration circuit ACC in one embodiment; Figure 7 FIG. 1 is a schematic diagram of the structure of an INCDEC unit in an automatic offset voltage calibration circuit ACC in an embodiment. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0015] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0016] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0017] In one embodiment, Figure 1 As shown, a high-precision dynamic comparator with an offset voltage automatic calibration circuit is provided, including a signal sampling circuit 11, a preamplifier 13 and a dynamic latch 15. The signal sampling circuit 11 is based on a gate voltage bootstrap circuit BTSP and is designed using substrate voltage bias technology. The dynamic latch 15 includes a latch LAT, an offset voltage automatic calibration circuit ACC and a dynamic comparator. The sampling input end of the signal sampling circuit 11 is used to access the input signal to be sampled and the reference signal, the output end of the signal sampling circuit 11 is connected to the input end of the preamplifier 13, the output end of the preamplifier 13 is connected to the input end of the dynamic comparator, the output end of the dynamic comparator is respectively connected to the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC, and the output end of the offset voltage automatic calibration circuit ACC is connected to the calibration input end of the dynamic comparator. The signal sampling circuit 11 is used to sample the input signal and the reference signal. The preamplifier 13 is used to preamplify the sampled output of the signal sampling circuit 11, and the offset voltage automatic calibration circuit ACC is used to adaptively reduce the offset voltage of the dynamic comparator according to the process error in the manufacturing process. The dynamic comparator is used for data comparison, and the latch LAT is used for controlling whether the output signal of the dynamic comparator changes with the change of the input signal.

[0018] It can be understood that the signal sampling circuit 11 in this embodiment is mainly used to sample and output various input signals (such as the common ground voltage signal VSS, the input signal VSIG and the common mode voltage signal VCM in the art) and reference signals (such as the reference voltage VREF and the reference signal VREFN in the art). It adopts the gate voltage bootstrap circuit BTSP to perform sampling control and the substrate voltage bias technology, so that the sampling switch in the signal sampling circuit 11 has a smaller resistance when it is turned on and a larger resistance when it is turned off. For this purpose, those skilled in the art can use MOS transistor devices with inverters and gate voltage bootstrap circuits BTSP to design and obtain the required signal sampling circuit 11. There can be many specific circuit structures as long as they can be used to provide the required functions.

[0019] The preamplifier 13 can adopt the structural design of the switched capacitor preamplifier 13 to achieve accurate amplification of the sampled output. The dynamic latch 15 is designed with a latch LAT, an offset voltage automatic calibration circuit ACC and a dynamic comparator. The dynamic comparator reset and comparison are controlled by the input signal CLK (clock). However, before the data comparison is performed, the offset voltage automatic calibration circuit ACC provides the same input voltage to the core transistors in the dynamic comparator, and then adaptively reduces the dynamic comparator offset voltage caused by the process error in the manufacturing process according to the comparison result. Finally, the latch LAT controls whether the output signal of the dynamic comparator changes with the input signal.

[0020] The high-precision dynamic comparator with automatic offset voltage calibration circuit adopts a switched capacitor preamplifier 13, so that when the comparator is applied to the FLASH ADC, the DC parameters will not be different due to the difference in common mode voltage, thereby reducing the offset voltage between different comparators; and the substrate voltage bias technology is adopted, so that the resistance of the sampling switch is smaller when it is turned on and larger when it is turned off. The offset voltage automatic calibration circuit ACC is adopted so that the circuit can adjust the offset voltage adaptively according to the process error in the manufacturing process. Compared with the traditional comparator, the design form of the switched capacitor comparator is adopted, so that the comparator input signal is near the common mode voltage VCM, ensuring that each comparator will not have an offset voltage error caused by different DC parameters due to different common mode voltages, and the offset voltage automatic calibration circuit ACC is adopted to make the offset voltage of the comparator smaller.

[0021] In one embodiment, Figure 2As shown, the signal sampling circuit 11 includes an inverter INV0, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a gate voltage bootstrap circuit BTSP, a transistor NMOS0, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor NMOS4, a transistor NMOS5, a transistor NMOS6, a transistor NMOS7, a transistor PMOS0, a capacitor C0 and a capacitor C1. The PHI terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP through the inverter INV0, the PHIB terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP, the VIN terminal of the gate voltage bootstrap circuit BTSP is used to access the input signal VSIG, and the OUT terminal of the gate voltage bootstrap circuit BTSP is connected to the gate of the transistor NMOS0 and the gate of the transistor NMOS1 respectively.

[0022] The drain of transistor NMOS0 is connected to the drain of transistor NMOS1 and is used to access the input signal VSIG, the substrate of transistor NMOS0 is respectively connected to the source of transistor NMOS1 and the drain of transistor NMOS2, the source of transistor NMOS0 is connected to one end of capacitor C0, the gate of transistor NMOS2 is used to access the control signal VSAMP, the source of transistor NMOS2 is grounded, the drain of transistor NMOS3 is connected to the drain of transistor PMOS0 and is used to access the reference signal VREF, the source of transistor NMOS3 is connected to the source of transistor PMOS0 and connected to one end of capacitor C0, the other end of capacitor C0 is connected to the first input end of the preamplifier 13, the inverter INV1, the inverter INV2 and the inverter INV3 are connected in series in sequence, the input end of inverter INV1 is used to access the input signal PHIB, the output end of inverter INV3 is connected to the gate of transistor PMOS0, and the gate of transistor NMOS3 is connected to the output end of inverter INV2.

[0023] Inverter INV4 and inverter INV5 are connected in series, the input end of inverter INV4 is used to access the input signal NCON2, the output end of inverter INV5 is connected to the gate of transistor NMOS5, the drain of transistor NMOS4 and the drain of transistor NMOS5 are both connected to one end of capacitor C1, the drain of transistor NMOS6 is connected to the other end of capacitor C1, the other end of capacitor C1 is connected to the second input end of preamplifier 13, the gate of transistor NMOS4 is connected to the output end of inverter INV0, the source of transistor NMOS4 is used to access the signal VSS, the source of transistor NMOS5 is used to access the reference signal VREFN, the gate of transistor NMOS6 is used to access the input signal PHIB, the substrate of transistor NMOS6 is used to access the signal VSS, the source of transistor NMOS6 and the source of transistor NMOS7 are both used to access the signal VCM, the drain of transistor NMOS7 is connected to the other end of capacitor C0, the substrate of transistor NMOS7 is used to access the signal VSS, and the gate of transistor NMOS7 is used to access the input signal NCON2.

[0024] It can be understood that in this specification, NMOS is an N-type MOS tube and PMOS is a P-type MOS tube. The input signal VSAMP controls whether the transistor NMOS0 samples the input signal through the inverter INV0 and the gate voltage bootstrap circuit BTSP. The signal VSAMP is the control signal of the gate voltage bootstrap circuit BTSP. When the signal VSAMP is at a high level, VSAMB is at a low level, the gate voltage bootstrap circuit BTSP enters a reset state, the transistor NMOS0 is turned off, the transistor NMOS1 is turned off, and the transistor NMOS2 is turned on, so that the substrate of the transistor NMOS0 is connected to GND (ground), the transistor NMOS4 is turned off, and the sampling of the signal VSS is stopped. At this time, since the transistor NMOS0 is in the off state, when its substrate is grounded, the equivalent PN junction of the source, drain and substrate is more reverse biased, thereby making its off resistance larger.

[0025] When the signal VSAMP is at a low level, VSAMPB is at a high level, the gate voltage bootstrap circuit BTSP enters the working state, the transistor NMOS0 is turned on, the transistor NMOS1 is turned on so that the substrate of the transistor NMOS0 is connected to the input signal VSIG, the transistor NMOS2 is turned off, and the transistor NMOS4 is turned on. At this time, the transistor NMOS0 samples the input signal VSIG and stores the input signal VSIG to the capacitor C0. The transistor NMOS4 is turned on and the signal VSS is stored in the capacitor C1. At this time, the source of the transistor NMOS0 is short-circuited with the substrate, which can reduce the threshold voltage changes with the input and reduce its threshold voltage, so that its on-resistance is smaller when it is turned on. In this way, the substrate voltage bias technology is formed, which makes the sampling switch have a smaller resistance when it is turned on and a larger resistance when it is turned off.

[0026] The input signal PHIB is used to control whether the transistor NMOS3 and the transistor PMOS0 sample the reference voltage VREF. Specifically, the input signal PHIB is a control signal for whether to sample the reference signal VREF. When the input signal PHIB is at a high level, the potential at point A is at a high level and the potential at point B is at a low level through the action of the inverter INV1, the inverter INV2 and the inverter INV3, so that the transistor NMOS3, the transistor NMOS6 and the transistor PMOS0 are turned on, so that the reference signal VREF is stored in the capacitor C0, and the signal VCM is stored in the capacitor C1. When the input signal PHIB is at a low level, the potential at point A is at a low level and the potential at point B is at a high level through the action of the inverter INV1, the inverter INV2 and the inverter INV3, so that the transistor NMOS3 and the transistor PMOS0 are turned off, and the reference signal VREF and the signal VCM are not sampled at this time.

[0027] The input signal NCON2 controls the transistor NMOS5 and the NMOS tube NMOS7 to sample the common mode voltage VCM and the reference voltage VREFN through the inverter INV4 and the inverter INV5. Specifically, when the signal NCON2 is at a high level, the signal NCON2LATE is at a high level through the inverter INV4 and the inverter INV5, so that the transistor NMOS7 is turned on, so that the common mode voltage signal VCM and the reference signal VREFN are stored in the capacitor C1; when the signal NCON2 is at a low level, the signal NCON2LATE is at a low level through the inverter INV4 and the inverter INV5, so that the transistor NMOS7 is turned off and the sampling of the signal VCM and the signal VREFN is stopped.

[0028] In one embodiment, Figure 3As shown, the preamplifier 13 includes a transistor NMOS8, a transistor NMOS9, a transistor NMOS10, a transistor NMOS11 and a transistor NMOS12. The gate of the transistor NMOS8 is used to access the bias voltage VBIAS, and the source of the transistor NMOS8 is grounded. The drain of transistor NMOS8 is connected to the source of transistor NMOS9 and the source of transistor NMOS10 respectively, the substrate of transistor NMOS9 is connected to the substrate of transistor NMOS10 and is used to access the signal VSS, the gate of transistor NMOS9 is connected to the first output end of the signal sampling circuit 11, the gate of transistor NMOS10 is connected to the second output end of the signal sampling circuit 11, the drain of transistor NMOS9 is connected to the drain of transistor NMOS11 and is connected to the first input end of the dynamic comparator, the drain of transistor NMOS10 is connected to the drain of transistor NMOS12 and is connected to the second input end of the dynamic comparator, the source of transistor NMOS11 is connected to the source of transistor NMOS12 and is used to access the power supply voltage VDD, and the gate of transistor NMOS11 is connected to the gate of transistor NMOS12 and is used to access the power supply voltage VDD.

[0029] It can be understood that the input signal VBIAS gives a bias voltage to the pre-comparator current source. Specifically, the pre-comparator current source is composed of a transistor NMOS8. When the input signal VBIAS is at a high level, the transistor NMOS8 is turned on, and the preamplifier 13 enters the working state, and the current flows from the transistor NMOS9 and the transistor NMOS10 into the transistor NMOS8; when the input signal VBIAS is at a low level, the transistor NMOS8 is turned off, and the entire preamplifier 13 has no current flowing in, thereby stopping working.

[0030] In one embodiment, Figure 4 As shown, the dynamic comparator in the dynamic latch 15 includes an inverter INV6, an inverter INV7, an NOR gate NOR1, an NOR gate NOR2, a transistor NMOS13, a transistor NMOS14, a transistor NMOS15, a transistor NMOS16, a transistor NMOS17, a transistor PMOS1, a transistor PMOS2, a transistor PMOS3, a transistor PMOS4, a transistor PMOS5, a transistor PMOS6, a transistor PMOS7, a transistor PMOS8, a transistor PMOS9, a transistor PMOS10, a transistor PMOS11, a transistor PMOS12, a transistor PMOS13 and a transistor PMOS14.

[0031] The gate of transistor NMOS17 is used to access the clock signal CLK, the source of transistor NMOS17 is grounded, the drain of transistor NMOS17 is respectively connected to the source of transistor NMOS13 and the source of transistor NMOS14, the gate of transistor NMOS13 is connected to the second output terminal of preamplifier 13, the gate of transistor NMOS14 is connected to the first output terminal of preamplifier 13, the substrate of transistor NMOS13 and the substrate of transistor NMOS14 are both used to access the signal VSS, the drain of transistor NMOS13 is connected to the drain of transistor NMOS15, the drain of transistor NMOS14 is connected to the drain of transistor NMOS16, and the substrate of transistor NMOS15 and the substrate of transistor NMOS16 are both used to access the signal VSS.

[0032] The source of transistor NMOS15, the drain of transistor PMOS2, the drain of transistor PMOS1, the gate of transistor PMOS3 and the gate of transistor NMOS16 are connected, the source of transistor NMOS16, the drain of transistor PMOS3, the drain of transistor PMOS4, the gate of transistor PMOS2 and the gate of transistor NMOS15 are connected, the source of transistor PMOS1, the source of transistor PMOS2, the source of transistor PMOS3 and the source of transistor PMOS4 are all used to access the power supply voltage VDD, the gate of transistor PMOS1 and the gate of transistor PMOS4 are connected. The gates of S4 are all used to access the clock signal CLK, the input end of the inverter INV6 is connected to the drain of the transistor PMOS2, the input end of the inverter INV7 is connected to the drain of the transistor PMOS3, the output end of the inverter INV6 is connected to the first input end of the NOR gate NOR1, the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR2, the output end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR2, and the output end of the NOR gate NOR2 is respectively connected to the second input end of the NOR gate NOR1, the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC.

[0033] The gates of transistors PMOS5 to PMOS9 are connected to each other and to the drain of transistor NMOS15. The gates of transistors PMOS10 to PMOS14 are connected to each other and to the drain of transistor NMOS16. The substrates of transistors PMOS5 to PMOS14 are used to access the power supply voltage VDD. The source and drain of transistor PMOS5 are connected to each other. The source and drain of transistor PMOS6 are connected to each other. The source and drain of transistor PMOS7 are connected to each other. The source and drain of transistor PMOS6 are connected to each other. 9 is connected to the source and drain, the sources of transistors PMOS5 to PMOS9 are respectively connected to the right output terminal of the offset voltage automatic calibration circuit ACC, the source and drain of transistor PMOS10 are connected, the source and drain of transistor PMOS11 are connected, the source and drain of transistor PMOS12 are connected, the source and drain of transistor PMOS13 are connected, the source and drain of transistor PMOS14 are connected, and the sources of transistors PMOS10 to PMOS14 are respectively connected to the left output terminal of the offset voltage automatic calibration circuit ACC.

[0034] It can be understood that the right output terminal of the offset voltage automatic calibration circuit ACC in this embodiment is Figure 4 The left output terminal of the offset voltage automatic calibration circuit ACC is Figure 4 L<4:0> in . The input signal CLK is used to control the reset and comparison of the dynamic comparator. Specifically, when the input signal CLK is at a high level, the transistor NMOS17 is turned on, and the transistors PMOS1 and PMOS4 are turned off, so that the entire dynamic comparator enters the working state. When the input signal CLK is at a low level, the transistor NMOS17 is turned off, and the transistors PMOS1 and PMOS4 are turned on, so that the output terminals ON and OP are charged to a high level, thereby entering the reset state. Among them, Figures 2 to 4 The circuit terminals in the circuit are numbered 01 to 04, and the circuit terminals with the same number in each circuit structure diagram are connected. Figure 5 and Figure 6 The same principle applies in Chinese.

[0035] In one embodiment, Figure 4 , Figure 5 and Figure 6 As shown, the offset voltage automatic calibration circuit ACC includes INCNDEC units 0 to INCNDEC units 9 (i.e., INC0 to INC9), D flip-flops 0 to D flip-flops 9 (i.e., D0 to D9), a left output gate circuit and a right output gate circuit, and the INCNDEC units correspond to the D flip-flops 9 one by one. The clock terminal of each D flip-flop ( CLK ) are used to access the offset voltage calibration clock signal ACC_CLK, the reset terminal of each D flip-flop ( R) are used to access the offset voltage automatic calibration reset signal RST, the D end of each D flip-flop is connected to the S end of the corresponding INCNDEC unit, the Q end of each D flip-flop is connected to the B end of the corresponding INCNDEC unit, the DEC ends of INCNDEC unit 0 to INCNDEC unit 4 are all connected to the output end of the NOR gate NOR2, INCNDEC units 0 to INCNDEC units 4 are cascaded with the Cin end through the CB end in turn, and the CB end of INCNDEC unit 4 is left floating.

[0036] The DEC terminals of INCNDEC units 5 to INCNDEC units 9 are connected to the output terminal of NOR gate NOR2 through inverter INV12. INCNDEC units 5 to INCNDEC units 9 are cascaded with Cin terminals through CB terminals in sequence, and the CB terminal of INCNDEC unit 9 is suspended. The output terminal of the left output gate circuit is connected to the Cin terminal of INCNDEC unit 0, and the input terminal of the left output gate circuit is respectively connected to the source of transistor PMOS10, transistor PMOS11, transistor PMOS12, transistor PMOS13 and transistor PMOS14. The output terminal of the right output gate circuit is connected to the Cin terminal of INCNDEC unit 5, and the input terminal of the right output gate circuit is respectively connected to the drain of transistor PMOS5, transistor PMOS6, transistor PMOS7, transistor PMOS8 and transistor PMOS9.

[0037] It can be understood that the offset voltage calibration clock signal ACC_CLK is used to provide a clock signal for the offset voltage automatic calibration circuit ACC. Among them, the offset voltage calibration clock signal ACC_CLK is also an input signal provided by the outside world and is only used to provide a clock signal for the offset voltage automatic calibration circuit ACC. The offset voltage automatic calibration reset signal RST is a reset signal of the offset voltage automatic calibration circuit ACC. The offset voltage automatic calibration reset signal RST is also an input signal provided by the outside world and is only used to reset the offset voltage automatic calibration circuit ACC.

[0038] The flash lock signal FLASH_LOCK is used to control whether the output signal of the comparator changes. Specifically, the flash lock signal FLASH_LOCK is an input signal, which is used to control whether the output of the latch LAT will change with the input. When the FLASH_LOCK signal is a valid signal, the output result of the comparator changes with the change of the input signal, and the output signal of the latch LAT also changes accordingly. When the FLASH_LOCK signal is an invalid signal, the output result of the comparator also changes with the change of the input signal, but the output signal of the latch LAT will only output the signal at the moment when the FLASH_LOCK signal changes from a valid signal to an invalid signal.

[0039] In one embodiment, Figure 6 As shown, the right output gate circuit includes inverter INV8, inverter INV9, NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, NAND gate NAND5, NAND gate NAND6, NOR gate NOR3, NOR gate NOR4, NOR gate NOR5 and NOR gate NOR6, and the left output gate circuit includes inverter INV10, inverter INV11, NAND gate NAND7, NAND gate NAND8, NAND gate NAND9, NAND gate NAND10, NAND gate NAND11, NAND gate NAND12, NOR gate NOR7, NOR gate NOR8, NOR gate NOR9 and NOR gate NOR10.

[0040] The input ends of the NAND gate NAND1, the NAND gate NAND2, the NOR gate NOR3 and the NOR gate NOR4 serve as the input ends of the right output gate circuit, the two input ends of the NOR gate NOR5 are respectively connected to the output end of the NAND gate NAND1 and the output end of the NAND gate NAND2, the output end of the NOR gate NOR5 is connected to the first input end of the NAND gate NAND4, the two input ends of the NAND gate NAND3 are respectively connected to the output ends of the NOR gate NOR3 and the NOR gate NOR4, the other input end of the NAND gate NAND3 is connected to the Q inverting end of the D flip-flop 9, the output end of the NAND gate NAND3 is respectively connected to one input end of the NOR gate NOR6 and one input end of the NAND gate NAND11, and the other input end of the NOR gate NOR6 is connected to the Q inverting end of the D flip-flop 9. The input end is connected to the output end of the NOR gate NOR2, the output end of the NOR gate NOR6 is connected to the input end of the inverter INV8, one input end of the NAND gate NAND5 is connected to the output end of the NOR gate NOR2, the other input end of the NAND gate NAND5 is connected to the output end of the NAND gate NAND9, the second input end of the NAND gate NAND4 is connected to the Q end of the D flip-flop 9, the third input end of the NAND gate NAND4 is connected to the output end of the NOR gate NOR2, the three input ends of the NAND gate NAND6 are respectively connected to the output ends of the NAND gate NAND4, the NAND gate NAND5 and the inverter INV8, and the output end of the NAND gate NAND6 is connected to the Cin end of the INCNDEC unit 5 through the inverter INV9.

[0041] The input ends of the NAND gate NAND7, the NAND gate NAND8, the NOR gate NOR7 and the NOR gate NOR8 serve as the input ends of the left output gate circuit, the two input ends of the NOR gate NOR9 are respectively connected to the output ends of the NAND gate NAND7 and the output end of the NAND gate NAND8, the output end of the NOR gate NOR9 is connected to the first input end of the NAND gate NAND10, the two input ends of the NAND gate NAND9 are respectively connected to the output ends of the NOR gate NOR7 and the NOR gate NOR8, the other input end of the NAND gate NAND9 is connected to the Q inverting end of the D flip-flop 4, the output ends of the NAND gate NAND9 are respectively connected to one input end of the NOR gate NOR10 and the other input end of the NOR gate NOR10 An input end is connected to the output end of the inverter INV12, the output end of the NOR gate NOR10 is connected to the input end of the inverter INV10, another input end of the NAND gate NAND11 is connected to the output end of the inverter INV12, the second input end of the NAND gate NAND10 is connected to the Q end of the D flip-flop 4, the third input end of the NAND gate NAND10 is connected to the output end of the inverter INV12, the three input ends of the NAND gate NAND12 are respectively connected to the output ends of the NAND gate NAND10, the NAND gate NAND11 and the inverter INV10, and the output end of the NAND gate NAND12 is connected to the Cin end of the INCNDEC unit 0 through the inverter INV11.

[0042] In one embodiment, Figure 7 As shown, the INCNDEC unit includes an XOR gate XOR0, an XOR gate XOR1, a NAND gate NAND13, and an inverter INV13. The first input end of the XOR gate XOR0 is used as a DEC end, the second input end of the XOR gate XOR0 is connected to the second input end of the XOR gate XOR1 as a B end, the output end of the XOR gate XOR0 is connected to the first input end of the NAND gate NAND13, the second input end of the NAND gate NAND13 is connected to the first input end of the XOR gate XOR1 as a Cin end, the output end of the NAND gate NAND13 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is used as a CB end, and the output end of the XOR gate XOR1 is used as an S end.

[0043] Compared with the traditional comparator, the whole circuit adopts the design structure of the switched capacitor comparator, so that the input signal of the comparator is near the common mode voltage VCM, ensuring that each comparator will not have an offset voltage error caused by different DC parameters due to different common mode voltages, and adopts an offset voltage automatic calibration circuit ACC, so that the offset voltage of the comparator is smaller. In the manufacture of chips, some devices with the same requirements are not exactly the same after they are actually produced, so the drain discharge speeds of transistors NMOS15 and NMOS16 are different, thereby introducing offset voltage, which will cause misjudgment when the input signals of the comparator are not much different. The principle of the offset voltage automatic calibration circuit ACC is to give the same input voltage to transistors NMOS13 and NMOS14 before comparing the data, and then according to the comparison result, the offset voltage automatic calibration circuit ACC adaptively adds capacitance to the drains of transistors NMOS15 and NMOS16, so that the discharge speeds of the two points tend to be consistent, thereby reducing the offset voltage.

[0044] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A high-precision dynamic comparator with an automatic offset voltage calibration circuit, characterized in that: It includes a signal sampling circuit, a preamplifier and a dynamic latch. The signal sampling circuit is based on a gate voltage bootstrap circuit BTSP and is designed using a substrate voltage bias technology. The dynamic latch includes a latch LAT, an offset voltage automatic calibration circuit ACC and a dynamic comparator. The sampling input end of the signal sampling circuit is used to access the input signal to be sampled and the reference signal, the output end of the signal sampling circuit is connected to the input end of the preamplifier, the output end of the preamplifier is connected to the input end of the dynamic comparator, the output end of the dynamic comparator is respectively connected to the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC, and the output end of the offset voltage automatic calibration circuit ACC is connected to the calibration input end of the dynamic comparator; The signal sampling circuit is used to sample the input signal and the reference signal, the preamplifier is used to preamplify the sampled output of the signal sampling circuit, the offset voltage automatic calibration circuit ACC is used to adaptively reduce the offset voltage of the dynamic comparator according to the process error in the manufacturing process, the dynamic comparator is used to perform data comparison, and the latch LAT is used to control whether the output signal of the dynamic comparator changes with the change of the input signal.

2. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 1, characterized in that: The signal sampling circuit includes an inverter INV0, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a gate voltage bootstrap circuit BTSP, a transistor NMOS0, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor NMOS4, a transistor NMOS5, a transistor NMOS6, a transistor NMOS7, a transistor PMOS0, a capacitor C0 and a capacitor C1; The PHI terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP through the inverter INV0, the PHIB terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP, the VIN terminal of the gate voltage bootstrap circuit BTSP is used to access the input signal VSIG, and the OUT terminal of the gate voltage bootstrap circuit BTSP is respectively connected to the gate of the transistor NMOS0 and the gate of the transistor NMOS1; The drain of the transistor NMOS0 is connected to the drain of the transistor NMOS1 and is used to access the input signal VSIG, the substrate of the transistor NMOS0 is respectively connected to the source of the transistor NMOS1 and the drain of the transistor NMOS2, the source of the transistor NMOS0 is connected to one end of the capacitor C0, the gate of the transistor NMOS2 is used to access the control signal VSAMP, the source of the transistor NMOS2 is grounded, the drain of the transistor NMOS3 is connected to the drain of the transistor PMOS0 and is used to access the reference signal VREF, the source of the transistor NMOS3 is connected to the source of the transistor PMOS0 and connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the first input end of the preamplifier, the inverter INV1, the inverter INV2 and the inverter INV3 are connected in series in sequence, the input end of the inverter INV1 is used to access the input signal PHIB, the output end of the inverter INV3 is connected to the gate of the transistor PMOS0, and the gate of the transistor NMOS3 is connected to the output end of the inverter INV2; The inverter INV4 and the inverter INV5 are connected in series, the input end of the inverter INV4 is used to access the input signal NCON2, the output end of the inverter INV5 is connected to the gate of the transistor NMOS5, the drain of the transistor NMOS4 and the drain of the transistor NMOS5 are both connected to one end of the capacitor C1, the drain of the transistor NMOS6 is connected to the other end of the capacitor C1, the other end of the capacitor C1 is connected to the second input end of the preamplifier, the gate of the transistor NMOS4 is connected to the output end of the inverter INV0, and the transistor NMOS6 is connected to the output end of the inverter INV0. The source of S4 is used to access the signal VSS, the source of the transistor NMOS5 is used to access the reference signal VREFN, the gate of the transistor NMOS6 is used to access the input signal PHIB, the substrate of the transistor NMOS6 is used to access the signal VSS, the source of the transistor NMOS6 and the source of the transistor NMOS7 are both used to access the signal VCM, the drain of the transistor NMOS7 is connected to the other end of the capacitor C0, the substrate of the transistor NMOS7 is used to access the signal VSS, and the gate of the transistor NMOS7 is used to access the input signal NCON2.

3. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 1, characterized in that: The preamplifier includes a transistor NMOS8, a transistor NMOS9, a transistor NMOS10, a transistor NMOS11 and a transistor NMOS12; The gate of the transistor NMOS8 is used to access the bias voltage VBIAS, the source of the transistor NMOS8 is grounded, the drain of the transistor NMOS8 is respectively connected to the source of the transistor NMOS9 and the source of the transistor NMOS10, the substrate of the transistor NMOS9 is connected to the substrate of the transistor NMOS10 and is used to access the signal VSS, the gate of the transistor NMOS9 is connected to the first output end of the signal sampling circuit, the gate of the transistor NMOS10 is connected to the second output end of the signal sampling circuit, the drain of the transistor NMOS9 is connected to the drain of the transistor NMOS11 and is connected to the first input end of the dynamic comparator, the drain of the transistor NMOS10 is connected to the drain of the transistor NMOS12 and is connected to the second input end of the dynamic comparator, the source of the transistor NMOS11 is connected to the source of the transistor NMOS12 and is used to access the power supply voltage VDD, and the gate of the transistor NMOS11 is connected to the gate of the transistor NMOS12 and is used to access the power supply voltage VDD.

4. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to any one of claims 1 to 3, characterized in that: The dynamic comparator in the dynamic latch includes an inverter INV6, an inverter INV7, a NOR gate NOR1, a NOR gate NOR2, a transistor NMOS13, a transistor NMOS14, a transistor NMOS15, a transistor NMOS16, a transistor NMOS17, a transistor PMOS1, a transistor PMOS2, a transistor PMOS3, a transistor PMOS4, a transistor PMOS5, a transistor PMOS6, a transistor PMOS7, a transistor PMOS8, a transistor PMOS9, a transistor PMOS10, a transistor PMOS11, a transistor PMOS12, a transistor PMOS13 and a transistor PMOS14; The gate of the transistor NMOS17 is used to access the clock signal CLK, the source of the transistor NMOS17 is grounded, the drain of the transistor NMOS17 is respectively connected to the source of the transistor NMOS13 and the source of the transistor NMOS14, the gate of the transistor NMOS13 is connected to the second output terminal of the preamplifier, the gate of the transistor NMOS14 is connected to the first output terminal of the preamplifier, the substrate of the transistor NMOS13 and the substrate of the transistor NMOS14 are both used to access the signal VSS, the drain of the transistor NMOS13 is connected to the drain of the transistor NMOS15, the drain of the transistor NMOS14 is connected to the drain of the transistor NMOS16, and the substrate of the transistor NMOS15 and the substrate of the transistor NMOS16 are both used to access the signal VSS; The source of the transistor NMOS15, the drain of the transistor PMOS2, the drain of the transistor PMOS1, the gate of the transistor PMOS3 and the gate of the transistor NMOS16 are connected, the source of the transistor NMOS16, the drain of the transistor PMOS3, the drain of the transistor PMOS4, the gate of the transistor PMOS2 and the gate of the transistor NMOS15 are connected, the source of the transistor PMOS1, the source of the transistor PMOS2, the source of the transistor PMOS3 and the source of the transistor PMOS4 are all used to access the power supply voltage VDD, the gate of the transistor PMOS1 and the gate of the transistor PMOS4 are connected. The gates of MOS4 are all used to access the clock signal CLK, the input end of the inverter INV6 is connected to the drain of the transistor PMOS2, the input end of the inverter INV7 is connected to the drain of the transistor PMOS3, the output end of the inverter INV6 is connected to the first input end of the NOR gate NOR1, the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR2, the output end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR2, and the output end of the NOR gate NOR2 is respectively connected to the second input end of the NOR gate NOR1, the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC; The gates of the transistors PMOS5 to PMOS9 are connected to the drain of the transistor NMOS15, the gates of the transistors PMOS10 to PMOS14 are connected to the drain of the transistor NMOS16, the substrates of the transistors PMOS5 to PMOS14 are connected to the power supply voltage VDD, the source and drain of the transistor PMOS5 are connected, the source and drain of the transistor PMOS6 are connected, the source and drain of the transistor PMOS7 are connected, the source and drain of the transistor PMOS9 are connected. The sources of the transistors PMOS5 to PMOS9 are respectively connected to the right output terminal of the automatic offset voltage calibration circuit ACC, the source and drain of the transistor PMOS10 are connected, the source and drain of the transistor PMOS11 are connected, the source and drain of the transistor PMOS12 are connected, the source and drain of the transistor PMOS13 are connected, the source and drain of the transistor PMOS14 are connected, and the sources of the transistors PMOS10 to PMOS14 are respectively connected to the left output terminal of the automatic offset voltage calibration circuit ACC.

5. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 4, characterized in that: The offset voltage automatic calibration circuit ACC includes INCNDEC units 0 to INCNDEC units 9, D flip-flops 0 to D flip-flops 9, a left output gate circuit and a right output gate circuit, and the INCNDEC units correspond to the D flip-flops 9 one by one; The clock end of each D flip-flop is used to access the offset voltage calibration clock signal, the reset end of each D flip-flop is used to access the offset voltage automatic calibration reset signal, the D end of each D flip-flop is connected to the S end of the corresponding INCNDEC unit, the Q end of each D flip-flop is connected to the B end of the corresponding INCNDEC unit, the DEC end of INCNDEC unit 0 to INCNDEC unit 4 is connected to the output end of the NOR gate NOR2, INCNDEC unit 0 to INCNDEC unit 4 are cascaded with the Cin end through the CB end in turn, and the CB end of INCNDEC unit 4 is left floating; The DEC terminals of INCNDEC units 5 to INCNDEC units 9 are all connected to the output terminal of NOR gate NOR2 through inverter INV12, and INCNDEC units 5 to INCNDEC units 9 are cascaded with Cin terminals through CB terminals in sequence, and the CB terminal of INCNDEC unit 9 is suspended; The output end of the left output gate circuit is connected to the Cin end of the INCNDEC unit 0, and the input end of the left output gate circuit is respectively connected to the source of the transistor PMOS10, the transistor PMOS11, the transistor PMOS12, the transistor PMOS13 and the transistor PMOS14. The output end of the right output gate circuit is connected to the Cin end of the INCNDEC unit 5, and the input end of the right output gate circuit is respectively connected to the drain of the transistor PMOS5, the transistor PMOS6, the transistor PMOS7, the transistor PMOS8 and the transistor PMOS9.

6. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 5, characterized in that: The right output gate circuit includes an inverter INV8, an inverter INV9, a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, a NAND gate NAND4, a NAND gate NAND5, a NAND gate NAND6, a NOR gate NOR3, a NOR gate NOR4, a NOR gate NOR5 and a NOR gate NOR6; the left output gate circuit includes an inverter INV10, an inverter INV11, a NAND gate NAND7, a NAND gate NAND8, a NAND gate NAND9, a NAND gate NAND10, a NAND gate NAND11, a NAND gate NAND12, a NOR gate NOR7, a NOR gate NOR8, a NOR gate NOR9 and a NOR gate NOR10; The input ends of the NAND gate NAND1, the NAND gate NAND2, the NOR gate NOR3 and the NOR gate NOR4 serve as the input ends of the right output gate circuit, the two input ends of the NOR gate NOR5 are respectively connected to the output end of the NAND gate NAND1 and the output end of the NAND gate NAND2, the output end of the NOR gate NOR5 is connected to the first input end of the NAND gate NAND4, the two input ends of the NAND gate NAND3 are respectively connected to the output ends of the NOR gate NOR3 and the NOR gate NOR4, the other input end of the NAND gate NAND3 is connected to the Q inverting end of the D flip-flop 9, the output end of the NAND gate NAND3 is respectively connected to one input end of the NOR gate NOR6 and one input end of the NAND gate NAND11, the NOR gate NOR6 The other input end of is connected to the output end of the NOR gate NOR2, the output end of the NOR gate NOR6 is connected to the input end of the inverter INV8, one input end of the NAND gate NAND5 is connected to the output end of the NOR gate NOR2, the other input end of the NAND gate NAND5 is connected to the output end of the NAND gate NAND9, the second input end of the NAND gate NAND4 is connected to the Q end of the D flip-flop 9, the third input end of the NAND gate NAND4 is connected to the output end of the NOR gate NOR2, the three input ends of the NAND gate NAND6 are respectively connected to the output ends of the NAND gate NAND4, the NAND gate NAND5 and the inverter INV8, and the output end of the NAND gate NAND6 is connected to the Cin end of the INCNDEC unit 5 through the inverter INV9; The input ends of the NAND gate NAND7, the NAND gate NAND8, the NOR gate NOR7 and the NOR gate NOR8 serve as the input ends of the left output gate circuit, the two input ends of the NOR gate NOR9 are respectively connected to the output end of the NAND gate NAND7 and the output end of the NAND gate NAND8, the output end of the NOR gate NOR9 is connected to the first input end of the NAND gate NAND10, the two input ends of the NAND gate NAND9 are respectively connected to the output ends of the NOR gate NOR7 and the NOR gate NOR8, the other input end of the NAND gate NAND9 is connected to the Q inverting end of the D flip-flop 4, the output ends of the NAND gate NAND9 are respectively connected to one input end of the NOR gate NOR10, the Another input end is connected to the output end of the inverter INV12, the output end of the NOR gate NOR10 is connected to the input end of the inverter INV10, another input end of the NAND gate NAND11 is connected to the output end of the inverter INV12, the second input end of the NAND gate NAND10 is connected to the Q end of the D flip-flop 4, the third input end of the NAND gate NAND10 is connected to the output end of the inverter INV12, the three input ends of the NAND gate NAND12 are respectively connected to the output ends of the NAND gate NAND10, the NAND gate NAND11 and the inverter INV10, and the output end of the NAND gate NAND12 is connected to the Cin end of the INCNDEC unit 0 through the inverter INV11.

7. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 5, characterized in that: The INCNDEC unit includes an XOR gate XOR0, an XOR gate XOR1, a NAND gate NAND13, and an inverter INV13. The first input end of the XOR gate XOR0 is used as a DEC end, the second input end of the XOR gate XOR0 is connected to the second input end of the XOR gate XOR1 as a B end, the output end of the XOR gate XOR0 is connected to the first input end of the NAND gate NAND13, the second input end of the NAND gate NAND13 is connected to the first input end of the XOR gate XOR1 as a Cin end, the output end of the NAND gate NAND13 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is used as a CB end, and the output end of the XOR gate XOR1 is used as an S end.

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