Response and interstage gain ADC circuit

Abstract

The invention relates to the technical field of circuits, and provides a response and interstage gain ADC circuit, which comprises a signal input end, a filter circuit, a signal sampling circuit, a loop amplifier, a ring oscillator circuit and a signal output end which are electrically connected in sequence, the loop amplifier comprises an input matching circuit, an inverter circuit, a power amplification circuit and an output matching circuit, the input end of the input matching circuit serves as the input end of the loop amplifier, the output end of the input matching circuit is connected with the input end of the inverter circuit, and the output end of the inverter circuit is connected with the input end of the power amplification circuit. The output end of the power amplification circuit is connected with the input end of the output matching circuit, and the output end of the output matching circuit serves as the output end of the loop amplifier. According to the response and interstage gain ADC circuit, the effects of quick response and interstage high gain of the ADC circuit can be improved through the loop amplifier, the stability is good, and the reliability is high.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a response and inter-stage gain ADC circuit. Background Art

[0002] Modern communication systems require high-speed and high-precision ADCs. The high precision of ADCs can prevent distortion and loss of weak signals, while the application of high-speed ADCs can reduce the number of frequency conversions in the system. Among various ADC structures, pipeline ADCs have become a popular research structure for high-performance ADCs due to their excellent compromise between accuracy, speed, and power consumption.

[0003] The interstage amplifier is now the most critical module in the ADC, and its performance directly determines the accuracy of the signal sampled by the ADC. The transconductance amplifier commonly used in early designs has certain limitations with the advancement of technology. On the one hand, the power supply voltage is reduced, resulting in insufficient voltage margin for the transconductance amplifier of the common source and common gate structure; on the other hand, the reduction of intrinsic gain leads to limited gain of the single-stage operational amplifier, and the technology of cascading multiple amplifiers to increase the gain will introduce multiple zeros and poles, resulting in poor stability of the operational amplifier. Summary of the invention

[0004] The invention provides a response and inter-stage gain ADC circuit, aiming to solve the problems of poor gain effect and stability of the existing ADC circuit.

[0005] An embodiment of the present invention provides a response and inter-stage gain ADC circuit, comprising: a signal input terminal, a filter circuit, a signal sampling circuit, a loop amplifier, a ring oscillator circuit and a signal output terminal electrically connected in sequence;

[0006] The loop amplifier comprises an input matching circuit, an inverter circuit, a power amplifier circuit and an output matching circuit. The input end of the input matching circuit serves as the input end of the loop amplifier, the output end of the input matching circuit is connected to the input end of the inverter circuit, the output end of the inverter circuit is connected to the input end of the power amplifier circuit, the output end of the power amplifier circuit is connected to the input end of the output matching circuit, and the output end of the output matching circuit serves as the output end of the loop amplifier.

[0007] Preferably, the input matching circuit includes a first switch, a second switch, a third switch and a first capacitor;

[0008] The first end of the first switch and the first end of the second switch serve as input ends of the input matching circuit respectively, the second end of the first switch is connected to the second end of the second switch and are commonly connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the third switch and serves as the output end of the input matching circuit, and the second end of the third switch is used to connect to the VCM port.

[0009] Preferably, the inverter circuit includes a second capacitor, a fourth switch, a first inverter, a second inverter, a third inverter, a third capacitor, a fifth switch, a fourth capacitor and a sixth switch;

[0010] The first end of the second capacitor is connected to the second end of the first capacitor, the second end of the second capacitor is respectively connected to the first end of the fourth switch and the input end of the first inverter, the output end of the first inverter is respectively connected to the second end of the fourth switch, the first end of the third capacitor and the first end of the fourth capacitor, the second end of the third capacitor is respectively connected to the first end of the fifth switch and the input end of the second inverter, the second end of the fourth capacitor is respectively connected to the input end of the third inverter and the first end of the sixth switch, the second end of the fifth switch and the second end of the sixth switch are respectively used to connect to an external power supply; the output end of the second inverter and the output end of the third inverter are respectively used as the output end of the inverter circuit.

[0011] Preferably, the power amplifier circuit includes a first MOS tube and a second MOS tube, the gate of the first MOS tube is connected to the output end of the second inverter, the gate of the second MOS tube is connected to the output end of the third inverter, the source of the first MOS tube is connected to the external power supply, the drain of the first MOS tube is connected to the drain of the second MOS tube and serves as the output end of the power amplifier circuit, and the source of the second MOS tube is grounded.

[0012] Preferably, the output matching circuit includes a fifth capacitor, a sixth capacitor, a seventh switch and an eighth switch;

[0013] The first end of the fifth capacitor is connected to the second end of the first capacitor, the second end of the fifth capacitor is respectively connected to the first end of the eighth switch, the first end of the seventh switch serves as the input end of the output matching circuit, the second end of the seventh switch is connected to the first end of the sixth capacitor and the first end of the eighth switch, the second end of the sixth capacitor is grounded, and the second end of the eighth switch serves as the output end of the output matching circuit.

[0014] Preferably, the filtering circuit includes a first inductor and a seventh capacitor, the first end of the first inductor serves as the input end of the filtering circuit, the second end of the first inductor is connected to the first end of the seventh capacitor, the second end of the seventh capacitor is grounded, and the second end of the first inductor also serves as the output end of the filtering circuit.

[0015] Preferably, the ring oscillator circuit comprises an input port, a comparator, a logic output circuit and a digital-to-analog circuit;

[0016] The output end of the signal sampling circuit is connected to the input end of the input port, the output end of the digital-to-analog circuit is connected to the input end of the input port, the output end of the input port is connected to the input end of the comparator, the output end of the comparator is connected to the input end of the logic output circuit, and the output end of the logic output circuit is connected to the input end of the digital-to-analog circuit and connected together to the signal output end.

[0017] Compared with the prior art, the beneficial effect of the present invention lies in that the signal input end, the filter circuit, the signal sampling circuit, the loop amplifier, the ring oscillator circuit and the signal output end are electrically connected in sequence; the input end of the loop amplifier input matching circuit serves as the input end of the loop amplifier, the output end of the input matching circuit is connected to the input end of the inverter circuit, the output end of the inverter circuit is connected to the input end of the power amplifier circuit, the output end of the power amplifier circuit is connected to the input end of the output matching circuit, and the output end of the output matching circuit serves as the output end of the loop amplifier; the loop amplifier can improve the fast response of the ADC circuit and the effect of high inter-stage gain, and the stability is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0019] Figure 1 is a circuit diagram of a response and inter-stage gain ADC circuit provided by an embodiment of the present invention;

[0020] Figure 2 is a circuit diagram of a loop amplifier provided by an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the frequency response of the loop amplifier provided by an embodiment of the present invention;

[0022] Figure 4 It is a waveform diagram of a key node in the loop operational amplifier amplification stage provided by an embodiment of the present invention.

[0023] In the figure, 1. signal input terminal, 2. filter circuit, 3. signal sampling circuit, 4. loop amplifier, 41. input matching circuit, 42. inverter circuit, 43. power amplifier circuit, 44. output matching circuit, 5. ring oscillator circuit, 51. input port, 52. comparator, 53. logic output circuit, 54. digital-to-analog circuit, 6. signal output terminal, 7. first switch, 8. second switch, 9. third switch, 10. fourth switch, 11. fifth switch, 12. sixth switch, 13. seventh switch, 14. eighth switch, 15. first inverter, 16. second inverter, and 17. third inverter. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] Combined with Figure 1-Figure 4 As shown, an embodiment of the present invention provides a response and inter-stage gain ADC circuit, comprising: a signal input terminal 1, a filter circuit 2, a signal sampling circuit 3, a loop amplifier 4, a ring oscillator circuit 5 and a signal output terminal 6 which are electrically connected in sequence. The loop amplifier 4 comprises an input matching circuit 41, an inverter circuit 42, a power amplifier circuit 43 and an output matching circuit 44, the input terminal of the input matching circuit 41 serves as the input terminal of the loop amplifier 4, the output terminal of the input matching circuit 41 is connected to the input terminal of the inverter circuit 42, the output terminal of the inverter circuit 42 is connected to the input terminal of the power amplifier circuit 43, the output terminal of the power amplifier circuit 43 is connected to the input terminal of the output matching circuit 44, and the output terminal of the output matching circuit 44 serves as the output terminal of the loop amplifier 4.

[0026] In this embodiment, the input matching circuit 41 includes a first switch 7, a second switch 8, a third switch 9 and a first capacitor C1; the first end of the first switch 7 and the first end of the second switch 8 respectively serve as input ends of the input matching circuit 41, the second end of the first switch 7 is connected to the second end of the second switch 8 and is commonly connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the third switch 9 and serves as the output end of the input matching circuit 41, and the second end of the third switch 9 is used to connect to the VCM port.

[0027] In this embodiment, the inverter circuit 42 includes a second capacitor C2, a fourth switch 10, a first inverter 15, a second inverter 16, a third inverter 17, a third capacitor C3, a fifth switch 11, a fourth capacitor C4 and a sixth switch 12; a first end of the second capacitor C2 is connected to a second end of the first capacitor C1, a second end of the second capacitor C2 is respectively connected to a first end of the fourth switch 10 and an input end of the first inverter 15, an output end of the first inverter 15 is respectively connected to a second end of the fourth switch 10, a first end of the third capacitor C3 and a first end of the fourth capacitor C4, a second end of the third capacitor C3 is respectively connected to a first end of the fifth switch 11 and an input end of the second inverter 16, a second end of the fourth capacitor C4 is respectively connected to an input end of the third inverter 17 and a first end of the sixth switch 12, a second end of the fifth switch 11 and a second end of the sixth switch 12 are respectively used to connect to an external power supply; an output end of the second inverter 16 and an output end of the third inverter 17 are respectively used as output ends of the inverter circuit 42.

[0028] In this embodiment, the power amplifier circuit 43 includes a first MOS transistor Mcp and a second MOS transistor Mcn, the gate of the first MOS transistor Mcp is connected to the output end of the second inverter 16, the gate of the second MOS transistor Mcn is connected to the output end of the third inverter 17, the source of the first MOS transistor Mcp is connected to the external power supply, the drain of the first MOS transistor Mcp is connected to the drain of the second MOS transistor Mcn and serves as the output end of the power amplifier circuit 43, and the source of the second MOS transistor Mcn is grounded.

[0029] In this embodiment, the output matching circuit 44 includes a fifth capacitor C5, a sixth capacitor C6, a seventh switch 13 and an eighth switch 14; the first end of the fifth capacitor C5 is connected to the second end of the first capacitor C1, the second end of the fifth capacitor C5 is respectively connected to the first end of the eighth switch 14, the first end of the seventh switch 13 serves as the input end of the output matching circuit 44, the second end of the seventh switch 13 is connected to the first end of the sixth capacitor C6 and the first end of the eighth switch 14, the second end of the sixth capacitor is grounded, and the second end of the eighth switch 14 serves as the output end of the output matching circuit 44.

[0030] In this embodiment, the filter circuit 2 includes a first inductor L1 and a seventh capacitor C7, the first end of the first inductor L1 serves as the input end of the filter circuit 2, the second end of the first inductor L1 is connected to the first end of the seventh capacitor C7, the second end of the seventh capacitor C7 is grounded, and the second end of the first inductor L1 also serves as the output end of the filter circuit 2.

[0031] In this embodiment, the ring oscillator circuit 5 includes an input port 51, a comparator 52, a logic output circuit 53 and a digital-to-analog circuit 54; the output end of the signal sampling circuit 3 is connected to the input end of the input port 51, the output end of the digital-to-analog circuit 54 is connected to the input end of the input port 51, the output end of the input port 51 is connected to the input end of the comparator 52, the output end of the comparator 52 is connected to the input end of the logic output circuit 53, the output end of the logic output circuit 53 is connected to the input end of the digital-to-analog circuit 54 and is connected together to the signal output end 6.

[0032] Specifically, the loop amplifier structure is as follows: Figure 1 Compared with the ring oscillator, the signal of the loop amplifier is divided into two branch signals after passing through the first inverter 15. After the two branch signals are superimposed with the bias voltage Vos, two different output signals VBp and VBN are obtained, which respectively drive the second MOS transistor Mcn and the first MOS transistor Mcp to work in the subthreshold region. Figure 2 As shown, when the second MOS transistor Mcn and the first MOS transistor Mcp operate in the subthreshold region, a very high output impedance is formed at the output node, so that the output pole approaches the origin and is separated from the secondary pole, thereby improving the phase margin of the operational amplifier and stabilizing the loop amplifier 4.

[0033] Specifically, the working process of the entire amplifier is mainly divided into two working stages: a self-zero (reset) stage and an amplification stage.

[0034] In the self-zero stage, the clock of the first switch 7 is high, the clock of the second switch 8 is low, and the operational amplifier loop is in the off state. At this time, the input node VIN and the output node Vout are reset to the common mode level (VCM), and the input and output of the first stage in the amplifier are short-circuited and biased to the optimal bias potential. The difference between the common mode voltage and the optimal bias potential is stored by compensating the second capacitor C2 to ensure the gain of the amplifier in the amplification stage. At the same time, the third capacitor C3 and the fourth capacitor C4 are charged to Vos to provide the required bias voltage for the amplification stage.

[0035] During the amplification stage, the AMP clock is at a high level, the RST clock is at a low level, and the op amp loop is in a closed state. At this time, this stage can be subdivided into three stages: initial ramping stage (Initial Ramping), stable convergence stage (Stabilization) and stable stage (Steady State).

[0036] Figure 4It is a waveform diagram of the input node VIN, the output node VA of the first inverter, the second input node VBp, and the third input node VBN during the amplification stage. The working characteristics of the three stages will be analyzed based on this diagram below.

[0037] (1) Initial ramp stage

[0038] When the time is from 0 to 2 ns, the circuit operates in the initial ramp stage. At time t = 0, a step signal is input to the operational amplifier. At this time, the node VA is quickly biased to the low potential (VSS), while the nodes VBp and VBN are biased to the high potential (VDD), and the output signal will start to drop from the common-mode potential. Due to the effect of the negative feedback network, the input signal also drops quickly. Ideally, when the input voltage drops to the common-mode voltage, the final ideal voltage value will be obtained at the output terminal. However, there is a delay in the actual circuit, and the circuit requires a certain response time, which causes the output signal to continue to drop, resulting in overcharge, and the input signal also follows it down. Therefore, at t = 2 ns, the input signal is less than the common-mode voltage.

[0039] (2) Stable convergence stage

[0040] When the time is from 2 to 14 ns, the circuit operates in the stable convergence stage. At this time, the input signal converges to near VCM after the initial ramp stage and the output signal VA is obtained through amplification by the first-stage inverter. When VA - Vos > VCM, VBP starts to drop to VSS, and the PMOS transistor Mcp driven by it starts to charge the load capacitor, and the output terminal voltage starts to rise. When VA + Vos < VCM, VBN starts to rise to VDD, and the NMOS transistor McN driven by it starts to discharge the load capacitor, and the output voltage starts to drop. When VA - Vos < VCM and VA + VoS > VCM. At this time, VBp remains at a high level, while VBN remains at a low level, Mcp and McN are in the cut-off state, and the output voltage remains unchanged. Different from the ring oscillator, the existence of the Vos voltage reduces the charge and discharge time of the load capacitor at the output terminal, and thus reduces the swing of the output voltage. During the oscillation period of the operational amplifier, the waveforms of the nodes VIN and VA are both decaying oscillations. Due to the limited gain of the first two-stage structure, the waveform of VBp oscillates accordingly, and the minimum value of its voltage is constantly increasing, while VBN oscillates, and the maximum value of its voltage is constantly decreasing.

[0041] (3) Stable stage

[0042] When the time t=14~16ns, the circuit works in the stable stage. After the oscillation convergence in the stable convergence stage, the amplitude of VA will converge to the vicinity of the Vos voltage value, and the amplitudes of VBN and VBp will also drop significantly, making the third-level MOS tube work in the subthreshold region, thereby increasing the output resistance Rout and making the main pole of the circuit close to the DC point. The circuit will quickly enter a stable state and no longer oscillate. The first MOS tube Mcp and the second MOS tube Mcn are quickly cut off, and the output resistance approaches infinity.

[0043] Research shows that when the bias voltage Vos is larger, the dead zone voltage is larger, the circuit enters a stable state faster, and the op amp amplifies faster. However, since the output will be locked in the dead zone after stabilization and randomly distributed within the range, an increase in the bias voltage will cause the dead zone to expand, which will reduce the accuracy of the amplifier. The opposite is true when the bias voltage Vos is smaller.

[0044] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0045] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A response and inter-stage gain ADC circuit, characterized in that: include: A signal input terminal, a filter circuit, a signal sampling circuit, a loop amplifier, a ring oscillator circuit and a signal output terminal electrically connected in sequence; The loop amplifier comprises an input matching circuit, an inverter circuit, a power amplifier circuit and an output matching circuit. The input end of the input matching circuit serves as the input end of the loop amplifier, the output end of the input matching circuit is connected to the input end of the inverter circuit, the output end of the inverter circuit is connected to the input end of the power amplifier circuit, the output end of the power amplifier circuit is connected to the input end of the output matching circuit, and the output end of the output matching circuit serves as the output end of the loop amplifier.

2. The response and inter-stage gain ADC circuit according to claim 1, characterized in that: The input matching circuit includes a first switch, a second switch, a third switch and a first capacitor; The first end of the first switch and the first end of the second switch serve as input ends of the input matching circuit respectively, the second end of the first switch is connected to the second end of the second switch and are commonly connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the third switch and serves as the output end of the input matching circuit, and the second end of the third switch is used to connect to the VCM port.

3. The response and inter-stage gain ADC circuit as claimed in claim 2, characterized in that: The inverter circuit includes a second capacitor, a fourth switch, a first inverter, a second inverter, a third inverter, a third capacitor, a fifth switch, a fourth capacitor and a sixth switch; The first end of the second capacitor is connected to the second end of the first capacitor, the second end of the second capacitor is respectively connected to the first end of the fourth switch and the input end of the first inverter, the output end of the first inverter is respectively connected to the second end of the fourth switch, the first end of the third capacitor and the first end of the fourth capacitor, the second end of the third capacitor is respectively connected to the first end of the fifth switch and the input end of the second inverter, the second end of the fourth capacitor is respectively connected to the input end of the third inverter and the first end of the sixth switch, the second end of the fifth switch and the second end of the sixth switch are respectively used to connect to an external power supply; the output end of the second inverter and the output end of the third inverter are respectively used as the output end of the inverter circuit.

4. The response and inter-stage gain ADC circuit as claimed in claim 3, characterized in that: The power amplifier circuit includes a first MOS tube and a second MOS tube, the gate of the first MOS tube is connected to the output end of the second inverter, the gate of the second MOS tube is connected to the output end of the third inverter, the source of the first MOS tube is connected to the external power supply, the drain of the first MOS tube is connected to the drain of the second MOS tube and serves as the output end of the power amplifier circuit, and the source of the second MOS tube is grounded.

5. The response and inter-stage gain ADC circuit as claimed in claim 4, characterized in that: The output matching circuit includes a fifth capacitor, a sixth capacitor, a seventh switch and an eighth switch; The first end of the fifth capacitor is connected to the second end of the first capacitor, the second end of the fifth capacitor is respectively connected to the first end of the eighth switch, the first end of the seventh switch serves as the input end of the output matching circuit, the second end of the seventh switch is connected to the first end of the sixth capacitor and the first end of the eighth switch, the second end of the sixth capacitor is grounded, and the second end of the eighth switch serves as the output end of the output matching circuit.

6. The response and inter-stage gain ADC circuit according to claim 1, characterized in that: The filter circuit includes a first inductor and a seventh capacitor, wherein the first end of the first inductor serves as the input end of the filter circuit, the second end of the first inductor is connected to the first end of the seventh capacitor, the second end of the seventh capacitor is grounded, and the second end of the first inductor also serves as the output end of the filter circuit.

7. The response and inter-stage gain ADC circuit according to claim 1, characterized in that: The ring oscillator circuit includes an input port, a comparator, a logic output circuit and a digital-to-analog circuit; The output end of the signal sampling circuit is connected to the input end of the input port, the output end of the digital-to-analog circuit is connected to the input end of the input port, the output end of the input port is connected to the input end of the comparator, the output end of the comparator is connected to the input end of the logic output circuit, and the output end of the logic output circuit is connected to the input end of the digital-to-analog circuit and connected together to the signal output end.

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