Transmission Gate Switch Sampling Circuit with Substrate Bias

Abstract

The present invention relates to a transmission gate switch sampling circuit with substrate bias. By adopting the substrate bias technology for transistors NMOS1 and PMOS1, the body effect of the sampling transistor is reduced. At the same time, the gate voltage bootstrap circuits of the NMOS transistor and the PMOS transistor are used to ensure that the VGS of the sampling transistor is a constant value within the entire input range. Moreover, the structure of the sampling transistor is a transmission gate switch with substrate bias technology. By canceling the channel charge flowing into the holding capacitor when it is turned off, the channel charge injection effect is reduced. It can not only reduce the influence of the input signal on the threshold voltage of the sampling transistor, that is, reduce the influence of the body effect of the sampling transistor on the switch nonlinearity, but also effectively suppress the influence of the channel charge injection effect on the sampling circuit. When actually applied to the sampling / holding circuit, it effectively improves its dynamic range and sampling accuracy, achieving the effect of improving the sampling performance of the sampling / holding circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of sampling circuit design, and relates to a transmission gate switch sampling circuit with substrate bias. Background Art

[0002] In the context of the rapid development of current electronic technologies, the application scale of sampling / holding circuits continues to grow. With the high-speed development of fields such as the Internet of Things, artificial intelligence, autonomous driving, and 5G communication, the demand for sampling / holding circuits is increasing continuously, driving their development towards high precision, low power consumption, high speed, and miniaturization. High-performance sampling / holding circuits are one of the key technologies in many integrated circuit applications. As a crucial component in the sampling / holding circuit, the performance of the switch determines the accuracy and linearity of the entire sampling / holding circuit. However, with the increase in sampling frequency and the decrease in power supply voltage, the linearity of traditional MOS switches is continuously decreasing, limiting the dynamic range and sampling accuracy of the sampling / holding circuit. Therefore, it is extremely urgent to develop a sampling / holding circuit with excellent sampling performance. Summary of the Invention

[0003] Aiming at the problems existing in the above traditional technologies, the present invention proposes a transmission gate switch sampling circuit with substrate bias, which can effectively improve the sampling performance of the sampling / holding circuit.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] Provide a transmission gate switch sampling circuit with substrate bias, including an inverter, transistor NMOS1, transistor NMOS2, transistor NMOS3, transistor PMOS1, a holding capacitor, an NMOS gate voltage bootstrap circuit, and a PMOS gate voltage bootstrap circuit;

[0006] The first clock terminal of the NMOS transistor gate bootstrap circuit and the input terminal of the inverter are both used to connect to the sampling control input terminal. The output terminal of the inverter is respectively connected to the second clock terminal of the NMOS transistor gate bootstrap circuit and the clock terminal of the PMOS transistor gate bootstrap circuit. The input terminal of the NMOS transistor gate bootstrap circuit, the input terminal of the PMOS transistor gate bootstrap circuit, the source electrode of transistor NMOS1, the source electrode of transistor NMOS2, and the source electrode of transistor PMOS1 are all used to connect to the signal input terminal. The output terminal of the NMOS transistor gate bootstrap circuit is respectively connected to the gate electrode of transistor NMOS1, the gate electrode of transistor NMOS2, and the second gate drive terminal of the PMOS transistor gate bootstrap circuit. The control terminal of the NMOS transistor gate bootstrap circuit is connected to the first gate drive terminal of the PMOS transistor gate bootstrap circuit. The bias terminal of the PMOS transistor gate bootstrap circuit is connected to the substrate electrode of transistor PMOS1. The output terminal of the PMOS transistor gate bootstrap circuit is connected to the gate electrode of transistor PMOS1. The drain electrode of transistor NMOS1 and the drain electrode of transistor PMOS1 are connected together as the sampling output terminal. The drain electrode of transistor NMOS2 is respectively connected to the substrate electrode of transistor NMOS1 and the drain electrode of transistor NMOS3. The source electrode of transistor NMOS3 is grounded. The gate electrode of transistor NMOS3 is used to connect to the sampling control input terminal. One end of the holding capacitor is connected to the sampling output terminal, and the other end of the holding capacitor is grounded;

[0007] Transistors NMOS2 and NMOS3 are used to reduce the body effect of transistor NMOS1 through the substrate bias effect. The NMOS transistor gate bootstrap circuit is used to keep the gate-source voltage of transistor NMOS1 constant during the sampling stage. The PMOS transistor gate bootstrap circuit is used to reduce the body effect of transistor PMOS1 through the substrate bias effect and keep the gate-source voltage of transistor PMOS1 constant during the sampling stage. Transistors NMOS1 and PMOS1 form a transmission gate switch.

[0008] In one embodiment, the NMOS transistor gate bootstrap circuit includes transistors NMOS4 to NMOS9, transistors PMOS2 to PMOS5, and capacitor C1;

[0009] The source of transistor NMOS4 is the input terminal of the NMOS transistor gate voltage bootstrap circuit. The substrate of transistor NMOS4 is grounded. The drain of transistor NMOS4 is connected to the source of transistor NMOS5, the source of transistor NMOS6, the drain of transistor NMOS7, and one end of capacitor C1 respectively. The source of transistor NMOS7 is grounded. The gate of transistor NMOS7 is the first clock terminal of the NMOS transistor gate voltage bootstrap circuit. The other end of capacitor C1 is connected to the source of transistor PMOS3 and serves as the control terminal of the NMOS transistor gate voltage bootstrap circuit. The drain of transistor PMOS3 is used to connect to the power supply. The gate of transistor PMOS3 is connected to the drain of transistor PMOS4, the source of transistor NMOS8, and the gate of transistor NMOS4 respectively;

[0010] The source of transistor PMOS4 is connected to the source of transistor PMOS3. The gate of transistor PMOS4 is connected to the drain of transistor NMOS5, the drain of transistor NMOS6, and the source of transistor PMOS2 respectively. The drain and substrate of transistor PMOS2 are both used to connect to the power supply. The substrates of transistor NMOS5 and transistor NMOS6 are both grounded. The gate of transistor NMOS5 is connected to the gate of transistor NMOS4 and serves as the output terminal of the NMOS transistor gate voltage bootstrap circuit. The gate of transistor NMOS6 is connected to the gate of transistor PMOS2 and serves as the second clock terminal of the NMOS transistor gate voltage bootstrap circuit;

[0011] The substrate of transistor NMOS8 is grounded. The gate of transistor NMOS8, the substrate and drain of transistor PMOS5 are all used to connect to the power supply. The source of transistor PMOS5 is connected to the drain of transistor NMOS8 and the drain of transistor NMOS9 respectively. The source of transistor NMOS9 is grounded. The gate of transistor PMOS5 is connected to the gate of transistor NMOS9 and connected to the first clock terminal of the NMOS transistor gate voltage bootstrap circuit.

[0012] In one embodiment, the PMOS transistor gate voltage bootstrap circuit includes transistors NMOS10 to NMOS14, transistors PMOS6 to PMOS12, capacitor C2, and capacitor C3;

[0013] The gate of transistor NMOS10 is connected to the gate of transistor PMOS6 and serves as the clock terminal of the PMOS gate voltage bootstrap circuit. The source of transistor NMOS10 is grounded. The drain of transistor NMOS10 is respectively connected to the source of transistor PMOS6, one end of capacitor C2, and the source of transistor NMOS11. The substrate terminal of transistor PMOS6, the drain of transistor PMOS6, and the drain of transistor PMOS7 are all used to connect to the power supply. The source of transistor PMOS7 is respectively connected to the source of transistor PMOS8, the other end of capacitor C2, and the source of transistor PMOS9. The gate of transistor PMOS7 is respectively connected to the drain of transistor PMOS8 and the drain of transistor NMOS11. The gates of transistor PMOS8 and transistor NMOS11 are both used to connect to the power supply;

[0014] The gate of transistor PMOS9 is used to connect to the power supply. The drain of transistor PMOS9 is respectively connected to the source of transistor NMOS12 and one end of capacitor C3. The gate of NMOS12 is the first gate drive terminal of the PMOS gate voltage bootstrap circuit. The drain of transistor NMOS12, the source of transistor NMOS13, and the drain of transistor PMOS11 are connected together as the bias terminal of the PMOS gate voltage bootstrap circuit. The drain of transistor NMOS13 is the input terminal of the PMOS gate voltage bootstrap circuit. The gate of transistor NMOS13 is the second gate drive terminal of the PMOS gate voltage bootstrap circuit. The sources of transistor PMOS11 and transistor PMOS12 are both used to connect to the power supply. The gates of transistor PMOS11, transistor PMOS12, and transistor NMOS14 are all connected to the clock terminal of the PMOS gate voltage bootstrap circuit. The drain of transistor PMOS12 is respectively connected to the drain of transistor NMOS14 and the drain of transistor PMOS10. The source of transistor NMOS14 and the gate of transistor PMOS10 are both grounded. The substrate terminal of transistor PMOS10 is used to connect to the power supply. The source of transistor PMOS10 is connected to the other end of capacitor C3 and serves as the output terminal of the PMOS gate voltage bootstrap circuit.

[0015] One technical solution in the above technical solutions has the following advantages and beneficial effects:

[0016] The above transmission gate switch sampling circuit with substrate bias reduces the body effect of the sampling transistor by adopting the substrate bias technology for the transistor NMOS1 and the transistor PMOS1. At the same time, the NMOS transistor gate voltage bootstrap circuit and the PMOS transistor gate voltage bootstrap circuit are used to ensure that the VGS of the sampling transistor is a constant value within the entire input range. Moreover, the structure of the sampling transistor is a transmission gate switch with substrate bias technology. By canceling out the channel charge flowing into the holding capacitor when it is turned off, the channel charge injection effect is reduced. It can not only reduce the influence of the input signal on the threshold voltage of the sampling transistor, that is, reduce the influence of the body effect of the sampling transistor on the switch nonlinearity, but also effectively suppress the influence of the channel charge injection effect on the sampling circuit. When actually applied to the sampling / holding circuit, it effectively improves its dynamic range and sampling accuracy, achieving the effect of improving the sampling performance of the sampling / holding circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of a transmission gate switch sampling circuit with substrate bias in an embodiment;

[0019] Figure 2 It is a schematic structural diagram of an NMOS transistor gate voltage bootstrap circuit in an embodiment;

[0020] Figure 3 It is a schematic structural diagram of a PMOS transistor gate voltage bootstrap circuit in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the following further describes the present invention in detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0022] It should be noted that when "embodiment" is mentioned in this text, it means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of the present invention. The display of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0023] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0024] In one embodiment, as Figure 1 shown, a transmission gate switch sampling circuit with substrate bias is provided, which includes an inverter INV1, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor PMOS1, a holding capacitor C0, an NMOS gate voltage bootstrap circuit and a PMOS gate voltage bootstrap circuit.

[0025] The first clock terminal (CLK) of the NMOS transistor gate voltage bootstrap circuit (i.e., BTSP_NMOS) and the input terminal of the inverter INV1 are both used to connect to the sampling control input terminal (VSAMP). The output terminal of the inverter INV1 is respectively connected to the second clock terminal (CLKB) of the NMOS transistor gate voltage bootstrap circuit and the clock terminal (CLK) of the PMOS transistor gate voltage bootstrap circuit (i.e., BTSP_PMOS). The input terminal (VIN) of the NMOS transistor gate voltage bootstrap circuit, the input terminal (VIN) of the PMOS transistor gate voltage bootstrap circuit, the source electrode of the transistor NMOS1, the source electrode of the transistor NMOS2, and the source electrode of the transistor PMOS1 are all used to connect to the signal input terminal (i.e., VSIG). The output terminal (VOUT) of the NMOS transistor gate voltage bootstrap circuit is respectively connected to the gate electrode of the transistor NMOS1, the gate electrode of the transistor NMOS2, and the second gate driving terminal (i.e., VG2) of the PMOS transistor gate voltage bootstrap circuit. The control terminal (i.e., VC) of the NMOS transistor gate voltage bootstrap circuit is connected to the first gate driving terminal (i.e., VG1) of the PMOS transistor gate voltage bootstrap circuit. The bias terminal (i.e., VB) of the PMOS transistor gate voltage bootstrap circuit is connected to the substrate electrode of the transistor PMOS1. The output terminal (OUT) of the PMOS transistor gate voltage bootstrap circuit is connected to the gate electrode of the transistor PMOS1. The drain electrode of the transistor NMOS1 and the drain electrode of the transistor PMOS1 are connected together as the sampling output terminal OUT. The drain electrode of the transistor NMOS2 is respectively connected to the substrate electrode of the transistor NMOS1 and the drain electrode of the transistor NMOS3. The source electrode of the transistor NMOS3 is grounded. The gate electrode of the transistor NMOS3 is used to connect to the sampling control input terminal VSAMP. One end of the holding capacitor C0 is connected to the sampling output terminal OUT, and the other end of the holding capacitor C0 is grounded.

[0026] The transistors NMOS2 and NMOS3 are used to reduce the body effect of the transistor NMOS1 through the substrate bias effect. The NMOS transistor gate voltage bootstrap circuit is used to keep the gate-source voltage of the transistor NMOS1 constant during the sampling stage. The PMOS transistor gate voltage bootstrap circuit is used to reduce the body effect of the transistor PMOS1 through the substrate bias effect and keep the gate-source voltage of the transistor PMOS1 constant during the sampling stage. The transistors NMOS1 and PMOS1 form a transmission gate switch.

[0027] It can be understood that the power supply terminals of the NMOS transistor gate bootstrap circuit and the PMOS transistor gate bootstrap circuit are used to connect to the power supply VDD, and the ground terminals of the NMOS transistor gate bootstrap circuit and the PMOS transistor gate bootstrap circuit are both used to connect to the ground (VSS). Among them, the transistor NMOS and the transistor PMOS are metal-oxide-semiconductors of two different channel types respectively. The transistor NMOS is an N-type metal-oxide-semiconductor, and the transistor PMOS is a P-type metal-oxide-semiconductor. The same type of transistor devices hereinafter can be understood similarly. For the NMOS transistor gate bootstrap circuit, its CLK and CLKB signals are a pair of complementary clock signals. When CLK is at a high level, CLKB is at a low level, and vice versa; the CLK and CLKB signals control the NMOS transistor gate bootstrap circuit to ensure that it conducts or turns off at the correct time to achieve gate voltage bootstrapping. For the PMOS transistor gate bootstrap circuit, its working clock follows the CLKB signal to achieve the corresponding gate voltage bootstrapping function.

[0028] Specifically, the transistor NMOS1 and the transistor PMOS1 are used as sampling transistors to form a transmission gate switch. The transistor NMOS2 and the transistor NMOS3 perform substrate biasing on the transistor NMOS1, thereby reducing the body effect of the transistor NMOS1. The PMOS transistor gate bootstrap circuit performs substrate biasing on the transistor PMOS1, thereby reducing the body effect of the transistor PMOS1. The channel charge injection effect is reduced by canceling the channel charge flowing into the holding capacitor C0 when the transmission gate switch is turned off, so as to effectively suppress the influence of the channel charge injection effect on the sampling circuit. At the same time, the VGS (gate-source voltage) of the transistor NMOS1 is made to be a constant value during the sampling stage through the NMOS transistor gate bootstrap circuit BTSP_NMOS, and the VGS of the transistor PMOS1 is made to be a constant value during the sampling stage through the PMOS transistor gate bootstrap circuit BTSP_PMOS, so as to make the VGS of the sampling transistor be a constant value within the entire input range, and reduce the degree of change of the sampling resistance of the sampling circuit with the input signal.

[0029] The above-described transmission gate switch sampling circuit with substrate bias reduces the body effect of the sampling transistor by adopting the substrate bias technology for transistors NMOS1 and PMOS1. At the same time, the gate voltage bootstrap circuits of the NMOS transistor and the PMOS transistor are used to ensure that the VGS of the sampling transistor is a constant value within the entire input range. Moreover, the structure of the sampling transistor is a transmission gate switch with substrate bias technology. By canceling the channel charge flowing into the holding capacitor C0 when it is turned off, the channel charge injection effect is reduced. It can not only reduce the influence of the input signal on the threshold voltage of the sampling transistor, that is, reduce the influence of the body effect of the sampling transistor on the switch non-linearity, but also effectively suppress the influence of the channel charge injection effect on the sampling circuit. When actually applied to the sampling / holding circuit, it effectively improves its dynamic range and sampling accuracy, achieving the effect of improving the sampling performance of the sampling / holding circuit.

[0030] In one embodiment, as Figure 2 shown, the gate voltage bootstrap circuit of the NMOS transistor may include transistors NMOS4 to NMOS9, transistors PMOS2 to PMOS5, and capacitor C1. The source of transistor NMOS4 is the input terminal VIN of the gate voltage bootstrap circuit of the NMOS transistor. The substrate terminal of transistor NMOS4 is grounded to VSS. The drain of transistor NMOS4 is respectively connected to the source of transistor NMOS5, the source of transistor NMOS6, the drain of transistor NMOS7, and one end of capacitor C1. The source of transistor NMOS7 is grounded to VSS. The gate of transistor NMOS7 is the first clock terminal CLK of the gate voltage bootstrap circuit of the NMOS transistor. The other end of capacitor C1 is connected to the source of transistor PMOS3 and serves as the control terminal VC of the gate voltage bootstrap circuit of the NMOS transistor. The drain of transistor PMOS3 is used to connect to the power supply VDD. The gate of transistor PMOS3 is respectively connected to the drain of transistor PMOS4, the source of transistor NMOS8, and the gate of transistor NMOS4.

[0031] The source of the PMOS transistor PMOS4 is connected to the source of the PMOS transistor PMOS3. The gate of the PMOS transistor PMOS4 is respectively connected to the drain of the NMOS transistor NMOS5, the drain of the NMOS transistor NMOS6, and the source of the PMOS transistor PMOS2. The drain and the substrate of the PMOS transistor PMOS2 are both used to connect to the power supply VDD. The substrates of the NMOS transistors NMOS5 and NMOS6 are both grounded to VSS. The gate of the NMOS transistor NMOS5 is connected to the gate of the NMOS transistor NMOS4 and serves as the output terminal OUT of the NMOS transistor gate voltage bootstrap circuit. The gate of the NMOS transistor NMOS6 is connected to the gate of the PMOS transistor PMOS2 and serves as the second clock terminal CLKB of the NMOS transistor gate voltage bootstrap circuit. The substrate of the NMOS transistor NMOS8 is grounded to VSS. The gate of the NMOS transistor NMOS8, the substrate of the PMOS transistor PMOS5, and the drain of the PMOS transistor PMOS5 are all used to connect to the power supply VDD. The source of the PMOS transistor PMOS5 is respectively connected to the drain of the NMOS transistor NMOS8 and the drain of the NMOS transistor NMOS9. The source of the NMOS transistor NMOS9 is grounded to VSS. The gate of the PMOS transistor PMOS5 is connected to the gate of the NMOS transistor NMOS9 and is connected to the first clock terminal CLK of the NMOS transistor gate voltage bootstrap circuit.

[0032] It can be understood that in this embodiment, the structural design of the NMOS transistor gate voltage bootstrap circuit as shown in Figure 2 is adopted to provide the required gate voltage bootstrap function with a more concise and efficient circuit structure design. Its structural design using almost all transistors can effectively reduce the circuit area and improve the circuit response speed.

[0033] Among them, the specific implementation process of maintaining a constant value of VGS in the sampling stage can be as follows: In the reset stage, that is, when CLK is at a high level, the NMOS transistors NMOS7, NMOS8, NMOS9, PMOS transistor PMOS2, and PMOS transistor PMOS3 are turned on, and the PMOS transistor PMOS4 is turned off. At this time, the current charges the capacitor C1 through the PMOS transistor PMOS3, so that the voltage difference of the capacitor C1 reaches VDD. When CLK is at a low level, the NMOS transistors NMOS4 and NMOS6 are turned on, the NMOS transistors NMOS7 and NMOS9 are turned off, the PMOS transistors PMOS2 and PMOS3 are turned off, and the PMOS transistors PMOS4 and PMOS5 are turned on. Based on the law of conservation of charge, since the voltage value of the capacitor C1 has been charged to VDD in the reset stage, in the sampling stage, the voltage of the VC node is VIN + VDD, so that the potential of the OUT node of the gate voltage bootstrap circuit is also VIN + VDD, so that the gate potential of the transistor (sampling transistor) NMOS1 is VIN + VDD, and the input signal of the source stage of the NMOS transistor NMOS1 in the sampling stage is VIN. Therefore, through the NMOS gate voltage bootstrap voltage, the VGS of the NMOS transistor NMOS1 can be a constant value in the sampling stage.

[0034] In one embodiment, as Figure 3 shown, the PMOS gate voltage bootstrap circuit includes transistors NMOS10 to NMOS14, transistors PMOS6 to PMOS12, capacitor C2, and capacitor C3. The gate of transistor NMOS10 is connected to the gate of transistor PMOS6 and serves as the clock terminal CLK of the PMOS gate voltage bootstrap circuit. The source of transistor NMOS10 is grounded, and the drain of transistor NMOS10 is respectively connected to the source of transistor PMOS6, one end of capacitor C2, and the source of transistor NMOS11. The substrate terminal of transistor PMOS6, the drain of transistor PMOS6, and the drain of transistor PMOS7 are all used to connect to the power supply VDD. The source of transistor PMOS7 is respectively connected to the source of transistor PMOS8, the other end of capacitor C2, and the source of transistor PMOS9. The gate of transistor PMOS7 is respectively connected to the drain of transistor PMOS8 and the drain of transistor NMOS11. The gates of transistor PMOS8 and transistor NMOS11 are both used to connect to the power supply VDD.

[0035] The gate of transistor PMOS9 is used to connect to the power supply VDD. The drain of transistor PMOS9 is respectively connected to the source of transistor NMOS12 and one end of capacitor C3. The gate of NMOS12 is the first gate drive terminal VG1 of the PMOS gate voltage bootstrap circuit. The drain of transistor NMOS12, the source of transistor NMOS13, and the drain of transistor PMOS11 are connected together as the bias terminal VB of the PMOS gate voltage bootstrap circuit. The drain of transistor NMOS13 is the input terminal VIN of the PMOS gate voltage bootstrap circuit. The gate of transistor NMOS13 is the second gate drive terminal VG2 of the PMOS gate voltage bootstrap circuit. The sources of transistor PMOS11 and transistor PMOS12 are both used to connect to the power supply VDD. The gates of transistor PMOS11, transistor PMOS12, and transistor NMOS14 are all connected to the clock terminal CLK of the PMOS gate voltage bootstrap circuit. The drain of transistor PMOS12 is respectively connected to the drain of transistor NMOS14 and the drain of transistor PMOS10. The source of transistor NMOS14 and the gate of transistor PMOS10 are both grounded. The substrate terminal of transistor PMOS10 is used to connect to the power supply VDD. The source of transistor PMOS10 is connected to the other end of capacitor C3 and serves as the output terminal OUT of the PMOS gate voltage bootstrap circuit.

[0036] It can be understood that in this embodiment, the following is adopted as Figure 3The structural design of the PMOS transistor gate voltage bootstrap circuit shown provides the above-mentioned required another gate voltage bootstrap function with a more concise and efficient circuit structure design. It also adopts an almost all-transistor structure design, which can effectively reduce the circuit area and improve the circuit response speed.

[0037] Among them, in the PMOS transistor gate voltage bootstrap circuit, the substrate of the transistor PMOS1 is controlled by the transistor NMOS12, the transistor NMOS13, and the transistor PMOS11 to achieve the required substrate bias effect. At the same time, the constant control of the VGS of the transistor PMOS1 is achieved through the cooperation of the transistor PMOS7, the transistor PMOS9, the transistor PMOS10, the transistor PMOS12, the transistor NMOS14, etc. and the capacitor C3 (i.e., the bootstrap capacitor). The control principle can be understood by analogy with the NMOS transistor gate voltage bootstrap circuit. Those skilled in the art can adopt the specific structural design of other PMOS transistor gate voltage bootstrap circuits that can achieve the same function according to the above implementation principle, as long as the same control purpose can be achieved.

[0038] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0039] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, all of which belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A transmission gate switch sampling circuit with substrate bias, characterized in that It includes transistor NMOS1, transistor NMOS2, transistor NMOS3, transistor PMOS1 and PMOS gate voltage bootstrap circuit. Transistor NMOS1 and transistor PMOS1 act as sampling transistors and together form a transmission gate switch. Transistor NMOS2 and transistor NMOS3 are used to reduce the body effect of transistor NMOS1 through the substrate bias effect. The PMOS gate voltage bootstrap circuit is used to reduce the body effect of transistor PMOS1 through the substrate bias effect and keep the gate-source voltage of transistor PMOS1 constant during the sampling phase; The input terminal of the PMOS gate voltage bootstrap circuit, the source of transistor NMOS1, the source of transistor NMOS2 and the source of transistor PMOS1 are all used to connect to the signal input terminal. The drain of transistor NMOS1 and the drain of transistor PMOS1 are connected together as the sampling output terminal. The drain of transistor NMOS2 is respectively connected to the substrate terminal of transistor NMOS1 and the drain of transistor NMOS3. The source of transistor NMOS3 is grounded, and the gate of transistor NMOS3 is used to connect to the sampling control input terminal; The PMOS gate voltage bootstrap circuit includes transistors NMOS10 to NMOS14, transistors PMOS6 to PMOS12, capacitor C2 and capacitor C3; The gate of transistor NMOS10 is connected to the gate of transistor PMOS6 and serves as the clock terminal of the PMOS gate voltage bootstrap circuit. The source of transistor NMOS10 is grounded. The drain of transistor NMOS10 is respectively connected to the source of transistor PMOS6, one end of capacitor C2 and the source of transistor NMOS11. The substrate terminal, the drain of transistor PMOS6 and the drain of transistor PMOS7 are all used to connect to the power supply. The source of transistor PMOS7 is respectively connected to the source of transistor PMOS8, the other end of capacitor C2 and the source of transistor PMOS9. The gate of transistor PMOS7 is respectively connected to the drain of transistor PMOS8 and the drain of transistor NMOS11. The gates of transistor PMOS8 and transistor NMOS11 are both used to connect to the power supply; The gate of transistor PMOS9 is used to connect to the power supply. The drain of transistor PMOS9 is respectively connected to the source of transistor NMOS12 and one end of capacitor C3. The gate of transistor NMOS12 is the first gate driving terminal of the PMOS gate voltage bootstrap circuit. The drain of transistor NMOS12, the source of transistor NMOS13 and the drain of transistor PMOS11 are connected together as a bias terminal and connected to the substrate of transistor PMOS1. The drain of transistor NMOS13 is the input terminal of the PMOS gate voltage bootstrap circuit. The gate of transistor NMOS13 is the second gate driving terminal of the PMOS gate voltage bootstrap circuit. The sources of transistor PMOS11 and transistor PMOS12 are both used to connect to the power supply. The gates of transistor PMOS11, transistor PMOS12 and transistor NMOS14 are all connected to the clock terminal of the PMOS gate voltage bootstrap circuit. The drain of transistor PMOS12 is respectively connected to the drain of transistor NMOS14 and the drain of transistor PMOS10. The source of transistor NMOS14 and the gate of transistor PMOS10 are both grounded. The substrate of transistor PMOS10 is used to connect to the power supply. The source of transistor PMOS10 is connected to the other end of capacitor C3 and connected to the gate of transistor PMOS1.

2. The transmission gate switch sampling circuit with substrate bias according to claim 1, wherein It further includes an inverter, a holding capacitor and an NMOS gate voltage bootstrap circuit; the NMOS gate voltage bootstrap circuit is used to keep the gate-source voltage of transistor NMOS1 constant during the sampling stage; The first clock terminal of the NMOS gate voltage bootstrap circuit and the input terminal of the inverter are both used to connect to the sampling control input terminal. The output terminal of the inverter is respectively connected to the second clock terminal of the NMOS gate voltage bootstrap circuit and the clock terminal of the PMOS gate voltage bootstrap circuit. The input terminal of the NMOS gate voltage bootstrap circuit is used to connect to the signal input terminal. The output terminal of the NMOS gate voltage bootstrap circuit is respectively connected to the gate of transistor NMOS1, the gate of transistor NMOS2 and the second gate driving terminal of the PMOS gate voltage bootstrap circuit. The control terminal of the NMOS gate voltage bootstrap circuit is connected to the first gate driving terminal of the PMOS gate voltage bootstrap circuit. One end of the holding capacitor is connected to the sampling output terminal, and the other end of the holding capacitor is grounded.

3. The transmission gate switch sampling circuit with substrate bias according to claim 2, characterized in that, The NMOS gate voltage bootstrap circuit includes transistors NMOS4 to NMOS9, transistors PMOS2 to PMOS5 and capacitor C1; The source of transistor NMOS4 is the input terminal of the NMOS gate voltage bootstrap circuit. The substrate of transistor NMOS4 is grounded. The drain of transistor NMOS4 is connected to the source of transistor NMOS5, the source of transistor NMOS6, the drain of transistor NMOS7, and one end of capacitor C1 respectively. The source of transistor NMOS7 is grounded. The gate of transistor NMOS7 is the first clock terminal of the NMOS gate voltage bootstrap circuit. The other end of capacitor C1 is connected to the source of transistor PMOS3 and serves as the control terminal of the NMOS gate voltage bootstrap circuit. The drain of transistor PMOS3 is used to connect to the power supply. The gate of transistor PMOS3 is connected to the drain of transistor PMOS4, the source of transistor NMOS8, and the gate of transistor NMOS4 respectively; The source of transistor PMOS4 is connected to the source of transistor PMOS3. The gate of transistor PMOS4 is connected to the drain of transistor NMOS5, the drain of transistor NMOS6, and the source of transistor PMOS2 respectively. The drain and substrate of transistor PMOS2 are both used to connect to the power supply. The substrates of transistor NMOS5 and transistor NMOS6 are both grounded. The gate of transistor NMOS5 is connected to the gate of transistor NMOS4 and serves as the output terminal of the NMOS gate voltage bootstrap circuit. The gate of transistor NMOS6 is connected to the gate of transistor PMOS2 and serves as the second clock terminal of the NMOS gate voltage bootstrap circuit; The substrate of transistor NMOS8 is grounded. The gate of transistor NMOS8, the substrate and drain of transistor PMOS5 are all used to connect to the power supply. The source of transistor PMOS5 is connected to the drain of transistor NMOS8 and the drain of transistor NMOS9 respectively. The source of transistor NMOS9 is grounded. The gate of transistor PMOS5 is connected to the gate of transistor NMOS9 and connected to the first clock terminal of the NMOS gate voltage bootstrap circuit.

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