Manufacturing method of circuit board, circuit board and circuit board assembly

Abstract

The circuit board manufacturing method comprises the steps that a circuit substrate is provided and comprises a dielectric layer, a conductive part and a first insulating layer, the conductive part is located on the surface of the dielectric layer, and the first insulating layer covers the surface, away from the dielectric layer, of the conductive part; the circuit substrate is electroplated, a first electroplated layer is formed on the surface of the conductive part, and the first electroplated layer further wraps part of the surface of the first insulating layer to form a groove; removing the first insulating layer; and forming a solder mask layer, wherein the groove is exposed to the solder mask layer. After the conductive part is formed through etching, the first electroplated layer is formed in an electroplating mode, so that the bonding pad is formed, the etching factor can be improved, a line with smaller spacing can be formed, and the wiring density can be improved; through shielding of the first insulating layer, a bonding pad with a groove is conveniently formed in the electroplating process, and reflow soldering is carried out after conductive paste is placed in the groove in the process of installing an electronic element on a circuit board, so that the possibility of a bridging short circuit phenomenon is reduced or avoided. The invention further provides a circuit board and a circuit board assembly.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a method for manufacturing a circuit board, a circuit board, and a circuit board assembly. Background Art

[0002] With the miniaturization of terminal devices, the packaging density of circuit boards in terminal devices has gradually increased. The packaging density of circuit boards can be improved by reducing the size of pads, the spacing between pads, and increasing the wiring density. However, the reduction in the size and spacing of pads will increase the risk of poor quality (such as short circuit); the increase in wiring density makes the circuit board processing process more difficult, and the traditional etching process encounters a bottleneck. Summary of the invention

[0003] The present application provides a method for manufacturing a circuit board, comprising the following steps: providing a circuit substrate, comprising a dielectric layer, a conductive portion and a first insulating layer, wherein the conductive portion is located on a surface of the dielectric layer, and the first insulating layer covers a surface of the conductive portion away from the dielectric layer; electroplating the circuit substrate to form a first electroplating layer on the surface of the conductive portion, wherein the first electroplating layer also covers a portion of the surface of the first insulating layer to form a groove; removing the first insulating layer; and forming a solder mask, wherein the solder mask covers a portion of the first electroplating layer, and the groove is exposed to the solder mask.

[0004] In some embodiments of the present application, the circuit substrate includes multiple conductive parts. Before electroplating the circuit substrate, the manufacturing method also includes: forming a spacer layer between adjacent conductive parts, the spacer layer and the conductive parts are spaced apart; and after electroplating the circuit substrate, removing the spacer layer.

[0005] In some embodiments of the present application, a method for manufacturing a circuit substrate includes the following steps: covering a first dry film on the substrate, the substrate including a dielectric layer and a first copper layer located on the surface of the dielectric layer, the first dry film covering the first copper layer; exposing and developing the first dry film to form a first insulating layer; etching the first copper layer to form a conductive portion, and the first copper layer covered by the first insulating layer is etched to form a conductive portion.

[0006] In some embodiments of the present application, the circuit substrate also includes a conductive lead, which is spaced apart from the conductive part; the method for manufacturing the circuit substrate also includes: before the step of covering the surface of the substrate with a first dry film, covering the substrate with a tape, the tape covering a portion of the surface of the first copper layer; when covering the first dry film, the first dry film covers the surface of the first copper layer exposed to the tape; after exposing and developing the first dry film to form a first insulating layer, the first insulating layer is spaced apart from the tape; and after etching the first copper layer, removing the tape, and etching the first copper layer covered by the tape to form a conductive lead.

[0007] In some embodiments of the present application, when the circuit substrate includes a conductive lead, a spacer layer is further formed between the conductive lead and the conductive portion, and the spacer layer is spaced apart from the conductive lead and the conductive portion.

[0008] In some embodiments of the present application, the circuit substrate also includes a conductive lead, which is spaced apart from the conductive portion; the method for manufacturing the circuit substrate also includes: covering the substrate with a second dry film, the substrate including a dielectric layer and a first copper layer located on the surface of the dielectric layer, the second dry film covering the first copper layer; exposing and developing the second dry film to form a second insulating layer, a portion of the surface of the first copper layer is exposed to the second insulating layer; forming a shielding layer on the surface of the first copper layer exposed to the second insulating layer; removing the second insulating layer, pressing a third dry film, the third dry film covering the first copper layer exposed to the shielding layer; exposing and developing the third dry film to form a first insulating layer, the first insulating layer and the shielding layer being spaced apart; and etching a portion of the first copper layer and the shielding layer to form a conductive portion and a conductive lead, the first copper layer covered by the shielding layer is etched to form a conductive lead.

[0009] In some embodiments of the present application, when the circuit substrate is electroplated, a second electroplating layer is also formed on the surface of the conductive lead.

[0010] A circuit board comprises a dielectric layer and a soldering pad; the soldering pad is located on the surface of the dielectric layer, the soldering pad comprises a conductive part and a first electroplating layer, the conductive part is located on the surface of the dielectric layer, the first electroplating layer covers part of the surface of the conductive part, a surface of the first electroplating layer facing away from the dielectric layer is provided with a groove, and a surface of the conductive part facing away from the dielectric layer is exposed to the groove.

[0011] In some embodiments of the present application, the circuit board further includes a conductive lead, which is located on a surface of the dielectric layer where the pad is disposed, and the conductive lead is spaced apart from the pad.

[0012] A circuit board assembly comprises a circuit board, a conductive paste and an electronic component. The conductive paste is contained in a groove; and the electronic component is connected to the conductive paste.

[0013] The method for manufacturing a circuit board provided in the embodiment of the present application first forms a conductive portion by etching, and then forms a first electroplating layer by electroplating, thereby forming a soldering pad, which is beneficial to improving the etching factor, forming lines with smaller spacing, and improving wiring density; in addition, by shielding through the first insulating layer, it is convenient to form a soldering pad with a groove during the electroplating process, and in the process of installing the electronic components on the circuit board, the conductive paste is placed in the groove and reflow soldering is performed. After the conductive paste is melted, due to the barrier effect of the groove, the melted conductive paste is located in the corresponding groove, thereby reducing or avoiding the possibility of bridging short circuit phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A schematic top view of a circuit substrate provided in an embodiment of the present application.

[0015] Figure 2 for Figure 1 The schematic cross-sectional view of the circuit substrate along the AA direction is shown.

[0016] Figure 3 For Figure 2 The schematic cross-sectional view of the circuit substrate after being covered with the fourth dry film is shown.

[0017] Figure 4 For exposure and development Figure 3 The schematic cross-sectional view of the fourth dry film after forming a spacer layer is shown.

[0018] Figure 5 For Figure 4 The schematic cross-sectional view of the circuit substrate shown is after electroplating to form a first electroplating layer and a second electroplating layer.

[0019] Figure 6 To remove Figure 5 Schematic cross-sectional view after the spacer layer is shown.

[0020] Figure 7 For Figure 6 The schematic cross-sectional view of the first electroplating layer and the second electroplating layer after a solder mask is formed on the surface thereof.

[0021] Figure 8 For Figure 7 The schematic cross-sectional view of the circuit board obtained after a surface treatment layer is formed on the surface of the first electroplating layer is shown.

[0022] Fig. 9 A schematic cross-sectional process diagram of manufacturing a circuit substrate provided in some embodiments of the present application.

[0023] Fig.10 A schematic cross-sectional process diagram of manufacturing a circuit substrate provided in some other embodiments of the present application.

[0024] Fig.11 A schematic cross-sectional view of a circuit board assembly provided in an embodiment of the present application.

[0025] Main component symbols

[0026]

[0027] DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. In the following description, many specific details are set forth to facilitate a full understanding of the present application, and the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this article are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes all and any combination of one or more related listed items.

[0030] In the embodiments of the present application, for the convenience of description and not to limit the present application, the term "connection" used in the patent application specification and claims of the present application is not limited to physical or mechanical connection, whether direct or indirect. "Up", "down", "above", "below", "left", "right", etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship also changes accordingly.

[0031] See also Figures 1 to 10 The present application embodiment provides a method for manufacturing a circuit board 100, and the manufacturing method may include the following steps:

[0032] Step S1: Please refer to Figure 1 and Figure 2 , a circuit substrate 10 is provided, the circuit substrate 10 includes a dielectric layer 11, a conductive portion 132, a conductive lead 134 and a first insulating layer 136, the conductive portion 132 and the conductive lead 134 are located on the surface of the dielectric layer 11, and the first insulating layer 136 covers the surface of the conductive portion 132 away from the dielectric layer 11.

[0033] The circuit substrate 10 includes a conductive layer 13, which is located on the surface of the dielectric layer 11. The conductive layer 13 is formed by etching. The cross section of the conductive layer 13 is roughly trapezoidal, with a small width on the side away from the dielectric layer 11 and a large width on the side close to the dielectric layer 11. The conductive layer 13 includes a conductive portion 132, and the conductive portion 132 and the conductive lead 134 are located on the same surface of the dielectric layer 11. The conductive portion 132 and the conductive lead 134 are arranged at intervals, and the conductive layer 13 is connected to the conductive lead 134. The number of the conductive portion 132 can be one or more, and the number of the conductive lead 134 is at least two. In this embodiment, the number of the conductive portion 132 and the conductive lead 134 are both two. The conductive leads 134 are distributed on both sides of the conductive portion 132, and the adjacent conductive portions 132 are arranged at intervals. The conductive lead 134 can be used for electroplating in subsequent processes.

[0034] The first insulating layer 136 covers the surface of the conductive portion 132 away from the dielectric layer 11 , and is used to shield the surface of the conductive portion 132 away from the dielectric layer 11 .

[0035] The number of dielectric layers 11 is not limited to one layer. The material of the dielectric layer 11 can be selected from one of polyimide (PI), liquid crystal polymer (LCP), modified polyimide (MPI), polypropylene (PP), polyethylenenaphthalate diformic acid glycol ester (PEN), glass fiber, polytetrafluoroethylene (PTFE), and the like.

[0036] Step S2: Please refer to Figure 3 and Figure 4 A spacer layer 20 is formed between adjacent conductive portions 132 and / or between the conductive portion 132 and the conductive lead 134 , and the spacer layer 20 is spaced apart from the conductive portion 132 and / or the conductive lead 134 .

[0037] The material of the spacer layer 20 may be photosensitive resin, ink, dry film, wet film, etc. In some embodiments, the steps of forming the spacer layer 20 may include:

[0038] Step S21: Please refer to Figure 3 , a fourth dry film 21 is covered on the circuit substrate 10 , and the fourth dry film 21 covers the conductive portion 132 , the conductive lead 134 , the first insulating layer 136 and the surface of the dielectric layer 11 .

[0039] Step S22: Please refer to Figure 4The fourth dry film 21 is exposed and developed to form a spacer layer 20 between adjacent conductive portions 132 and between the conductive portions 132 and the conductive leads 134 .

[0040] Along the stacking direction of the circuit substrate 10, the height of the spacer layer 20 is higher than the height of the conductive part 132, so that the spacer layer 20 can play a blocking role in the subsequent electroplating process. As the height of the spacer layer 20 increases, the height of the subsequently formed electroplating layer can also increase accordingly.

[0041] Along the direction perpendicular to the stacking arrangement, the width of the spacer layer 20 can be reduced as much as possible. The width of the spacer layer 20 determines the distance between adjacent electroplated layers formed subsequently. In some embodiments, the width of the spacer layer 20 can be less than 20 μm.

[0042] Step S3: Please refer to Figure 5 The circuit substrate 10 is electroplated to form a first electroplating layer 31 on the surface of the conductive portion 132 , and a second electroplating layer 41 is formed on the surface of the conductive lead 134 . The first electroplating layer 31 also covers a portion of the surface of the first insulating layer 136 to form a groove 312 .

[0043] During the electroplating process, a clamp (not shown) may be used to clamp the conductive lead 134 at a clamping point 138 (see Figure 1 ) as a cathode to electroplate the circuit substrate 10 to form an electroplating layer (not shown, including a first electroplating layer 31 and a second electroplating layer 41), and the electroplating layer is formed on the surface of the conductive layer 13 to form a circuit together with the conductive layer 13 (not shown). Each conductive portion 132 forms a pad 30 with the corresponding first electroplating layer 31. The surface of the first electroplating layer 31 facing away from the dielectric layer 11 forms a groove 312, and the first electroplating layer 31 covers the conductive portion 132 exposed to the dielectric layer 11 and the surface of the first insulating layer 136. After the spacer layer 20 is set and the electroplating layer is formed by the electroplating step, the distance between adjacent circuits is reduced, which can increase the wiring density of the circuit board 100, that is, the increase in wiring density is not limited by the etching ability.

[0044] The side surfaces of the first electroplating layer 31 and the second electroplating layer 41 are both connected to the spacer layer 20 . The height of the first electroplating layer 31 can be increased by controlling the electroplating conditions, thereby increasing the depth of the groove 312 .

[0045] The distance between adjacent pads 30 and the distance between adjacent pads 30 and the second electroplating layer 41 can be controlled by the width of the spacer layer 20 . For example, the width of the spacer layer 20 can be reduced, and the wiring density of the circuit board 100 can be increased.

[0046] The surface flatness of the spacer layer 20 determines the flatness of the first electroplating layer 31 and the second electroplating layer 41 . If the surface flatness of the spacer layer 20 is good, the surface flatness of the first electroplating layer 31 and the second electroplating layer 41 will be good.

[0047] In other embodiments, the step of forming the spacer layer 20 may also be omitted. The deposition rate of the electroplated layer may be adjusted by adjusting the electroplating conditions and the solution formulation. For example, reducing the Cu content in the solution used for electroplating 2+ and H + The ratio of can reduce the deposition rate of electroplating; or add an appropriate amount of leveling agent, such as an organic compound containing a quaternary amine structure. Since the molecule has a strong positive charge, the N at this position + Will be adsorbed to the high current area on the cathode surface and 2+ Compete for high current density area and significantly reduce Cu 2+ The landing probability can be reduced by electrostatic adsorption on the surface, reducing the current density of the conductive part 132 near the dielectric layer 11, thereby reducing the deposition rate. Compared with etching, the embodiment of the present application is conducive to improving the etching factor by electroplating the conductive lead 134, and the line spacing is reduced, which is suitable for high-density wiring.

[0048] Levelers (such as organic compounds containing thiol structures) can also be added to the potion to facilitate Cu 2+ The formation of complexes accelerates the nucleation rate of copper.

[0049] Step S4: Please refer to Figure 6 , remove the first insulating layer 136 and the spacer layer 20.

[0050] In some embodiments, the entire first insulating layer 136 and the entire spacer layer 20 may be removed, and the surface of the dielectric layer 11 exposed to the pad 30 and the surface of the second electroplating layer 41 are exposed.

[0051] In other embodiments, only the portion of the spacer layer 20 protruding from the pad 30 and the second electroplating layer 41 may be removed, and the remaining spacer layer 20 may serve as an insulating layer for the spacer pad 30 and / or the second electroplating layer 41 .

[0052] Step S5: Please refer to Figure 7 , a solder resist layer 50 is formed, the solder resist layer 50 covers a portion of the first electroplating layer 31 and the second electroplating layer 41 , and the groove 312 is exposed to the solder resist layer 50 .

[0053] Part of the first electroplating layer 31 and the surface of the conductive part 132 covered by the first insulating layer 136 are exposed to the solder mask 50. The surface of the conductive part 132 covered by the first insulating layer 136 is not etched, so the surface flatness is good, which is beneficial to increase the reliability of the electrical connection.

[0054] Step S6: Please refer to Figure 8 A surface treatment layer 55 is formed on the surface of the first plating layer 31 and the conductive portion 132 exposed to the solder resist layer 50 .

[0055] The surface treatment layer 55 can increase the conductivity of the pad 30 and prevent the first electroplating layer 31 and the conductive portion 132 from being oxidized when exposed to the surface of the solder mask 50. The surface treatment layer 55 can be a gold layer.

[0056] See also Fig. 9 In some embodiments, the method for manufacturing the circuit substrate 10 may include the following steps:

[0057] Step S111 : covering the substrate 60 with an adhesive tape 63 . The substrate 60 includes a dielectric layer 11 and a first copper layer 61 located on a surface of the dielectric layer 11 . The adhesive tape 63 covers a portion of the surface of the first copper layer 61 .

[0058] The substrate 60 may be a copper-clad laminate or a circuit substrate. In this embodiment, the substrate 60 is a single-sided copper-clad laminate.

[0059] The number of the adhesive tapes 63 is the same as the number of the conductive leads 134 to be formed subsequently. The adhesive tape 63 includes a base material layer (not shown) and an adhesive layer (not shown), the adhesive layer being located between the base material layer and the first copper layer 61, and the adhesive layer plays a bonding role.

[0060] The material of the substrate layer may be polyvinyl chloride (PVC), polyethylene (PE), polypropylene, or polyethylene glycol terephthalate (PET). The adhesive layer may be an acrylic pressure-sensitive adhesive.

[0061] The adhesive strength of the adhesive tape 63 at room temperature (eg, 10° C.-20° C.) is greater than 2 N / cm. After being heated (eg, 60° C.-80° C.), the adhesive strength is greatly reduced, for example, less than 0.2 N / cm.

[0062] Step S112 : Covering the surface of the first copper layer 61 exposed to the tape 63 with a first dry film 65 .

[0063] The first dry film 65 may also cover the adhesive tape 63 .

[0064] Step S113 : exposing and developing the first dry film 65 to form a first insulating layer 136 .

[0065] The number of the first insulating layer 136 is the same as the number of the pads 30 to be formed subsequently. The first insulating layer 136 is spaced apart from the tape 63. The first insulating layer 136 covers the surface of the first copper layer 61. In the subsequent process, the surface of the first copper layer 61 covered by the first insulating layer 136 is not etched, which is beneficial to improve the surface flatness of the pads 30 to be formed subsequently.

[0066] Step S114: etching the first copper layer 61 to form a conductive portion 132 and a conductive lead 134. The first copper layer 61 covered by the first insulating layer 136 is etched to form the conductive portion 132, and the first copper layer 61 covered by the tape 63 is etched to form the conductive lead 134.

[0067] Step S115: Remove the tape 63 to obtain the circuit substrate 10 (see Figure 2 ).

[0068] The adhesive strength of the adhesive tape 63 can be reduced by heating in a drying oven, and then the adhesive tape 63 can be torn off without affecting the quality of the surface of the first copper layer 61 in the bonding area.

[0069] See also Fig.10 In some other embodiments, a method for manufacturing a circuit substrate 10 is also provided, which may include the following steps:

[0070] Step S121 : covering the substrate 60 with a second dry film 70 . The substrate 60 includes a dielectric layer 11 and a first copper layer 61 located on a surface of the dielectric layer 11 . The second dry film 70 covers the first copper layer 61 .

[0071] Step S122 : exposing and developing the second dry film 70 to form a second insulating layer 71 , and a portion of the surface of the first copper layer 61 is exposed to the second insulating layer 71 .

[0072] Step S123 : forming a shielding layer 73 on the surface of the first copper layer 61 exposed to the second insulating layer 71 .

[0073] Step S124 : removing the second insulating layer 71 , and laminating the third dry film 80 , wherein the third dry film 80 covers the first copper layer 61 exposed to the shielding layer 73 .

[0074] The third dry film 80 may also cover the shielding layer 73 .

[0075] Step S125 : exposing and developing the third dry film 80 to form a first insulating layer 136 , wherein the first insulating layer 136 is spaced apart from the shielding layer 73 .

[0076] Step S126: etching a portion of the first copper layer 61 and the shielding layer 73 to form a conductive portion 132 and a conductive lead 134, and removing the first insulating layer 136 to obtain a circuit substrate 10 (see Figure 2), the first copper layer 61 covered by the first insulating layer 136 is etched to form the conductive portion 132, and the first copper layer 61 covered by the shielding layer 73 is etched to form the conductive lead 134.

[0077] Please refer again Figure 8 The embodiment of the present application further provides a circuit board 100 , which may include a dielectric layer 11 , a solder pad 30 , and a conductive lead 134 , wherein the solder pad 30 and the conductive lead 134 are located on the same surface of the dielectric layer 11 .

[0078] The pad 30 includes a conductive portion 132 and a first electroplating layer 31. The conductive portion 132 is located on the surface of the dielectric layer 11. The first electroplating layer 31 covers a portion of the surface of the conductive portion 132 and is connected to the dielectric layer 11. A groove 312 is provided on the surface of the first electroplating layer 31 facing away from the dielectric layer 11, and the surface of the conductive portion 132 facing away from the dielectric layer 11 is exposed to the groove 312.

[0079] The conductive lead 134 is spaced apart from the pad 30 .

[0080] In some embodiments, the circuit board 100 further includes a second electroplating layer 41 , which covers the conductive lead 134 and is connected to the dielectric layer 11 .

[0081] See also Fig.11 The embodiment of the present application also provides a circuit board assembly 200, which includes a circuit board 100, an electronic component 210 and a conductive paste 220. The conductive paste 220 is received in a groove 312 and connected to the electronic component 210 so that the electronic component 210 is electrically connected to the circuit board 100.

[0082] The manufacturing method of the circuit board 100 provided in the embodiment of the present application first forms the conductive part 132 by etching, and then forms the first electroplating layer 31 by electroplating, thereby forming the pad 30, which is beneficial to improve the etching factor, form a circuit with a smaller spacing, and improve the wiring density; in addition, through the shielding of the first insulating layer 136, it is convenient to form the pad 30 with the groove 312 during the electroplating process. In the process of installing the electronic component 210 on the circuit board 100, the conductive paste 220 is placed in the groove 312 and reflow soldering is performed. After the conductive paste 220 is melted, due to the barrier effect of the groove 312, the melted conductive paste 220 is located in the corresponding groove 312, thereby reducing or avoiding the possibility of bridging short circuit phenomenon.

[0083] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for manufacturing a circuit board, characterized in that: The following steps are involved: A circuit substrate is provided, comprising a dielectric layer, a conductive portion and a first insulating layer, wherein the conductive portion is located on a surface of the dielectric layer, and the first insulating layer covers a surface of the conductive portion away from the dielectric layer; Electroplating the circuit substrate to form a first electroplating layer on the surface of the conductive portion, wherein the first electroplating layer also covers a portion of the surface of the first insulating layer to form a groove; removing the first insulating layer; as well as A solder resist layer is formed, wherein the solder resist layer covers a portion of the first electroplating layer, and the groove is exposed to the solder resist layer.

2. The method for manufacturing a circuit board according to claim 1, characterized in that: The circuit substrate includes a plurality of the conductive parts. Before electroplating the circuit substrate, the manufacturing method further includes: forming a spacer layer between adjacent conductive portions, wherein the spacer layer is spaced apart from the conductive portions; and After electroplating the circuit substrate, the spacer layer is removed.

3. The method for manufacturing a circuit board according to claim 1 or 2, characterized in that: The method for manufacturing the circuit substrate comprises the following steps: Covering a first dry film on a substrate, wherein the substrate comprises the dielectric layer and a first copper layer located on a surface of the dielectric layer, and the first dry film covers the first copper layer; exposing and developing the first dry film to form the first insulating layer; The first copper layer is etched to form the conductive portion, and the first copper layer covered by the first insulating layer is etched to form the conductive portion.

4. The method for manufacturing a circuit board according to claim 3, characterized in that: The circuit substrate further comprises a conductive lead, wherein the conductive lead is spaced apart from the conductive portion; The method for manufacturing the circuit substrate further includes: Before the step of covering the surface of the substrate with the first dry film, covering the substrate with an adhesive tape, wherein the adhesive tape covers a portion of the surface of the first copper layer; When covering the first dry film, the first dry film covers the surface of the first copper layer exposed to the tape; After exposing and developing the first dry film to form the first insulating layer, the first insulating layer and the tape are spaced apart; and After etching the first copper layer, the tape is removed, and the first copper layer covered by the tape is etched to form the conductive lead.

5. The method for manufacturing a circuit board according to claim 4, characterized in that: When the circuit substrate includes the conductive lead, the spacer layer is further formed between the conductive lead and the conductive portion, and the spacer layer is spaced apart from the conductive lead and the conductive portion.

6. The method for manufacturing a circuit board according to claim 1 or 2, characterized in that: The circuit substrate further comprises a conductive lead, wherein the conductive lead is spaced apart from the conductive portion; The method for manufacturing the circuit substrate further includes: Covering a second dry film on a substrate, wherein the substrate comprises the dielectric layer and a first copper layer located on a surface of the dielectric layer, and the second dry film covers the first copper layer; exposing and developing the second dry film to form a second insulating layer, wherein a portion of the surface of the first copper layer is exposed to the second insulating layer; forming a shielding layer on a surface of the first copper layer exposed to the second insulating layer; removing the second insulating layer, and laminating a third dry film, wherein the third dry film covers the first copper layer exposed to the shielding layer; exposing and developing the third dry film to form the first insulating layer, wherein the first insulating layer is spaced apart from the shielding layer; and Part of the first copper layer and the shielding layer are etched to form the conductive portion and the conductive lead, and the first copper layer covered by the shielding layer is etched to form the conductive lead.

7. The method for manufacturing a circuit board according to claim 6, characterized in that: When the circuit substrate is electroplated, a second electroplating layer is also formed on the surface of the conductive lead.

8. A circuit board, characterized in that: include: dielectric layer; A pad is located on the surface of the dielectric layer, and the pad includes a conductive part and a first electroplating layer. The conductive part is located on the surface of the dielectric layer, the first electroplating layer covers a portion of the surface of the conductive part, a surface of the first electroplating layer facing away from the dielectric layer is provided with a groove, and the surface of the conductive part facing away from the dielectric layer is exposed to the groove.

9. The circuit board according to claim 8, characterized in that: The circuit board further comprises a conductive lead, wherein the conductive lead is located on a surface of the dielectric layer where the pad is disposed, and the conductive lead is spaced apart from the pad.

10. A circuit board assembly, characterized in that: include: The circuit board according to claim 8 or 9; Conductive paste, contained in the groove; as well as The electronic component is connected with the conductive paste.

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