Enhanced GaN HEMT device and preparation method thereof

Abstract

The invention discloses a preparation method of an enhanced GaN HEMT (High Electron Mobility Transistor) device. The preparation method comprises the following steps: growing a nucleating layer, a buffer layer, a channel layer, a barrier layer and a barrier layer on a substrate; etching off the barrier layer at the middle position and a part of the barrier layer; epitaxially growing a cap layer on the etching region and the upper surface of the barrier layer; thinning the cap layer to the barrier layer; removing the barrier layer and exposing the barrier layer; performing ion implantation on two sides of the barrier layer, the channel layer and the buffer layer to obtain an ion implantation isolation region; plasma processing is carried out on the two sides of the barrier layer to obtain a plasma processing area, and a source electrode and a drain electrode are formed in the plasma processing area; growing a dielectric layer on the upper surfaces of the barrier layer, the source electrode, the drain electrode and the cap layer; forming a grid electrode on the dielectric layer; growing a passivation layer on the upper surfaces of the dielectric layer and the grid electrode; and etching the dielectric layer and the passivation layer to expose the grid electrode, the source electrode and the drain electrode. The invention further discloses an enhanced GaN HEMT device, and the performance of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an enhanced GaN HEMT device and a preparation method thereof. Background Art

[0002] With the development of the times, people's requirements for the performance of power semiconductor materials are getting higher and higher. In order to improve device performance, people have discovered and applied gallium nitride materials. As a third-generation semiconductor, gallium nitride materials have a larger bandgap, higher critical breakdown electric field and stronger radiation resistance compared with traditional silicon-based materials and second-generation semiconductors (represented by gallium arsenide). In particular, the high electron mobility transistor (GaN HEMT) composed of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) has a very high electron mobility. The principle of GaN HEMT is to form a natural conductive channel based on spontaneous polarization and piezoelectric polarization effects, which makes it a naturally depleted device. However, in application scenarios such as power electronics, in order to improve safety, the device is required to be enhanced. Therefore, enhanced GaN HEMT devices are urgently needed in the industry.

[0003] At present, there are several main methods for realizing enhancement-mode GaN HEMT devices: Cascode structure, P-type gate structure, groove gate structure and fluorine ion implantation structure formed by cascading an enhancement-mode Si MOS tube and a D-Mode depletion-mode GaN HEMT. Among them, Cascode, P-type gate and groove gate structures have all been commercially applied.

[0004] For GaN HEMT devices with a P-type gate structure, the epitaxial structure is usually: substrate, nucleation layer, buffer layer, channel layer, barrier layer and p-GaN cap layer from bottom to top. The main principle is to use the p-GaN cap layer to raise the conduction band at the channel interface to above the Fermi level to achieve the purpose of exhausting the two-dimensional electron gas. The process flow of preparing an enhanced GaN HEMT based on the above-mentioned traditional epitaxial structure is usually: patterning the p-GaN gate, etching the p-GaN cap layer outside the gate area through photolithography and etching processes to expose the AlGaN barrier layer, depositing the passivation layer, etching the passivation layer to expose the source and drain areas, growing the source and drain electrode metals and rapidly thermally annealing to form ohmic contacts, etching the passivation layer to expose the gate area, and growing the gate metal to form a Schottky contact gate.

[0005] There are several problems with the above process:

[0006] 1. When epitaxially growing AlGaN barrier layer and p-GaN cap layer, the p-GaN cap layer usually needs to be doped with bis(cyclopentadienyl)magnesium (CP 2Mg) is used as a dopant, and the temperature is usually high during the MOCVD process. Mg ions will diffuse downward to the AlGaN barrier layer and even the GaN channel layer. The diffused Mg ions act as acceptor impurities, which will reduce the concentration of the two-dimensional electron gas, thereby increasing the on-resistance and affecting the device performance.

[0007] 2. In the process of patterning the p-GaN cap layer, the most ideal situation of this process is to etch away all the p-GaN cap layer outside the gate area until the surface of the AlGaN barrier layer is just exposed. However, in actual implementation, it is impossible to stop exactly on the surface of the AlGaN barrier layer. Generally, 2nm to 5nm of the AlGaN barrier layer will be over-etched, and the etching accuracy is difficult to control. This thickness reduction will reduce the concentration of the two-dimensional electron gas and increase the on-resistance of the device. If the remaining part of the p-GaN cap layer is not etched cleanly, the on-resistance of the device will increase and the leakage current will increase, reducing the performance of the device.

[0008] 3. In order to achieve more accurate etching, it is necessary to improve the etching selectivity of GaN / AlGaN. Currently, Cl 2 / O 2 Oxygen-containing gases or BCl 3 / SF 6 Fluorine-containing gases such as AlGaN generate Al 2 O 3 and AlF 3 If the source and drain metals are grown directly on the two dielectric layers, the contact resistance of the ohmic contact will increase, resulting in a larger on-resistance and reduced device performance. Summary of the invention

[0009] In view of this, an object of the present invention is to provide a method for preparing an enhancement mode GaN HEMT device.

[0010] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0011] The present invention provides a method for preparing an enhanced GaN HEMT device, comprising the following steps:

[0012] Step 1, epitaxially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a blocking layer in sequence on a substrate;

[0013] Step 2, etching away the blocking layer and part of the barrier layer in the middle position to obtain an etched area;

[0014] Step 3, epitaxially growing a cap layer on the etching area and the upper surface of the barrier layer;

[0015] Step 4, thinning the cap layer to the upper surface of the barrier layer;

[0016] Step 5, removing the blocking layer to expose the barrier layer; performing ion implantation on both sides of the barrier layer, both sides of the channel layer and both sides of a portion of the upper surface of the buffer layer to obtain an ion implantation isolation region;

[0017] Step 6, defining a source region and a drain region on the left and right sides above the barrier layer, respectively, performing plasma treatment on the source region and the drain region to obtain a plasma treated region, forming a source and a drain on the upper surface of the plasma treated region, and annealing the source and the drain to form an ohmic contact;

[0018] Step 7, growing a dielectric layer on the barrier layer, the source electrode, the drain electrode and the cap layer;

[0019] Step 8, defining a gate region on the upper surface of the dielectric layer and directly above the cap layer, and forming a gate in the gate region;

[0020] Step 9, growing a passivation layer on the dielectric layer and the gate surface;

[0021] Step 10: Etch the passivation layer above the gate and the dielectric layer and passivation layer above the source and drain to expose the gate, source and drain.

[0022] Furthermore, in step 1, the thickness of the barrier layer is 15 nm to 40 nm, and the thickness of the blocking layer is 70 nm to 110 nm.

[0023] Furthermore, in step 2, the etching depth of the barrier layer is 5 nm to 15 nm, the remaining depth is 5 nm to 25 nm, and the sum of the etching depth and the remaining depth of the barrier layer is equal to the thickness of the barrier layer.

[0024] Furthermore, the concentration of Mg ions doped in the capping layer is greater than 10 19 cm -3 , the thickness of the capping layer is greater than 150 nm.

[0025] Furthermore, the thickness of the cap layer remaining after thinning in step 4 is equal to the sum of the thickness of the blocking layer and the etching depth of the barrier layer, that is, the upper surface of the cap layer remaining after thinning is flush with the upper surface of the blocking layer.

[0026] Furthermore, the thickness of the dielectric layer is 5 nm to 10 nm.

[0027] Furthermore, the thickness of the passivation layer is 200nm-500nm.

[0028] Furthermore, the epitaxial growth method in step 1 and step 3 adopts one of MOCVD, HVPE and MBE; the removal of the barrier layer in step 5 adopts wet removal technology; the plasma treatment in step 6 adopts hydrogen plasma; the dielectric layer growth method in step 7 adopts ALD; the passivation layer growth method in step 9 adopts one of PECVD, LPCVD and ALD.

[0029] Further, the material of the substrate includes one or more of sapphire, Si, GaN, SiC, QST, SOI and diamond;

[0030] The material of the nucleation layer is AlN;

[0031] The material of the buffer layer is one or more of GaN doped with iron or carbon and a superlattice structure of alternately grown AlN / GaN;

[0032] The material of the channel layer is GaN;

[0033] The material of the barrier layer is Al x Ga 1-x N, x is 0.18-0.3.

[0034] The material of the barrier layer is Si 3 N 4 or SiO 2 ;

[0035] The material of the cap layer is p-GaN;

[0036] The material of the source electrode is one or more of Ti, Al, Ni, Au, TiN and Pt;

[0037] The material of the drain electrode is one or more of Ti, Al, Ni, Au, TiN and Pt;

[0038] The material of the dielectric layer is AlN;

[0039] The material of the gate is one or more of Ni, Au and TiN;

[0040] The material of the passivation layer is SiO 2 or Si 3 N 4 .

[0041] The present invention also provides an enhanced GaN HEMT device, which is prepared according to the above-mentioned method for preparing an enhanced GaN HEMT device; the device comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer grown in sequence from bottom to top; an etching region is provided on a portion of the upper surface at a middle position of the barrier layer, and a cap layer is grown in the etching region; ion implantation isolation regions are provided on both sides of the barrier layer, both sides of the channel layer and both sides of a portion of the upper surface of the buffer layer; a source region and a drain region are provided on the left and right sides above the barrier layer, respectively, a plasma treatment region is provided in the source region and the drain region, and a source and a drain are formed on the upper surface of the plasma treatment region; a dielectric layer is grown on the upper surfaces of the barrier layer, the source, the drain and the cap layer; a gate region is provided on the upper surface of the dielectric layer and directly above the cap layer, and a gate is formed in the gate region; a passivation layer is grown on the upper surfaces of the dielectric layer and the gate; grooves are etched above the gate, the source and the drain to expose the gate, the source and the drain.

[0042] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0043] 1. Etching Si in epitaxial structure 3 N 4 After the barrier layer and part of the AlGaN barrier layer, the secondary epitaxial p-GaN cap layer can effectively prevent the diffusion of Mg ions doped in the p-GaN cap layer into the underlying AlGaN barrier layer, avoiding the problem of increased on-resistance due to the diffusion of Mg ions into the AlGaN barrier layer, thereby ensuring the performance of the device, and the barrier layer will be removed later to further reduce the impact of Mg ion diffusion; at the same time, due to the use of wet Si 3 N 4 The blocking layer is removed, and the AlGaN barrier layer is directly exposed, thus avoiding the selective etching problem of the p-GaN cap layer / AlGaN barrier layer and the etching damage problem on the surface of the AlGaN barrier layer in the traditional process.

[0044] 2. Use chemical mechanical polishing to grind the p-GaN cap layer to Si 3 N 4 Barrier layer, then wet removal of Si 3 N 4 The barrier layer completes the p-GaN capping layer patterning. Currently, some similar technologies will directly use the stripping Si 3 N 4The p-GaN capping layer is formed on the barrier layer, but due to the good sidewall adhesion during film growth, the edge is prone to unevenness and burrs during peeling, which affects the subsequent process and device performance. Since chemical mechanical polishing has different grinding speeds for different materials, the p-GaN capping layer can be better stopped on the Si after grinding. 3 N 4 The barrier layer, therefore, can not only obtain a relatively flat p-GaN cap layer pattern, but also has a larger process window. 3 N 4 The barrier layer can directly complete the p-GaN capping layer patterning, directly avoiding the problems caused by the traditional E-mode etching of p-GaN, such as over-etching of the AlGaN barrier layer will reduce the on-resistance, incomplete etching of the p-GaN capping layer will increase the leakage current, and the injection of ions during etching will reduce the concentration of the two-dimensional electron gas. 3 N 4 The thickness of the barrier layer can be used to better control the thickness of the remaining p-GaN cap layer.

[0045] 3. Since the surface of the p-GaN cap layer is ground, a 5-10nm AlN dielectric layer is grown by ALD to passivate the surface of the p-GaN cap layer and the AlGaN barrier layer, which reduces the surface state and the gate leakage current, improves the gate reliability, and passivates the surface of the AlGaN barrier layer to reduce the current collapse effect.

[0046] 4. Hydrogen plasma is used to pre-treat the surface of the AlGaN barrier layer to reduce the ohmic contact resistance of the source and drain. Compared with the techniques of etching source and drain grooves and regrowth doping of source and drain grooves, the process is relatively simple and conforms to the process flow of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A diagram of the epitaxial basic structure of sequentially epitaxially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a blocking layer on a substrate in a method for preparing an enhanced GaN HEMT device provided in an embodiment of the present invention (schematic diagram of step 1).

[0049] Figure 2 For Figure 1A structural diagram of the etching area is etched on the structure (schematic diagram of step 2).

[0050] Figure 3 For Figure 2 Structural diagram of growing a cap layer on the structure (schematic diagram of step 3).

[0051] Figure 4 For Figure 3 The cap layer is thinned to the structural diagram of the barrier layer (schematic diagram of step 4).

[0052] Figure 5 For Figure 4 Structural diagram of removing the barrier layer from the structure (schematic diagram of step 5).

[0053] Figure 6 For Figure 5 After ion implantation is performed on both sides of the barrier layer, both sides of the channel layer and both sides of part of the upper surface of the buffer layer, a structural diagram of the ion implantation isolation region is obtained (schematic diagram of step 5).

[0054] Figure 7 For Figure 6 After plasma treatment is performed on the source region and the drain region, a structural diagram of the plasma treated area is obtained (schematic diagram of step 6).

[0055] Figure 8 For Figure 7 A structural diagram of forming a source and a drain on the upper surface of the plasma treatment area on the structure (schematic diagram of step 6).

[0056] Fig. 9 For Figure 8 Structural diagram of growing a dielectric layer on the structure (schematic diagram of step 7).

[0057] Fig.10 For Fig. 9 A structural diagram of a gate is formed on the structure (schematic diagram of step 8).

[0058] Fig.11 For Fig.10 Structural diagram of growing a passivation layer on the structure (schematic diagram of step 9).

[0059] Fig.12 For Fig.11 After etching the dielectric layer and the passivation layer on the structure, the gate, source and drain are exposed (schematic diagram of step 10).

[0060] The numbers in the figure are: 1-substrate; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-barrier layer; 6-blocking layer; 7-capping layer; 8-ion implantation isolation region; 9-plasma treatment region; 10-source; 11-drain; 12-dielectric layer; 13-gate; 14-passivation layer; 15-etching region; 16-source region; 17-drain region; 18-gate region; 19-groove. DETAILED DESCRIPTION

[0061] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present invention, but are not intended to limit the scope of the present invention. Similarly, the following examples are only partial embodiments of the present invention rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0062] See also Figure 1-Figure 12 A method for preparing an enhanced GaN HEMT device of the present invention comprises the following steps:

[0063] Step 1, epitaxially grow a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5 and a blocking layer 6 on a substrate 1 in sequence; the epitaxial growth method adopts one of MOCVD (metal organic vapor deposition), HVPE (hydride vapor phase epitaxy) and MBE (molecular beam epitaxy). The thickness of the barrier layer 5 is 15nm to 40nm. If the thickness of the barrier layer 5 is too thin, the concentration of the two-dimensional electron gas will be reduced and the on-resistance will be increased. If the thickness of the barrier layer 5 is too thick, the crystal quality will be reduced and a large number of defects will be generated. The thickness of the blocking layer 6 is 70nm to 110nm.

[0064] Step 2, etching away the blocking layer 6 and part of the barrier layer 5 in the middle position to obtain an etched area 15; wherein the etching depth of the barrier layer 5 is 5nm to 15nm, the remaining depth is 5nm to 25nm, and the sum of the etching depth of the barrier layer 5 and the remaining depth is equal to the thickness of the barrier layer 5. The difference in the remaining depth will affect the threshold voltage, and the lower the remaining depth, the higher the threshold voltage.

[0065] Step 3: epitaxially grow a cap layer 7 on the etching area 15 and the upper surface of the barrier layer 6; wherein the concentration of Mg ions doped in the cap layer 7 is greater than 10 19 cm -3 The thickness of the cap layer 7 is greater than 150 nm, which provides a certain process window for the subsequent thinning process. The epitaxial growth method is one of MOCVD, HVPE and MBE.

[0066] Step 4, thinning the cap layer 7 to the upper surface of the barrier layer 6; at this time, the thickness of the cap layer 7 remaining after thinning is equal to the sum of the thickness of the barrier layer 6 and the etching depth of the barrier layer 5, that is, the upper surface of the cap layer 7 remaining after thinning is flush with the upper surface of the barrier layer 6.

[0067] Step 5: remove the blocking layer 6 to expose the barrier layer 5. The blocking layer is removed by wet removal technology. The wet removal technology can quickly and efficiently remove Si 3 N 4 barrier layer 6, and reduce the damage to the surface of the AlGaN barrier layer 5; ion implantation is performed on both sides of the barrier layer 5, both sides of the channel layer 4 and both sides of the upper surface of part of the buffer layer 3 to obtain an ion implantation isolation region 8;

[0068] Step 6: define a source region 16 and a drain region 17 on the left and right sides above the barrier layer 5, respectively, and obtain a plasma-treated region 9 after the source region 16 and the drain region 17 are subjected to plasma treatment. The plasma treatment uses hydrogen plasma, which can generate NH on the surface of the AlGaN barrier layer 5. 3 A source electrode 10 and a drain electrode 11 are formed on the upper surface of the plasma treatment area 9, and the source electrode 10 and the drain electrode 11 are annealed to form an ohmic contact;

[0069] Step 7, growing a dielectric layer 12 on the barrier layer 5, the source 10, the drain 11 and the cap layer 7 to reduce the gate leakage current while protecting the surface of the barrier layer 5 outside the gate region 18; wherein the thickness of the dielectric layer 12 is 5nm to 10nm, and the growth method thereof is ALD (atomic layer deposition).

[0070] Step 8: defining a gate region 18 on the upper surface of the dielectric layer 12 and directly above the cap layer 7, and forming a gate 13 in the gate region 18;

[0071] Step 9, growing a passivation layer 14 on the upper surface of the dielectric layer 12 and the gate 13 to passivate the device surface; wherein the thickness of the passivation layer 14 is 200nm to 500nm, and the growth method thereof adopts one of PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition) and ALD (atomic layer deposition).

[0072] Step 10: Etch the passivation layer 14 above the gate 13 and the dielectric layer 12 and the passivation layer 14 above the source 10 and the drain 11 to expose the gate 13, the source 10 and the drain 11.

[0073] Wherein, the material of the substrate 1 includes one or more of sapphire, Si, GaN, SiC, QST, SOI and diamond;

[0074] The material of the nucleation layer 2 is AlN;

[0075] The material of the buffer layer 3 is one or more of GaN doped with iron or carbon and a superlattice structure of alternately grown AlN / GaN;

[0076] The material of the channel layer 4 is GaN;

[0077] The material of the barrier layer 5 is Al x Ga 1-x N, x is 0.18-0.3 (the AlGaN mentioned below refers to this component content).

[0078] The material of the barrier layer 6 is Si 3 N 4 or SiO 2 ;

[0079] The material of the cap layer 7 is p-GaN;

[0080] The material of the source electrode 10 is one or more of Ti, Al, Ni, Au, TiN and Pt;

[0081] The material of the drain electrode 11 is one or more of Ti, Al, Ni, Au, TiN and Pt;

[0082] The material of the dielectric layer 12 is AlN;

[0083] The material of the gate 13 is one or more of Ni, Au and TiN;

[0084] The material of the passivation layer 14 is SiO 2 or Si 3 N 4 .

[0085] Embodiment 1:

[0086] 1) AlN nucleation layer 2, GaN buffer layer 3, GaN channel layer 4, AlGaN barrier layer 5 and Si are sequentially deposited on Si substrate 1 by MOCVD process. 3 N 4 Here, the thickness of the AlGaN barrier layer 5 is 25 nm, and the thickness of the Si 3 N 4 The thickness of the barrier layer 6 is 70 nm. Figure 1 shown.

[0087] 2) Use photolithography and etching process to cut the Si 3 N 4 The barrier layer 6 and part of the AlGaN barrier layer 5 (upper surface) are etched, wherein the Si 3 N 4 The barrier layer 6 is completely etched away, the AlGaN barrier layer 5 is etched to a depth of 15 nm, and the remaining depth is 10 nm. Figure 2 shown.

[0088] 3) A p-GaN capping layer 7 is grown epitaxially by MOCVD process, wherein the Mg ion concentration doped in the p-GaN capping layer 7 is greater than 10 19 cm -3 , wherein the thickness of the p-GaN cap layer 7 above the barrier layer 6 is 200 nm. Figure 3 shown.

[0089] 4) Chemical mechanical polishing is used to thin the p-GaN cap layer 7 to the Si 3 N 4 The upper surface of the barrier layer 6. Figure 4 As shown, the thickness of the remaining p-GaN cap layer 7 is 85 nm. In addition to chemical mechanical polishing, ICP dry etching or a combination of chemical mechanical polishing and ICP dry etching can also be used. Adding ICP dry etching can make the surface roughness of the obtained p-GaN cap layer 7 lower.

[0090] 5) Wet removal of Si 3 N 4 The barrier layer 6 exposes the AlGaN barrier layer 5, such as Figure 5 Ion implantation is performed on both sides of the AlGaN barrier layer 5, both sides of the GaN channel layer 4 and both sides of the upper surface of part of the GaN buffer layer 3 to obtain an ion implantation isolation region 8, as shown in FIG. Figure 6 As shown;

[0091] 6) Using a photolithography process, a source region 16 and a drain region 17 are defined on the left and right sides above the AlGaN barrier layer 5, respectively. The source region 16 and the drain region 17 are treated with hydrogen plasma to obtain a plasma treated region 9, such as Figure 7 The source 10 and the drain 11 are formed on the upper surface of the plasma treatment area 9 by electron beam evaporation process, the source 10 is located on the left side, and the drain 11 is located on the right side. The source 10 (such as Ti / Al laminated metal) and the drain 11 (such as Ti / Al laminated metal) are subjected to RTA annealing (rapid thermal annealing) to form an ohmic contact, as shown in FIG. Figure 8As shown. After rapid thermal annealing, the metal Ti and AlGaN form a TiN alloy, thereby forming nitrogen vacancies in the AlGaN barrier layer 5, where the nitrogen vacancies act as donors, thereby achieving the effect of n-type doping and reducing the ohmic contact resistance. Hydrogen plasma treatment can generate NH 3 And form nitrogen vacancies, which is also beneficial to reduce the ohmic contact resistance. At the same time, since the Mg ions doped in the p-GaN cap layer 7 have been 3 N 4 The blocking layer 6 blocks and does not diffuse to the AlGaN barrier layer 5, so there is no situation where the Mg-H complex reduces the on-resistance. At the same time, compared with the technology of etching the source groove and the drain groove and then growing doping, the plasma treatment process is simpler.

[0092] 7) Using the ALD process to grow the AlN dielectric layer 12, while reducing the leakage current of the gate 13, the surface of the AlGaN barrier layer 5 outside the gate region 18 is protected. The thickness of the AlN dielectric layer 12 is 5 nm. Fig. 9 Compared with the direct use of PECVD or LPCVD to grow Si 3 N 4 Or SiO 2 The AlGaN barrier layer 5 is passivated. The AlN dielectric layer 12 grown by ALD has better compactness and can better passivate the surface of the AlGaN barrier layer 5. The AlN dielectric layer 12 and the subsequent passivation layer 14 are grown after the RTA annealing of the source 10 and the drain 11 to avoid the existing AlN dielectric layer 12 from being broken due to the melting and expansion of the metal caused by the high temperature of the RTA annealing.

[0093] 8) Using a photolithography process, a gate region 18 is defined on the upper surface of the AlN dielectric layer 12 and directly above the p-GaN cap layer 7, and an electron beam evaporation process is used to form a gate 13 in the gate region 18 to form a Schottky contact gate 13, such as Fig.10 shown.

[0094] 9) Using PECVD process to grow SiO 2 Passivation layer 14, used to passivate the device surface, SiO 2 The thickness of the passivation layer 14 is 200 nm. Fig.11 shown.

[0095] 10) Using photolithography and etching process, etch the SiO above the gate 13 2 The passivation layer 14 and the AlN dielectric layer 12 and SiO2 on the source 10 and the drain 11 2 The passivation layer 14 exposes the gate 13, the source 10 and the drain 11. Fig.12 shown.

[0096] The present invention also provides an enhanced GaN HEMT device, which is prepared according to the above-mentioned method for preparing an enhanced GaN HEMT device; the device comprises a Si substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4 and an AlGaN barrier layer 5 grown in sequence from bottom to top; an etching region 15 is provided on a portion of the upper surface at the middle position of the AlGaN barrier layer 5, so that the thickness of the AlGaN barrier layer 5 below the gate region 18 is less than the thickness of the AlGaN barrier layer 5 outside the gate region 18, so as to increase the threshold voltage; a p-GaN cap layer 7 is grown in the etching region 15; ion implantation isolation regions are provided on both sides of the AlGaN barrier layer 5, both sides of the GaN channel layer 4 and both sides of the portion of the upper surface of the GaN buffer layer 3 8; a source region 16 and a drain region 17 are respectively provided on the left and right sides above the AlGaN barrier layer 5, and a hydrogen plasma treatment area 9 is provided in the source region 16 and the drain region 17 for reducing the contact resistance; a source 10 and a drain 11 are formed on the upper surface of the hydrogen plasma treatment area 9; an AlN dielectric layer 12 is grown on the upper surfaces of the AlGaN barrier layer 5, the source 10, the drain 11 and the p-GaN cap layer 7; a gate region 18 is provided on the upper surface of the AlN dielectric layer 12 and directly above the p-GaN cap layer 7, and a gate 13 is formed in the gate region 18; SiO2 is grown on the upper surfaces of the AlN dielectric layer 12 and the gate 13 2 The passivation layer 14 has a groove 19 etched on the gate 13 , the source 10 and the drain 11 to expose the gate 13 , the source 10 and the drain 11 .

[0097] In this embodiment, the thickness of the AlGaN barrier layer 5 is 25 nm, the etching depth of the middle position of the AlGaN barrier layer 5 is 15 nm, the remaining depth is 10 nm, and the sum of the etching depth and the remaining depth of the AlGaN barrier layer 5 is equal to the thickness of the AlGaN barrier layer 5. The thickness of the p-GaN cap layer 7 (after thinning) is equal to the thickness of the Si 3 N 4 The thickness of the barrier layer 6 and the etching depth of the AlGaN barrier layer 5, that is, the thickness of the upper surface of the remaining p-GaN cap layer 7 after thinning and the Si 3 N 4 The upper surface of the barrier layer 6 is flush. The thickness of the AlN dielectric layer 12 is 5 nm. 2 The thickness of the passivation layer 14 is 200 nm.

[0098] The device prepared by the above method has a Si 3 N 4The barrier layer 6 has a blocking effect on Mg ions, which avoids the problem of increased on-resistance caused by the diffusion of Mg ions into the AlGaN barrier layer 5. It further allows the surface of the AlGaN barrier layer 5 to be treated with hydrogen plasma to form more nitrogen vacancies to reduce the ohmic contact resistance. 3 N 4 The wet removal of the barrier layer 6 replaces the selective etching process of p-GaN / AlGaN, avoiding the over-etching of the AlGaN barrier layer 5 and the influence of the incomplete etching of p-GaN on the device performance; the chemical mechanical polishing process is adopted to make the side wall of the gate 13 smoother; the AlN dielectric layer 12 passivates the surface of the AlGaN barrier layer 5 and reduces the leakage current of the gate 13. The device manufactured according to the above method can obtain good device performance.

[0099] The above descriptions are only some embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for preparing an enhanced GaN HEMT device, characterized in that: The steps include: Step 1, epitaxially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a blocking layer in sequence on a substrate; Step 2, etching away the blocking layer and part of the barrier layer in the middle position to obtain an etched area; Step 3, epitaxially growing a cap layer on the etching area and the upper surface of the barrier layer; Step 4, thinning the cap layer to the upper surface of the barrier layer; Step 5, removing the blocking layer to expose the barrier layer; performing ion implantation on both sides of the barrier layer, both sides of the channel layer and both sides of a portion of the upper surface of the buffer layer to obtain an ion implantation isolation region; Step 6, defining a source region and a drain region on the left and right sides above the barrier layer, respectively, performing plasma treatment on the source region and the drain region to obtain a plasma treated region, forming a source and a drain on the upper surface of the plasma treated region, and annealing the source and the drain to form an ohmic contact; Step 7, growing a dielectric layer on the barrier layer, the source electrode, the drain electrode and the cap layer; Step 8, defining a gate region on the upper surface of the dielectric layer and directly above the cap layer, and forming a gate in the gate region; Step 9, growing a passivation layer on the dielectric layer and the gate surface; Step 10: Etch the passivation layer above the gate and the dielectric layer and passivation layer above the source and drain to expose the gate, source and drain.

2. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: In step 1, the thickness of the barrier layer is 15 nm to 40 nm, and the thickness of the blocking layer is 70 nm to 110 nm.

3. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: In step 2, the etching depth of the barrier layer is 5 nm to 15 nm, the remaining depth is 5 nm to 25 nm, and the sum of the etching depth and the remaining depth of the barrier layer is equal to the thickness of the barrier layer.

4. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The concentration of Mg ions doped in the capping layer is greater than 10 19 cm -3 , the thickness of the capping layer is greater than 150 nm.

5. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The remaining thickness of the cap layer after thinning in step 4 is equal to the sum of the thickness of the blocking layer and the etching depth of the barrier layer, that is, the upper surface of the cap layer remaining after thinning is flush with the upper surface of the blocking layer.

6. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The thickness of the dielectric layer is 5nm-10nm.

7. The method for preparing an enhancement mode GaN HEMT device according to claim 1, characterized in that: The thickness of the passivation layer is 200nm-500nm.

8. The method for preparing an enhancement mode GaN HEMT device according to claim 1, characterized in that: The epitaxial growth method in step 1 and step 3 adopts one of MOCVD, HVPE and MBE; the barrier layer is removed in step 5 by wet removal technology; the plasma treatment in step 6 adopts hydrogen plasma; the dielectric layer is grown in step 7 by ALD; the passivation layer is grown in step 9 by one of PECVD, LPCVD and ALD.

9. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The material of the substrate includes one or more of sapphire, Si, GaN, SiC, QST, SOI and diamond; The material of the nucleation layer is AlN; The material of the buffer layer is one or more of GaN doped with iron or carbon and a superlattice structure of alternately grown AlN / GaN; The material of the channel layer is GaN; The material of the barrier layer is Al x Ga 1-x N, x is 0.18-0.3; The material of the barrier layer is Si3N4 or SiO2; The material of the cap layer is p-GaN; The material of the source electrode is one or more of Ti, Al, Ni, Au, TiN and Pt; The material of the drain electrode is one or more of Ti, Al, Ni, Au, TiN and Pt; The material of the dielectric layer is AlN; The material of the gate is one or more of Ni, Au and TiN; The material of the passivation layer is SiO2 or Si3N4.

10. An enhancement mode GaN HEMT device, characterized in that: The device is prepared according to a preparation method of an enhanced GaN HEMT device according to any one of claims 1 to 9; the device comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer grown in sequence from bottom to top; an etching region is provided on a portion of the upper surface at a middle position of the barrier layer, and a cap layer is grown in the etching region; ion implantation isolation regions are provided on both sides of the barrier layer, both sides of the channel layer and both sides of a portion of the upper surface of the buffer layer; a source region and a drain region are provided on the left and right sides above the barrier layer, respectively, a plasma treatment region is provided in the source region and the drain region, and a source and a drain are formed on the upper surface of the plasma treatment region; a dielectric layer is grown on the upper surfaces of the barrier layer, the source, the drain and the cap layer; a gate region is provided on the upper surface of the dielectric layer and directly above the cap layer, and a gate is formed in the gate region; a passivation layer is grown on the upper surfaces of the dielectric layer and the gate; grooves are etched above the gate, the source and the drain to expose the gate, the source and the drain.

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