Method for reducing local through holes and improving latch-up resistance

Abstract

The invention provides a method for reducing local through holes and improving latch-up resistance, and the core idea is to reduce active region through holes in a middle region of a PMOS (P-channel Metal Oxide Semiconductor) and an NMOS (N-channel Metal Oxide Semiconductor) and limit the maximum current of a parasitic transistor, so that the possibility of latch-up and the possibility of circuit damage during latch-up are reduced. The layout structure of the existing PMOS + NMOS driving transistor is improved, and the robustness of the driving circuit is improved from the perspective of layout design. Comprising an NWELL region, a PWELL region, a first P + contact region, a second P + contact region, a third P + contact region, a fourth P + contact region, a first N + contact region, a second N + contact region and a fourth N + contact region, first, second, third, fourth, fifth and sixth active regions; first and second polycrystalline gates; first, second, third, fourth, fifth, sixth, seventh and eighth contact holes; first, second, third, fourth and fifth through holes; and first, second, third, fourth, fifth, sixth, seventh, eighth and ninth metals.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices and relates to a layout structure for improving anti-latch capability. Technical Background

[0002] Latch up is the latch effect, which often occurs in driving circuits containing larger PMOS and NMOS in CMOS, BiMOS or BCD integrated circuits. The latch effect is a condition that generates a low-impedance path between the power pin and the ground of the device. This low-impedance path may cause system turbulence or catastrophic damage due to excessive current levels. When the external trigger causes the emitter of the parasitic transistor inside the driving circuit to be forward biased and generate a sufficiently large current, the other parasitic transistor is also forward biased and forward-conducted. When the product of the common emitter current amplification factor β of the two parasitic transistors is greater than 1, the circuit will generate a low-resistance channel to double the current after triggering. At this time, if the power supply can provide the current to maintain the trigger, the device will remain in the latched state and cannot be turned off, and the chip is prone to burn out due to overheating.

[0003] The most direct means of anti-latching is to make the current amplification factor of the parasitic transistor small enough; in layout design, the distance between the source and drain regions of the MOS tube and the well boundary is generally increased, or the contact between the substrate and the well potential is reasonably distributed to minimize the equivalent resistance Rsub and Rwell of the substrate and the well. Under current technology, the engineering design rules will leave a large gap between the substrate contact and the source contact. From the perspective of anti-latching, there is a large well resistance between the substrate contact and the source contact, which undoubtedly makes the latch effect more likely to occur.

[0004] In order to solve this problem, the present invention breaks through engineering common sense and, from the perspective of suppressing the maximum current of the parasitic transistor, uses a design that reduces the active area through holes in the middle area between PMOS and NMOS to provide anti-latch, thereby improving the robustness of the driving circuit transistor from the perspective of layout design. Summary of the invention

[0005] The problem to be solved by the present invention is to improve the anti-latch capability of the circuit by changing the layout structure without changing the working performance of the driving circuit.

[0006] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows: An anti-latch layout structure comprises an A1 portion: an NWELL region (100), a first P+ contact region (201) located inside the NWELL region (100), a second N+ contact region (102) located inside the NWELL region (100), and a first active region (401) located inside the first P+ contact region (201), and further comprises a first polycrystalline gate (001), a first metal (301), a first contact hole (501) located in the first active region (401), and a second contact hole (502) located in the first active region (401), wherein the first P+ contact region (201) and the second N+ contact region (102) may be adjacent to or non-adjacent to each other, and the first P+ contact region (201) and the second N+ contact region (102) are connected to VDD via the first contact hole (501), the first metal (301), the second through hole (602), the eighth metal (308), and the first through hole (601); The A2 portion includes: a third N+ contact region (103) is provided inside the NWELL region (100); a third active region (403) is located inside the third N+ contact region (103); the third N+ contact region (103) surrounds the A1 portion; the third N+ contact region (103) is connected to VDD through a fifth contact hole (505), a fourth metal (304), a second through hole (602), an eighth metal (308), and a first through hole (601); The device further comprises a B1 portion: a PWELL region (200), a first N+ contact region (101) located inside the PWELL region (200), a second P+ contact region (202), and a second active region (402) located inside the first N+ contact region (101), and further comprises a second polycrystalline gate (002), a second metal (302), and a third contact hole (503) located in the second active region (402), wherein the first N+ contact region (101) and the second P+ contact region (202) may be adjacent to or non-adjacent to each other, and the first N+ contact region (101) and the second P+ contact region (202) are connected to GND via the third contact hole (503), the second metal (302), the fourth through hole (604), the seventh metal (307), and the fifth through hole (605); The B2 portion includes: a third P+ contact region (203) is provided inside the PWELL (200), a fourth active region (404) is located inside the third P+ contact region (203), the third P+ contact region (203) surrounds the B1 portion, and the third P+ contact region (203) is connected to GND through a sixth contact hole (506), a fifth metal (305), a fourth through hole (604), a seventh metal (307), and a fifth through hole (605);

[0007] It also includes a C part: a first P+ contact area (201) is provided inside the NWELL area (100) and is connected to the first N+ contact area (101) located inside the PWELL area (200) through a second contact hole (502), a third metal (303), and a fourth contact hole (504).

[0008] As a preferred embodiment, a fourth N+ contact region (104) is provided, a fifth active region (405) is provided inside the fourth N+ contact region (104), and the fourth N+ contact region (104) surrounds the B2 portion; wherein the fourth N+ contact region (104) is connected to VDD through a seventh contact hole (507), a sixth metal (306), a third through hole (603), an eighth metal (308), and a first through hole (601).

[0009] As the second preferred method, A fourth P+ contact area (204) is provided, a sixth active area (406) is provided inside the fourth P+ contact area (204), and the fourth P+ contact area (204) surrounds the A2 or B2 portion; wherein the fourth P+ contact area (204) is connected to GND through an eighth contact hole (508) and a ninth metal (309).

[0010] The beneficial effects of the present invention are: breaking through the existing common layout scheme, from the perspective of suppressing the maximum current of the parasitic transistor, using the design of reducing the active area through holes in the middle area between PMOS and NMOS to provide anti-latch, thereby improving the robustness of driving circuits such as PMOS+NMOS from the perspective of layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The equivalent circuit diagram of the parasitic latch effect of the traditional PMOS+NMOS driving circuit; Figure 2 The layout structure of Example 1; 001 is the first polycrystalline gate, 002 is the second polycrystalline gate; 100 is the NWELL region, 101 is the first N+ contact region, 102 is the second N+ contact region, 103 is the third N+ contact region, 104 is the fourth N+ contact region; 200 is the PWELL region, 201 is the first P+ contact region, 202 is the second P+ contact region, 203 is the third P+ contact region, 204 is the fourth P+ contact region; 301 is the first metal, 302 is the second metal, 303 is the third metal, 304 is the fourth metal, 305 is the fifth metal, 306 is the sixth metal, 307 is the seventh metal , 308 is the eighth metal, 309 is the ninth metal; 401 is the first active area, 402 is the second active area, 403 is the third active area, 404 is the fourth active area, 405 is the fifth active area, 406 is the sixth active area; 501 is the first contact hole, 502 is the second contact hole, 503 is the third contact hole, 504 is the fourth contact hole, 505 is the fifth contact hole, 506 is the sixth contact hole, 507 is the seventh contact hole, 508 is the eighth contact hole; 601 is the first through hole, 602 is the second through hole, 603 is the third through hole, 604 is the fourth through hole, 605 is the fifth through hole. DETAILED DESCRIPTION

[0012] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. Example

[0013] like Figure 2 As shown, the device structure of this embodiment includes part A1: NWELL region (100), a first P+ contact region (201) located inside the NWELL region (100), a second N+ contact region (102) located inside the NWELL region (100), and a first active region (401) located inside the first P+ contact region (201), and also includes a first polycrystalline gate (001), a first metal (301), a first contact hole (501) located in the first active region (401), and a second contact hole (502) located in the first active region (401), wherein the first P+ contact region (201) and the second N+ contact region (102) may be adjacent to or non-adjacent to each other, and the first P+ contact region (201) and the second N+ contact region (102) are connected to VDD through the first contact hole (501), the first metal (301), the second through hole (602), the eighth metal (308), and the first through hole (601); The A2 portion includes: a third N+ contact region (103) is provided inside the NWELL region (100); a third active region (403) is located inside the third N+ contact region (103); the third N+ contact region (103) surrounds the A1 portion; the third N+ contact region (103) is connected to VDD through a fifth contact hole (505), a fourth metal (304), a second through hole (602), an eighth metal (308), and a first through hole (601); The device further comprises a B1 portion: a PWELL region (200), a first N+ contact region (101) located inside the PWELL region (200), a second P+ contact region (202), and a second active region (402) located inside the first N+ contact region (101), and further comprises a second polycrystalline gate (002), a second metal (302), and a third contact hole (503) located in the second active region (402), wherein the first N+ contact region (101) and the second P+ contact region (202) may be adjacent to or non-adjacent to each other, and the first N+ contact region (101) and the second P+ contact region (202) are connected to GND via the third contact hole (503), the second metal (302), the fourth through hole (604), the seventh metal (307), and the fifth through hole (605); The B2 portion includes: a third P+ contact region (203) is provided inside the PWELL (200), a fourth active region (404) is located inside the third P+ contact region (203), the third P+ contact region (203) surrounds the B1 portion, and the third P+ contact region (203) is connected to GND through a sixth contact hole (506), a fifth metal (305), a fourth through hole (604), a seventh metal (307), and a fifth through hole (605); It also includes a C part: a first P+ contact area (201) is provided inside the NWELL area (100) and is connected to the first N+ contact area (101) located inside the PWELL area (200) through a second contact hole (502), a third metal (303), and a fourth contact hole (504); A fourth N+ contact region (104) is provided, a fifth active region (405) is provided inside the fourth N+ contact region (104), and the fourth N+ contact region (104) surrounds the B2 portion; wherein the fourth N+ contact region (104) is connected to VDD through a seventh contact hole (507), a sixth metal (306), a third through hole (603), an eighth metal (308), and a first through hole (601); A fourth P+ contact area (204) is provided, a sixth active area (406) is provided inside the fourth P+ contact area (204), and the fourth P+ contact area (204) surrounds the A2 or B2 portion; wherein the fourth P+ contact area (204) is connected to GND through an eighth contact hole (508) and a ninth metal (309).

[0014] The working principle of this embodiment is: In the existing commonly used PMOS+NMOS driving circuit, according to the process design rules, there is usually a certain distance between the P+ contact area and the N+ contact area. However, there is a certain distance between the substrate contact and the source contact of the MOS tube, which will cause a large resistance in the well area between the substrate contact and the source contact. If the resistance generates a voltage drop due to the current flowing through it, there will undoubtedly be a potential difference between the source area and the substrate. This potential difference is the emitter bias of the parasitic transistor. When the potential difference reaches a certain voltage value, the internal parasitic transistor will be turned on, causing the circuit to latch.

[0015] In Example 1, the design of reducing the local through holes in the active area between the PMOS and NMOS regions significantly suppresses the maximum current of the parasitic transistor, that is, reduces the maximum bias voltage of the emitter of the parasitic transistor, thereby making it more difficult to trigger the latch-up condition. Moreover, even when latch-up occurs, the maximum current in the parasitic transistor is within the safe range that the device can withstand, thereby preventing device damage and circuit failure. This better protects and improves the circuit's anti-latch capability.

[0016] In addition, in Embodiment 1, an additional isolation ring may be added to absorb part of the current flowing through the substrate parasitic resistance, thereby achieving the effect of reducing the emitter bias of the parasitic transistor, thereby further improving the anti-latch capability of the circuit.

[0017] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An anti-latch layout structure, characterized in that: The invention comprises an A1 part: an NWELL region (100), a first P+ contact region (201) located inside the NWELL region (100), a second N+ contact region (102) located inside the NWELL region (100), and a first active region (401) located inside the first P+ contact region (201), and further comprises a first polycrystalline gate (001), a first metal (301), a first contact hole (501) located in the first active region (401), and a second contact hole (502) located in the first active region (401), wherein the first P+ contact region (201) and the second N+ contact region (102) may be adjacent to or non-adjacent to each other, and the first P+ contact region (201) and the second N+ contact region (102) are connected to VDD via the first contact hole (501), the first metal (301), the second through hole (602), the eighth metal (308), and the first through hole (601); The A2 portion includes: a third N+ contact region (103) is provided inside the NWELL region (100); a third active region (403) is located inside the third N+ contact region (103); the third N+ contact region (103) surrounds the A1 portion; the third N+ contact region (103) is connected to VDD through a fifth contact hole (505), a fourth metal (304), a second through hole (602), an eighth metal (308), and a first through hole (601); The device further comprises a B1 portion: a PWELL region (200), a first N+ contact region (101) located inside the PWELL region (200), a second P+ contact region (202), and a second active region (402) located inside the first N+ contact region (101), and further comprises a second polycrystalline gate (002), a second metal (302), and a third contact hole (503) located in the second active region (402), wherein the first N+ contact region (101) and the second P+ contact region (202) may be adjacent to or non-adjacent to each other, and the first N+ contact region (101) and the second P+ contact region (202) are connected to GND via the third contact hole (503), the second metal (302), the fourth through hole (604), the seventh metal (307), and the fifth through hole (605); The B2 portion includes: a third P+ contact region (203) is provided inside the PWELL (200), a fourth active region (404) is located inside the third P+ contact region (203), the third P+ contact region (203) surrounds the B1 portion, and the third P+ contact region (203) is connected to GND through a sixth contact hole (506), a fifth metal (305), a fourth through hole (604), a seventh metal (307), and a fifth through hole (605); It also includes a C part: a first P+ contact area (201) is provided inside the NWELL area (100) and is connected to the first N+ contact area (101) located inside the PWELL area (200) through a second contact hole (502), a third metal (303), and a fourth contact hole (504).

2. The anti-latch layout structure according to claim 1, characterized in that: A fourth N+ contact region (104) is provided, a fifth active region (405) is provided inside the fourth N+ contact region (104), and the fourth N+ contact region (104) surrounds the B2 portion; wherein the fourth N+ contact region (104) is connected to VDD through a seventh contact hole (507), a sixth metal (306), a third through hole (603), an eighth metal (308), and a first through hole (601).

3. The anti-latch layout structure according to claim 1, characterized in that: A fourth P+ contact area (204) is provided, a sixth active area (406) is provided inside the fourth P+ contact area (204), and the fourth P+ contact area (204) surrounds the A2 or B2 portion; wherein the fourth P+ contact area (204) is connected to GND through an eighth contact hole (508) and a ninth metal (309).

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