Package including substrate having dielectric layers of different materials

Abstract

A package includes a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 951,601 filed in the U.S. Patent Office on September 23, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features are directed to a package having a substrate and an integrated device.

[0005] background

[0006] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various functions. The performance of a package and its components may depend on how these components are coupled together. There is a continuing need for a package to include a more compact form factor with improved connections so that the package can be implemented in a smaller device and provide improved performance.

[0007] Overview

[0008] Various features are directed to a package having a substrate and an integrated device.

[0009] An example provides a package including a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a material different from the first dielectric layer and the third dielectric layer.

[0010] Another example provides a substrate including a first dielectric layer, a second dielectric layer, and a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a material different from that of the first dielectric layer and the third dielectric layer.

[0011] Another example provides a method for manufacturing a package. The method provides a substrate, the substrate including a first dielectric layer; a second dielectric layer; a third dielectric layer; and a plurality of interconnects located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer. The method couples an integrated device to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0014] Figure 1 A cross-sectional cutaway view of a substrate is illustrated.

[0015] Figure 2 A cross-sectional profile view of a package including a substrate, integrated devices, and passive devices is illustrated.

[0016] Figure 3 A plan view of a substrate is illustrated.

[0017] Figure 4 A close-up cross-sectional profile view illustrating an integrated device coupled to a substrate.

[0018] Figures 5A-5D An exemplary process for fabricating a substrate having different dielectric layers is illustrated.

[0019] Figure 6 An exemplary flow chart of a method for manufacturing a package including a substrate having different dielectric layers is illustrated.

[0020] Figure 7 An exemplary process for fabricating a package including a substrate, integrated devices, and passive devices is illustrated.

[0021] Figure 8 An exemplary flow chart of a method for fabricating a package including a substrate, an integrated device, and passive devices is illustrated.

[0022] Fig. 9 Various electronic devices are illustrated that may integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein.

[0023] Detailed Description

[0024] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0025] The present disclosure describes a package including a substrate and an integrated device coupled to the substrate. The substrate includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnections located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a material different from the first dielectric layer and the third dielectric layer. In some implementations, the second dielectric layer does not have a glass material, and the first dielectric layer and / or the third dielectric layer include a glass material. In some implementations, the first dielectric layer and / or the third dielectric layer include prepreg. Using dielectric layers with different materials for different layers helps to provide interconnections with smaller spacing and / or smaller pitches, potentially allowing higher density interconnections, shorter electrical paths for current and / or signals, which may lead to improved performance of integrated devices and packages.

[0026] Exemplary package including an integrated device and a substrate including dielectric layers having different materials

[0027] Figure 1 A cross-sectional cutaway view of substrate 102 is illustrated. Substrate 102 may be an embedded trace substrate (ETS). Substrate 102 may be a coreless substrate without a core layer. Substrate 102 includes dielectric layer 120, dielectric layer 130, dielectric layer 140, a plurality of interconnects 122, solder resist layer 150, and solder resist layer 160.

[0028] Dielectric layer 120 may be a first dielectric layer. Dielectric layer 130 may be a second dielectric layer. Dielectric layer 140 may be a third dielectric layer. Dielectric layer 120 is coupled to a first surface of dielectric layer 130. Dielectric layer 140 is coupled to a second surface of dielectric layer 130. Dielectric layer 130 may be located between dielectric layer 120 and dielectric layer 140. Dielectric layer 130 may include a material different from one or more materials from dielectric layer 120 and dielectric layer 140. In some implementations, dielectric layer 130 (e.g., second dielectric layer) is free of glass material. In some implementations, dielectric layer 120 (e.g., first dielectric layer) and / or dielectric layer 140 (e.g., third dielectric layer) include glass material. In some implementations, dielectric layer 120 and / or dielectric layer 140 include prepreg. Solder resist layer 150 may be located on (e.g., above) a surface of dielectric layer 120. The solder resist layer 160 may be located on (eg, below) a surface of the dielectric layer 140 .

[0029] A plurality of interconnects 122 may be located at least in dielectric layer 120, dielectric layer 130, and dielectric layer 140. Some interconnects from the plurality of interconnects 122 may be located in and / or on surfaces of dielectric layer 120, dielectric layer 130, and dielectric layer 140. The plurality of interconnects 122 include interconnects 122aa, interconnects 122ab, interconnects 122ac, interconnects 122ad, interconnects 122ae, interconnects 122af, interconnects 122ag, interconnects 122ba, interconnects 122bb, interconnects 122bc, interconnects 122bd, interconnects 122be, interconnects 122bf, and interconnects 122bg. Interconnects 122aa, interconnects 122ab, interconnects 122ac, interconnects 122ad, interconnects 122ae, interconnects 122af, and / or interconnects 122ag may define a first column of interconnects 105a. Interconnect 122aa is coupled to interconnect 122ab. Interconnect 122ab is coupled to interconnect 122ac. Interconnect 122ac is coupled to interconnect 122ad. Interconnect 122ad is coupled to interconnect 122ae. Interconnect 122ae is coupled to interconnect 122af. Interconnect 122af is coupled to interconnect 122ag. Interconnect 122ba, interconnect 122bb, interconnect 122bc, interconnect 122bd, interconnect 122be, interconnect 122bf, and / or interconnect 122bg may define a second column interconnect 105b. Interconnect 122ba is coupled to interconnect 122bb. Interconnect 122bb is coupled to interconnect 122bc. Interconnect 122bc is coupled to interconnect 122bd. Interconnect 122bd is coupled to interconnect 122be. Interconnect 122be is coupled to interconnect 122bf. Interconnect 122bf is coupled to interconnect 122bg. The first column interconnect 105 a and the second column interconnect 105 b may be part of a plurality of column interconnects 105 .

[0030] An integrated device (not shown) may be coupled to substrate 102 via a plurality of solder pillar interconnects 104 and a plurality of solder interconnects 106. The plurality of solder pillar interconnects 104 include solder pillar interconnects 104a and solder pillar interconnects 104b. The plurality of solder interconnects 106 include solder interconnects 106a and solder interconnects 106b.

[0031] The solder pillar interconnect 104a is coupled to the first column interconnect 105a through the solder interconnect 106a. The solder pillar interconnect 104b is coupled to the second column interconnect 105b through the solder interconnect 106b. A plurality of solder interconnects 190 are coupled to the substrate 102. A plurality of solder interconnects 190 are coupled to the plurality of interconnects 122. For example, a plurality of solder interconnects 190 are coupled to the first column interconnect 105a and the second column interconnect 105b. In one example, the solder interconnect 190a is coupled to the first column interconnect 105a, and the second solder interconnect 190b is coupled to the second column interconnect 105b.

[0032] like Figure 1As shown in FIG. 1 , the plurality of solder pillar interconnects 104 may include an integrated device bump pitch P. ID Similarly, the plurality of solder interconnects 106 may include an integrated device bump solder pitch P ID In addition, the plurality of solder interconnects 190 may include a solder bump having an integrated passive device solder pitch P. IPDS In some implementations, the pitch between adjacent column interconnects (eg, 105a, 105b) may be P CI In some implementations, the pitch between adjacent column interconnects (e.g., 105a, 105b) is approximately the same as the pitch between adjacent solder interconnects (e.g., 106a, 106b) coupled to adjacent column interconnects (e.g., 105a, 105b). In some implementations, the pitch between adjacent column interconnects (e.g., 105a, 105b) is approximately the same as the pitch between adjacent solder pillar interconnects (e.g., 104a, 104b) coupled to adjacent column interconnects (e.g., 105a, 105b) through adjacent solder interconnects (e.g., 106a, 106b). In some implementations, the pitch between adjacent column interconnects (e.g., 105a, 105b) is approximately the same as the pitch between adjacent solder interconnects (e.g., 190a, 190b) coupled to adjacent column interconnects (e.g., 105a, 105b).

[0033] In some implementations, a pair of pad interconnects on a particular metal layer (e.g., M1, M2, M3, M4) from the first column interconnect 105a and the second column interconnect 105b may have approximately the same pitch as another pair of pad interconnects on another metal layer (e.g., M1, M2, M3, M4) from the first column interconnect 105a and the second column interconnect 105b. For example, in some implementations, the pitch between interconnect 122aa and interconnect 122ba is approximately the same as the pitch between interconnect 122ac and interconnect 122bc. In some implementations, the pitch between interconnect 122aa and interconnect 122ba is approximately the same as the pitch between interconnect 122ae and interconnect 122be. In some implementations, the pitch between interconnect 122aa and interconnect 122ba is approximately the same as the pitch between interconnect 122ag and interconnect 122bg.

[0034] In some implementations, a pair of through-hole interconnects between two specific metal layers from the first column interconnect 105a and the second column interconnect 105b may have approximately the same pitch as another pair of through-hole interconnects between two other metal layers from the first column interconnect 105a and the second column interconnect 105b. For example, in some implementations, the pitch between interconnect 122ab and interconnect 122bb is approximately the same as the pitch between interconnect 122ad and interconnect 122bd. In some implementations, the pitch between interconnect 122ab and interconnect 122bb is approximately the same as the pitch between interconnect 122af and interconnect 122bf.

[0035] In some implementations, a pair of pad interconnects on a particular metal layer from the first column interconnect 105a and the second column interconnect 105b may have approximately the same pitch as a pair of via interconnects between two metal layers from the first column interconnect 105a and the second column interconnect 105b. For example, in some implementations, the pitch between interconnect 122aa and interconnect 122ba is approximately the same as the pitch between interconnect 122ab and interconnect 122bb. In some implementations, the pitch between interconnect 122ac and interconnect 122bc is approximately the same as the pitch between interconnect 122ad and interconnect 122bd. In some implementations, the pitch between interconnect 122ae and interconnect 122be is approximately the same as the pitch between interconnect 122af and interconnect 122bf.

[0036] Using dielectric layers with different materials for different layers helps provide interconnects with smaller spacing and / or smaller pitches, thereby allowing higher density interconnects, shorter electrical paths for current and / or signals, which may lead to improved performance of integrated devices and packages. In addition, using different dielectric materials between two other dielectric layers will not significantly affect the overall warpage of the substrate, thereby providing a substrate with reliable interconnects.

[0037] In some implementations, the pad interconnects (e.g., 122aa, 122ac, 122ae, 122ag, 122ba, 122bc, 122be, 122bg) from the first column interconnect 105a and / or the second column interconnect 105b may each have a minimum width and / or minimum diameter of about 90 microns. In some implementations, the first dielectric layer 120 may have a minimum thickness (T1) of about 20 microns. In some implementations, the second dielectric layer 130 may have a minimum thickness (T2) of about 15 microns. In some implementations, the third dielectric layer 140 may have a minimum thickness (T3) of about 20 microns. Thus, in some implementations, the thickness (T2) of the second dielectric layer 130 may be thinner than the thickness (T1) of the first dielectric layer 120 and / or the thickness (T3) of the third dielectric layer 140.

[0038] In some implementations, the through-hole interconnects (e.g., 122ab, 122af, 122bb, 122bf) from the first column interconnect 105a and / or the second column interconnect 105b located in the first dielectric layer 120 and / or the third dielectric layer 140 may each have a minimum width and / or minimum diameter of about 60 microns at its widest portion. In some implementations, the through-hole interconnects (e.g., 122ad, 122bd) from the first column interconnect 105a and / or the second column interconnect 105b located in the second dielectric layer 130 may each have a minimum width and / or minimum diameter of about 50 microns at its widest portion. In some implementations, the above configuration using different dielectric layers between the two dielectric layers helps to provide each interconnect pair from adjacent column interconnects on the same metal layer to have similar or identical spacing (S). I ).

[0039] In some implementations, the first column interconnect 105a is configured to provide an electrical path for power between the integrated device and the passive device. In some implementations, the second column interconnect 105b is configured to provide an electrical path for ground between the integrated device and the passive device. The passive device may include a capacitor (e.g., a discrete inductor). The passive device may include a decoupling capacitor configured to couple to a power source and / or a power distribution network.

[0040] Notice that Figure 1 A substrate including four metal layers is illustrated. However, other implementations may include substrates having more than four metal layers. In addition, other substrates may include other dielectric layers similar to the second dielectric layer 130. For example, in some implementations, the substrate may include five metal layers including a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer, wherein the second dielectric layer and the third dielectric layer are similar to the second dielectric layer 130, and wherein the first dielectric layer and the fourth dielectric layer are similar to the first dielectric layer 120.

[0041] Figure 2 A package 200 including a substrate 102, an integrated device 202, a passive device 205, a passive device 207, and a passive device 209 is illustrated. The integrated device 202 is coupled to a first surface (e.g., a top surface) of the substrate 102 through a plurality of solder pillar interconnects 104 and a plurality of solder interconnects 106. The passive device 205 is coupled to a second surface (e.g., a bottom surface) of the substrate 102 through a plurality of solder interconnects 250. The passive device 207 is coupled to a second surface (e.g., a bottom surface) of the substrate 102 through a plurality of solder interconnects 270. The passive device 209 is coupled to a second surface (e.g., a bottom surface) of the substrate 102 through a plurality of solder interconnects 290. In some implementations, at least a portion of the passive device 205, at least a portion of the passive device 207, and / or at least a portion of the passive device 209 may overlap vertically with the integrated device 202.

[0042] The substrate 102 includes a plurality of column interconnects 222. The plurality of column interconnects 222 are a portion of the plurality of column interconnects 122 of the substrate 102. The plurality of column interconnects 222 may be configured and / or arranged in a similar manner to the first column interconnects 105a and / or the second column interconnects 105b.

[0043] The integrated device 202 is configured to be electrically coupled to the passive device 205 through an electrical path (e.g., for power) including solder pillar interconnects from the plurality of solder pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, a column interconnect 222a, and solder interconnects from the plurality of solder interconnects 250. The integrated device 202 is configured to be electrically coupled to the passive device 205 through an electrical path (e.g., for ground) including solder pillar interconnects from the plurality of solder pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, a column interconnect 222b, and solder interconnects from the plurality of solder interconnects 250.

[0044] The integrated device 202 is configured to be electrically coupled to the passive device 207 through an electrical path (e.g., for power) that includes solder pillar interconnects from the plurality of solder pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, a column interconnect 222c, and solder interconnects from the plurality of solder interconnects 270. The integrated device 202 is configured to be electrically coupled to the passive device 207 through an electrical path (e.g., for ground) that includes solder pillar interconnects from the plurality of solder pillar interconnects 104, solder interconnects from the plurality of solder interconnects 106, at least one column interconnect 222d, and solder interconnects from the plurality of solder interconnects 270.

[0045] The integrated device 202 is configured to be electrically coupled to the passive device 209 through an electrical path (e.g., for power) including: a solder pillar interconnect from the plurality of solder pillar interconnects 104, a solder interconnect from the plurality of solder interconnects 106, a column interconnect 222e, and a solder interconnect from the plurality of solder interconnects 290. The integrated device 202 is configured to be electrically coupled to the passive device 207 through an electrical path (e.g., for ground) including: a solder pillar interconnect from the plurality of solder pillar interconnects 104, a solder interconnect from the plurality of solder interconnects 106, a column interconnect 222f, and a solder interconnect from the plurality of solder interconnects 290. In some implementations, the integrated device 202, the passive device 205, the passive device 207, and the passive device 209 are configured to be electrically coupled to a power distribution network.

[0046] Figure 3 A plan view of the substrate 102 is illustrated. Figure 3As shown in , substrate 102 includes first dielectric layer 120, multiple interconnects 302, and multiple interconnects 304. Multiple interconnects 302 and multiple interconnects 304 are located in a region 300 of substrate 102 that vertically overlaps with an integrated device (e.g., 202). Multiple interconnects 302 and multiple interconnects 304 may be located on a first metal layer (e.g., M1) of substrate 102. The pitch and / or spacing of multiple interconnects 302 is greater than the pitch and / or spacing of multiple interconnects 304. Multiple interconnects 302 may include at least one interconnect as in Figure 1 and 2 The plurality of interconnects and / or the plurality of interconnects 304 may be a portion of the plurality of interconnects 122.

[0047] Figure 4 A close-up view illustrating how an integrated device may be coupled to a substrate. The integrated device 202 may be coupled to the substrate 102 via a plurality of solder pillar interconnects and a plurality of solder interconnects. The integrated device 202 and the substrate 102 may be part of a package 200. The integrated device 202 includes a die portion 402, a plurality of solder pillar interconnects 104, and a plurality of solder interconnects 106. The plurality of solder pillar interconnects 104 are coupled to the die portion 402. The plurality of solder interconnects 106 are coupled to the plurality of solder pillar interconnects 104. The integrated device 202 may include a flip chip.

[0048] The die portion 402 includes a die substrate 420, an interconnection portion 422, a passivation layer 405, a passivation layer 408, a plurality of pads 407, a passivation layer 408, and a plurality of under-bump metallization interconnections 409. The die substrate 420 may include silicon (Si). A plurality of cells (e.g., logic cells) and / or a plurality of transistors (not shown) may be formed in and / or on the die substrate 420. Different implementations may use different types of transistors, such as field effect transistors (FETs), planar FETs, fin FETs, and surround gate FETs. In some implementations, a front-end process (FEOL) process may be used to manufacture the plurality of cells (e.g., logic cells) and / or transistors in and / or on the die substrate 420. The interconnection portion 422 is located on the die substrate 420 and is coupled to the die substrate 120. The interconnection portion 422 may be coupled to a plurality of cells and / or transistors located in and / or on the die substrate 420. The interconnect portion 422 (eg, die interconnect portion) may include a plurality of die interconnects (not shown) coupled to a plurality of cells and / or transistors. In some implementations, a back-end of line (BEOL) process may be used to fabricate the interconnect portion 422 .

[0049] Passivation layer 405 is located on interconnection portion 422 and coupled to interconnection portion 122. Passivation layer 405 can be a hard passivation layer. Passivation layer 408 is located on passivation layer 405. Passivation layer 408 can include a polymer passivation layer. Multiple pads 407 are located on interconnection portion 422. Multiple pads 407 can be coupled to the die interconnect of interconnection portion 422. In some implementations, passivation layer 405, passivation layer 408 and / or multiple pads 407 can be considered as part of interconnection portion 422. In some implementations, passivation layer 405, passivation layer 408 and multiple pads 407 can be manufactured using a back-end process (BEOL) process. Multiple under bump metallization interconnects 409 are coupled to multiple pads 407. Multiple under bump metallization interconnects 409 can be located on multiple pads 407. In some implementations, additional interconnects can exist between multiple pads 407 and multiple under bump metallization interconnects 409. For example, there may be a metallization interconnect between the plurality of pads 407 and the plurality of under bump metallization interconnects 409. Examples of metallization interconnects include redistribution interconnects. In some implementations, the plurality of under bump metallization interconnects 409 may be coupled to the plurality of pads 407 via a metallization interconnect (e.g., a redistribution interconnect).

[0050] The plurality of solder pillar interconnects 104 may be coupled to the die portion 402. The plurality of solder pillar interconnects 104 may be coupled to the plurality of under bump metallization interconnects 409. The plurality of solder pillar interconnects 104 may be coupled to the die portion 402 through the plurality of under bump metallization interconnects 409. The plurality of solder pillar interconnects 104 may be a means for solder pillar interconnection. The plurality of under bump metallization interconnects 409 may be a means for under bump metallization interconnection.

[0051] The plurality of pads 407 include a first pad 407a and a second pad 407b. The plurality of under bump metallization interconnects 409 include a first under bump metallization interconnect 409a and a second under bump metallization interconnect 409b. The plurality of solder pillar interconnects 104 include a first solder pillar interconnect 104a and a second solder pillar interconnect 104b. The plurality of solder interconnects 106 include a first solder interconnect 106a and a second solder interconnect 106b.

[0052] The first under bump metallization interconnect 409a is coupled to the first pad 407a. The first solder pillar interconnect 104a is coupled to the first under bump metallization interconnect 409a. The first solder interconnect 106a is coupled to the first solder pillar interconnect 104a. Note that in some implementations, the first solder pillar interconnect 104a is coupled to the first under bump metallization interconnect 409a through at least one metallization interconnect. That is, at least one metallization interconnect (e.g., a redistribution interconnect) may be located between the first solder pillar interconnect 104a and the first under bump metallization interconnect 409a.

[0053] The second under bump metallization interconnect 409b is coupled to the second pad 407b. The second solder pillar interconnect 104b is coupled to the second under bump metallization interconnect 409b. The second solder interconnect 106b is coupled to the second solder pillar interconnect 104b. Note that in some implementations, the second solder pillar interconnect 104b is coupled to the second under bump metallization interconnect 409b through at least one metallization interconnect. That is, at least one metallization interconnect (e.g., a redistribution interconnect) may be located between the second solder pillar interconnect 104b and the second under bump metallization interconnect 409b.

[0054] Integrated device 202 is coupled to substrate 102 via multiple solder interconnects 106 and multiple solder pillar interconnects 104. For example, solder interconnect 106a may be directly coupled to interconnect 122aa and solder pillar interconnect 104a. In some implementations, solder interconnect 106b may be directly coupled to interconnect 122ba and solder pillar interconnect 104b.

[0055] An integrated device (e.g., 202) may include a die (e.g., a bare semiconductor die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, an integrated device based on silicon (Si), an integrated device based on silicon carbide (SiC), a memory, a power management processor, and / or a combination thereof. An integrated device (e.g., 202) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a core particle. A core particle may be manufactured using a process that provides a better yield than other processes used to manufacture other types of integrated devices, which may reduce the overall cost of manufacturing the core particle. Different core particles may have different sizes and / or shapes. Different core particles may be configured to provide different functions. Different core particles may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Thus, for example, a single integrated device may be divided into several chiplets. As mentioned, the use of several core particles that perform several functions may reduce the overall cost of the package relative to using a single chip to perform all functions of the package. In some implementations, one or more core particles and / or one or more integrated devices (e.g., 202) described in the present disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 202) may be manufactured using a first technology node, and a core particle may be manufactured using a second technology node that is not as advanced as the first technology node. In this example, the integrated device (e.g., 202) may include a component (e.g., an interconnect, a transistor) having a first minimum size, and the core particle may include a component (e.g., an interconnect, a transistor) having a second minimum size, wherein the second minimum size is greater than the first minimum size. In some implementations, the packaged integrated device and the other integrated device may be manufactured using the same technology node or different technology nodes. In some implementations, the packaged die and the other die may be manufactured using the same technology node or different technology nodes.

[0056] Exemplary Process for Making a Substrate

[0057] In some implementations, manufacturing the substrate includes several processes. Figures 5A-5D Exemplary processes for providing or manufacturing a substrate are described. In some implementations, Figures 5A-5DThe process may be used to provide or manufacture the substrate 102. However, Figures 5A-5D The process may be used to manufacture any substrate described in this disclosure.

[0058] It should be noted that Figures 5A-5D The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0059] like Figure 5A As shown in , stage 1 illustrates a state after providing a core layer 501. The core layer 501 may include a seed layer 503 located on a first surface of the core layer 501 and a seed layer 505 located on a second surface of the core layer 501. The core layer 501 may be a dielectric. The core layer 501 may be a carrier.

[0060] Stage 2 illustrates a state after interconnects are formed in and on the surfaces of core layer 501, seed layer 503, and / or seed layer 505. Multiple interconnects 502 may be formed on (e.g., above) a first surface of core layer 501 and / or seed layer 503. Seed layer 503 may be a portion of multiple interconnects 502. Multiple interconnects 502 may be formed on (e.g., below) a second surface of core layer 512 and / or seed layer 505. Seed layer 505 may be a portion of multiple interconnects 512. Multiple interconnects 502 and / or multiple interconnects 512 may be formed using masking, plating, and / or etching processes.

[0061] Stage 3 illustrates a state after dielectric layer 520 is formed on (e.g., above) the first surface of core layer 501, seed layer 503, and / or multiple interconnects 502. Stage 4 also illustrates a state after dielectric layer 530 is formed on (e.g., below) the second surface of core layer 501, seed layer 505, and / or multiple interconnects 512. Dielectric layer 520 and dielectric layer 530 may be formed using deposition and / or lamination processes. Dielectric layer 520 and dielectric layer 530 may be different from core layer 501.

[0062] Stage 4 illustrates a state after forming a plurality of cavities 521 in dielectric layer 520 and a plurality of cavities 531 in dielectric layer 530. A photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation) may be used to form the plurality of cavities 521 and the plurality of cavities 531. A mask, exposure, and / or development process may be used to form the plurality of cavities 521 and the plurality of cavities 531.

[0063] Stage 5 illustrates a state after interconnects are formed in and on the surfaces of dielectric layer 520 and dielectric layer 530. Multiple interconnects 522 may be formed on (e.g., above) the first surface of dielectric layer 520 and multiple cavities 521. Multiple interconnects 532 may be formed on (e.g., below) the second surface of dielectric layer 530 and multiple cavities 531. Multiple interconnects 522 and / or multiple interconnects 532 may be formed using masking, plating, and / or etching processes.

[0064] like Figure 5B As shown in FIG. 6 , stage 6 illustrates a state after dielectric layer 540 is formed on (e.g., above) the first surface of dielectric layer 520 and plurality of interconnects 522. Stage 7 further illustrates a state after dielectric layer 550 is formed on (e.g., below) the second surface of dielectric layer 530 and plurality of interconnects 532. Dielectric layer 540 and dielectric layer 550 may be formed using deposition and / or lamination processes. Dielectric layer 540 and / or dielectric layer 550 may be a dielectric material different from the dielectric material of dielectric layer 520 and / or dielectric layer 530.

[0065] Stage 7 illustrates a state after forming a plurality of cavities 541 in dielectric layer 540 and a plurality of cavities 551 in dielectric layer 550. A photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation) may be used to form the plurality of cavities 541 and the plurality of cavities 551. A mask, exposure, and / or development process may be used to form the plurality of cavities 541 and the plurality of cavities 551.

[0066] Stage 8 illustrates a state after interconnects are formed in and on the surfaces of dielectric layer 540 and dielectric layer 550. Multiple interconnects 542 may be formed on (e.g., above) the first surface of dielectric layer 540 and multiple cavities 541. Multiple interconnects 552 may be formed on (e.g., below) the second surface of dielectric layer 550 and multiple cavities 551. Multiple interconnects 542 and / or multiple interconnects 552 may be formed using masking, plating, and / or etching processes.

[0067] like Figure 5C As shown in FIG. 1 , stage 9 illustrates a state after dielectric layer 560 is formed on (e.g., above) the first surface of dielectric layer 540 and the plurality of interconnects 542. Stage 9 also illustrates a state after dielectric layer 570 is formed on (e.g., below) the second surface of dielectric layer 550 and the plurality of interconnects 552. Dielectric layer 560 and dielectric layer 570 may be formed using a deposition and / or lamination process. Dielectric layer 560 and / or dielectric layer 570 may be a dielectric material different from the dielectric material of dielectric layer 540 and / or dielectric layer 550. Dielectric layer 560 and / or dielectric layer 570 may be a dielectric material similar to the dielectric material of dielectric layer 520 and / or dielectric layer 530.

[0068] Stage 10 illustrates a state after forming a plurality of cavities 561 in dielectric layer 560 and a plurality of cavities 571 in dielectric layer 570. A photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation) may be used to form the plurality of cavities 561 and the plurality of cavities 571. A mask, exposure, and / or development process may be used to form the plurality of cavities 561 and the plurality of cavities 571.

[0069] Stage 11 illustrates a state after interconnects are formed in and on the surfaces of dielectric layer 560 and dielectric layer 570. Multiple interconnects 562 may be formed on (e.g., above) the first surface of dielectric layer 560 and multiple cavities 561. Multiple interconnects 572 may be formed on (e.g., below) the second surface of dielectric layer 570 and multiple cavities 571. Multiple interconnects 562 and / or multiple interconnects 572 may be formed using masking, plating, and / or etching processes. Stage 11 may illustrate substrate 590a and substrate 590b coupled to core layer 501.

[0070] like Figure 5D , stage 12 illustrates a state after substrate 590b is separated from core layer 501. A portion of seed layer 505 may also be removed. Substrate 590a may also be separated from core layer 501 in a similar manner. Substrate 590b may represent substrate 102 including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 530, second dielectric layer 130 may be dielectric layer 550, and third dielectric layer 140 may be dielectric layer 570. Multiple interconnects 122 may represent multiple interconnects 532, multiple interconnects 552, and / or multiple interconnects 572.

[0071] In a similar manner, substrate 590a may represent substrate 102 including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 520, second dielectric layer 130 may be dielectric layer 540, and third dielectric layer 140 may be dielectric layer 560. Multiple interconnects 122 may represent multiple interconnects 522, multiple interconnects 542, and / or multiple interconnects 562.

[0072] Stage 13 illustrates a state after forming the solder resist layer 150 and the solder resist layer 160. The solder resist layer 150 and the solder resist layer 160 may be formed using a lamination process and / or a deposition process.

[0073] Note that additional dielectric layers and / or additional interconnects may be formed by repeating some of the above processes.

[0074] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0075] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0076] In some implementations, manufacturing the substrate includes several processes. Figure 6 An exemplary flow chart of a method 600 for providing or manufacturing a substrate is illustrated. In some implementations, Figure 6 The method 600 may be used to provide or manufacture the substrate 102 described in the present disclosure. However, the method 600 may be used to provide or manufacture any substrate described in the present disclosure.

[0077] It should be noted that Figure 6 The method of the present invention can combine one or more processes to simplify and / or illustrate the method for providing or manufacturing a substrate. In some implementations, the order of each process can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0078] The method provides (at 605) a core layer and at least one seed layer. Figure 5A As shown in , stage 1 illustrates a state after providing a core layer 501. The core layer 501 may include a seed layer 503 located on a first surface of the core layer 501 and a seed layer 505 located on a second surface of the core layer 501. The core layer 501 may be a dielectric. The core layer 501 may be a carrier.

[0079] The method forms (at 610 ) and patterns a plurality of interconnects on (eg, over, under) the core layer and / or the at least one seed layer. Figure 5A Stage 2 of illustrative embodiment illustrates a state after interconnects are formed in and on the surface of core layer 501, seed layer 503, and / or seed layer 505. Multiple interconnects 502 may be formed on (e.g., above) the first surface of core layer 501 and / or seed layer 503. Seed layer 503 may be a part of multiple interconnects 502. Multiple interconnects 502 may be formed on (e.g., below) the second surface of core layer 512 and / or seed layer 505. Seed layer 505 may be a part of multiple interconnects 512. Multiple interconnects 502 and / or multiple interconnects 512 may be formed using masking, plating, and / or etching processes.

[0080] The method forms (at 615) at least one dielectric layer over (eg, above, below) the plurality of interconnects, the core layer, and / or the seed layer. Figure 5AStage 3 of the embodiment illustrates a state after dielectric layer 520 is formed on (e.g., above) the first surface of core layer 501, seed layer 503, and / or multiple interconnects 502. Stage 3 also illustrates a state after dielectric layer 530 is formed on (e.g., below) the second surface of core layer 501, seed layer 505, and / or multiple interconnects 512. Dielectric layer 520 and dielectric layer 530 may be formed using deposition and / or lamination processes. Dielectric layer 520 and dielectric layer 530 may be different from core layer 501.

[0081] The method forms (at 620) a plurality of interconnects in and on at least one dielectric layer (eg, a first dielectric layer). Forming the plurality of interconnects may include forming a plurality of cavities in at least one dielectric layer (eg, a first dielectric layer) and performing a plating process. Figure 5A Stage 4 of illustrative embodiment illustrates a state after forming a plurality of cavities 521 in dielectric layer 520 and a plurality of cavities 531 in dielectric layer 530. The plurality of cavities 521 and the plurality of cavities 531 may be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). The plurality of cavities 521 and the plurality of cavities 531 may be formed using a mask, exposure, and / or development process. Note that in some implementations, forming cavities in a dielectric layer may be considered as forming part of a dielectric layer.

[0082] Figure 5A Stage 5 of illustrative embodiment illustrates a state after interconnects are formed in and on the surfaces of dielectric layer 520 and dielectric layer 530. Multiple interconnects 521 may be formed on (e.g., above) the first surface of dielectric layer 520 and multiple cavities 521. Multiple interconnects 532 may be formed on (e.g., below) the second surface of dielectric layer 530 and multiple cavities 531. Multiple interconnects 522 and / or multiple interconnects 532 may be formed using masking, plating, and / or etching processes.

[0083] The method forms (at 625) at least one dielectric layer on (e.g., above, below) the dielectric layer (e.g., the first dielectric layer). The dielectric layer may be a second dielectric layer formed on the first dielectric layer. The second dielectric layer may be a material different from the material of the first dielectric layer. Figure 5B As shown, stage 6 illustrates a state after dielectric layer 540 is formed on (e.g., above) the first surface of dielectric layer 520 and plurality of interconnects 522. Stage 7 further illustrates a state after dielectric layer 550 is formed on (e.g., below) the second surface of dielectric layer 530 and plurality of interconnects 532. Dielectric layer 540 and dielectric layer 550 may be formed using deposition and / or lamination processes. Dielectric layer 540 and / or dielectric layer 550 may be a dielectric material different from the dielectric material of dielectric layer 520 and / or dielectric layer 530.

[0084] The method forms (at 630) a plurality of interconnects in and on at least one dielectric layer (eg, the second dielectric layer). Forming the plurality of interconnects may include forming a plurality of cavities in at least one dielectric layer (eg, the second dielectric layer) and performing a plating process. Figure 5B Stage 7 of illustrative embodiment illustrates a state after forming a plurality of cavities 541 in dielectric layer 540 and a plurality of cavities 551 in dielectric layer 550. The plurality of cavities 541 and the plurality of cavities 551 may be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). The plurality of cavities 541 and the plurality of cavities 551 may be formed using a mask, exposure, and / or development process. Note that in some implementations, forming cavities in a dielectric layer may be considered as forming part of a dielectric layer.

[0085] Figure 5B Stage 8 of illustrative embodiments illustrates a state after interconnects are formed in and on the surfaces of dielectric layer 540 and dielectric layer 550. Multiple interconnects 542 may be formed on (e.g., above) the first surface of dielectric layer 540 and multiple cavities 541. Multiple interconnects 552 may be formed on (e.g., below) the second surface of dielectric layer 550 and multiple cavities 551. Multiple interconnects 542 and / or multiple interconnects 552 may be formed using masking, plating, and / or etching processes.

[0086] The method (at 630) forms at least one dielectric layer on (e.g., above, below) the dielectric layer (e.g., the second dielectric layer). The dielectric layer may be a third dielectric layer formed on the second dielectric layer. The third dielectric layer may be a different material than the second dielectric layer. The third dielectric layer may be the same or similar material as the first dielectric layer. Figure 5C As shown, stage 9 illustrates a state after dielectric layer 540 is formed on (e.g., above) the first surface of dielectric layer 540 and the plurality of interconnects 542. Stage 9 also illustrates a state after dielectric layer 570 is formed on (e.g., below) the second surface of dielectric layer 550 and the plurality of interconnects 552. Dielectric layer 560 and dielectric layer 570 may be formed using a deposition and / or lamination process. Dielectric layer 560 and / or dielectric layer 570 may be a dielectric material different from the dielectric material of dielectric layer 540 and / or dielectric layer 550. Dielectric layer 560 and / or dielectric layer 570 may be a dielectric material similar to the dielectric material of dielectric layer 520 and / or dielectric layer 530.

[0087] The method forms (at 640) a plurality of interconnects in and on at least one dielectric layer (eg, a third dielectric layer). Forming the plurality of interconnects may include forming a plurality of cavities in at least one dielectric layer (eg, a third dielectric layer) and performing a plating process. Figure 5CStage 10 of illustrative embodiment illustrates a state after forming a plurality of cavities 561 in dielectric layer 560 and a plurality of cavities 571 in dielectric layer 570. The plurality of cavities 561 and the plurality of cavities 571 may be formed using a photolithography process (e.g., exposure and development) and / or a laser process (e.g., laser ablation). The plurality of cavities 561 and the plurality of cavities 571 may be formed using a mask, exposure, and / or development process. Note that in some implementations, forming cavities in a dielectric layer may be considered as part of forming a dielectric layer.

[0088] Figure 5C Stage 11 of the present invention illustrates a state after interconnects are formed in and on the surfaces of dielectric layer 560 and dielectric layer 570. Multiple interconnects 562 may be formed on (e.g., above) the first surface of dielectric layer 560 and multiple cavities 561. Multiple interconnects 572 may be formed on (e.g., below) the second surface of dielectric layer 570 and multiple cavities 571. Multiple interconnects 562 and / or multiple interconnects 572 may be formed using masking, plating, and / or etching processes. Stage 11 may illustrate substrate 590a and substrate 590b coupled to core layer 501.

[0089] The method decouples (at 645) the core layer from the dielectric layers. In some implementations, portions of the seed layer may also be removed. Figure 5D Stage 12 of illustrative embodiment illustrates a state after substrate 590b is separated from core layer 501. A portion of seed layer 505 may also be removed. Substrate 590a may also be separated from core layer 501 in a similar manner. Substrate 590b may represent substrate 102 including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 530, second dielectric layer 130 may be dielectric layer 550, and third dielectric layer 140 may be dielectric layer 570. Multiple interconnects 122 may represent multiple interconnects 532, multiple interconnects 552, and / or multiple interconnects 572.

[0090] In a similar manner, substrate 590a may represent substrate 102 including dielectric layer 120, dielectric layer 130, and dielectric layer 140. For example, first dielectric layer 120 may be dielectric layer 520, second dielectric layer 130 may be dielectric layer 540, and third dielectric layer 140 may be dielectric layer 560. Multiple interconnects 122 may represent multiple interconnects 522, multiple interconnects 542, and / or multiple interconnects 562.

[0091] In some implementations, the method may further form one or more solder resist layers over the one or more dielectric layers. Figure 5D The stage of FIG. 1 illustrates a state after forming the solder resist layer 150 and the solder resist layer 160. The solder resist layer 150 and the solder resist layer 160 may be formed using a lamination process and / or a deposition process. Note that the above method may be used to manufacture a substrate having more metal layers and more dielectric layers.

[0092] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0093] Exemplary process for manufacturing a package including a substrate, an integrated device, and passive devices

[0094] In some embodiments, manufacturing the package includes several processes. Figure 7 Exemplary processes for providing or manufacturing a package including a substrate are described. In some implementations, Figure 7 The process can be used to provide or manufacture Figure 2 of package 200. However, Figure 7 The process may be used to manufacture any package described in this disclosure.

[0095] It should be noted that Figure 7 The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0096] like Figure 7 As shown in , stage 1 illustrates a state after providing substrate 102. Substrate 102 includes a first dielectric layer 120, a second dielectric layer 130, a third dielectric layer 140, a solder resist layer 150, a solder resist layer 160, and a plurality of interconnects 122. The second dielectric layer 130 may include a dielectric material different from the dielectric material of the first dielectric layer 120 and / or the third dielectric layer 140. The second dielectric layer 130 may be free of glass material. In some implementations, dielectric layer 130 may include a Build-Up Film (ABF). The first dielectric layer 120 and / or the third dielectric layer 140 may include a glass material. Figures 5A-5D An example of manufacturing a substrate is explained.

[0097] Stage 2 illustrates a state after the integrated device 202 is coupled to the first surface of the substrate 102 through the plurality of solder pillar interconnects 104 and the plurality of solder interconnects 106. The integrated device 202 may be coupled to the substrate 102 using a solder reflow process. Figure 4 An example of how the integrated device 202 may be coupled to the substrate 102 is illustrated.

[0098] Stage 2 also illustrates a state after at least one passive device (e.g., 205, 207, 209) is coupled to the second surface of the substrate 102 through a plurality of solder interconnects (e.g., 250, 270, 290). The at least one passive device may be coupled to the substrate 102 using a solder reflow process.

[0099] Stage 3 illustrates a state after providing (e.g., forming) an encapsulation layer 208 over the substrate 102. The encapsulation layer 208 may encapsulate the integrated device 202. The encapsulation layer 208 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 208 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 208 may be photoetchable. The encapsulation layer 208 may be a means for encapsulation.

[0100] Stage 4 illustrates a state after the plurality of solder interconnects 450 are coupled to the second surface of the substrate 102 through a solder reflow process. The plurality of solder interconnects 450 may be coupled to the plurality of interconnects 122.

[0101] Exemplary flow chart of a method for manufacturing a package including a substrate, an integrated device, and passive devices

[0102] In some implementations, manufacturing the package includes several processes. Figure 8 An exemplary flow chart of a method 800 for providing or manufacturing a package including a substrate is illustrated. In some implementations, Figure 8 The method 800 may be used to provide or manufacture the Figure 2 However, the method 800 may be used to provide or manufacture any package described in the present disclosure.

[0103] It should be noted that Figure 8 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0104] The method provides (at 1205) a substrate (e.g., 102). The substrate 102 may be provided by a supplier or manufactured. Different implementations may use different processes to manufacture the substrate 102. Examples of processes that may be used to manufacture the substrate include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 102 includes a first dielectric layer 120, a second dielectric layer 130, a third dielectric layer 140, a solder resist layer 150, a solder resist layer 160, and a plurality of interconnects 122. The second dielectric layer 130 may include a dielectric material different from the first dielectric layer 120 and / or the third dielectric layer 140. The second dielectric layer 130 may be free of a glass material. The first dielectric layer 120 and / or the third dielectric layer 140 may include a glass material. Figures 5A-5D An example of manufacturing a substrate is explained. Figure 7 Stage 1 of illustrates an example of providing a substrate.

[0105] The method may (at 810) couple an integrated device to a first surface of a substrate and couple at least one passive device to a second surface of the substrate. Figure 7 Stage 2 of illustrative embodiment illustrates a state after the integrated device 202 is coupled to the first surface of the substrate 102 through the plurality of solder pillar interconnects 104 and the plurality of solder interconnects 106. The integrated device 202 may be coupled to the substrate 102 using a solder reflow process. Figure 4 An example of how the integrated device 202 may be coupled to the substrate 102 is illustrated.

[0106] Stage 2 also illustrates a state after at least one passive device (e.g., 205, 207, 209) is coupled to the second surface of substrate 102 via a plurality of solder interconnects (e.g., 250, 270, 290). The at least one passive device may be coupled to substrate 102 using a solder reflow process.

[0107] The method forms (at 815) an encapsulation over the substrate and the integrated device. An encapsulation layer may be coupled to the substrate and the integrated device. Figure 7 Stage 3 of the embodiment illustrates a state after providing (e.g., forming) an encapsulation layer 208 on the substrate 102. The encapsulation layer 208 may encapsulate the integrated device 202. The encapsulation layer 208 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 208 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 208 may be photoetchable. The encapsulation layer 208 may be a device for encapsulation.

[0108] The method couples (at 820) the plurality of solder interconnects to the second surface of the substrate 102. The plurality of solder interconnects 450 may be coupled to the substrate 102 using a solder reflow process.

[0109] The packages (eg, 200 ) described in this disclosure may be fabricated one at a time, or may be fabricated together (as part of one or more wafers) and subsequently singulated into individual packages.

[0110] Exemplary Electronic Devices

[0111] Fig. 9Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 902, a laptop computer device 904, a fixed location terminal device 906, a wearable device 908, or a motor vehicle 910 may include a device 900 as described herein. The device 900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig. 9 The devices 902, 904, 906, and 908, and the vehicle 910 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 900, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0112] Figure 1-4 , 5A-5D and / or 6-9, one or more of the components, processes, features, and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-4 , 5A-5D and / or 6-9 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-4 , 5A-5D and / or 6-9 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0113] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various parts, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0114] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the discussed features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives thereof refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. It is further noted that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X-XX may mean a value between X and XX (inclusive). The value(s) between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0115] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through holes, pads, pillars, metallization layers, redistribution layers, and / or under bump metallization (UBM) layers / interconnections. In some implementations, interconnection may include conductive materials that can be configured to provide electrical paths for signals (e.g., data signals), grounding, and / or power supplies. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0116] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0117] Further examples are described below to facilitate understanding of the present disclosure.

[0118] Aspect 1: A package includes: a substrate including a first dielectric layer; a second dielectric layer; and a third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a material different from the first dielectric layer and the third dielectric layer. The substrate includes a plurality of interconnects located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The package includes: an integrated device coupled to the substrate.

[0119] Aspect 2: The package of aspect 1, wherein the second dielectric layer is free of glass material, and wherein the first dielectric layer and / or the third dielectric layer comprises glass material.

[0120] Aspect 3: The package of aspects 1 to 2, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

[0121] Aspect 4: The package of aspects 1 to 3, wherein the first dielectric layer comprises a first thickness, and wherein the second dielectric layer comprises a second thickness, the second thickness being less than the first thickness.

[0122] Aspect 5: A package as in Aspect 4, wherein the plurality of interconnections include: a first through-hole interconnection in a first dielectric layer, wherein the first through-hole interconnection includes a first through-hole thickness; and a second through-hole interconnection in a second dielectric layer, wherein the second through-hole interconnection includes a second through-hole thickness, and the second through-hole thickness is less than the first through-hole thickness.

[0123] Aspect 6: The package of aspects 1 to 5, wherein the integrated device is coupled to the first surface of the substrate via a plurality of solder pillar interconnects and a plurality of solder interconnects.

[0124] Aspect 7: The package of aspect 6, further comprising: an integrated passive device coupled to the second surface of the substrate, wherein the integrated passive device is coupled to two adjacent interconnects from the plurality of interconnects.

[0125] Aspect 8: The package of aspect 7, wherein the plurality of solder pillar interconnects include two adjacent solder pillar interconnects, the two adjacent solder pillar interconnects include a minimum solder pillar interconnect pitch, and wherein the two adjacent interconnects include a minimum pitch that is substantially the same as the minimum solder pillar interconnect pitch.

[0126] Aspect 9: A package as in Aspects 7 to 8, wherein the plurality of interconnects include: a first plurality of interconnects arranged as a first column of interconnects extending vertically through the entire substrate; and a second plurality of interconnects arranged as a second column of interconnects extending vertically through the entire substrate, wherein the first column of interconnects is configured to provide a first electrical path between the integrated device and the integrated passive device, and wherein the second column of interconnects is configured to provide a second electrical path between the integrated device and the integrated passive device.

[0127] Aspect 10: The package of aspect 9, wherein the first column of interconnects is configured to be coupled to a power source, and wherein the second column of interconnects is configured to be coupled to ground.

[0128] Aspect 11: The package of aspects 9 to 10, wherein the first column of interconnects is adjacent to the second column of interconnects, and wherein the first column of interconnects and the second column of interconnects have a minimum pitch.

[0129] Aspect 12: The package of aspects 1 to 11, wherein the substrate is a coreless substrate without a core layer.

[0130] Aspect 13: A substrate includes a first dielectric layer; a second dielectric layer; a third dielectric layer; and a plurality of interconnects located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material from the first dielectric layer and the third dielectric layer.

[0131] Aspect 14: The substrate of aspect 13, wherein the second dielectric layer is free of glass material, and wherein the first dielectric layer and / or the third dielectric layer comprises glass material.

[0132] Aspect 15: The substrate of any of aspects 13 to 14, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

[0133] Aspect 16: The substrate of any of aspects 13 to 15, wherein the first dielectric layer comprises a first thickness, and wherein the second dielectric layer comprises a second thickness, the second thickness being less than the first thickness.

[0134] Aspect 17: The substrate of aspects 13 to 16, wherein the plurality of interconnects comprises: a first plurality of interconnects and a second plurality of interconnects, wherein a first column of interconnects is adjacent to a second column of interconnects, and wherein the first column of interconnects and the second column of interconnects have a minimum pitch.

[0135] Aspect 18: The substrate of aspect 17, wherein each pair of interconnects from the first column of interconnects and the second column of interconnects comprises a same minimum pitch.

[0136] Aspect 19: The substrate according to any one of aspects 13 to 18, wherein the substrate is a coreless substrate having no core layer.

[0137] Aspect 20: A substrate as in Aspects 13 to 19, wherein the substrate is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0138] Aspect 21: A method for manufacturing a package. The method provides a substrate, the substrate comprising a first dielectric layer; a second dielectric layer; a third dielectric layer; and a plurality of interconnects located in the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer comprises a different material than the first dielectric layer and the third dielectric layer. The method couples an integrated device to the substrate.

[0139] Aspect 22: The method of aspect 21, wherein the second dielectric layer is free of glass material, and wherein the first dielectric layer and / or the third dielectric layer comprises glass material.

[0140] Aspect 23: The method of aspects 21 to 22, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

[0141] Aspect 24: The method of aspects 21 to 23, wherein the first dielectric layer comprises a first thickness, and wherein the second dielectric layer comprises a second thickness, the second thickness being less than the first thickness.

[0142] Aspect 25: A method as in Aspect 24, wherein the plurality of interconnections include: a first through-hole interconnection in a first dielectric layer, wherein the first through-hole interconnection includes a first through-hole thickness; and a second through-hole interconnection in a second dielectric layer, wherein the second through-hole interconnection includes a second through-hole thickness, and the second through-hole thickness is less than the first through-hole thickness.

[0143] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: A substrate, comprising: a first dielectric layer; a second dielectric layer; and a third dielectric layer; wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and wherein the second dielectric layer comprises a material different from that of the first dielectric layer and the third dielectric layer; and a plurality of interconnects in the first dielectric layer, the second dielectric layer, and the third dielectric layer; and An integrated device is coupled to the substrate.

2. The package according to claim 1, wherein the second dielectric layer is free of glass material, and The first dielectric layer and / or the third dielectric layer comprises glass material. 3 . The package of claim 1 , wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

4. The package according to claim 1, wherein the first dielectric layer comprises a first thickness, and The second dielectric layer comprises a second thickness, and the second thickness is less than the first thickness.

5. The package of claim 4, wherein the plurality of interconnects comprises: a first via interconnect in the first dielectric layer, wherein the first via interconnect comprises a first via thickness; as well as A second via interconnect is located in the second dielectric layer, wherein the second via interconnect comprises a second via thickness, the second via thickness being less than the first via thickness.

6. The package of claim 1, wherein the integrated device is coupled to the first surface of the substrate via a plurality of solder pillar interconnects and a plurality of solder interconnects.

7. The package of claim 6, further comprising: An integrated passive device is coupled to the second surface of the substrate, wherein the integrated passive device is coupled to two adjacent interconnects from the plurality of interconnects.

8. The package according to claim 7, wherein the plurality of solder pillar interconnects include two adjacent solder pillar interconnects, the two adjacent solder pillar interconnects including a minimum solder pillar interconnect pitch, and Wherein the two adjacent interconnects include a minimum pitch that is substantially the same as the minimum solder pillar interconnect pitch.

9. The package of claim 7, wherein the plurality of interconnects comprises: a first plurality of interconnects arranged as a first column of interconnects extending vertically across the substrate; as well as a second plurality of interconnects arranged as a second column of interconnects extending vertically across the entire substrate, wherein the first column of interconnects is configured to provide a first electrical path between the integrated device and the integrated passive device, and Wherein the second column of interconnects is configured to provide a second electrical path between the integrated device and the integrated passive device.

10. The package according to claim 9, Wherein the first column of interconnects is configured to be coupled to a power source, and wherein the second column of interconnects is configured to be coupled to ground.

11. The package according to claim 9, wherein the first column of interconnects is adjacent to the second column of interconnects, and Wherein the first column of interconnects and the second column of interconnects have a minimum pitch.

12. The package of claim 1, wherein the substrate is a coreless substrate having no core layer.

13. A substrate, comprising: a first dielectric layer; a second dielectric layer; a third dielectric layer; wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and wherein the second dielectric layer comprises a material different from the first dielectric layer and the third dielectric layer; as well as A plurality of interconnects are located in the first dielectric layer, the second dielectric layer, and the third dielectric layer.

14. The substrate according to claim 13, wherein the second dielectric layer is free of glass material, and The first dielectric layer and / or the third dielectric layer comprises glass material.

15. The substrate of claim 13, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

16. The substrate according to claim 13, wherein the first dielectric layer comprises a first thickness, and The second dielectric layer comprises a second thickness, and the second thickness is less than the first thickness.

17. The substrate according to claim 13, wherein the plurality of interconnects comprises a first column of interconnects and a second column of interconnects, wherein the first column of interconnects is adjacent to the second column of interconnects, and Wherein the first column of interconnects and the second column of interconnects have a minimum pitch.

18. The substrate of claim 17, wherein each pair of interconnects from the first column of interconnects and the second column of interconnects comprises a same minimum pitch.

19. The substrate of claim 13, wherein the substrate is a coreless substrate having no core layer.

20. The substrate of claim 13, wherein the substrate is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

21. A method for manufacturing a package, comprising: A substrate is provided, the substrate comprising: a first dielectric layer; a second dielectric layer; a third dielectric layer; wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and wherein the second dielectric layer comprises a material different from that of the first dielectric layer and the third dielectric layer; and a plurality of interconnects in the first dielectric layer, the second dielectric layer, and the third dielectric layer; and An integrated device is coupled to the substrate.

22. The method of claim 21, wherein the second dielectric layer is free of glass material, and The first dielectric layer and / or the third dielectric layer comprises glass material.

23. The method of claim 21, wherein the first dielectric layer and / or the third dielectric layer comprises a prepreg.

24. The method of claim 21, wherein the first dielectric layer comprises a first thickness, and The second dielectric layer comprises a second thickness, and the second thickness is less than the first thickness.

25. The method of claim 24, wherein the plurality of interconnections comprises: a first via interconnect in the first dielectric layer, wherein the first via interconnect comprises a first via thickness; as well as A second via interconnect is located in the second dielectric layer, wherein the second via interconnect comprises a second via thickness, the second via thickness being less than the first via thickness.

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