Evaluating performance of droop mitigation schemes

Abstract

The present technology relates to a droop mitigation scheme, and discloses a method of evaluating performance of a droop mitigation scheme, where the method is performed at a circuit, the method comprising: receiving a clock output signal, where the droop mitigation scheme has been used to generate the clock output signal; and analyzing the clock output signal to generate an output, wherein the output provides an indication of performance of the droop mitigation scheme.

Description

[0001] The present technology relates to droop mitigation schemes. In particular, the present technology relates to evaluating the performance of droop mitigation schemes for generating clock output signals.

[0002] Some computer circuits (e.g., central processor units (CPUs) or graphics processor units (GPUs)) may experience performance issues. For example, the CPU may experience voltage sag due to large changes in the current required by the power delivery network (PDN).

[0003] There exists a need for mitigation actions to address such performance issues.

[0004] The present technology is directed to solving or mitigating such performance issues or improving upon known mitigation techniques.

[0005] In a first method, a method of evaluating performance of a droop mitigation scheme is provided, wherein the method is performed at a circuit, the method comprising: receiving a clock output signal, wherein the droop mitigation scheme has been used to generate the clock output signal; and analyzing the clock output signal to generate an output, wherein the output provides an indication of the performance of the droop mitigation scheme.

[0006] The method may further include using a droop mitigation scheme to generate the clock output signal, wherein the droop mitigation scheme may include adjusting a frequency of the clock output signal in response to the droop event.

[0007] Using the droop mitigation scheme to generate a clock output signal may include: receiving a plurality of clock input signals, the plurality of clock input signals including a nominal clock signal and a fallback clock signal; providing the nominal clock signal as the clock output signal during at least a first time period; providing the fallback clock signal or no signal as the clock output signal during at least a second time period. The method may also include: monitoring a voltage for a voltage droop event.

[0008] Using the droop mitigation scheme to generate a clock output signal may also include: initially providing a nominal clock signal as the clock output signal; and in response to detecting a voltage droop event, providing a backed-off clock signal or no signal as the clock output signal.

[0009] The nominal clock signal and the backed-off clock signal may have different frequencies.

[0010] The method may also include evaluating the performance of the droop mitigation scheme based at least on the output, wherein evaluating the performance of the droop mitigation scheme based at least on the output may include comparing the output value of the output to one or more thresholds. Evaluating the performance of the droop mitigation scheme based on the output may include providing a droop performance indication signal or adjusting the droop mitigation scheme in response to determining that the output is below a threshold.

[0011] The circuit may include a clock circuit including a plurality of clock sources and a clock multiplexer, wherein the plurality of clock sources include a nominal clock source and a fallback clock source.

[0012] The circuit may include a droop detector configured to detect droop in the nominal clock signal.

[0013] The circuit may include a droop mitigation state machine configured to provide a clock selection signal to the clock circuit in response to detection of a droop in the nominal clock signal by the droop detector.

[0014] The circuit may include a delay monitor configured to generate an output, wherein the delay monitor may include at least one delay line and an encoder.

[0015] In another method, a circuit for evaluating the performance of a droop mitigation scheme is provided, the circuit comprising a delay monitor configured to: receive a clock output signal, wherein the droop mitigation scheme has been used to generate the clock output signal; analyze the clock output signal to generate an output, wherein the output provides an indication of the performance of the droop mitigation scheme.

[0016] The circuit may also include a clock circuit configured to use a droop mitigation scheme to generate a clock output signal, wherein the droop mitigation scheme may include adjusting the clock output signal in response to detection of a droop event.

[0017] The circuit may also include a sag detector configured to detect a sag in the monitored voltage supply.

[0018] The circuit may also include a droop mitigation state machine configured to provide a clock selection signal to the clock circuit in response to detection of a droop in the monitored voltage supply by the droop detector.

[0019] The circuit may also include a delay monitor configured to generate an output, wherein the delay monitor may include at least one delay line and an encoder.

[0020] In another approach, a system is provided, the system comprising: the above circuit, the circuit being implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are mounted on the board.

[0021] In another method, a chip-containing product is provided, the chip-containing product including the above system, the system and at least one other product component being assembled on another board.

[0022] In another method, a non-transitory computer readable medium is provided for storing computer readable code to manufacture the above circuit.

[0023] Therefore, according to the method and circuit of the present technology, the performance of the droop mitigation scheme can be evaluated, and the method can be implemented in the form of a non-transitory computer-readable medium, which includes a structure of data and commands that can be operated to enable a device to construct a set of electronic logic components, and when the set of electronic logic components is embedded in an electronic device and activated thereon, the electronic device performs the steps of the method of the present technology as described above.

[0024] As will be apparent to those skilled in the art, a hybrid approach may also be taken where hardware logic, firmware and / or software may be used in any combination to implement the present technology.

[0025] Specific implementations of the disclosed technology will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0026] Figure 1 A simplified view of a method for evaluating the performance of a sag mitigation solution is shown;

[0027] Figure 2 A simplified view of a sag mitigation solution is shown;

[0028] Figure 3 A simplified representation of a timing diagram is shown;

[0029] Figure 4 A simplified representation of another timing diagram is shown;

[0030] Figure 5 A simplified representation of one possible apparatus, system or arrangement of electronic circuit components operable to illustrate a method for evaluating the performance of a sag mitigation solution;

[0031] Figure 6 shows a simplified representation of a delay monitor; and

[0032] Figure 7 The system and chip-containing products are shown.

[0033] Now turn to Figure 1 , shows a very simplified view of a method 100 according to a specific implementation of the presently described technology. The method 100 includes the following steps: at a clock circuit, generating a clock output signal, wherein a droop mitigation scheme has been used to generate the clock signal (step 102); at a delay monitor, receiving the clock output signal from the clock circuit (step 104); at the delay monitor, analyzing the clock output signal to generate an output (e.g., having an output value or a score), wherein the output provides an indication of the performance of the droop mitigation scheme (step 106). Optionally, the method 100 also includes: based at least on the output, evaluating the performance of the droop mitigation scheme (step 108).

[0034] Method 100 is a method for evaluating the performance of a droop mitigation scheme. "Droop" refers to the loss or reduction of the supply voltage across a processor / chip caused by fluctuations in the workload. Droop is typically caused by a sudden change in activity for the processor / chip, or when the current load changes at or near the resonant frequency of the power delivery network impedance. The so-called "droop mitigation scheme" means a scheme or method that can be used to mitigate the negative effects of voltage droop, that is, a scheme or method for reducing or eliminating the impact on the functionality of the processor / chip due to the loss of supply voltage across the processor / chip during a droop event.

[0035] At 102, method 100 includes, at a clock circuit, generating a clock output signal. As will be explained in further detail below, generating the clock output signal involves receiving a plurality of clock input signals, and selecting one of the clock input signals or not selecting the clock input signal as the clock output signal. In this example, the clock output signal is generated by the clock circuit according to a droop mitigation scheme. The droop mitigation scheme mitigates the negative effects of voltage droop. In this sense, the output of the clock circuit is a mitigated clock signal.

[0036] In this example, a droop mitigation scheme is used to generate a clock output signal. The droop mitigation scheme relies on selecting an initial clock signal with a specific frequency (e.g., 3.5 GHz) and voltage (e.g., 0.95 V) as the clock output signal, and adjusting the frequency in response to the detection of a droop event. Figure 2 An illustrative example sag mitigation scheme is explained in further detail.

[0037] We now turn briefly to Figure 2, which shows an example droop mitigation scheme 200. The example droop mitigation scheme 200 includes the following steps: receiving a plurality of clock input signals at a clock multiplexer (step 202); initially selecting, by the clock multiplexer, a nominal clock signal as a clock output signal (step 204); receiving, at the clock multiplexer, a signal indicating that a droop event has been detected (step 206); and in response to receiving the signal indicating that a droop event has been detected, selecting, by the clock multiplexer, a fallback clock signal as the clock output signal (step 208). Optionally, the droop mitigation scheme 200 also includes: receiving, at the clock multiplexer, a signal indicating that a droop event has ended or is no longer detected (step 210); and in response to receiving the signal indicating that a droop event has ended or is no longer detected, selecting, by the clock multiplexer, the nominal clock signal as the clock output signal (step 212).

[0038] At 202, a plurality of clock input signals are received at a clock multiplexer. The plurality of clock input signals include a nominal clock signal and a fallback clock signal. The nominal clock signal and the fallback clock signal have different frequencies. Because the effects of droop are more severe at higher clock frequencies, the fallback clock signal to be selected by the clock multiplexer during a droop event typically has a lower frequency than the nominal clock signal. In an example, for example, the nominal clock signal has a frequency of 3.5 GHz and the fallback clock signal has a frequency of 3.2 GHz.

[0039] At 204, the nominal clock signal is initially selected by the clock multiplexer for use as the clock output signal. In other words, by default, the clock output signal is the nominal clock signal. As explained in further detail below, the clock multiplexer includes a clock select input that receives a signal from the droop mitigation state machine.

[0040] During the method 200, a sag detector is used to monitor the voltage of the subsystem for a voltage sag event. The occurrence of a voltage sag event may be obtained, for example, via an interface at the sag detector.

[0041] Upon detection of a droop event by the droop detector, a trigger signal is output from the droop detector, and the trigger signal is input to the droop mitigation state machine.

[0042] At 206, the clock multiplexer receives a signal indicating that a droop event has been detected and mitigation action should be taken. The signal indicating that a droop event has been detected and mitigation action should be taken is received at a clock select input of the clock multiplexer from a droop mitigation state machine, which in turn receives a trigger signal output from a droop detector.

[0043] At 208, in response to receiving a signal indicating that a droop event has been detected and mitigation action should be taken, the clock multiplexer selects the fallback clock signal as the clock output signal. In other words, the output from the droop mitigation state machine provided to the clock select input of the clock multiplexer causes the clock multiplexer to switch its output from the nominal clock signal (having a first frequency) to the fallback clock signal (having a second frequency). As will be appreciated, when the output of the clock multiplexer switches between the nominal clock signal and the fallback clock signal, there will be at least some switching time. During this switching time, no output signal clock is provided by the clock output signal.

[0044] At 210, the clock multiplexer receives a signal indicating that the droop event has ended / is no longer detected and no mitigation action should be taken. The signal output by the droop mitigation state machine, provided as a clock select input at the clock multiplexer, can change when the droop detector no longer detects droop, that is, when the trigger output from the droop detector switches from high to low. There can be a programmable delay between when the droop mitigation state machine no longer receives a trigger input from the droop detector and when the output of the droop mitigation state machine switches. For example, the delay can be 6 clock cycles of the back-off clock signal, although this is only an example and the delay can be any number of clock cycles.

[0045] At 212, in response to receiving a signal indicating that the droop event has ended or is no longer detected, the clock multiplexer selects the nominal clock signal as the clock output signal. Again, as will be appreciated, there will be at least some switching time during which the output of the clock multiplexer switches between the fallback clock signal and the nominal clock signal. During this switching time, no output signal clock is provided by the clock output signal.

[0046] Because the effects of droop are more severe at higher clock frequencies, the example droop mitigation scheme 200 reduces droop by using a reduced clock frequency for some or all durations of droop events.

[0047] Figure 3 is a timing diagram illustrating the effects of an example sag mitigation scheme 200 during a sag event.

[0048] Initially, in region A, the voltage of the monitored subsystem is above the threshold set for the droop detector, and thus no droop event is detected. Initially, in region A, the output of the droop detector (TRIG_DROOP) is low, and the nominal clock signal (NOMclock) is used as the clock output signal (clkout).

[0049] At time t1, i.e., at the beginning of region B, the voltage drops below the threshold set for the droop detector. Therefore, a droop event is detected in region B. Upon detection of the droop event, the output of the droop detector (TRIG_DROOP) switches from low to high. As a result of the high output of the droop detector, the droop mitigation state machine causes the clock multiplexer (after a delay) to select the fallback clock signal (FBclock) as the clock output signal (clkout).

[0050] At time t2, i.e., at the beginning of region C, the voltage rises above the threshold set by the droop detector. Therefore, no droop events are detected in region C. At the end of the detection of the droop event, the output of the droop detector (TRIG_DROOP) switches from high to low. As a result of the low output of the droop detector, the droop mitigation state machine causes the clock multiplexer (after a delay) to select the nominal clock signal (NOMclock) as the clock output signal (clkout). In this example, the droop mitigation state machine uses a programmable delay between when the droop mitigation state machine no longer receives a high trigger input from the droop detector and when the output of the droop mitigation state machine switches from high to low. In this example, the delay is 6 clock cycles of the fallback clock signal, although this is only an example and a delay that can be any number of clock cycles can be used.

[0051] As will be appreciated, other droop mitigation schemes are possible. For example, another droop mitigation scheme is "stop clock", where the clock output signal is stopped in response to detection of a voltage droop event (rather than switching to a fallback clock). Yet another droop mitigation scheme is "ignore droop", where no action is taken in response to detection of a voltage droop event (i.e., the nominal clock is used throughout the duration of the droop event). Method 100 provides a way to properly characterize different droop mitigation schemes to learn which scheme is most effective in mitigating droop for a particular processor / chip design.

[0052] Back to Figure 1 At 104 , method 100 includes receiving, at a delay monitor, a mitigated clock output signal from a clock circuit (ie, an output of a clock multiplexer).

[0053] At 106, the method 100 includes, at a delay monitor, analyzing the clock output signal to generate an output. The delay monitor is configured to generate an output (e.g., an output value or a fraction) that indicates the performance of the droop mitigation scheme. The output corresponds to a count of the number of fine gate stages passed through the delay line during a predetermined number of clock cycles, which can be, for example, one clock cycle, although this is only an example and the output can correspond to a count of the number of fine gate stages passed through the delay line during any predetermined number of clock cycles. The output indicates a voltage of the subsystem.

[0054] At 108, method 100 includes evaluating performance of the droop mitigation scheme based at least on the output. The performance of the droop mitigation scheme can be evaluated by monitoring and recording changes in the output over a period of time (particularly before, during, and after a droop event), and comparing the output to one or more thresholds.

[0055] The evaluation circuit can be used to save the output from the delay monitor in a memory. For example, the output can be saved every n clock cycles of the nominal clock, where n=1, 2, 3, etc. As an alternative, the output is statistically analyzed in terms of the minimum and maximum values ​​of the output fraction within the time period. Monitoring the changes in the output within the time period (particularly before, during, and after the droop event) provides an indication of how well the droop mitigation scheme for generating the mitigated clock signal has been performed. The evaluation circuit can be used to compare the output from the delay monitor with multiple thresholds.

[0056] Figure 4 An example of the change in output over a time period is shown. Initially, the output is above the threshold AVAL, and therefore the output is in the "safe zone". When the droop mitigation scheme works effectively, the output remains above the first threshold and in the safe zone before, during, and after the droop event.

[0057] exist Figure 4 In an example of , the output drops below a threshold AVAL during time T. The output dropping below the threshold indicates that the droop mitigation scheme is not working effectively and the circuit is being affected by droop. In response to the output dropping below the threshold, the evaluation circuit can provide a droop performance indication signal to indicate that the droop mitigation scheme should be adjusted and / or replaced with an alternative droop mitigation scheme. Parameters of the droop mitigation scheme can be automatically adjusted. For example, in response to determining that the output has dropped below the threshold AVAL, the frequency of the back-off clock signal can be automatically reduced by the evaluation circuit.

[0058] Now turn to Figure 5, shows a simplified representation of one possible device, system or arrangement of electronic circuit components forming a circuit 500 capable of operating according to a specific implementation of the presently described technology. In particular, the circuit 500 can be used to perform the method 100 and the method 200.

[0059] Circuit 500 includes clock circuit 502, droop detector 504, droop mitigation state machine 506, delay monitor 508, and evaluation circuit 520. Circuit 500 may form part of a processing unit such as a CPU or GPU. Circuit 500 may be used to provide a clock signal to other components of a CPU or GPU.

[0060] The clock circuit 502 includes a plurality of clock sources 510 / 512 and a clock multiplexer 514. Each clock source 510 / 512 generates a clock signal 510a / 512a having a specific frequency and voltage. The clock sources 510 / 512 include a nominal clock source 510 and a fallback clock source 512. The nominal clock signal 510a (NOMclock) and the fallback clock signal 512a (FBclock) have different frequencies, as described above.

[0061] Because the effects of droop are more severe at higher clock frequencies, the back-off clock signal 512a to be selected by the clock multiplexer 514 during a droop event typically has a lower frequency than the nominal clock signal 510a. In an example, the nominal clock signal has a frequency of 3.5 GHz and the back-off clock signal has a frequency of 3.2 GHz.

[0062] In use, the clock multiplexer 514 receives each clock signal 510a / 512a as an input and outputs a clock output signal 514a (clkout). The selection of the clock output signal 514a is controlled by a clock select input 516. The clock select input 516 is configured to receive a clock select signal 516a from the droop mitigation state machine. When the signal at the clock select input 516 (i.e., the output from the droop mitigation state machine) is 2'b01, the clock output signal 514a (clkout) will be the nominal clock signal 510a (NOMclock). When the signal at the clock select input 516 (i.e., the output from the droop mitigation state machine) is 0'b10, the clock output signal 514a (clkout) will be the fallback clock signal 512a (FBclock). When the signal at clock select input 516 (ie, output from the droop mitigation state machine) is 2'b00, no clock is selected for clock output signal 514a (clkout), ie, the clkout signal is stopped, so that propagation of the clock signal from clock circuit 502 is stopped.

[0063] The default output 506a of the droop mitigation state machine 506 is 2'b01, and thus by default, the clock output signal 514a (clkout) will be the nominal clock signal 510a (NOMclock). Upon receiving an indication from the droop detector 504 that a droop event has been detected, the output of the droop mitigation state machine 506 switches to 2'b10, and the clock output signal 514a (clkout) will be the fallback clock signal 512a (FBclock). When switching between the nominal clock signal 510a and the fallback clock signal 512a, no output signal is provided from the clock circuit.

[0064] A programmable delay may be used by the droop mitigation state machine 506 between when the droop mitigation state machine no longer receives a high trigger input from the droop detector and when the output of the droop mitigation state machine switches from high to low. For example, the delay may be 6 clock cycles of the back-off clock signal.

[0065] The droop detector 504 is configured to monitor (i.e., continuously monitor) the monitored voltage (e.g., of a subsystem) for voltage droop events. The droop detector 504 compares its output (e.g., a score) with one or more thresholds. When the score of the monitored voltage drops below the threshold, the droop detector 504 identifies a droop event. Upon detection of a droop event by the droop detector 504, a trigger signal (TRIG_DROOP) is output from the droop detector 504 and is input to the droop mitigation state machine 506. TRIG_DROOP is synchronized with the rising edge of the nominal clock signal 510a.

[0066] Droop mitigation state machine 506 is configured to control mitigation actions taken by clock circuit 502 when droop detector 504 detects a droop event. Droop mitigation state machine 506 is configured to receive a trigger signal (TRIG_DROOP) from the output of droop detector 504 and provide a clock select input 516 to clock multiplexer 514.

[0067] The output of the droop mitigation state machine 506 can be 2'b01, 2'b10, or 2'b00. When the output from the droop mitigation state machine 506 is 2'b01, the nominal clock signal 510a is selected as the clock output signal 514a. When the output from the droop mitigation state machine 506 is 2'b10, the fallback clock signal 512a is selected as the clock output signal 514a. When the output from the droop mitigation state machine 506 is 2'b00, no clock is selected for the clock output signal 514a, so that the clkout signal is stopped and the propagation of the clock signal from the clock circuit 502 is stopped. The default output 506a of the droop mitigation state machine 506 is 2'b01, and therefore by default, the clock output signal 514a (clkout) will be the nominal clock signal 510a (NOMclock).

[0068] In the above about Figure 2 In the example droop mitigation scheme 200 outlined, the output of the droop mitigation state machine 506 switches from 2'b01 to 2'b10 when a droop event is detected (i.e., when TRIG_DROOP switches from low to high), but other schemes are possible. For example, in the "stop clock" droop mitigation scheme, the output of the droop mitigation state machine 506 switches from 2'b01 to 2'b00 when a droop event is detected. In the "ignore droop" droop mitigation scheme, the output of the droop mitigation state machine 506 does not change from 2'b01 when a droop event is detected.

[0069] The droop mitigation state machine 506 may provide a programmable switching delay. For example, when TRIG_DROOP switches from high to low, the output of the droop mitigation state machine 506 may not switch immediately from, for example, 2'b01 to 2'b10. Instead, the droop mitigation state machine 506 may switch its output after a countdown of, for example, 6 clock cycles of the back-off clock signal. If TRIG_DROOP switches back to high during the delay, the countdown may be reset.

[0070] The delay monitor 508 is configured to receive the mitigated clock output signal (i.e., the output 514a of the clock multiplexer 514) from the clock circuit 502, and analyze the clock output signal 514a to generate an output (dm_min_vio_v). The output indicates the performance of the droop mitigation scheme used to generate the clock output signal 514a. The output corresponds to a count of the number of fine gate stages passed through in the delay line during a predetermined number of clock cycles.

[0071] Figure 6An example delay monitor 508 is shown in detail in . The delay monitor 508 includes a coarse delay line 602, a fine delay line 604, and an encoder 606. The delay monitor optionally includes a fractional offset 608 between the coarse delay and the fine delay.

[0072] The output is provided by the output of the encoder. The output corresponds to a count of the number of fine gate stages passed through the fine delay line 604 during a predetermined number of clock cycles. The output can be measured at each output clock cycle of the clock circuit 502 and averaged over a predetermined number of clock cycles for analysis.

[0073] Evaluation circuit 520 includes memory 522 and processing circuit 524. Memory 522 can be used to store output from delay monitor 508. For example, memory 522 can store the time evolution of output value or score (or, for example, average score per 1000 clock cycles). In another example, memory 522 can store the maximum and minimum values ​​of the output in a time period. Memory 522 can also be used to store one or more thresholds, and the output is compared with the one or more thresholds to evaluate the performance of the droop mitigation scheme. For example, memory 522 can be used to store threshold AVAL. Processing circuit 524 can be used to provide a droop performance indication signal to indicate that the droop mitigation scheme should be adjusted and / or replaced with an alternative droop mitigation scheme, and can be configured to adjust or reduce the frequency of the fallback clock signal 512a in response to determining that the output from delay monitor 508 has dropped below threshold AVAL.

[0074] As will be appreciated by those skilled in the art, the present technology may be embodied as a method, circuit or computer readable medium including data and commands for the construction of a circuit. Thus, the present technology may take the form of a complete hardware implementation, a complete software implementation, or an implementation that combines software and hardware. Where the word "component" is used, it will be understood by those skilled in the art to refer to any portion of any of the above implementations.

[0075] like Figure 7As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, and the circuit described above is implemented on one chip or distributed on two or more of these chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer can be provided as a semiconductor package, which includes a semiconductor device that implements the circuit described above, and a protective housing (e.g., made of metal, plastic, glass, or ceramic) for accommodating a semiconductor device that implements the circuit described above, and a connector (such as a pad, solder ball, or pin) for connecting the semiconductor device to the external environment. In the case of providing more than one chip 400, these chips can be provided as separate integrated circuits (provided as separate packages), or can be packaged into a multi-chip semiconductor package by a semiconductor provider (e.g., using an interposer, or by using three-dimensional integration to provide a multi-layer chip product including two or more vertically stacked integrated circuit layers).

[0076] In some examples, a collection of chiplets (i.e., small modular chips with specific functionality) may themselves be referred to as a chip. A chiplet may be packaged individually in a semiconductor package and / or packaged with other chiplets into a multi-chiplet semiconductor package (e.g., using an interposer, or by using three-dimensional integration to provide a multi-layer chiplet product including two or more vertically stacked integrated circuit layers).

[0077] One or more packaged chips 400 are assembled on board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, for example, plastic, glass, ceramic, or a flexible substrate material such as paper, plastic, or textile material. At least one system component 404 includes one or more external components that are not part of one or more packaged chips 400. For example, at least one system component 404 may include, for example, any one or more of the following: another packaged chip (e.g., provided by a different manufacturer or produced at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0078] A chip-containing product 416 is manufactured, which includes a system 406 (including board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product component 412 includes one or more additional components that are not part of system 406. As a non-exhaustive list of examples, one or more product components 412 may include user input / output devices such as keyboards, touch screens, microphones, speakers, display screens, tactile devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical movements; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on additional board 414.

[0079] Plate 402 or additional plates 414 may be disposed on or within a device housing or other structural support (eg, a frame or blade) to provide a product that may be manipulated by a user and / or is intended for operational use by a person or company.

[0080] System 406 or chip-containing product 416 may be at least one of an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automated control system. For example, as a non-exhaustive list of examples, the chip-containing product may be any one of the following: telecommunications equipment, mobile phones, tablet computers, laptop computers, computers, servers (e.g., rack servers or blade servers), infrastructure equipment, networking equipment, vehicles or other automotive products, industrial machines, consumer devices, smart cards, credit cards, smart glasses, avionics equipment, robotic equipment, cameras, televisions, smart TVs, DVD players, set-top boxes, wearable devices, home appliances, smart meters, medical devices, heating / lighting control equipment, sensors, and / or control systems for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0081] As will be appreciated by those skilled in the art, the present technology may be embodied as a method, circuit or computer readable medium including data and commands for the construction of a circuit. Thus, the present technology may take the form of a complete hardware implementation, a complete software implementation, or an implementation that combines software and hardware. Where the word "component" is used, it will be understood by those skilled in the art to refer to any portion of any of the above implementations.

[0082] The concepts described herein may be embodied in computer readable code for manufacturing devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying the concepts. The computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0083] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions of concepts embodying concepts or other behavioral representations of concepts using system-level modeling languages ​​such as SystemC and SystemVerilog that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0084] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate definitions for manufacturing devices embodying the present technology. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer readable code to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts prior to manufacturing the integrated circuit, or the FPGA may be deployed directly in a product.

[0085] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to make a device embodying the present technology. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to make a device and computer readable code defining instructions to be executed by the defined device once manufactured.

[0086] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless transmission of the code over a network) or non-transitory computer readable medium such as a semiconductor, a magnetic disk, or an optical disk. An integrated circuit fabricated using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0087] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0088] In the present application, a feature list beginning with the phrase "at least one of..." means that any one or more of those features may be provided individually or in combination. For example, "at least one of [A], [B], and [C]" covers any of the following options: only A (without B or C), only B (without A or C), only C (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0089] Although illustrative embodiments of the present technology have been described in detail herein with reference to the accompanying drawings, it should be understood that the present technology is not limited to those precise embodiments and that various changes and modifications may be implemented therein by those skilled in the art without departing from the scope of the present technology as defined by the appended claims.

Claims

1. A method of evaluating the performance of a droop mitigation scheme, wherein the method is performed at a circuit, the method comprising: receiving a clock output signal, wherein the droop mitigation scheme has been used to generate the clock output signal; as well as The clock output signal is analyzed to generate an output, wherein the output provides an indication of the performance of the droop mitigation scheme.

2. The method according to claim 1, further comprising: using the droop mitigation scheme to generate the clock output signal, The droop mitigation scheme includes adjusting the frequency of the clock output signal in response to a droop event.

3. The method according to claim 2, wherein: Using a droop mitigation scheme to generate the clock output signal includes: receiving a plurality of clock input signals, the plurality of clock input signals comprising a nominal clock signal and a fallback clock signal; providing the nominal clock signal as the clock output signal during at least a first time period; and The backed-off clock signal or no signal is provided as the clock output signal during at least a second time period.

4. The method according to claim 3, further comprising: Monitor the voltage for voltage sag events.

5. The method according to claim 4, wherein: Using the droop mitigation scheme to generate a clock output signal also includes: initially providing the nominal clock signal as the clock output signal; In response to detecting a voltage sag event, the backed-off clock signal or no signal is provided as the clock output signal.

6. The method according to any one of claims 3 to 5, wherein: The nominal clock signal and the backed-off clock signal have different frequencies.

7. The method according to any preceding claim, further comprising: The performance of the sag mitigation scheme is evaluated based at least on the output.

8. The method according to claim 7, wherein: Evaluating the performance of the sag mitigation scheme based at least on the output includes: The output value of the output is compared to one or more threshold values.

9. The method according to claim 8, wherein: Evaluating the performance of the sag mitigation solution based on the output includes: In response to determining that the output is below a threshold, a droop performance indication signal is provided.

10. The method according to claim 8, wherein: Evaluating the performance of the sag mitigation solution based on the output includes: In response to determining that the output is below a threshold, the droop mitigation scheme is adjusted.

11. A method according to any preceding claim, wherein: The circuit includes a clock circuit including a plurality of clock sources and a clock multiplexer, wherein the plurality of clock sources include a nominal clock source and a fallback clock source.

12. The method according to claim 11, wherein: The circuit includes a droop detector configured to detect droop in the nominal clock signal.

13. The method according to claim 12, wherein: The circuit includes a droop mitigation state machine configured to provide a clock selection signal to the clock circuit in response to detection of droop in the nominal clock signal by the droop detector.

14. A method according to any preceding claim, wherein: The circuit includes a delay monitor configured to generate the output, the delay monitor including at least one delay line and an encoder.

15. A circuit for evaluating performance of a droop mitigation scheme, the circuit comprising a delay monitor configured to: receiving a clock output signal, wherein the droop mitigation scheme has been used to generate the clock output signal; The clock output signal is analyzed to generate an output, wherein the output provides an indication of the performance of the droop mitigation scheme.

16. The circuit according to claim 15, further comprising a clock circuit, wherein the clock circuit is configured to: using the droop mitigation scheme to generate the clock output signal, Wherein the droop mitigation scheme includes adjusting the clock output signal in response to detection of a droop event.

17. The circuit of claim 16, further comprising a sag detector configured to detect a sag in the monitored voltage supply.

18. The circuit of claim 17, further comprising a droop mitigation state machine configured to provide a clock selection signal to the clock circuit in response to detection of a droop in the monitored voltage supply by the droop detector.

19. The circuit of any one of claims 15 to 18, further comprising a delay monitor configured to generate the output, the delay monitor comprising at least one delay line and an encoder.

20. A system, comprising: The circuit according to any one of claims 15 to 19, wherein the circuit is implemented in at least one packaged chip; at least one system component; and plate, The at least one packaged chip and the at least one system component are mounted on the board.

21. A chip-containing product, comprising the system according to claim 20, the system and at least one other product component being assembled on a further board.

22. A non-transitory computer readable medium for storing computer readable code to manufacture the circuit according to any one of claims 15 to 19.

Images