Bus extension device and data processing method

Abstract

The application relates to the field of electronic information technology, and particularly discloses a bus expansion device and a data processing method. The bus expansion device comprises a bus expansion module configured to be connected to a target bus. The bus expansion module is configured to interact with the target bus to have a first-width data signal, and generate a first target data signal based on the first-width data signal or generate the first-width data signal based on a second target data signal obtained. The data width of the first target data signal is a first target width, and the data width of the second target data signal is a second target width. The first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width. Based on the bus expansion module, the width of the target bus can be expanded, the module of the data bus with a data width greater than the first width can be controlled, the problem of application limitation is improved, and the technical effect of flexible application is achieved.

Description

Technical Field

[0001] This application relates to the field of electronic information technology, specifically to a bus expansion device and a data processing method. Background Technology

[0002] A Low Pin Count (LPC) bus is a parallel bus with a low pin count, consisting of 13 signal lines: 7 mandatory signals and 6 optional signals. LPC communication requires only 7 mandatory signals, making its implementation quite flexible. However, due to the data width limitations of LPC buses or similar buses, it can only perform operations on devices with a corresponding data width, thus limiting its applications. Summary of the Invention

[0003] This application provides a bus expansion device and a data processing method to at least solve the problem of bus application limitations caused by data width in related technologies.

[0004] According to a first aspect, this application provides a bus expansion device configured in a server; the bus expansion device includes:

[0005] A bus expansion module is configured to connect to a target bus; the bus expansion module is configured to interact with the target bus to generate a data signal with a first width, and generate a first target data signal based on the data signal with the first width, or generate the data signal with the first width based on an acquired second target data signal;

[0006] Wherein, the data width of the first target data signal is the first target width, and the data width of the second target data signal is the second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width.

[0007] According to a second aspect, this application provides a data processing method, executed based on the bus expansion device provided in the first aspect, the data processing method comprising:

[0008] Acquire the data signal with a first width transmitted by the target bus;

[0009] A first target data signal is generated based on the data signal having a first width, wherein the data width of the first target data signal is the first target width, and the first target width is equal to or greater than the first width;

[0010] or,

[0011] Acquire the second target data signal;

[0012] A data signal with a first width is generated based on the second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is greater than or equal to the first width.

[0013] Through this application, a bus expansion device is provided with a bus expansion module connected to a target bus. The bus expansion module interacts with the target bus with a data signal having a first width, and can generate a first target data signal based on the data signal having the first width. The data width of the first target data signal is greater than or equal to the first width. Alternatively, it can generate a data signal with the first width based on an acquired second target data signal. The data width of the second target data signal is greater than or equal to the first width. Thus, based on the bus expansion module, the width of the target bus can be expanded, enabling control of modules on data buses with a data width greater than the first width. This improves the problem of application limitations and achieves the technical effect of flexible application. Attached Figure Description

[0014] Figure 1 This is an LPC interface scheme in related technologies;

[0015] Figure 2 This is a schematic diagram of the application architecture of a bus expansion device according to an embodiment of this application. Figure 1 ;

[0016] Figure 3 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 1 ;

[0017] Figure 4 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 2 ;

[0018] Figure 5 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 3 ;

[0019] Figure 6 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 4 ;

[0020] Figure 7 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 5 ;

[0021] Figure 8 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 6 ;

[0022] Figure 9This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 7 ;

[0023] Figure 10 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 8 ;

[0024] Figure 11 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 9 ;

[0025] Figure 12 This is a schematic diagram of the state transition process of the algorithm state machine of a bus expansion device according to an embodiment of this application;

[0026] Figure 13 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 10 ;

[0027] Figure 14 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 10 one;

[0028] Figure 15 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 10 two;

[0029] Figure 16 This is a schematic diagram of the application architecture of a bus expansion device according to an embodiment of this application. Figure 2 ;

[0030] Figure 17 This is a flowchart illustrating a data processing method according to an embodiment of this application. Figure 1 ;

[0031] Figure 18 This is a flowchart illustrating a data processing method according to an embodiment of this application. Figure 2 ;

[0032] Figure 19 This is a flowchart illustrating a data processing method according to an embodiment of this application. Figure 3 . Detailed Implementation

[0033] The core improvement of this application is to provide a bus expansion device and a data processing method for expanding the data width of the target bus data signal, thereby enabling control of modules on data buses whose data signal width is greater than the data width of the target bus, thus improving application flexibility.

[0034] In some implementations, clock multiplication can be used to control modules with high-speed clock signals via a low-speed target bus, thereby improving data processing speed.

[0035] In some implementations, a password control module can also be set up to enhance the security of data communication.

[0036] In some implementations, the aforementioned bus expansion device can also be set up based on programmable logic devices, which allows for flexible deployment and convenient implementation.

[0037] The technical solutions provided by the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0038] Figure 1 This is an LPC interface scheme in related technologies. For example... Figure 1 As shown, the LPC bus is located below the Southbridge chip (PCH) of the server / computer (CPU). Modules with LPC interfaces, such as TPM (Trusted Platform Module) / TCM (Trusted Cryptography Module), can be inserted into the LPC slot on the motherboard to communicate with the Southbridge chip (PCH). Because the LPC bus only has a 4-bit data bus, the server / computer can only control LPC devices with a 4-bit data width (such as TPM / TCM) through the LPC bus, and cannot control IO (Input / Output) devices / modules with a data width exceeding 4 bits, such as 16-bit, 32-bit, and 64-bit IO devices / modules, thus limiting its application.

[0039] To address this, this application proposes a bus expansion device and a data processing method, which overcomes application limitations by expanding the data width. The above example only uses the LPC bus to illustrate application limitations caused by data width; application limitations on other buses due to data width can also be improved using the technical solutions provided in this application, and are not limited thereto.

[0040] For example, Figure 2 This is a schematic diagram of the application architecture of a bus expansion device according to an embodiment of this application. Figure 1 .like Figure 2As shown, the bus expansion device 100 provided in this embodiment is configured on server 10. Exemplarily, the bus expansion device 100 can be connected between the target bus 01 and server 10, or the bus expansion device 100 can be disposed within server 10 (e.g., Figure 2 The bus expansion device 100 is connected to the host computer 20 via a target bus 01 at one end and to the cryptographic module 30 at the other end. The host computer 20 may include upper-layer application software operated by the user. The user can set keys, registers, and data to be processed based on operations on the host computer 20, and send these to the bus expansion device 100 via the target bus 01. The host computer 20 can also receive data from the bus expansion device 100 after processing. The bus expansion device 100 expands the data transmitted from the target bus 01 to the width corresponding to that of the cryptographic module 30 and transmits it to the cryptographic module 30. The cryptographic module 30 processes the received data and returns the processed data to the bus expansion device 100. The bus expansion device 100 performs data conversion on the received processed data, outputs data with a width that meets the transmission width of the target bus 01, and returns the processed data to the host computer 20 via the target bus 01.

[0041] For example, Figure 3 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 1 .like Figure 3 As shown, the bus expansion device 100 provided in this application embodiment may include: a bus expansion module 110, configured to connect to a target bus 01; the bus expansion module 110 is configured to interact with the target bus 01 to generate a data signal with a first width, and generate a first target data signal based on the data signal with the first width, or generate a data signal with the first width based on an acquired second target data signal; wherein, the data width of the first target data signal is the first target width, and the data width of the second target data signal is the second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width.

[0042] The target bus 01 can be a bidirectional data / address bus with a certain data width, which can be represented as a first width. It is understood that this first width is relatively small. By expanding the data width of the data signals transmitted on the target bus 01 based on the bus expansion device 100, control of modules / devices with a larger data width can be achieved. For example, the target bus 01 can be an LPC bus or other buses with a low data width, and is not limited here.

[0043] The bus expansion module 110 is connected to the target bus 01 and can receive or output a data signal with a first width transmitted from the target bus 01. Further, the bus expansion module 110 can expand the received data signal with the first width to generate a first target data signal with a first target width, thereby controlling a module / device with the first target width. Alternatively, the bus expansion module 110 can acquire a second target data signal with a second target width transmitted from a module / device with a second target width, convert the second target data signal into at least one data signal with the first width, and transmit it through the target bus 01, thereby controlling a module / device with the second target width through the target bus 01.

[0044] The first target width and the second target width may be the same or different, and are not limited here. When the second target width and the first target width are the same, the module / device controlled based on the target bus may be the same module / device, and are not limited here.

[0045] In some implementations, when both the first target width and the second target width are equal to the first width, control of the module / device with the first width can be achieved based on the target bus, so that the setting of the bus expansion device 100 will not affect the control of the module / device with the first width.

[0046] In some implementations, when the first target width is greater than the first width and the second target width is greater than the first width, control of modules / devices with larger data widths can be achieved based on the target bus and the bus expansion device 100, thereby breaking the application limitations of the target bus.

[0047] The bus expansion device 100 provided in this application embodiment includes a bus expansion module 110. The bus expansion module 110 can receive a data signal with a first width transmitted by a target bus 01 and generate a first target data signal with a first target width; or acquire a second target data signal and generate a data signal with a first width, and transmit it via the target bus 01; wherein the first target width is greater than or equal to the first width, and the second target width is greater than or equal to the first width, thereby realizing the expansion of the data width transmitted by the target bus 01, breaking the application limitations of the target bus 01 caused by the data width limitation, and improving the application flexibility of the target bus 01.

[0048] In some implementations, Figure 4 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 2 The diagram illustrates a specific structure of the bus expansion module 110. For example... Figure 4As shown in the embodiment of this application, in the bus expansion device 100, the bus expansion module 110 may include a control module 111, a counting module 112, and a first data buffer 113. The counting module 112 and the first data buffer 113 are respectively connected to the control module 111. The counting module 112 is configured to count the data cycles of the target bus and transmit the count value to the control module 111. The first data buffer 113 is configured to store the data signal of at least one data cycle transmitted by the target bus. The control module 111 is configured to generate a first target data signal based on the data signal of at least one data cycle stored in the first data buffer 113 when the count value reaches the target count value, and output a periodic valid signal of the first target data signal.

[0049] The input of the counting module 112 is connected to the bus cycle signal LFRAME of the target bus 01, and the output of the counting module 112 is connected to the control module 111. The bus cycle signal LFRAME is the start signal of the data cycle of the target bus 01, and the bus cycle signal LFRAME is active low. Based on this, when the bus cycle signal LFRAME switches to a low level, it indicates the start of a data cycle; the period when the bus cycle signal LFRAME is low corresponds to one data cycle. The counting module 112 can count the data cycles of the target bus, and in each data cycle, a valid data signal LAD[3..0] is transmitted on the target bus.

[0050] For example, the count value can be n (n = 1, 2, ..., N), that is, n is a positive integer. The target count value can be set by the user based on the data width requirements of the target data signal, that is, based on the data expansion requirements, and its specific value is not limited here. When the count value reaches the target count value, the control module 111 outputs the periodic valid signal of the first target data signal, that is, generates the expanded bus periodic signal. Figure 4 The extended bus cycle signal is shown in FRAME.

[0051] For example, when the first width is 4 bits and the first target width is 16 bits, the target count value is 16 bits / 4 bits, that is, the target count value is 4. Based on this, when the count value accumulates from 1, the target bus transmits 4 data signals LAD[3..0] with the first width, that is, after satisfying 4×4 bits = 16 bits, the control module 111 generates an extended bus cycle signal FRAME. For example, the extended bus cycle signal FRAME is active low.

[0052] The first data buffer 113 is used to temporarily store data signals corresponding to the number of target count values ​​transmitted on the target bus. For example, the first data buffer 113 may be a volatile storage unit, such as random access memory (RAM) or other components with storage functions, which are not limited here.

[0053] The capacity of the first data buffer 113 can be set according to the needs of data width expansion. The capacity of the first data buffer 113 can be changed in different application scenarios. For example, the capacity of the first data buffer 113 can be set to an integer multiple of the first width to store the target bus transmitted data signal LAD[3..0]. For example, if the first width is 4 bits, the capacity of the first data buffer 113 can be 4N bits, where N represents the target count value.

[0054] The control module 111 can receive the count value from the counting module 112, and output the extended bus cycle signal FRAME based on the count value reaching the target count value; and output the first target data signal DATA[4n-1..0] (n=1,2,…,N) after data splicing according to the data stored in the first data buffer 113. For example, when the first target width is 16 bits, the target count value N=4, and the first target data signal can be DATA[15..0].

[0055] In the bus expansion device 100 provided in this application embodiment, the bus expansion module 110 includes a control module 111, a counting module 112, and a first data buffer 113. The counting module 112 can count the data cycles of the target bus and transmit the count value to the control module 111. The first data buffer 113 can store the data signal of at least one data cycle transmitted by the target bus. The control module 111 can generate a first target data signal based on the target count value reaching the target count value, based on the data signal of at least one data cycle stored in the first data buffer 113, and output the periodic valid signal of the first target data signal, thereby realizing data width expansion.

[0056] In some implementations, Figure 5 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 3 The diagram illustrates a specific structure of a counter. For example... Figure 5 As shown, in the bus expansion device provided in this application embodiment, the counting module 112 may include an accumulator ADD; the accumulator ADD counts the data cycles based on the cycle start signal (i.e., the bus cycle signal LFRAME) transmitted by the target bus.

[0057] When the bus cycle signal LFRAME is low, the count is incremented by 1, generating a periodic count value cnt[5..0] at the output Q of the reset-enabled D flip-flop DR_FF_1. Taking a count range of 1 to 32 as an example, when the count value cnt = 32, it returns to 0 and restarts the count. When the count is valid, the accumulator ADD increments by 1. For example, when the bus cycle signal is low, the accumulator ADD increments by 1, generating a periodic count value cnt[5..0] at the output Q of the reset-enabled D flip-flop DR_FF_1. For example, if the target count value is 32, the count range is 1 to 32. When the count value reaches 32, the accumulator ADD returns to 0 and restarts the count.

[0058] In the bus expansion device 100 provided in this application embodiment, the counting module 112 includes an accumulator ADD, which can realize the counting function based on a simple hardware circuit structure, and the hardware structure is simple.

[0059] It should be noted that, in other implementations, the counting module 112 can also be implemented based on other structural components with counting functions, which will not be elaborated or limited here.

[0060] In some implementations, Figure 6 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 4 The diagram illustrates a specific structure of the first data buffer 113. For example... Figure 6 As shown, in the bus expansion device provided in this application embodiment, the first data buffer 113 includes at least one first storage unit 1131; the capacity of the first storage unit 1131 matches the first width and is configured to store data signals for at least one data cycle.

[0061] The first data buffer 113 may include a first storage unit 1131, which stores a data signal with a first width transmitted by the target bus, enabling the bus expansion device 100 to control modules / devices with the first width. Alternatively, the first data buffer 113 may include two or more first storage units 1131, each of which can store a data signal with a first width transmitted by the target bus, enabling the splicing and expansion of data signals. The capacity of the first storage unit 1131 may be equal to the first width to store the data signal with the first width.

[0062] For example, if the first width is 4 bits, then the capacity of the first storage unit can be 4 bits. If the target count value is N, then the number of first storage units 1131 can be N, and the data stored in each first storage unit 1131 can be D[4n-1, 4n-4] (n = 1, 2, ..., N), so as to realize the N-fold expansion of the data signal transmitted to the target bus.

[0063] In the bus expansion device 100 provided in this application embodiment, the first data buffer 113 may include a number of first storage units 1131 matching the number of target count values. Each first storage unit 1131 may store the data signal within one data cycle of the target bus transmission, so as to splice and output the data signal within at least one data cycle stored in the first data buffer 113, thereby realizing data expansion and improving the flexibility of bus application.

[0064] For some implementation methods, please refer to [link / reference]. Figure 5 In the bus expansion device provided in this application embodiment, the control module 111 includes an RS flip-flop RS_FF and a first inverter. For example, the first inverter is shown as a first NOT gate NOT_14. The data input terminal D of the RS flip-flop RS_FF is connected to a first level, the carry terminal C of the RS flip-flop RS_FF is connected to a second level, the set terminal S and the clear terminal R of the RS flip-flop RS_FF are connected to the counting module 112, and the output terminal of the RS flip-flop RS_FF is connected to the output terminal of the control module 111 through the first inverter. The RS flip-flop RS_FF outputs a periodic valid signal of the first target data signal, i.e., the expanded bus periodic signal, based on the count value reaching the target count value.

[0065] In this configuration, the first level is high, and the second level is low. The set input S of the RS flip-flop RS_FF is connected to the output of the AND gate AND_2, and the clear input R is connected to the output of the OR gate OR. The specific connections are as follows: Figure 5As shown, the output Q of RS_FF is connected to the output of the control module through NOT_14. The data input D of RS flip-flop RS_FF is connected to a high level, causing the output Q to output '0' or '1' depending on the values ​​of the set input S and the clear input R; specifically, when R = '1', Q = '0'; when S = '1' and R = '0', Q = '1'. The carry input C of RS flip-flop RS_FF is connected to a low level, so the value of output Q is not affected by the carry signal at the carry input C. The set input S of RS flip-flop RS_FF is connected to the output of AND_2, and the clear input R is connected to the output of OR gate; when the system is reset (LRESET = '0'), the reset signal LRESET transmitted by the target bus becomes '1' through NOT_7 and is input to OR gate, causing OR gate to output '1'. At this time, the clear input R of RS flip-flop RS_FF is '1', causing the output Q to output '0'; when the system is in a non-reset state ( When LRESET = '1', and the output of the D flip-flop DR_FF_1 with reset is cnt[5..0] = "100000" (100000 is a binary number, corresponding to the decimal number 32), the lower 5 bits of cnt, cnt[4..0] = "00000", become "11111" after passing through NOT_9 to NOT12, and then output a high level '1' after passing through AND_2. Therefore, the set input S of the RS flip-flop RS_FF = '1'. The highest bit of cnt[5] = '1' becomes '0' after passing through NOT_8 and is input to OR. In the non-reset state, LRESET = '1' becomes '0' after passing through NOT_7 and is also input to OR. At this time, OR outputs '0', so the value of the reset terminal R of RS flip-flop RS_FF is '0', and the output terminal Q of RS flip-flop RS_FF is '1'. When cnt is 1 to 31, since the highest bit cnt[5] = '0', it becomes '1' after passing through NOT_8, so OR outputs '1'. At this time, the reset terminal R of RS flip-flop RS_FF is '1', and the output terminal Q is '0'. The output terminal Q of RS flip-flop RS_FF is connected to the output terminal FRAME through NOT_14. Therefore, whenever the count value cnt reaches 32, the extended bus cycle signal FRAME is low. In other cases, the extended bus cycle signal FRAME is high.

[0066] Therefore, when the count value reaches the target count value, such as 32, the output of the control module is an extended bus cycle signal FRAME, which is a valid signal, for example, a low level is generated; in other cases, the extended bus cycle signal FRAME is an invalid signal, for example, a high level signal is output.

[0067] In the bus expansion device 100 provided in this application embodiment, by setting the control module 111 to include an RS flip-flop RS_FF and a first inverter, it is possible to realize the function of outputting the expanded bus period signal based on the target count value based on a simple hardware circuit structure, and the hardware structure is simple.

[0068] It should be noted that, in other implementation methods, the control module 111 can also be implemented based on other structural components, which will not be elaborated or limited here.

[0069] In some implementations, Figure 7 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 5 This illustrates another specific structure of the control module 111. For example... Figure 7 As shown in the embodiment of this application, in the bus expansion device, the control module 111 further includes a second inverter and a first D flip-flop D_FF_2. For example, the second inverter is shown as a second NOT gate NOT_15. The clock terminal of the first D flip-flop D_FF_2 is connected to the period start signal of the target bus through the second inverter. The input terminal of the first D flip-flop D_FF_2 is connected to the data signal of the target bus. The output terminal Q of the first D flip-flop D_FF_2 is connected to the first data buffer 113. Based on the period start signal being a valid signal, the first D flip-flop D_FF_2 stores the data signal of the target bus in the first data buffer 113, and based on the different count values, transmits the data in the first storage unit 1131 in the first data buffer 113 to the position corresponding to the first target data signal.

[0070] The control module 111 can read the data transmitted on the target bus and store it in the first data buffer 113, and output the data in the first data buffer 113 to the data port DATA[127..0].

[0071] Figure 7In this circuit, the bus cycle signal LFRAME is connected to the clock terminal of the first D flip-flop D_FF_2 via the second NOT gate NOT_15. When the bus cycle signal LFRAME is active (low level), the data signal LAD[3..0] with a first width is sequentially stored in the first storage cell 1131 of the first data buffer 113 through the output terminal Q of the first D flip-flop D_FF_2. Furthermore, according to different count values, the data corresponding to different first storage cells 1131 are transmitted to the position corresponding to the first target data signal. For example, the first target data signal is represented as DATA[127..0]. When the count value is 1, the data of the first first storage cell 1131 in the first data buffer 113 is transmitted to the lower 4 bits DATA[3..0] of the first target data signal DATA[127..0], and so on.

[0072] In the bus expansion device 100 provided in this application embodiment, by setting the control module 111 to include a second inverter and a first D flip-flop D_FF_2, it is possible to realize the splicing of data between different first storage units 1131 in the first data buffer 113 based on the counting order, thereby realizing the data width expansion and improving the application flexibility of the target bus.

[0073] It should be noted that, in other implementation methods, the control module 111 can also be implemented based on other structural components, which will not be elaborated or limited here.

[0074] In some implementations, Figure 8 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 6 The diagram illustrates another specific structure of the bus expansion module 110. For example... Figure 8 As shown in the embodiment of this application, the bus expansion module 110 further includes a clock module 114, which is connected to the control module 111. The clock module 114 is configured to multiply the clock signal LCLK transmitted on the target bus under the control of the control module 111 to generate a target clock signal CLK. Specifically, the control module 111 can control the clock module 114 to adjust the clock coefficient and output the multiplied target clock signal.

[0075] The clock module 114 has its input terminal connected to the clock signal LCLK transmitted by the target bus. Taking the target bus as an LPC bus as an example, the frequency of this clock signal is 33MHz.

[0076] In the bus expansion device 100 provided in this application embodiment, the bus expansion module 110 further includes a clock module 114. Under the control of the control module 111, the clock module 114 can multiply the clock signal LCLK transmitted by the target bus, thereby expanding the data width while using the low-speed target bus to control the module / device of the high-speed clock signal.

[0077] For some implementation methods, please refer to [link / reference]. Figure 5 In the bus expansion device provided in this application embodiment, the clock module 114 may include a phase-locked loop (PLL); the input terminal of the PLL is connected to the clock signal LCLK of the target bus, and the PLL is configured to multiply the clock signal LCLK transmitted by the target bus to generate the target clock signal.

[0078] Among them, a phase-locked loop (PLL) can be used as the clock module 114 to improve the clock frequency.

[0079] For example, the multiplier of the phase-locked loop (PLL) can be 2, increasing the frequency of the target bus clock signal LCLK from 33MHz to 66MHz, and outputting this to the clock terminal CLK as the clock signal for the controlled module, such as a cryptographic module. Alternatively, as... Figure 5 As shown, the multiplication factor of the phase-locked loop (PLL) can be 4, which multiplies the input 33MHz clock signal by 4 and outputs a target clock signal of 132MHz.

[0080] In other implementations, the multiplication factor of the phase-locked loop (PLL) can be set to other values, which can be set according to the frequency multiplication requirements and are not limited here. Specifically, the control module 111 can control the PLL to adjust the multiplication factor and output a target clock signal that meets the frequency requirements.

[0081] In some implementations, the parameters of the phase-locked loop (PLL) can be adjusted according to the clock frequency of the controlled module, such as the cryptographic module, to synchronize the clock signal LCLK transmitted on the target bus with the clock of the cryptographic module.

[0082] In some implementations, the multiplier of the phase-locked loop (PLL) can be set to 1 to keep the clock frequency constant, meaning that the clock terminal CLK still outputs the target clock signal of 33MHz.

[0083] In the bus expansion device 100 provided in the embodiments of this application, by setting the clock module 114 to include a phase-locked loop (PLL) and setting the multiplication coefficient of the PLL, the matching requirements of different clock frequencies can be met, and the hardware circuit structure is simple and easy to implement.

[0084] In some implementation methods, continue to refer to Figure 5In the bus expansion device provided in this application embodiment, the control module 111 further includes a second D flip-flop D_FF_1; the clock terminal of the second D flip-flop D_FF_1 is connected to the clock signal of the target bus, and the data input terminal of the second D flip-flop D_FF_1 is connected to the reset signal of the target bus; the second D flip-flop D_FF_1 is configured to output a new reset signal RESET corresponding to the first target data signal after controlling the effective time of the reset based on the target bus reset signal LRESET. For example, the reset signal can be a low-level active signal.

[0085] Specifically, the target bus reset signal LRESET is delayed by one clock cycle through the second D flip-flop D_FF_1 to form a new reset signal RESET, which is then output to the reset terminal of the bus expansion module 110.

[0086] In the bus expansion device 100 provided in the embodiments of this application, the control module 111 can also receive the reset signal LRESET transmitted by the target bus and perform control, such as adjusting or keeping the effective time of the reset unchanged, and then outputting a new reset signal RESET to meet the reset requirements of the controlled device.

[0087] It should be noted that, Figure 5 The image shows the clock signal transmitted based on the target bus in the bus expansion module. Figure 5 (shown as LCLK in the image), reset signal ( Figure 5 (shown as LRESET in the image) and data cycle signal ( Figure 5 (shown as LFRAME in the image), generating the extended clock signal ( Figure 5 (shown as CLK in the middle), reset signal ( Figure 5 (shown as RESET in the image) and data cycle signal ( Figure 5 The relevant circuit structure (shown as FRAME in the image) may include a phase-locked loop (PLL). Figure 5 (shown as a PLL in the image), 1 D flip-flop ( Figure 5 (shown as D_FF_1), and one D flip-flop with a reset input. Figure 5 (shown as DR_FF_1), 1 RS flip-flop ( Figure 5 (Shown as RS_FF), 2 two-to-one data selectors ( Figure 5 (MUX_1 to MUX_2 are shown in the diagram), and a 6-bit accumulator ( Figure 5 (shown as ADD in the middle), 2 AND gates ( Figure 5 (shown as AND_1 to AND_2), 1 OR gate ( Figure 5 (shown as OR in the text), 14 NOT gates ( Figure 5 (shown as NOT_1 to NOT_14); the connections between the structures are as follows: Figure 5 As shown. In other implementations, the bus expansion module can also be implemented using other circuit structures that implement the above-mentioned expansion functions, and there are no limitations.

[0088] In some implementations, Figure 9 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 7 This illustrates another specific structure of the bus expansion device. For example... Figure 9 As shown, the bus expansion device 100 provided in this application embodiment may further include a password control module 120, which is connected to the bus expansion module 110. The password control module 120 is also configured to connect to a target password module 300. The password control module 120 is configured to generate a password control signal based on a first target data signal, and the password control signal is configured to control the target password module 300.

[0089] The first target data signal is an extended signal of the data signal transmitted based on the target bus 01. The cryptographic control module 120 is connected to the bus extension module 110, and can receive the first target data signal and generate a cryptographic control signal to control the target cryptographic module 300 connected to the cryptographic control module 120. The cryptographic control signal can also be understood as a cryptographic algorithm control signal, capable of controlling the target cryptographic module 300. The data width of the first target data signal matches the data width of the target cryptographic module 300 to achieve control over the target cryptographic module 300.

[0090] The bus expansion device 100 provided in this application embodiment includes a bus expansion module 110 and a password control module 120. It can expand the width of the data signal transmitted on the target bus based on the bus expansion module 110, thereby improving the application flexibility of the target bus; and it can control the target password module 300 based on the password control module 120, thereby improving the security of the data.

[0091] In some embodiments, when the bus expansion module 110 expands the width of the data signal by a factor of 1, that is, when the data width of the first target data signal is the same as the data width of the data signal transmitted by the target bus, the target cryptographic module 300 may be a TCM or a TPM. In other embodiments, when the bus expansion module 110 expands the width of the data signal by a factor of greater than 1, that is, when the data width of the first target data signal is greater than the data width of the data signal transmitted by the target bus, the target cryptographic module 300 may be a cryptographic module with a corresponding data width, such as an SM4 cryptographic module, which is not limited here.

[0092] In some implementations, Figure 10 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 8The diagram illustrates a specific structure of the password control module 120. For example... Figure 10 As shown in the embodiment of this application, in the bus expansion device, the cryptographic control module 120 includes an algorithm state machine 121 and a second data buffer 122, which is connected to the algorithm state machine 121. The algorithm state machine 121 is configured to transmit the first target data signal to the second data buffer 122 based on a periodic valid signal of the first target data signal. The second data buffer 122 is configured to store at least one first target data signal in the second data buffer 122 under the control of the algorithm state machine 121, and to interact with the target cryptographic module 300. Exemplarily, the second data buffer 122 may be a volatile storage unit, such as random access memory (RAM) or other components with storage functions, which are not limited here.

[0093] The algorithm state machine 121 is capable of controlling data transmission between the first data buffer 113 and the second data buffer 122, as well as controlling the target cryptographic module 300. Specifically, when the extended bus cycle signal FRAME is valid, corresponding to the periodic valid signal of the first target data signal, the algorithm state machine 121 transmits the first target data signal to the second data buffer 122. The second data buffer 122 can temporarily store at least one first target data signal, and can generate control signals for the target cryptographic module 300 based on the stored at least one first target data signal, thereby realizing the control of the target cryptographic module 300.

[0094] In the bus expansion device 100 provided in this application embodiment, by setting the password control module 120 to include an algorithm state machine 121 and a second data buffer 122 connected to the bus expansion module 110, the first target data signal formed by splicing and expanding the data stored in the first data buffer 113 can be transmitted to the second data buffer 122 based on the effective period signal of the first target data signal, and further transmitted to the target password module 300, thereby realizing the control of the target password module 300.

[0095] In some implementations, Figure 11 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 9 The diagram illustrates another specific structure of the password control module 120. For example... Figure 11As shown in the embodiment of this application, in the bus expansion device, the cryptographic control module 120 further includes a function register 123. The input terminal of the function register 123 is connected to the algorithm state machine 121, and the output terminal of the function register 123 is connected to the target cryptographic module 300. The function register 123 is configured to output target operation instructions to the target cryptographic module 300 based on the control of the algorithm state machine 121. The target operation instructions include at least one of the following: an operation instruction to write a key to the target cryptographic module 300, an operation instruction to write a data block length to the target cryptographic module 300, and an operation instruction for data encryption and decryption.

[0096] For example, function register 123 can be a 3-bit register used to represent different operation commands of algorithm state machine 121 to target cryptographic module 300. Different operation commands can be output to target cryptographic module 300 through command port OP[2..0]. The functions of each bit are as follows: OP[0]: The initial value of this bit is '0', set by algorithm state machine 121. Setting it to '1' indicates the operation command to write the key to the target cryptographic module. For example, the key can be represented as KEY[4n-1..0]; OP[1]: The initial value of this bit is '0', set by algorithm state machine 121. Setting it to '1' indicates the operation command to write the length of the data block to the target cryptographic module. For example, the length of the data block can be represented as LEN[4n-1..0]; OP[2]: This bit is set by the user in the host computer software. Setting it to '1' indicates the operation command to encrypt data, and setting it to '0' indicates the operation command to decrypt data.

[0097] In the bus expansion device 100 provided in this application embodiment, by setting the password control module 120 to include a function register 123, it is possible to control different operations on the target password module 300 based on operation instructions, which ensures data security while keeping the control method simple.

[0098] In some implementations, Figure 12 This is a schematic diagram illustrating the state transition process of an algorithm state machine in a bus expansion device according to an embodiment of this application. It shows the flow steps of a state transition in algorithm state machine 121. For example... Figure 12 As shown, the algorithm state machine 121 includes the following states: IDLE, START, WR_KEY (write key), WR_LEN (write length), WR_DATA (write data), WAIT (wait), RD_DATA (read data), and FINISH (finish). Exemplarily, when the bus expansion device 100 is implemented based on a programmable device, such as a Field Programmable Gate Array (FPGA), the algorithm state machine 121 can be implemented through VHDL programming of the FPGA, which is not limited here.

[0099] like Figure 12 As shown, the transition / transition relationships between different states may include the following steps:

[0100] After the system is reset (e.g., RESET = "0"), it enters the IDLE state. When the reset ends and the target bus transmission cycle starts (e.g., FRAME = '0'), the algorithm state machine 121 enters the START state.

[0101] In the START state, the algorithm state machine 121 sets the function register 123 to write the key to the target cryptographic module 300, that is, the algorithm state machine 121 sets the OP[0] of the function register 123 to '1', and then enters the write key WR_KEY state.

[0102] In the write key WR_KEY state, the algorithm state machine 121 sends the key data in the second data buffer 122, such as KEY[127..0], to the target cryptographic module 300; and sets the function register 123 to the length to be written to the target cryptographic module 300, that is, sets the OP[1] of the function register 123 to '1', and then enters the write length WR_LEN state;

[0103] In the WR_LEN state of writing length, the algorithm state machine 121 sends the length data in the second data buffer 122, such as LEN[127..0], to the target cryptographic module 300, and then enters the WR_DATA state of writing data.

[0104] In the WR_DATA state, the algorithm state machine 121 sends the password data stored in at least one second storage unit 1221 in the second data buffer 122 to the target password module 300 according to the password length value LEN in the length data, and then enters the WAIT state.

[0105] While in the WAIT state, the algorithm state machine 121 waits for the target cryptographic module 300 to complete its operation, and then enters the read data RD_DATA state based on the completion of the operation (e.g., DONE = '1').

[0106] In the RD_DATA state, the algorithm state machine 121 reads the ciphertext or plaintext data after the target cryptographic module 300 has completed its operation and stores it in at least one second storage unit 1221 in the second data buffer 122; then it enters the FINISH state.

[0107] Upon exiting the FINISH state, the algorithm state machine 121 clears the flag bits of the function register 123, that is, it clears the OP[0] and OP[1] bits of the function register 123, and then returns to the IDLE state.

[0108] This completes one data processing cycle for the control target cryptographic module 300. The next data processing cycle will repeat the above steps.

[0109] In some implementations, Figure 13 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 10 The diagram illustrates a specific structure of the second data buffer 122. For example... Figure 13 As shown, in the bus expansion device provided in this application embodiment, the second data buffer 122 includes a key data storage unit 1222, a length data storage unit 1223, and at least one second storage unit 1221; the key data storage unit 1222 is configured to store key data, the length data storage unit 1223 is configured to store length data, and the second storage unit 1221 is configured to store cryptographic data of different data groups, and a group of cryptographic data includes a first target data signal.

[0110] For example, when the first data width is 4 bits, the first target width of the first target data signal is 4n bits, then the capacity of each second storage unit 1221 can be 4n bits. Similar to the first data buffer, the storage capacity of the entire second data buffer 122 can be set by the user according to data storage requirements, or dynamically changed based on different application scenarios, and is not limited here.

[0111] For example, with Figure 13 Taking the orientation of the second data buffer 122 as an example, in order from bottom to top, the first storage unit can be a key data storage unit 1222, used to store key data KEY[4n-1..0]; the second storage unit can be a length data storage unit 1223, used to store length data LEN[4n-1..0], which represents the number of data packets to be encrypted / decrypted, i.e., LEN=M (M≥1), indicating that there are M data packets to be encrypted / decrypted, and the corresponding data width is M×4n bits; the third to the (M+2)th storage units can be second storage units 1221, all used to store the first target data signal; the first target data signal DATA[4n-1..0] can be stored sequentially in the third to the (M+2)th second storage units 1221.

[0112] In the bus expansion device 100 provided in this application embodiment, the algorithm state machine 121 also controls the key data KEY[4n-1..0] in the second data buffer 122 to be transmitted to the key port of the target cryptographic module 300 through the key output terminal KEY; the length data LEN[4n-1..0] to the length port of the target cryptographic module 300 through the length output terminal LEN; the data packets DATA_1 to DATA_M are sequentially transmitted to the data input port of the target cryptographic module 300 through the data output terminal DATA_OUT[4n-1..0]; the command port OP[2..0] is connected to the command control port of the target cryptographic module 300 to realize the transmission of operation instructions and realize the control of the target cryptographic module 300 based on operation instructions.

[0113] In some implementations, Figure 14 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 10 The first example illustrates another specific structure of the bus expansion device. For instance... Figure 14 As shown, in the bus expansion device provided in this application embodiment, the algorithm state machine 121 and the second data buffer 122 are also connected to the control module 111 in the bus expansion module 110 respectively; the algorithm state machine 121 is also configured to receive data packets completed by the target cryptographic module 300, transmit the data packets to different second storage units 1221 in the second data buffer 122, and send a preparation completion signal to the control module 111; the control module 111 is also configured to read the second target data signal in the target second storage unit 1221 in the second data buffer 122 based on the preparation completion signal, and store the second target data signal in the first storage unit 1131 in the first data buffer 113 in the bus expansion module 110 according to the format of the first width.

[0114] Specifically, the algorithm state machine 121 can also receive the DONE signal from the target cryptographic module 300. When DONE = '1', it receives the data packets completed by the target cryptographic module 300 through the data input port DATA_IN[4n-1..0], which are either encrypted ciphertext or decrypted plaintext, and transmits the data packets sequentially to the second data buffer 122. After the data transmission is completed, the output terminal READY becomes high level '1'. Correspondingly, the control module 111 receives the READY signal from the algorithm state machine 121. When READY = '1', it reads the data in the second data buffer 122 through the data interaction port DATA. This data is the second target data signal, and the read data is stored sequentially in the first data buffer 113 according to the first width, for example, 4-bit format, so that the data can be transmitted through the target bus.

[0115] In some implementations, Figure 15 This is a schematic diagram of the structure of a bus expansion device according to an embodiment of this application. Figure 10 Second, the diagram illustrates the circuit structure for the bus expansion module 110 to read data DATA[127..0], store it in the first data buffer 113, and then transmit it to the target bus. Taking a first width of 4 bits and a second target width of 128 bits as an example, the control module 111 includes a tri-state buffer Tri, a multiplexer SEL, and 32 comparators CMP_1 to CMP_32. The control terminal of the tri-state buffer Tri is connected to the READY signal. When READY = '1', the tri-state buffer Tri is turned on, and the data DATA[127..0] can be output through the tri-state gate. After being split into 4 bits, it is connected to the corresponding input terminal d of the multiplexer SEL. One input terminal of comparators CMP_1 to CMP_32 is connected to the count value cnt, and the other input terminal is the comparison value, which is set to 1 to 32 respectively. The output terminals of CMP_1 to CMP_32 are respectively connected to the selection control terminal e of the multiplexer SEL. The output terminal of the multiplexer SEL is connected to the first data buffer 113. The multiplexer SEL can select the corresponding data for output according to the output results of each comparator. For example, when the count value cnt = 1, the first CMP_1 outputs a high level, and the other comparators output a low level. At this time, the data DATA[3..0] is output to the first data buffer 113 through the multiplexer SEL, and so on. After the data is transmitted to the first data buffer 113, it is then transmitted to the target bus.

[0116] In some implementations, the target bus includes an LPC bus; the bus expansion device is implemented based on a programmable logic device, and both the first target width and the second target width are integer multiples of the first width.

[0117] The bus expansion device 100 provided in this application embodiment can expand the LPC bus based on a programmable logic device, such as an FPGA, to control modules / devices with data bus widths greater than 4 bits, specifically integer multiples of 4 bits. Simultaneously, it can multiply the clock frequency based on a clock module, enabling control of modules / devices with high-speed clock signals (e.g., integer multiples of 33MHz) using a low-speed LPC bus, thereby improving data processing speed. Furthermore, a cryptographic control module can be employed to enhance security during data communication. Moreover, this solution does not affect the functionality of the existing system; that is, when the multiplier is 1, the data width relative to the LPC bus remains unchanged, maintaining the functionality of the existing system, and offering flexible deployment and convenient implementation.

[0118] Specifically, the bus expansion device 100 provided in this application embodiment can expand the LPC bus based on FPGA and can be applied to the fields of electronic information and data security. Specifically, by setting the bus expansion module to include a control module based on FPGA, it can process LPC bus data signals and control signals, enabling devices with LPC interfaces to control modules / devices / data buses with a width of 4nbit (n = 1, 2, ..., N), i.e., multiples of 4 bits, such as 16bit, 32bit, 64bit, etc., thereby expanding the data bus and improving application flexibility. Furthermore, by using a clock module to multiply the clock signal of the LPC bus and controlling the target cryptographic module through the algorithm state machine of the cryptographic control module, the data transmission speed and security can be improved. Therefore, this application embodiment can utilize the limited data width and clock signal of the LPC bus to control modules / devices with high-speed clock signals and data buses with multiples of 4 bits, possessing scalability, security, and not affecting the functionality of existing systems, and is flexible in deployment and convenient in implementation. In addition, by controlling the target cryptographic module, the overall security of the system can be improved, meeting the requirements of the information security field for data security processing.

[0119] In some implementations, Figure 16 This is a schematic diagram of the application architecture of a bus expansion device according to an embodiment of this application. Figure 2 Taking the SM4 cryptographic algorithm module as an example, this paper illustrates one application of the bus expansion device. Controlling other target cryptographic modules with different data widths based on this bus expansion device is similar and will not be elaborated upon here. The SM4 cryptographic algorithm is a national standard symmetric cryptographic algorithm module with a key width of 128 bits and a data width of 128 bits. The SM4 cryptographic algorithm processes data in 128-bit blocks, processing one data block at a time until all data blocks are processed, generating either encrypted ciphertext or decrypted plaintext.

[0120] The functions of each signal in the SM4 cryptographic algorithm module shown in the figure are explained below. Here, clk represents the clock signal, the specific value of which can be input from an external clock source. The higher the frequency, the faster the SM4 cryptographic algorithm module operates. In this embodiment, the clock signal can use a clock frequency of 132MHz; reset represents the reset signal; Data_in[127..0] represents the data input signal, with a data width of 128 bits; Key[127..0] represents the key signal, with a data width of 128 bits.

[0121] Len[127..0] represents the length signal, which represents the number of data groups; op[2..0] represents the command control signal; done represents the output signal after the data operation is completed; Data_out[127..0] represents the data output signal, with a data width of 128 bits.

[0122] like Figure 16 As shown, the bus expansion device 100 can be connected to the host computer software 200 via the LPC bus, and to the SM4 cryptographic algorithm module 3 via another bus.

[0123] The host computer software 200 is an upper-layer application software operated by the user terminal, which may include drivers, application software interfaces, etc. The user sets keys, registers, data to be processed, etc. through the host computer software and sends them to the bus expansion module 110 through the LPC bus; and receives data returned by the bus expansion module 110 through the LPC bus, which has been processed by the SM4 cryptographic algorithm module 3.

[0124] The bus expansion module 110 can be any of the bus expansion modules provided in the above embodiments. For example, in this bus expansion module 110, by setting the phase-locked loop (PLL) multiplier of the clock module 114 to 4, the control module 111 multiplies the clock signal LCLK input to the LPC bus by 4, and the output target clock signal CLK = 33 × 4 = 132 (MHz) serves as the clock signal for the SM4 cryptographic algorithm module. Since the data width of the SM4 cryptographic algorithm module is 128 bits, the count value n of the counting module 112 is 128 bits / 4 bits = 32; the data signal output by the bus expansion module is DATA[127..0].

[0125] The password control module 120 can adopt any of the password control modules provided in the above embodiments. For example, in this password control module 120, the storage unit of the second data buffer 122 has a capacity of 128 bits; correspondingly, the width of the interaction port, including the key output terminal KEY, the length output terminal LEN, the data output terminal DATA_OUT, and the data input terminal DATA_IN, is also 128 bits.

[0126] In some implementations, the bus expansion device 100, such as the FPGA, may also include a power supply module and a JTAG / AS interface. The power supply module provides operating voltages to the various modules of the FPGA, such as 1.5V, 3.3V, etc., which are not limited here. The JTAG / AS interface serves as the FPGA's debug / download interface, used for FPGA debugging and program downloading.

[0127] In this embodiment, the LPC bus is expanded and the clock frequency is multiplied based on FPGA, enabling it to control the SM4 cryptographic algorithm module with a data bus width 32 times that of 4 bits. In addition, the SM4 cryptographic algorithm module is controlled by an algorithm state machine in the FPGA, improving the speed and security of data processing.

[0128] Based on the same inventive concept, this application also provides a data processing method. This data processing method is executed based on any of the bus expansion devices provided in this application and has corresponding beneficial effects. The same or similar aspects can be understood with reference to the above text, and will not be repeated here.

[0129] For example, Figure 17 This is a flowchart illustrating a data processing method according to an embodiment of this application. Figure 1 .like Figure 17 As shown, the data processing method may include:

[0130] S510: Acquire the data signal with a first width transmitted by the target bus.

[0131] For example, a bus extension device can acquire a data signal with a first width transmitted by a target bus.

[0132] S520. Generate a first target data signal based on a data signal having a first width, wherein the data width of the first target data signal is the first target width, and the first target width is equal to or greater than the first width.

[0133] For example, the bus expansion device can expand the data signal with a first width to generate a first target data signal with a first target width, wherein the first target width can be equal to the first width so as not to affect the control of the module / device with the data signal with the first width; or the first target width can be greater than the first width so as to realize the control of the module / device with the data signal with a width greater than the first width.

[0134] In the data processing method provided in this application embodiment, by widening the data signal transmitted on the target bus, it is possible to control modules / devices with a data width equal to or greater than a first width, thereby improving the application flexibility of the target bus.

[0135] For example, Figure 18 This is a flowchart illustrating a data processing method according to an embodiment of this application. Figure 2 .like Figure 18 As shown, the data processing method may include:

[0136] S610, Acquire the second target data signal.

[0137] For example, the control module in the bus expansion device can acquire a second target data signal having a second target width.

[0138] S620. Generate a data signal with a first width based on the second target data signal, wherein the data width of the second target data signal is the second target width, and the second target width is greater than or equal to the first width.

[0139] For example, the control module in the bus expansion device can split the second target data signal with a second target width into a format with a first width and further store it in a first storage unit in a first data buffer so as to transmit it based on a target bus with a first width.

[0140] In the data processing method provided in this application embodiment, by performing data width conversion on the second target data signal, a data signal with a first width that can be transmitted on the target bus is generated, which enables control of modules / devices with other data widths based on the target bus, thereby improving the application flexibility of the target bus.

[0141] In some implementations, the bus expansion module may include a control module, a counting module, and a first data buffer.

[0142] Based on this, a first target data signal is generated from a data signal having a first width, which may specifically include:

[0143] The counting module counts the data cycles of the target bus and transmits the count value to the control module;

[0144] The first data buffer stores the data signal of at least one data cycle transmitted by the target bus;

[0145] The control module generates a first target data signal based on the data signal of at least one data cycle stored in the first data buffer when the count value reaches the target count value, and outputs a periodic valid signal of the first target data signal.

[0146] In the data processing method provided in this application embodiment, a bus expansion module is set up including a control module, a counting module, and a first data buffer. The counting module can count the data cycles of the target bus and transmit the count value to the control module. The first data buffer can store the data signal of at least one data cycle transmitted by the target bus. The control module can generate a first target data signal based on the target count value reaching the target count value, generate the first target data signal based on the data signal of at least one data cycle stored in the first data buffer, and output the periodic valid signal of the first target data signal, thereby realizing data width expansion.

[0147] In some implementations, the bus expansion module also includes a clock module.

[0148] Based on this, the data processing method may further include: under the control of the control module, the clock module multiplies the clock signal transmitted on the target bus to generate a target clock signal.

[0149] In the data processing method provided in this application embodiment, a clock module is also included by setting a bus expansion module. The clock module can multiply the clock signal transmitted by the target bus under the control of the control module, thereby expanding the data width while controlling the module / device of the high-speed clock signal using the low-speed target bus.

[0150] In some implementations, the bus expansion device also includes a cryptographic control module.

[0151] Based on this, the data processing method may further include: a cryptographic control module generating a cryptographic control signal based on a first target data signal, wherein the cryptographic control signal is configured to control a target cryptographic module.

[0152] The data processing method provided in this application embodiment can expand the width of the data signal transmitted on the target bus based on the bus expansion module, thereby improving the application flexibility of the target bus; and can control the target cryptographic module based on the cryptographic control module, thereby improving data security.

[0153] In some implementations, the cryptographic control module includes an algorithm state machine and a second data buffer.

[0154] Based on this, a cryptographic control signal is generated based on the first target data signal, which may specifically include:

[0155] The algorithm state machine transmits the first target data signal to the second data buffer based on the periodic valid signal of the first target data signal;

[0156] The second data buffer, based on the control of the algorithm state machine, stores at least one first target data signal into the second data buffer and interacts with the target cryptographic module.

[0157] In the data processing method provided in this application embodiment, by setting the cryptographic control module to include an algorithm state machine and a second data buffer connected to the bus expansion module, the first target data signal, formed by splicing and expanding the data stored in the first data buffer, can be transmitted to the second data buffer based on the effective periodic signal of the first target data signal, and further transmitted to the target cryptographic module, thereby realizing the control of the target cryptographic module.

[0158] In some implementations, interaction with the target cryptographic module may include:

[0159] The algorithm state machine sends the key data, length data, and cipher data of different data blocks in the second data buffer to the target cryptographic module;

[0160] The algorithm state machine reads the data processed by the target cryptographic module after it has been processed, and stores it in the second storage unit in the second data buffer.

[0161] This enables the transmission of data to and from the target cryptographic module, thereby facilitating interaction between the algorithm state machine and the target cryptographic module, and ultimately enabling control of the target cryptographic module.

[0162] In some implementations, a data signal with a first width is generated based on the second target data signal, which may specifically include:

[0163] The control module reads the second target data signal from the second target storage unit in the second data buffer, and stores the second target data signal in the first storage unit in the first data buffer according to the first width format; the data in the first data buffer is available for the host computer connected to the target bus to read.

[0164] This method of converting data width based on the control module, the second data buffer, and the first data buffer facilitates the conversion of the second target data signal with the second target width into a data signal with the first width. This makes it easier to transmit data signals with a larger data width based on the target bus and improves the application flexibility of the target bus.

[0165] In some implementations, Figure 19 This is a flowchart illustrating a data processing method according to an embodiment of this application. Figure 3 This illustrates the overall process of a single data processing step. For example... Figure 19 As shown, the data processing method may include:

[0166] S710. The user sets the key, block length, data to be processed, and the value of the OP[2] bit in the function register through the host computer software. OP[2] = '1' indicates data encryption operation and '0' indicates decryption operation.

[0167] S720, data is transmitted to the first data buffer via the target bus.

[0168] S730: After the data is converted by the bus expansion module, it is stored in the second data buffer in the format of the first target width.

[0169] S740 and the algorithm state machine send the data in the second data buffer to the target cryptographic module.

[0170] S750, the target cryptographic module obtains the key, block length, and data to be processed; and performs encryption or decryption operations on the data according to the value of OP[2].

[0171] S760, the algorithm state machine is in a waiting state.

[0172] During this step, wait for all data groups to complete processing. It can be determined whether all data groups have been processed, for example, by checking if DONE = '1'. If the result is no, it indicates that processing is not complete, and return to S750; if the result is yes, it indicates that processing is complete, and proceed to S770.

[0173] S770. When DONE = '1', the algorithm state machine reads the ciphertext or plaintext data after the operation is completed and stores it in the second data buffer. After all the data after the operation is completed, the signal READY = '1'.

[0174] During this step, it is determined whether the reading is complete, for example, whether READY = '1'. If the result is no, it means that the reading is not complete, and the reading action is returned. If the result is yes, it means that the reading is complete, and the subsequent S780 is executed.

[0175] S780 and the bus expansion module read the data in the second data buffer and store it in the first data buffer in the first width format.

[0176] The S790 host computer reads data from the first data buffer via the target bus.

[0177] This completes one data processing cycle.

[0178] In other implementations, if it is necessary to change the key, data, or packet length, the above steps can be repeated.

[0179] The data processing method provided in this application embodiment, through data width expansion, enables control of a target cryptographic module with a first target width based on the target bus, thereby improving the application flexibility of the target bus and ensuring data processing security.

[0180] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0181] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bus expansion device, characterized in that, Configured on the server; The bus expansion device includes: A bus expansion module is configured to connect to a target bus; the bus expansion module is configured to interact with the target bus to generate a data signal with a first width, and generate a first target data signal based on the data signal with the first width, or generate the data signal with the first width based on an acquired second target data signal; Wherein, the data width of the first target data signal is the first target width, and the data width of the second target data signal is the second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width; The bus expansion device further includes a cryptographic control module, which is connected to the bus expansion module; the cryptographic control module is configured to connect to a target cryptographic module. The cryptographic control module includes an algorithm state machine and a function register. The input of the function register is connected to the algorithm state machine, and the output of the function register is connected to the target cryptographic module. The function register is configured to control the algorithm state machine and output target operation instructions to the target cryptographic module. The target operation instructions include at least one of the following: an operation instruction to write a key to the target cryptographic module, an operation instruction to write a data block length to the target cryptographic module, and a data encryption / decryption operation instruction.

2. The bus expansion device according to claim 1, characterized in that, The bus expansion module includes a control module, a counting module, and a first data buffer, wherein the counting module and the first data buffer are respectively connected to the control module; The counting module is configured to count the data cycles of the target bus and transmit the count value to the control module; The first data buffer is configured to store the data signal of at least one data cycle transmitted by the target bus; The control module is configured to generate the first target data signal based on the data signal of the at least one data period stored in the first data buffer when the target count value is reached, and to output the periodic valid signal of the first target data signal.

3. The bus expansion device according to claim 2, characterized in that, The counting module includes an accumulator; The accumulator counts the data cycles based on the cycle start signal transmitted on the target bus.

4. The bus expansion device according to claim 2, characterized in that, The first data cache includes at least one first storage unit; The capacity of the first storage unit matches the first width and is configured to store the data signal for at least one data cycle.

5. The bus expansion device according to claim 2, characterized in that, The control module includes an RS flip-flop and a first inverter; the data input terminal of the RS flip-flop is connected to a first level, the carry terminal of the RS flip-flop is connected to a second level, the set terminal and the clear terminal of the RS flip-flop are connected to the counting module, and the output terminal of the RS flip-flop is connected to the output terminal of the control module through the first inverter; The RS trigger outputs a periodic valid signal of the first target data signal based on the count value reaching the target count value; The control module further includes a second inverter and a first D flip-flop; the clock terminal of the first D flip-flop is connected to the period start signal of the target bus through the second inverter, the input terminal of the first D flip-flop is connected to the data signal of the target bus, and the output terminal of the first D flip-flop is connected to the first data buffer. The first D flip-flop stores the target bus data signal in the first data buffer based on the period start signal as a valid signal, and transmits the data in the first storage unit corresponding to the first data buffer to the position corresponding to the first target data signal based on the different count values.

6. The bus expansion device according to claim 2, characterized in that, The bus expansion module also includes a clock module, which is connected to the control module. The clock module is configured to multiply the clock signal transmitted on the target bus under the control of the control module to generate a target clock signal.

7. The bus expansion device according to claim 6, characterized in that, The clock module includes a phase-locked loop; The input terminal of the phase-locked loop is connected to the clock signal of the target bus, and the phase-locked loop is configured to multiply the clock signal transmitted by the target bus to generate a target clock signal.

8. The bus expansion device according to claim 6, characterized in that, The control module further includes a second D flip-flop; the clock input of the second D flip-flop is connected to the clock signal of the target bus, and the data input of the second D flip-flop is connected to the reset signal of the target bus; the second D flip-flop is configured to output a new reset signal corresponding to the first target data signal after controlling the effective time of the reset based on the reset signal of the target bus.

9. The bus expansion device according to any one of claims 1-8, characterized in that, The cryptographic control module is configured to generate a cryptographic control signal based on the first target data signal, and the cryptographic control signal is configured to control the target cryptographic module.

10. The bus expansion device according to claim 9, characterized in that, The cryptographic control module further includes a second data buffer, which is connected to the algorithm state machine. The algorithm state machine is configured to transmit the first target data signal to the second data buffer based on a periodic valid signal of the first target data signal; The second data buffer is configured to store at least one of the first target data signals into the second data buffer based on the control of the algorithm state machine, and to interact with the target cryptographic module.

11. The bus expansion device according to claim 10, characterized in that, The second data buffer includes a key data storage unit, a length data storage unit, and at least one second storage unit; The key data storage unit is configured to store key data, the length data storage unit is configured to store length data, the second storage unit is configured to store cryptographic data of different data groups, and a group of cryptographic data includes a first target data signal.

12. The bus expansion device according to claim 11, characterized in that, The algorithm state machine includes the following states: idle, start, write key, write length, write data, wait, read data, and end; The transitions between the different states include the following steps: After the system is reset, it enters an idle state. When the reset ends and the target bus transmission cycle starts, the algorithm state machine enters the start state. In the initial state, the algorithm state machine sets the function register to write the key to the target cryptographic module, and then enters the key writing state; In the key writing state, the algorithm state machine sends the key data in the second data buffer to the target cryptographic module; and sets the function register to write the length to the target cryptographic module, and then enters the length writing state; In the write length state, the algorithm state machine sends the length data in the second data buffer to the target cryptographic module, and then enters the write data state; In the data writing state, the algorithm state machine sends the password data stored in at least one of the second storage units in the second data buffer to the target password module according to the password length value in the length data, and then enters the waiting state; In the waiting state, the algorithm state machine waits for the target cryptographic module to complete its operation, and then enters the data reading state based on the completion of the operation. In the data reading state, the algorithm state machine reads the ciphertext or plaintext data after the target cryptographic module has completed its operation and stores it in at least one of the second storage units in the second data buffer; then it enters the end state. In the final state, the algorithm state machine clears the flag bit of the function register and then returns to the idle state.

13. The bus expansion device according to claim 12, characterized in that, The algorithm state machine and the second data buffer are also respectively connected to the control module in the bus expansion module; The algorithm state machine is further configured to receive data packets completed by the target cryptographic module, transmit the data packets to different second storage units in the second data buffer, and send a preparation completion signal to the control module. The control module is further configured to read the second target data signal from the target second storage unit in the second data buffer based on the preparation completion signal, and store the second target data signal in the first storage unit in the first data buffer of the bus expansion module in the format of the first width.

14. The bus expansion device according to claim 1, characterized in that, The target bus includes an LPC bus; the bus expansion device is implemented based on a programmable logic device, and both the first target width and the second target width are integer multiples of the first width.

15. A data processing method, characterized in that, The data processing method is performed based on the bus expansion device according to any one of claims 1-14; the data processing method includes: Acquire the data signal with a first width transmitted by the target bus; A first target data signal is generated based on the data signal having a first width, wherein the data width of the first target data signal is the first target width, and the first target width is equal to or greater than the first width; or, Acquire the second target data signal; A data signal with a first width is generated based on the second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is greater than or equal to the first width.

16. The data processing method according to claim 15, characterized in that, The bus expansion module includes a control module, a counting module, and a first data buffer; the generation of the first target data signal based on the data signal with the first width includes: The counting module counts the data cycles of the target bus and transmits the count value to the control module; The first data buffer stores the data signal of at least one data cycle transmitted by the target bus; The control module reaches a target count value based on the count value, generates a first target data signal based on the data signal of at least one data period stored in the first data buffer, and outputs a periodic valid signal of the first target data signal.

17. The data processing method according to claim 16, characterized in that, The bus expansion module further includes a clock module; the data processing method further includes: Under the control of the control module, the clock module multiplies the clock signal transmitted on the target bus to generate a target clock signal.

18. The data processing method according to claim 16, characterized in that, The bus expansion device further includes a cryptographic control module; the data processing method further includes: The cryptographic control module generates a cryptographic control signal based on the first target data signal, and the cryptographic control signal is configured to control the target cryptographic module.

19. The data processing method according to claim 18, characterized in that, The cryptographic control module includes an algorithm state machine and a second data buffer; the generation of the cryptographic control signal based on the first target data signal includes: The algorithm state machine transmits the first target data signal to the second data buffer based on the periodic valid signal of the first target data signal; The second data buffer, based on the control of the algorithm state machine, stores at least one of the first target data signals into the second data buffer and interacts with the target cryptographic module; The interaction with the target cryptographic module includes: The algorithm state machine sends the key data, length data, and cipher data of different data blocks in the second data buffer to the target cryptographic module; The algorithm state machine reads the data processed by the target cryptographic module after the target cryptographic module has finished processing the cryptographic data, and stores it in the second storage unit in the second data cache area. The step of generating a data signal with a first width based on the second target data signal includes: The control module reads the second target data signal from the target second storage unit in the second data buffer, and stores the second target data signal in the first storage unit in the first data buffer according to the first width format; the data in the first data buffer is available for reading by the host computer connected to the target bus.

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