Etching method of combined pattern

Abstract

The invention relates to an etching method of a combined pattern, which is applied to a semiconductor device, the semiconductor device comprises a substrate, and a conductive layer, a dielectric layer, a mask layer and a photoresist layer which are sequentially stacked on the substrate along a direction vertical to the substrate, the conductive layer comprises a plurality of metal electrodes, and the combined pattern comprises at least one groove and at least one through hole. The method comprises the following steps: etching a semiconductor device with target etching air pressure; and inputting a main etching gas and an inert gas in a target proportion to reduce the etching speed difference between the grooves or the through holes in the combined pattern, so that at least one metal electrode is exposed out of each groove or each through hole in the combined pattern. According to the method, the etching rate between the combined patterns can be balanced at least by means of the etching air pressure and the mode of inputting the main etching gas and the inert gas in the target proportion, great loads are prevented from appearing at grooves and / or through holes formed through etching, and the influence on key electrical data of a semiconductor device is also avoided.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device etching, and in particular to an etching method for a combined pattern. Background Art

[0002] With the advancement of semiconductor manufacturing technology, the etching of semiconductors requires a combination of grooves and through-holes, which are usually combined in the same layer or across multiple layers for etching to form a complex circuit structure.

[0003] In the related art, when etching the combined pattern, the etching of the groove is usually considered as the main consideration, and the combined pattern of the groove and the through hole is etched through an etching process of a large pattern such as the groove, and the combined pattern is formed through sufficient over-etching.

[0004] However, the use of a combined pattern etching method based on trench etching can easily cause a huge load to appear at the grooves and through-holes formed by etching. The presence of the huge load makes it impossible for conventional stop layer thin film deposition to cover it, which will seriously affect the key electrical data of the semiconductor device. Summary of the invention

[0005] Based on this, it is necessary to provide an etching method for a combined pattern to address the above-mentioned technical problems, which can at least reduce the etching speed difference between each pattern in the combined pattern by controlling the etching gas pressure, and further balance the etching rates between the combined patterns by inputting the target ratio of the main etching gas and the inert gas, thereby avoiding extremely high loads in the grooves and through holes formed by etching, and also avoiding the impact on the key electrical data of the semiconductor device.

[0006] In a first aspect, the present application provides a method for etching a combined pattern, which is applied to a semiconductor device, wherein the semiconductor device includes a substrate and a conductive layer, a dielectric layer, a mask layer and a photoresist layer stacked in sequence on the substrate along a direction perpendicular to the substrate, the conductive layer includes a plurality of metal electrodes, and the combined pattern includes at least one groove and at least one through hole; wherein the method includes: etching the semiconductor device at a target etching pressure; inputting a target ratio of a main etching gas and an inert gas to reduce the etching speed difference between each groove or through hole in the combined pattern, so that each groove or through hole in the combined pattern exposes at least one metal electrode.

[0007] In the etching method of the combined pattern of the above-mentioned embodiment, by controlling the etching gas pressure, reducing the concentration of the plasma and the intensity of bombarding the hard mask, the etching rate of the grooves in the combined pattern can be reduced, so that the etching rates of the grooves and through holes in the combined pattern reach a preliminary balance. On this basis, by adding inert gas as a protective gas, the main etching gas can be prevented from changing the electrical properties of the material during the etching process, thereby reducing etching-induced damage.

[0008] In one of the embodiments, the method further comprises: etching the semiconductor device at a target voltage so that the difference in etching load ratio between different positions in the semiconductor device is within a target range.

[0009] In the combined pattern etching method of the above embodiment, by controlling the etching voltage, it is possible to promote uniform distribution of plasma without affecting the formation of the combined pattern as much as possible, thereby reducing the difference in etching load ratio between different positions of the semiconductor device.

[0010] In one embodiment, the target etching pressure is determined by the following steps: obtaining etching rates of the combined patterns under different etching pressures; and determining the etching pressure when the etching rates between the combined patterns are closest as the target etching pressure.

[0011] In the etching method of the combined pattern of the above-mentioned embodiment, by obtaining the etching rate of the combined pattern under different etching pressures, the etching pressure when the etching rates of the grooves and through holes in the combined pattern are balanced is taken as the target etching pressure, so that when the semiconductor is etched at the target etching pressure, the etching rates of the grooves and through holes in the combined pattern are balanced.

[0012] In one of the embodiments, the semiconductor device further comprises a bottom anti-reflective coating, wherein the bottom anti-reflective coating is located between the photoresist layer and the mask layer; wherein the target ratio of the main etching gas and the inert gas is determined by the following steps: when removing the bottom anti-reflective coating, the etching rate difference between the combined patterns when the main etching gas and the inert gas have different input ratios is obtained; and the input ratio between the main etching gas and the inert gas when the etching rate difference between the combined patterns is minimized is determined as the target ratio of the main etching gas and the inert gas.

[0013] In the etching method of the combined pattern of the above embodiment, the etching gas ratio when the etching rates of the grooves and the through holes in the combined pattern reach a balance when removing the bottom anti-reflective coating is determined as the target ratio of the main etching gas and the inert gas, so that when the target ratio of the main etching gas and the inert gas is input to remove the bottom anti-reflective coating, the etching rates of the grooves and the through holes in the combined pattern reach a balance.

[0014] In one embodiment, the main etching gas is hydrogen and the inert gas is nitrogen.

[0015] In the etching method of the combined pattern of the above embodiment, hydrogen is used as the main etching gas, which can inhibit the volatilization of polymer during the etching process to reduce the reaction rate, inhibit the etching speed of silicon, greatly increase the selectivity of silicon dioxide to silicon, and balance the etching rate difference between the grooves and through holes in the combined pattern. Nitrogen is used as an inert gas to prevent the hydrogen atoms generated during the etching process from changing the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing the critical size.

[0016] In one embodiment, the target ratio between the main etching gas and the inert gas is between 1 and 1 / 2.

[0017] In the etching method of the combination pattern of the above-mentioned embodiment, by limiting the target ratio between the main etching gas and the inert gas, when etching the combination pattern, a gas that can inhibit the volatilization of the polymer is added to reduce the reaction rate, while inhibiting the etching speed of silicon, greatly increasing the selectivity of silicon dioxide to silicon, balancing the etching rate difference between the grooves and through holes in the combination pattern, and preventing the main etching gas generated during the etching process from changing the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing critical dimensions.

[0018] In one embodiment, the target etching pressure is 30 mT-90 mT.

[0019] In the etching method of the combined pattern of the above embodiment, by limiting the target etching gas pressure, the plasma concentration is reduced and the intensity of bombarding the hard mask is slowed down when etching the combined pattern, thereby slowing down the etching speed of the grooves in the combined pattern, so that the etching rates of the grooves and through holes in the combined pattern are balanced.

[0020] In one embodiment, the target voltage is 150V-300V.

[0021] In the etching method of the combined pattern of the above embodiment, by limiting the target voltage, the difference in etching load ratio between different positions in the semiconductor device can be reduced. Without affecting the combined pattern load, the limitation of the target voltage can be used as an auxiliary to further promote the uniform distribution of plasma.

[0022] In one of the embodiments, the method further includes: etching with a target low-frequency power semiconductor device to reduce the etching speed difference between each pattern in the combined pattern.

[0023] In the etching method of the combined pattern of the above embodiment, when etching the semiconductor device at the target etching gas pressure, the target low-frequency power is added to further reduce the concentration of the plasma and slow down the intensity of bombarding the hard mask, so that the etching rates of the grooves and through holes in the combined pattern are further balanced.

[0024] In one embodiment, the target low frequency power is 0W-200W.

[0025] In the combined pattern etching method of the above embodiment, the etching rate of the grooves in the combined pattern is further weakened by reducing the low-frequency power for etching the combined pattern, reducing the concentration of plasma during etching and the intensity of bombarding the hard mask.

[0026] The above-mentioned combined pattern etching method reduces the etching speed difference between each pattern in the combined pattern by controlling the etching gas pressure, and further balances the etching rates between the combined patterns by inputting the target ratio of the main etching gas and the inert gas, thereby avoiding extremely large loads in the grooves and through holes formed by etching, and also avoiding the impact on the key electrical data of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic flow chart of an etching method for a combined pattern in one embodiment;

[0029] Figure 2 is a schematic flow chart of an etching method for a combined pattern in another embodiment;

[0030] Figure 3 is a comparative schematic diagram of etching of a combined pattern in one embodiment;

[0031] Figure 4 is a structural block diagram of an etching device for a combined pattern in one embodiment;

[0032] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment.

[0033] Figure numerals and descriptions: 10, first pattern; 20, second pattern; 30, third pattern; 40, fourth pattern; 50, polymer; 60, substrate; 70, dielectric layer; 80, mask layer; 90, photoresist layer; 11, metal layer; 100, target etching gas pressure control module; 200, reaction gas control module. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] Please refer to Figure 1 In an exemplary embodiment, a combined pattern etching method is provided, comprising the following steps S101 to S102. Wherein:

[0036] Step S101 , etching the semiconductor device at a target etching pressure.

[0037] Step S102 , inputting a target ratio of a main etching gas and an inert gas to reduce the etching speed difference between each pattern in the combined pattern.

[0038] It should be noted that in semiconductor etching, pattern loading refers to the effect of the distribution density or arrangement of the pattern on the wafer surface on the etching reaction rate during the etching process. Pattern loading affects the density distribution of the etching area. For example, on the wafer surface, if there are a large number of open areas (unprotected areas) and fewer pattern areas (such as areas covered by metal or photoresist), the reaction rate and etching rate of these areas may be different. Pattern loading usually refers to the ratio between the pattern area (area covered by photoresist or other materials) and the non-pattern area (exposed material area). The denser the pattern, the more reaction areas there are, which may cause the etching rate in some areas to increase or decrease, especially when the etching gas concentration is uneven or the physical and chemical reaction conditions are inconsistent, the difference in etching rate is more obvious.

[0039] In particular, when the morphologies and sizes of the combined patterns differ greatly, there are great differences in the extraction of a large amount of polymer generated by etching the lower dielectric layer from different combined patterns, and the etching rates of the combined patterns with large size differences themselves vary greatly, thus forming a huge load between the grooves and the through holes.

[0040] Furthermore, when etching the combined pattern, it is very easy to have a huge etching load at the grooves and through holes in the combined pattern, and at the same time, there is also a huge load between different etching positions (for example, the center of the semiconductor device, the edge of the semiconductor device). The superposition of the double load makes it difficult to eliminate the situation. The existence of this huge load makes it impossible for the conventional stop layer film to be covered, resulting in excessive etching at the grooves and insufficient etching of the through holes, which seriously affects the subsequent key electrical data such as Rc. The solution of the prior art is to consider the etching of the grooves of the combined pattern as the main method, and etch the combined pattern through the etching process of a large pattern such as a single groove. It is mainly considered that under the premise of sufficient etching plasma for the large pattern, sufficient over-etching can also open the through hole in the combined pattern. In the way of the prior art, the combined pattern is formed by sufficient over-etching. However, different patterns have very different selectivities for the same etching gas and etching pressure. Therefore, simply increasing the over-etching may accelerate the etching of the groove pattern where the polymer is easily extracted, and the small through hole pattern may even be insufficiently etched, which further increases the load.

[0041] The present application controls the etching gas pressure, reduces the concentration of plasma and the intensity of bombarding the hard mask, and can reduce the etching rate of the grooves in the combined pattern, so that the etching rates of the grooves and through holes in the combined pattern reach a preliminary balance. On this basis, when removing the bottom anti-reflective coating, by adding an inert gas as a protective gas, the main etching gas can be prevented from changing the electrical properties of the material during the etching process, thereby reducing etching-induced damage.

[0042] Here, the present application first considers the improvement of the etching load between the grooves and through holes in the combined pattern, which is the most difficult to balance, so that the semiconductor device can be etched at a target etching gas pressure, and when removing the bottom anti-reflective coating, the main etching gas and inert gas are input in a target ratio. This process can achieve the etching load required by the process when etching the semiconductor device.

[0043] Specifically, the target etching pressure can be determined by the following steps: obtaining the etching rates of the combined patterns under different etching pressures; and determining the etching pressure when the etching rates between the combined patterns are closest as the target etching pressure.

[0044] In the etching method of the combined pattern of the above-mentioned embodiment, by obtaining the etching rate of the combined pattern under different etching pressures, the etching pressure when the etching rates of the grooves and through holes in the combined pattern are balanced is taken as the target etching pressure, so that when the semiconductor is etched at the target etching pressure, the etching rates of the grooves and through holes in the combined pattern are balanced.

[0045] Specifically, the target etching pressure is between 30mT and 90mT.

[0046] As an example, the target etching gas pressure may be 30 mT, 40 mT, 50 mT, 60 mT, 80 mT, 90 mT, and so on.

[0047] In the etching method of the combined pattern of the above embodiment, by limiting the target etching gas pressure, the plasma concentration is reduced and the intensity of bombarding the hard mask is slowed down when etching the combined pattern, thereby slowing down the etching speed of the grooves in the combined pattern, so that the etching rates of the grooves and through holes in the combined pattern are balanced.

[0048] Specifically, the target ratio of the main etching gas and the inert gas can be determined by the following steps: when removing the bottom anti-reflective coating, the etching rate difference between the combined patterns when the main etching gas and the inert gas are input at different ratios is obtained; and the input ratio between the main etching gas and the inert gas when the etching rate difference between the combined patterns is minimized is determined as the target ratio of the main etching gas and the inert gas.

[0049] Wherein, the semiconductor device further comprises a bottom anti-reflection coating, and the bottom anti-reflection coating is located between the photoresist layer and the mask layer.

[0050] Wherein, the main etching gas is hydrogen and the inert gas is nitrogen.

[0051] Here, using hydrogen as the main etching gas can inhibit the volatilization of polymer during the etching process to reduce the reaction rate, inhibit the etching speed of silicon, greatly increase the selectivity of silicon dioxide to silicon, and balance the etching rate difference between the grooves and through holes in the combined pattern. Using nitrogen as an inert gas can prevent the hydrogen atoms generated during the etching process from changing the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing critical dimensions.

[0052] Specifically, the target ratio between the main etching gas and the inert gas is between 1 and 1 / 2.

[0053] As an example, the target ratio between the main etching gas and the inert gas is 1, 3 / 4, 4 / 5, 1 / 2, and so on.

[0054] Here, on the basis of determining the target etching pressure, when removing the bottom anti-reflective coating (BARC), the present application uses hydrogen as the main etching gas to inhibit polymer volatilization and reduce the reaction rate, inhibit the etching speed of silicon, greatly increase the selectivity of silicon dioxide to silicon, balance the etching rate difference between the groove and the through hole, and use nitrogen as a protective gas to prevent the hydrogen atoms generated during the etching process from changing the electrical properties of the material, thereby reducing etching induced damage and achieving the effect of reducing critical dimensions.

[0055] Experiments have shown that the ratio of hydrogen as the main etching gas and nitrogen as the inert gas must be maintained within a certain range. After many adjustments, it was found that a better trend was achieved when the ratio of hydrogen to nitrogen was 1:1. When the ratio of hydrogen to nitrogen was adjusted to 1:2, the control of key dimensions was better.

[0056] In the above-mentioned etching method of the combined pattern, the etching gas pressure is controlled to reduce the difference in etching speed between each pattern in the combined pattern, and the etching rates between the combined patterns are further balanced by inputting the target ratio of the main etching gas and the inert gas, thereby avoiding extremely high loads in the grooves and through holes formed by etching, and also avoiding the impact on the key electrical data of the semiconductor device.

[0057] Here, it should be noted that when etching a combined pattern, not only is pattern loading very likely to occur, but also extremely large loading is likely to occur between different positions, such as W / C loading, W / E loading, and the like.

[0058] Among them, W / C loading refers to the loading of the pattern at the center of the semiconductor device during etching; W / E loading refers to the loading of the pattern at the edge of the semiconductor device during etching. While reducing the pattern loading of the combined pattern, reducing the loading between different positions is also very important for improving the electrical data of the semiconductor device.

[0059] The present application improves the etching loads at different positions of the semiconductor device by adjusting the etching pressure and etching gas to improve the etching loads at different positions at different positions of the semiconductor device.

[0060] As an example, see Figure 2 In an exemplary embodiment, a combined pattern etching method is provided, comprising the following steps S201. Wherein:

[0061] S201, etching the semiconductor device at a target voltage so that the difference in etching load ratio between different positions in the semiconductor device is within a target range.

[0062] In this way, by controlling the etching voltage, it is possible to promote uniform distribution of plasma without affecting the formation of the combined pattern as much as possible, thereby reducing the difference in etching load ratios between different positions of the semiconductor device.

[0063] Here, the present application, without affecting the combined pattern load, uses voltage reduction as an aid. After improving the most difficult to balance etching load between the groove and the through hole in the combined pattern, the etching load of patterns at different positions is balanced by adjusting the voltage, so that the plasma is more evenly distributed on the surface of the entire semiconductor device, eliminating the double superimposed etching load.

[0064] Specifically, the target voltage is 150V-300V.

[0065] As an example, the target voltage may be 150V, 180V, 200V, 250V, 300V, etc.

[0066] Here, it should be noted that the voltage range of the target voltage of the present application is significantly smaller than the etching voltage under normal etching conditions. The present application limits the voltage and reduces the voltage intervention, so that the plasma is more evenly distributed on the surface of the entire wafer, which can improve the loading of W / C and W / E, and eliminate the double superimposed combination pattern loading and loading at different positions.

[0067] In some embodiments, the method further includes: etching with a target low-frequency power semiconductor device to reduce the etching speed difference between each pattern in the combined pattern.

[0068] Specifically, the target low frequency power is 0w-200w.

[0069] As an example, the target low frequency power may be 0w, 50w, 150w, 180w, 200w, and so on.

[0070] Here, the target low-frequency power of the present application is significantly lower than the normal low-frequency power. By reducing the etching gas pressure and lowering the low-frequency power, the concentration of the plasma and the intensity of bombarding the hard mask can be reduced, and the effect of the excessive etching rate of the groove pattern can be weakened.

[0071] Furthermore, the reduction of low-frequency power can also extend the life of the parts in the cavity.

[0072] As an example, see Figure 3 In an exemplary embodiment, a comparative schematic diagram of etching a combined pattern is provided. Figure 3 Figure a in the figure is a schematic diagram of a structure obtained by etching a combined pattern using the prior art. Figure 3 Figure b is a schematic diagram of the structure obtained by etching the combined pattern in the present application, the first pattern 10 is a groove, the second pattern 20 is a groove, the third pattern 30 is a through hole, and the fourth pattern 40 is a groove.

[0073] Among them, the etching method of the combined pattern proposed in the present application is applied to a semiconductor device, which includes a substrate 60 and a conductive layer 11, a dielectric layer 70, a mask layer 80 and a photoresist layer 90 stacked in sequence on the substrate along a direction perpendicular to the substrate, the conductive layer 11 includes multiple metal electrodes, and the combined pattern includes at least one groove and at least one through hole.

[0074] Exemplarily, the dielectric layer may be an oxide layer, a dielectric layer, a combination layer of an oxide layer and a dielectric layer, etc., wherein the oxide layer may be silicon dioxide (SiO2) or the like, and the dielectric layer may be TEOS (tetraethoxysilane), BPSG (Boro-phospho-silicate Glass), BD (low-K material), SIN (silicon nitride), SION (silicon oxynitride), etc.

[0075] like Figure 3 As shown in Figure a, when the semiconductor device is etched using the prior art, the etching rate of the groove is much higher than the etching rate of the through hole, and the prior art increases the etching of the through hole by over-etching the groove, speeding up the etching of the groove pattern where the polymer is easily extracted, and the small through hole pattern may even be under-etched, further increasing the load. Among them, the polymer in the first pattern 10, the second pattern 20, and the fourth pattern 40 is less, and the polymer in the third pattern 30 is seriously accumulated, resulting in the third pattern 30 still unable to reach the etching position even when the first pattern 10, the second pattern 20, and the fourth pattern 30 are all over-etched.

[0076] Please refer to Figure 3 In Figure b, when the semiconductor device is etched with the target gas pressure and the target ratio of the main etching gas (hydrogen) and the inert gas (nitrogen) is input when removing the bottom anti-reflective coating, the polymers in the first pattern 10, the second pattern 20, the third pattern 30, and the fourth pattern 40 are relatively uniform, and the hydrogen suppresses the volatilization rate of the polymer in the groove pattern. Under the action of the target gas pressure, the etching rates of the grooves and the through holes in the combined pattern reach a certain balance, the etching rate of the grooves is reduced, and the etching rate of the through holes is increased, so that when the grooves are etched to their target positions, the through holes can also reach the target positions, reducing the load. At the same time, adding inert gas as a protective gas can prevent the main etching gas from changing the electrical properties of the material during the etching process, thereby reducing etching-induced damage.

[0077] In the process of combined pattern etching of the present application, first, it is necessary to consider the improvement of the pattern load between the groove and the through hole. By reducing the etching gas pressure, reducing the low-frequency power, reducing the concentration of the plasma and the intensity of bombarding the hard mask, the influence of the excessive etching rate of the groove pattern on the pattern load can be weakened; secondly, when removing the bottom anti-reflective coating, by inputting the target ratio of the main etching gas and the inert gas to balance the etching rate between the combined patterns, the addition of hydrogen can inhibit the volatilization of the polymer, reduce the reaction rate, inhibit the etching speed of silicon, greatly increase the selectivity of silicon dioxide to silicon, and further balance the rate difference of the groove and through hole etching; after improving the pattern load, the voltage should be adjusted slightly without affecting the pattern loading, so as to weaken the voltage as an aid to promote the uniform distribution of the plasma.

[0078] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0079] Based on the same inventive concept, the embodiment of the present application also provides an etching control device for a combined pattern for implementing the etching method for a combined pattern involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the etching control device for one or more combined patterns provided below can refer to the limitations of the etching control method for a combined pattern above, and will not be repeated here.

[0080] Please refer to Figure 4In an exemplary embodiment, an etching control device for a combined pattern is provided, which is applied to a semiconductor device. The semiconductor device includes a substrate and a conductive layer, a dielectric layer, a mask layer and a photoresist layer stacked in sequence on the substrate along a direction perpendicular to the substrate, the conductive layer includes a plurality of metal electrodes, and the combined pattern includes at least one groove and at least one through hole. The etching control device for the combined pattern includes: a target etching pressure control module 100 and a reaction gas control module 200. The target etching pressure control module 100 is used to etch the semiconductor device at a target etching pressure; the reaction gas control module 200 is used to input a target ratio of a main etching gas and an inert gas when removing a bottom anti-reflective coating, so as to reduce the etching speed difference between each pattern in the combined pattern.

[0081] Each module in the etching control device of the above-mentioned combination pattern can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0082] In an exemplary embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a method for controlling etching of a combined pattern is implemented. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0083] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0084] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0085] Etching the semiconductor device at a target etching pressure;

[0086] A target ratio of main etching gas and inert gas is input to reduce the etching speed difference between each groove or through hole in the combined pattern, so that each groove or through hole in the combined pattern exposes at least one metal electrode.

[0087] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0088] Etching the semiconductor device at a target etching pressure;

[0089] A target ratio of main etching gas and inert gas is input to reduce the etching speed difference between each groove or through hole in the combined pattern, so that each groove or through hole in the combined pattern exposes at least one metal electrode.

[0090] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0091] Etching the semiconductor device at a target etching pressure;

[0092] A target ratio of main etching gas and inert gas is input to reduce the etching speed difference between each groove or through hole in the combined pattern, so that each groove or through hole in the combined pattern exposes at least one metal electrode.

[0093] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0094] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0095] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for etching a combined pattern, characterized in that: Applied in a semiconductor device, the semiconductor device comprises a substrate and a conductive layer, a dielectric layer, a mask layer and a photoresist layer stacked in sequence on the substrate in a direction perpendicular to the substrate, the conductive layer comprises a plurality of metal electrodes, and the combined pattern comprises at least one groove and at least one through hole; Wherein, the method comprises: Etching the semiconductor device at a target etching pressure; A target ratio of main etching gas and inert gas is input to reduce the etching speed difference between each groove or through hole in the combined pattern, so that each groove or through hole in the combined pattern exposes at least one metal electrode.

2. The method according to claim 1, characterized in that The method further comprises: The semiconductor device is etched at a target voltage so that the difference in etching load ratio between different positions in the semiconductor device is within a target range.

3. The method according to claim 1, characterized in that Determine the target etching gas pressure by following the steps below: Obtaining the etching rate of the combined pattern under different etching gas pressures; The etching pressure when the etching rates between the combined patterns are closest is determined as the target etching pressure.

4. The method according to claim 1, characterized in that: The semiconductor device further comprises a bottom anti-reflective coating, wherein the bottom anti-reflective coating is located between the photoresist layer and the mask layer; Wherein, the target ratio of the main etching gas to the inert gas is determined by the following steps: When removing the bottom anti-reflection coating, obtaining the etching rate difference between the combined patterns when different input ratios of the main etching gas and the inert gas are used; The input ratio between the main etching gas and the inert gas when the etching rate difference between the combined patterns is the smallest is determined as the target ratio between the main etching gas and the inert gas.

5. The method according to claim 1 or 4, characterized in that: The main etching gas includes hydrogen, and the inert gas includes nitrogen.

6. The method according to claim 1 or 4, characterized in that: The target ratio between the main etching gas and the inert gas is between 1 and 1 / 2.

7. The method according to claim 1, characterized in that The target etching pressure is 30mT-90mT.

8. The method according to claim 2, characterized in that: The target voltage is 150V-300V.

9. The method according to claim 1, characterized in that: The method further comprises: The semiconductor device is etched at a target low frequency power to reduce the etching speed difference between each pattern in the combined pattern.

10. The method according to claim 1, characterized in that The target low frequency power is 0w-200w.

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