Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes a step of determining, after a wire bonding step, a quality with respect to all ends of a wire being located or not within a bonding region. The semiconductor chip includes a plurality of position determination opening patterns arranged in a region around a main opening portion including a bonding region in a plan view. The bonding region has a rectangular shape having an area smaller than an opening area of the main opening portion in plan view. The bonding area is defined by a plurality of position-determining opening patterns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-184134 filed on October 26, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Laid-Open Patent Application Publication No. H2-90634

[0006] Patent Document 1 discloses a technology related to a semiconductor device including a bonding pad having an alignment mark formed of a slit or a protrusion corresponding to a positioning cross mark of a wire bonding machine. Summary of the invention

[0007] One of the performance indicators required of semiconductor devices is reliability. The reliability of a semiconductor device is the ability of the semiconductor device to continue to perform functions predefined in specifications, etc., within a predefined period of time.

[0008] For example, there is a semiconductor device in which a wire is connected to a pad formed on the main surface of a semiconductor chip. In this semiconductor device, due to misalignment of the bonding position of the connecting wire, characteristic fluctuation may occur.

[0009] If the misalignment of the bonding position can be detected quickly, semiconductor devices that have already experienced characteristic fluctuations due to the misalignment can be selectively excluded. Therefore, only semiconductor devices whose misalignment is within the allowable range, that is, only reliable semiconductor devices, can be selected as non-defective products.

[0010] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] The method for manufacturing a semiconductor device according to an embodiment includes a step of determining the quality of all bonding portions of the wire being located or not located in a bonding region after a wire bonding step. The semiconductor chip includes a plurality of position determination opening patterns, which are arranged in a region around a main opening portion including a bonding region. The bonding region has a rectangular shape, and the area of ​​the rectangular shape in a plan view is smaller than the opening area of ​​the main opening portion. The bonding region is defined by a plurality of position determination opening patterns and a second position determination opening pattern.

[0012] A semiconductor device according to another embodiment includes a main surface, a pad formed on the main surface, an insulating film, and a plurality of position determination opening patterns, in which an opening portion for exposing a portion of the pad is formed, the plurality of position determination opening patterns being arranged in a region around the main opening portion in a plan view. The plurality of position determination opening patterns include a first position determination opening pattern arranged at a position of a first corner portion among a first corner portion, a second corner portion, a third corner portion, and a fourth corner portion closest to the main opening portion, and a second position determination opening pattern arranged at a position of a third corner portion or a fourth corner portion among the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion closest to the main opening portion.

[0013] According to the above embodiments, the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing a circuit configuration example of a semiconductor device including a power transistor and a control circuit that controls the power transistor.

[0015] Figure 2 It is shown Figure 1 A perspective plan view of an example of a structure of a semiconductor device is shown.

[0016] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA.

[0017] Figure 4 It is shown Figures 1 to 3 A flow chart of an example of a manufacturing process of a semiconductor device is shown.

[0018] Figure 5 It is shown in Figure 4 An enlarged plan view of a portion of a lead frame prepared in a lead frame preparation step is shown.

[0019] Figure 6 is Figure 4 A plan view (top view) of a semiconductor chip prepared in the semiconductor chip preparation step.

[0020] Figure 7 is Figure 4 The semiconductor chip preparation step prepared in Figure 6 Plan views (top views) of different semiconductor chips.

[0021] Figure 8 It is along Figure 6 An enlarged cross-sectional view taken along line BB.

[0022] Fig. 9 It is shown Figure 4 An explanatory diagram showing an example of detailed steps of the wire bonding step shown.

[0023] Fig.10 It is schematically shown Figure 4 FIG. 1 is an explanatory diagram of a configuration example of a wire bonding device used in the wire bonding step shown.

[0024] Fig.11 is an enlarged cross-sectional view showing a first bonding step of a wire forming step.

[0025] Fig.12 is a plan view schematically showing the operation of the wedge tool in the bent portion forming step of the wire forming step.

[0026] Fig.13 It is shown in Fig. 9 An explanatory diagram of an example of an image displayed on a monitor when "teaching" is performed in the step of identifying the bonding area.

[0027] Fig.14 It is shown in Figure 4 An explanatory diagram of an example of an image displayed on a monitor in the quality determination step shown.

[0028] Fig.15 It is shown Figure 4 An explanatory diagram showing details of the quality determination steps shown.

[0029] Fig.16 is shown as Fig.13 An enlarged plan view of an area around a main opening portion of a semiconductor chip of a modification.

[0030] Fig.17 It is along Figure 6 An enlarged cross-sectional view taken along line CC.

[0031] Fig.18 It is shown Fig.17 An enlarged cross-sectional view of a variation of .

[0032] Fig.19 It is shown Fig.13 An enlarged plan view of another variation of .

[0033] Fig. 20 It is shown Fig.13 An enlarged plan view of another variation of .

[0034] Fig.21 It is shown Fig.13 An enlarged plan view of another variation of .

[0035] Fig. 22 It is shown Fig.10 A block diagram of a configuration example of a determination unit shown. DETAILED DESCRIPTION

[0036] <Description format, basic terms and usage in this application>

[0037] In this application, for convenience, the embodiments will be described in multiple sections, etc. when necessary. However, unless otherwise specified, these sections, etc. are not unrelated to each other, but are used as each part of a single example, and a part of an example is related to another example as part or all of a detail or a variation, regardless of the order of description. In addition, in principle, repeated descriptions of similar parts will be omitted. In addition, unless otherwise specified, or except for the case where the constituent elements are theoretically limited to this number or the constituent elements are obviously indispensable from the context, the constituent elements in this embodiment are not always indispensable.

[0038] Likewise, in the description of the embodiments and the like, the phrase "X is made of A" for materials, compositions and the like is not intended to exclude materials containing elements other than A, unless otherwise specified or unless it is clear from the context that this is not the case. For example, for a component, it means "X contains A as a main component". For example, "silicon member" and the like are not limited to pure silicon, and it is obvious that the silicon member includes a member made of a silicon-germanium (SiGe) alloy, a member made of a multi-component alloy containing silicon as a main component, and a member containing other additives and the like. Furthermore, when gold plating, a Cu layer, nickel plating and the like are mentioned, unless otherwise clearly specified, it includes members containing gold, Cu, nickel and the like as main components, as well as pure members.

[0039] In addition, when a specific value or amount is mentioned, values ​​or amounts greater than or less than that specific value or amount also apply unless otherwise stated or unless the value or amount is logically limited to that specific value or amount and it is clear from the context that the value or amount is limited to that specific value or amount.

[0040] Furthermore, in the drawings of the embodiments, the same or similar components are denoted by the same or similar reference signs or reference numerals, and description thereof will not be repeated in principle.

[0041] Furthermore, in the drawings, in the case where the shading rather complicates the drawings or the distinction from the blank is obvious, the shading may be omitted even in the cross section. In connection with this, when it is clear from the description, etc., the outline of the background may be omitted even for a hole closed by a plane. Furthermore, even in the case other than the cross section, a shading or dot pattern may be applied to clarify that a part is not a blank space or to clearly illustrate the boundary between areas.

[0042] In the embodiments described below, a power device or a power semiconductor device referred to as being incorporated into a power control circuit such as a power supply circuit will be described as an example of a semiconductor device. The semiconductor device described below is incorporated into a power conversion circuit and functions as a switching element. In addition, a transistor incorporated into a switching circuit for power conversion, etc. is referred to as a power transistor.

[0043] <Configuration example of power transistor and control circuit>

[0044] Figure 1 is a diagram showing a circuit configuration example of a semiconductor device including a power transistor and a control circuit that controls the power transistor. Figure 1 The power transistor shown is, for example, a power metal oxide semiconductor field effect transistor (MOSFET).

[0045] As a power transistor, a modification can be applied to replace the power MOSFET. For example, the technology described below can be widely applied to semiconductor devices using an insulated gate bipolar transistor (IGBT) as a power transistor. In this case, the "source" described below is applied while being replaced with "emitter".

[0046] exist Figure 1 In the embodiment of the present invention, the semiconductor device PKG1 includes a switch circuit CSW and a control circuit CCT. The switch circuit CSW includes a main transistor TrM as a power transistor, a sense transistor TrS, and a temperature sensor TS.

[0047] In the switch circuit CSW, the main transistor TrM is provided between the lead 44 as a power terminal for providing a power supply potential and the lead 41 (or the lead 47) as an output terminal. The main transistor TrM functions as a switching element for turning on and off the current flowing between the power terminal and the output terminal.

[0048] On the other hand, the sense transistor TrS has a function of detecting the current value of the current flowing through the main transistor TrM. Furthermore, the temperature sensor TS has a function of detecting the temperature of the switch circuit CSW.

[0049] In addition, the control circuit CCT has a function of controlling the switch circuit CSW. The control circuit CCT includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor TrM and the gate electrode of the sense transistor TrS. Figure 1 In the figure, the control circuit CCT is electrically connected to leads 43 and 46 which are input terminals of the semiconductor device PKG1, lead 42 which is a ground terminal, and lead 45 which is an output terminal for outputting the output of the control circuit CCT to the outside of the semiconductor device PKG1.

[0050] The control circuit CCT is configured to control the turning on and off of the main transistor TrM included in the switch circuit CSW based on the control signal input from the lead 43. That is, the control circuit CCT controls the turning on and off of the main transistor TrM by switching the gate voltage applied to the gate electrode of the main transistor TrM. By controlling the turning on and off of the main transistor TrM in this way, the current supplied from the lead 41 as the output terminal electrically connected to the source of the main transistor TrM to the load connected to the outside of the semiconductor device PKG1 can be controlled.

[0051] <Semiconductor devices>

[0052] Next, we will describe Figure 1 An example of the structure of a semiconductor device PKG1 is shown. Figure 2 It is shown Figure 1 A perspective plan view of an example of a structure of a semiconductor device is shown. Figure 3 It is along Figure 2 Note that in order to illustrate an example of the component layout of the semiconductor device PKG1, the semiconductor device PKG1 is shown in a perspective plan view, in which Figure 3 The sealing body 60 shown in the figure shows the semiconductor device PKG1. Figure 2 The semiconductor chip 30 shown is not present along the Figure 2 In the cross section taken by line AA, Figure 3 The outline of the semiconductor chip 30 and the insulating adhesive DT for bonding and fixing the semiconductor chip 30 to the semiconductor chip 10 are indicated by dotted lines. Figure 2 and Figure 3 Indicated by double dotted line Figure 1 The position where the sensing transistor TrS is formed is shown.

[0053] Figure 2 and Figure 3 The X direction is shown (see Figure 2 ), Y direction and Z direction (see Figure 3 ). The Y direction is an edge intersecting with the X direction, and in the following description, the X direction and the Y direction are perpendicular to each other. The Z direction is a direction perpendicular to each of the X direction and the Y direction. In other words, the Z direction is a normal direction relative to an XY plane including the X direction and the Y direction. In the following description, "thickness" refers to the length in the Z direction in principle. In addition, in the following description, "plan view" refers to a plan view viewing the XY plane in principle.

[0054] like Figure 2 and Figure 3As shown, the semiconductor device PKG1 according to the present embodiment includes a semiconductor chip 10, a die pad (metal plate, chip mounting portion, or heat sink) 20 on which the semiconductor chip 10 is mounted, and a semiconductor chip 30 (see Figure 2 ), multiple leads (terminals) 40 as external terminals and multiple wires 50.

[0055] like Figure 3 As shown, the semiconductor device PKG1 further includes a sealing body 60. The semiconductor chip 10, the semiconductor chip 30, and each of the plurality of wires 50 are sealed by the sealing body 60. In addition, the semiconductor chip 10, the upper surface 20t of the die pad 20, and the inner lead portions (sealing portions) 40M of the plurality of leads 40 (see Figure 3 ) is sealed by the sealing body 60.

[0056] The die pad 20 has an upper surface (surface) 20t and a lower surface 20b located on a side opposite to the upper surface 20t. The die pad 20 is a chip mounting member for mounting the semiconductor chip 10. Figure 3 In the example shown, the lower surface 20b of the die pad 20 is exposed from the sealing body 60. The lower surface 20b of the die pad 20 exposed from the sealing body 60 is covered by a metal film 22. The metal film 22 is made of, for example, solder. Figure 2 As shown, the die pad 20 is connected to one (lead 44) ​​of the plurality of leads 40. More specifically, the lead 44 is formed integrally with the die pad 20.

[0057] The semiconductor chip 10 is mounted on the upper surface 20t of the die pad 20 via the die bonding material DB. The semiconductor chip 10 includes a power transistor (in this embodiment, Figure 1 The main transistor TrM shown).

[0058] like Figure 3 As shown, the semiconductor chip 10 has an upper surface (main surface, front surface, or surface) 10t and a lower surface (main surface, rear surface, or surface) 10b on the side opposite to the upper surface 10t. Figure 2 As shown, the semiconductor chip 10 has four sides (chip sides) 10s in a plan view. The four sides 10s include a side 10s1 extending in the X direction, a side 10s2 intersecting the side 10s1 and extending in the Y direction intersecting the X direction, a side 10s3 extending in the Y direction and located on a side opposite to the side 10s2, and a side 10s4 extending in the X direction and located on a side opposite to the side 10s1. The side 10s1 is a side of the four sides 10s of the semiconductor chip 10 that is arranged at a position closest to each of the plurality of leads 40 and extends in the X direction. Figure 2In the illustrated example, the semiconductor chip 10 has a rectangular shape in a plan view, and is arranged such that a side 10 s 1 and a side 10 s 4 , which are long sides, extend along the X direction.

[0059] like Figure 2 As shown, the semiconductor chip 10 includes a plurality of pads (electrodes or electrode pads) 10P. A portion of each of the plurality of pads 10P is exposed from an insulating film IF of the semiconductor chip 10 described later on an upper surface 10 t of the semiconductor chip 10 .

[0060] The plurality of pads 10P include a source pad 10P1 connected to a source of a power transistor. Figure 2 In the example shown, part of the source pad 10P1 is exposed from the insulating film IF at two locations on the upper surface 10t. The source pad 10P1 is connected to the lead 40 (at Figure 2 In the example shown, lead 41 or lead 47). The detailed structure around source pad 10P1 will be described later.

[0061] The plurality of pads 10P include a plurality of pads 10P2 electrically connected to the semiconductor chip 30 via the wire 52. The plurality of pads 10P2 include a gate pad connected to the gate of the power transistor. In addition, at least some of the plurality of pads 10P2 are electrically connected to the sensing transistor TrS. In addition, some of the plurality of pads 10P2 are electrically connected to the semiconductor chip 30. Figure 1 The temperature sensor TS is shown.

[0062] like Figure 2 As shown, among the plurality of pads 10P, the exposed area of ​​the source pad 10P1 is larger than the exposed area of ​​the other pads 10P2. More specifically, each of the source pad 10P1 and the other pads 10P2 is exposed from the insulating film IF from an opening portion formed in the insulating film IF. The opening area of ​​the opening portion in which the source pad 10P1 is exposed from the insulating film IF is larger than the opening area of ​​the opening portion in which the other pads 10P2 are exposed from the insulating film IF.

[0063] Source pad 10P1 constitutes a current path through which a larger current flows than other pads 10P2. From the viewpoint of increasing the cross-sectional area of ​​the path through which a large current flows and reducing the resistance value, it is preferable to use a wire having a wire diameter larger than that of other wires 52 as wire 51 connected to source pad 10P1. In addition, from the viewpoint of reducing the resistance of the bonding portion between wire 51 and source pad 10P1, it is preferable to increase the area of ​​the bonding portion between wire 51 and source pad 10P1. Therefore, the exposed area of ​​source pad 10P1 is preferably large.

[0064] like Figure 3 As shown, the semiconductor chip 10 includes a drain electrode DE formed on the lower surface 10b. In the present embodiment, as described above, the die pad 20 is connected to one of the plurality of leads 40 (the lead 44). In addition, the die bonding material DB is made of solder or a conductive resin (e.g., so-called silver paste), and the die pad 20 is electrically connected to the drain electrode DE. Therefore, in the case of the semiconductor device PKG1, the die pad 20 can be used as a current path. Even if a large current flows, by using the drain electrode DE formed on the entirety of the lower surface 10b of the semiconductor chip 10 and the die pad 20 as a current path, the resistance value of the current path connected to the drain of the power transistor can be reduced.

[0065] like Figure 2 and Figure 3 As shown, the semiconductor chip 30 is mounted on the upper surface 10t of the semiconductor chip 10. The semiconductor chip 30 is connected to the upper surface 10t of the semiconductor chip 10 via an insulating adhesive DT (see Figure 3 ) is bonded and fixed to the upper surface 10t of the semiconductor chip 10.

[0066] The semiconductor chip 30 includes a control power transistor ( Figure 1 The control circuit CCT of the main transistor TrM shown (see Figure 1 ).

[0067] exist Figure 2 In the example shown, the semiconductor chip 30 is arranged between the two opening portions of the source pad 10P1 in a plan view. Figure 2 In the illustrated example, the mounting position of the semiconductor chip 30 includes the center of the upper surface 10 t in plan view.

[0068] The semiconductor chip 30 includes a plurality of pads (electrodes or electrode pads) 30P. Some of the plurality of pads 30P ( Figure 7 The plurality of pads 30P2 shown in the figure (which will be described later) are electrically connected to the pads 10P2 of the semiconductor chip 10 via the wires 52. The other pads ( Figure 7 The plurality of pads 30P3 shown in FIG. 1 (which will be described later) are connected to the leads 40 (at Figure 2 In the example shown, lead 42, lead 43, lead 45, and lead 46).

[0069] like Figure 3 As shown, the semiconductor chip 30 has an upper surface (main surface, front surface, or surface) 30 t and a lower surface (main surface, rear surface, or surface) 30 b on the side opposite to the upper surface 30 t.

[0070] The plurality of leads 40 are arranged along a side 10s1 extending along the X direction among the sides 10s of the semiconductor chip 10. Each of the plurality of leads 40 is connected to the semiconductor chip 10 or the semiconductor chip 30 via a wire 50.

[0071] like Figure 3 As shown, Figure 2 Each of the illustrated plurality of leads 40 includes an inner lead portion 40M sealed by a sealing body 60 and an outer lead portion (outer portion or exposed portion) 40X exposed from the sealing body 60 .

[0072] Each of the plurality of leads 40 has an upper surface 40t and a lower surface 40b. Each of the upper surface 40t of the outer lead portion 40X and the lower surface 40b of the outer lead portion 40X is covered with a metal film 48. The metal film 48 is made of, for example, solder.

[0073] Figure 2 The plurality of wires 50 shown include a wire 51 connected to the source pad 10P1 and the leads 41 and 47 of the semiconductor chip 10. One end of each of the plurality of wires 51 is connected to the corresponding source pad 10P1, and the other end thereof is connected to the wire bonding portion 40W (see FIG. 4 ) of the lead 41 (or the lead 47). Figure 3 ). The wire 51 is made of, for example, aluminum. The wire diameter of the wire 51 is larger than the wire diameters of the other wires 50 (wire 52 and wire 53). In other words, the wire 51 is wider than the other wires 50 (wire 52 and wire 53). Note that the width of the wire 50 mentioned here is the length in a direction perpendicular to the extending direction of the wire 50.

[0074] The plurality of wires 50 include a plurality of wires 52 connected to the pads 10P2 of the semiconductor chip 10 and the pads 30P of the semiconductor chip 30. One end of each of the plurality of wires 52 is connected to the corresponding pad 10P2, and the other end thereof is connected to the corresponding pad 30P.

[0075] The plurality of wires 50 includes a plurality of wires 53 connected to the pad 30P of the semiconductor chip 30 and one of the leads 42, 43, 45, and 46. One end of each of the plurality of wires 53 is connected to the corresponding pad 30P, and the other end thereof is connected to the wire bonding portion 40W of one of the leads 42, 43, 45, and 46 (see Figure 3 ).

[0076] Signal currents such as a control signal current and a signal current output from the sensing transistor TrS flow through the wires 52 and 53. Therefore, since the value of the current flowing through the wires 52 and 53 is smaller than the current value of the wire 51, the wire 50 having a smaller wire diameter than the wire 51 is used as the wires 52 and 53.

[0077] The sealing body 60 is mainly made of a thermosetting resin such as epoxy resin. In addition, in the present embodiment, in order to improve the characteristics of the sealing body 60 (e.g., expansion characteristics due to thermal effects), for example, filler particles such as silicon dioxide (silicon dioxide; SiO2) particles are mixed in the resin material.

[0078] <Method of Manufacturing Semiconductor Device>

[0079] Next, the manufacturing process will be described. Figures 1 to 3 A method for a semiconductor device is shown. Figure 4 It is shown Figures 1 to 3 FIG. 1 is a flow chart showing an example of a process for manufacturing a semiconductor device. Figure 4 In the example shown, the method for manufacturing a semiconductor device according to the present embodiment includes a lead frame preparation step, a semiconductor chip preparation step, a first semiconductor chip mounting step, a second semiconductor chip mounting step, a wire bonding step, a quality determination step, a sealing step, a solder film forming step, and a cutting step.

[0080] <Lead frame preparation step>

[0081] First, in Figure 4 In the lead frame preparation steps shown, the preparation Figure 5 Lead frame LF shown. Figure 5 It is shown in Figure 4 An enlarged plan view of a portion of a lead frame prepared in a lead frame preparation step is shown.

[0082] like Figure 5 As shown, the lead frame LF prepared in this step includes a plurality of device forming portions LFd connected to a frame portion LFf. Figure 5 Eight device forming parts LFd are shown. Each of the plurality of device forming parts LFd corresponds to Figure 1 A semiconductor device PKG1 is shown. The lead frame LF is a so-called multi-piece substrate in which a plurality of device forming portions LFd are arranged in a matrix form. Since a plurality of semiconductor devices PKG1 can be collectively manufactured by using the lead frame LF including the plurality of device forming portions LFd as described above (see Figure 1 ), so the manufacturing efficiency can be improved.

[0083] The lead frame LF is made of, for example, a metal material containing copper (Cu) as a main component. Each of the plurality of device forming portions LFd is connected to a corresponding frame portion LFf. The frame portion LFf is a supporting portion that supports each member formed in the device forming portion LFd until Figure 4 Cutting steps shown.

[0084] Figure 3 The die pad 20 and the plurality of leads 40 shown are formed in the device forming part LFd. The die pad 20 is connected to the corresponding frame part LFf via one of the plurality of leads 40 and is supported by the frame part LFf. Each of the plurality of leads 40 is connected to the corresponding frame part LFf and is supported by the frame part LFf.

[0085] Focusing on one of the plurality of device formation portions LFd, this step may be represented as a step of preparing a die pad having an upper surface 20t, ie, a die pad preparing step.

[0086] Furthermore, the plurality of leads 40 are connected to each other via corresponding tie bars LFt1. Figure 5 In the example shown, a plurality of die pads 20 are connected to each other via corresponding tie bars LFt2. Figure 5 As shown, the tie bar LFt2 is arranged on a side opposite to the plurality of leads 40 via the die pad 20 in the device forming portion LFd.

[0087] Notice, Figure 5 An example of a lead frame is shown, and the shape of the lead frame has various modifications. Figure 5 In the example shown, each of the plurality of leads 40 is connected to the corresponding frame portion LFf. In other words, the plurality of die pads 20 are arranged at a position farther from the corresponding frame portion LFf than the plurality of leads 40. Figure 5 In a variation of the lead frame shown, there is a case where the frame portion LFd is arranged between the device forming portions LFd adjacent to each other in the Y direction. In this case, in the Y direction, a plurality of leads 40 of the first device forming portion LFd are connected to one side of the frame portion LFf, and a plurality of leads 40 of the second device forming portion LFd are connected to the other side of the frame portion LFf (the side opposite to the above side in the Y direction). In this case, the tie bar LFt2 is arranged Figure 5 The frame portion LFf is located at the position shown, and a plurality of device forming portions LFd are arranged between the two tie bars LFt2.

[0088] <Semiconductor chip preparation step>

[0089] exist Figure 4 In the semiconductor chip preparation steps shown, the preparation Figure 6 The semiconductor chip 10 and Figure 7 A semiconductor chip 30 is shown. Figure 6 and Figure 7 Each of the Figure 4 A plan view (top view) of a semiconductor chip prepared in the semiconductor chip preparation step. Figure 8It is along Figure 6 An enlarged cross-sectional view taken along line BB.

[0090] about Figure 6 The semiconductor chip 10 and Figure 8 The semiconductor chip 30 shown in FIG. 1 is shown in FIG. Figure 6 In FIG. 1 , an extension line VL1 of the side OPS2 and an extension line VLS2 of the side OPS3 of the opening portion where a part of the source pad 10P1 is exposed are indicated by double-dashed lines. Figure 6 In FIG. 1 , the extension lines (extension line HL1 and extension line HL2) of the side OPS1 and the side OPS4 are indicated by double-dashed lines. These will be described later.

[0091] like Figure 7 As shown, the semiconductor chip 30 has four sides (chip sides) 30s in a plan view. The four sides 30s include a side 30s1 extending in the X direction, a side 30s2 intersecting the side 30s1 and extending in the Y direction intersecting the X direction, a side 30s3 extending in the Y direction and located on a side opposite to the side 30s2, and a side 30s4 extending in the X direction and located on a side opposite to the side 30s1. The side 30s1 is the side closest to the semiconductor chip 30 among the four sides 30s. Figure 2 The side at the position of each of the plurality of leads 40 shown and extending in the X direction. Figure 7 In the illustrated example, the semiconductor chip 30 has a rectangular shape in a plan view, and is arranged such that the side 30 s 2 and the side 30 s 3 , which are long sides, extend along the Y direction.

[0092] like Figure 8 As shown, the semiconductor chip 10 includes a main surface 11 t , pads 10P (eg, source pads 10P1 ) formed on the main surface 11 t , and an insulating film IF formed on the main surface 11 t .

[0093] exist Figure 8 In the example shown, the upper surface of the insulating layer 11 as the base layer of the source pad 10P1 corresponds to the main surface 11t. The insulating layer 11 is formed on the main surface of the semiconductor substrate. The insulating layer 11 is composed of, for example, silicon oxide. Although not shown, Figure 6 Each of the plurality of pads 10P2 shown is formed on the insulating layer 11. In addition, Figure 7 The semiconductor chip 30 shown includes Figure 8 The illustrated insulating layer 11 corresponds to an insulating layer, and each of the plurality of pads 30P is formed on the insulating layer.

[0094] In the present embodiment, the insulating film IF includes an inorganic insulating film CF formed on the main surface 11t and an organic insulating film OF formed on the inorganic insulating film CF. The inorganic insulating film PF is, for example, a silicon oxide film, a silicon nitride film, or a stacked film of these films. On the other hand, the organic insulating film OF is, for example, a resin film such as a polyimide resin film.

[0095] As a variation of this embodiment, there is a Figure 8 The organic insulating film OF shown is a case where the insulating film IF is composed of only the inorganic insulating film CF.

[0096] Since the organic insulating film OF has higher fluidity than the inorganic insulating film CF when formed, the organic insulating film OF is likely to be embedded in the unevenness of the surface of the base layer. Therefore, when the organic insulating film OF covering the inorganic insulating film CF is formed, the upper surface of the organic insulating film OF (in other words, the upper surface 10t of the semiconductor chip 10) becomes flat. Figure 2 As shown, in the present embodiment, the semiconductor chip 30 is mounted on the upper surface 10t of the semiconductor chip 10. When another device is mounted on the upper surface 10t of the semiconductor chip 10 as described above, the upper surface 10t of the semiconductor chip 10 is preferably flat.

[0097] When the insulating film includes an inorganic insulating film CF and an organic insulating film OF as in the present embodiment, an opening portion for exposing the source pad 10P1 from the insulating film IF is formed in each of the inorganic insulating film CF and the organic insulating film OF. The opening portion OPC is formed in the inorganic insulating film CF, and the opening portion OPO is formed in the organic insulating film OF.

[0098] The opening portion OPC formed in the inorganic insulating film CF is exposed from the organic insulating film OF through the opening portion OPO formed in the organic insulating film. Figure 8 As shown, the opening portion OPC and the opening portion OPO overlap each other in the thickness direction of the semiconductor chip 10. Therefore, in the opening portion OPC, part of the source pad 10P1 is exposed from the insulating film IF including the inorganic insulating film CF and the organic insulating film OF.

[0099] exist Figure 4 In the wire bonding step shown, Figure 2 The wire 51 shown is connected to a portion of the region (wire bonding region) of the source pad 10P1 that is exposed from the insulating film IF.

[0100] In this embodiment, the source pad 10P1 is located at multiple locations ( Figure 6 and Figure 7In the case of a structure in which a plurality of portions of one source pad 10P1 are exposed from the insulating film IF as described above, the area of ​​the source pad 10P1 can be increased. In some cases, during the operation of the power transistor, a large current flows through the source pad 10P1. Therefore, since the cross-sectional area of ​​the current path can be increased by increasing the area of ​​the source pad 10P1, this is preferable from the viewpoint of reducing the resistance of the current path.

[0101] Although not shown, as Figure 8 As a modification of the illustrated example, there is a case where source pads 10P1 separated from each other are formed at positions where opening portion OPC and opening portion OPO are formed.

[0102] <First Semiconductor Chip Mounting Step>

[0103] Next, in Figure 4 In the first semiconductor chip mounting step shown in FIG. Figure 2 The die bond material DB shown is mounted on the die pad 20. For example, in the step of mounting the semiconductor chip 10, the processes are performed in the following order.

[0104] First, the die bonding material DB is applied to the chip mounting area of ​​the die pad 20 (i.e., the planned area on which the semiconductor chip 10 is to be mounted) (die bonding material applying step). When the die bonding material DB is made of solder, a paste material (referred to as solder paste) containing a solder component, a flux component, and a resin component is applied in the die bonding material applying step. On the other hand, when the die bonding material DB is a conductive resin, a paste material (referred to as conductive resin paste) made of a resin mixed with a large amount of conductive particles is applied in the die bonding material applying step.

[0105] Next, the semiconductor chip 10 is pressed onto the applied paste material to bond the semiconductor chip 10 and the paste material (first semiconductor chip bonding step). Figure 2 As shown, the side 10s1 among the multiple sides 10s of the semiconductor chip 10 is along the arrangement direction of the multiple leads 40 ( Figure 2 The X direction in the figure is arranged.

[0106] Next, the die bonding material DB is cured to fix the semiconductor chip 10 on the die bonding material DB (die bonding material curing step). When the paste material applied in the die bonding material applying step is a solder paste, a reflow process is performed in this step. The reflow process is a process for heating the die bonding material DB until the temperature of the die bonding material DB becomes equal to or higher than the melting point of the solder component and then cooling the die bonding material DB. Through the reflow process, the solder component can be bonded to the metal material (in the present embodiment, the die pad 20 and the drain electrode DE of the semiconductor chip) which is in close contact with the die bonding material DB. In addition, since the solder component is Figure 4 In the state shown, the semiconductor chip 10 is cured, and thus the semiconductor chip 10 is fixed on the die pad 20 via the die bonding material DB.

[0107] The above-mentioned flux component is a surface activating component for increasing the surface activity of the solder component during the reflow process.

[0108] On the other hand, when the paste material applied in the die bonding material application step is a conductive resin paste, a curing / baking process is performed in this step. The curing / baking process is a process of performing heating until the temperature of the die bonding material DB becomes equal to or higher than the curing temperature of the thermosetting resin contained in the conductive resin. The curing / baking process is followed by a cooling step. Since the thermosetting resin component contained in the die bonding material DB is cured by performing the curing / baking process, the entire die bonding material DB is cured. Therefore, the semiconductor chip 10 is fixed on the die pad 20 via the die bonding material DB.

[0109] <Second Semiconductor Chip Mounting Step>

[0110] Next, in Figure 4 In the second semiconductor chip mounting step shown, Figure 3 As shown, the semiconductor chip 30 is mounted on the semiconductor chip 10 via the insulating adhesive DT. For example, in the step of mounting the semiconductor chip 30, the processes are performed in the following order.

[0111] Insulation Adhesive DT (See Figure 3 ) attached to Figure 4 The semiconductor chip 30 (see Figure 3 ) of the lower surface 30b (see Figure 3 ). The insulating adhesive DT includes an insulating adhesive that can be bonded to the semiconductor chip 30 and the semiconductor chip 10 (see Figure 3 ) and a thermosetting resin component that can be cured by heating. As described above, the adhesive material that can be attached to the semiconductor chip 30 in advance is called a die attach film.

[0112] In the second semiconductor chip mounting step, as Figure 3 As shown, the insulating adhesive DT attached to the lower surface 30b of the semiconductor chip 30 is attached to the upper surface 10t of the semiconductor chip 10 together with the semiconductor chip 30 (second semiconductor wafer attaching step).

[0113] In this step, if Figure 2 As shown, multiple sides 30s (see Figure 7 ) of the side 30s1 of the semiconductor chip 30 (see Figure 7 ) are arranged along the side 10s1 of the semiconductor chip 10.

[0114] Next, the insulating adhesive DT is cured to fix the semiconductor chip 30 on the semiconductor chip 10 (insulating adhesive curing step). In this step, a curing / baking process is performed. The curing / baking process is a process in which heating is performed until the temperature of the insulating adhesive DT becomes equal to or higher than the curing temperature of the thermosetting resin contained in the insulating adhesive DT. The curing / baking process is followed by a cooling step. Since the thermosetting resin component contained in the insulating adhesive DT is cured by performing the curing / baking process, the entire insulating adhesive DT is cured. Therefore, the semiconductor chip 30 is fixed on the semiconductor chip 10 via the insulating adhesive DT.

[0115] The curing / baking process described in the first semiconductor chip mounting step and the curing / baking process described in this step (second semiconductor chip mounting step) may be performed together after the second semiconductor chip mounting step. Figure 4 As shown by the dotted line in the figure, the curing / baking process can be Figure 4 The curing / baking step is performed after the wire bonding step shown (more specifically, after the quality determination step and before the sealing step). Figure 2 As shown, the semiconductor chip 30 is mounted near the plurality of pads 10P1 of the semiconductor chip 10. When gas is generated from the insulating adhesive DT during the curing / baking process and adheres to the surface of the pad 10P1, the electrical characteristics of the bonding portion between the wire 51 and the pad 10P1 may be affected. Therefore, from the perspective of improving the electrical reliability between the wire 51 and the pad 10P1, it is preferred to perform the curing / baking step after the wire bonding step.

[0116] <Wire bonding step>

[0117] Next, in Figure 4 In the wire bonding step shown, Figure 2As shown, the wire 50 is connected to each of the plurality of pads 10P of the semiconductor chip 10 and the plurality of pads 30P of the semiconductor chip 30. The wire bonding step includes a step of connecting the source pad 10P1 and the lead 40 (the lead 41 and the lead 47) via the wire 51, a step of connecting the pad 10P2 and the pad 30P via the wire 52, and a step of connecting the pad 30P and the lead 40 (the leads 42, 43, 45, and 46) via the wire 53.

[0118] As described above, since the signal current flows through the wire 52 and the wire 53, the wire 50 having a wire diameter smaller than the wire diameter of the wire 51 through which the large current flows is used as the wire 52 and the wire 53. Therefore, in the step of bonding the wire 52 and the wire 53, a ball bonding method using a capillary tool as a bonding tool (bonding head) can be used. On the other hand, a wedge bonding method using a wedge bonding tool is used as a bonding method for the wire 51.

[0119] The details of the wire bonding step, specifically, the step of connecting wire 51 to source pad 10P1 and the details of the quality determination step performed subsequently will be described later.

[0120] <Quality determination steps>

[0121] Next, in Figure 4 In the quality determination step shown, determine Figure 2 The end of the wire 51 shown is located or not located in the bonding region in the plan view. In this step, quality determination is performed on the position of the end portion of the wire 51 on one side of the source pad 10P1 that has been connected to the semiconductor chip 10 or the semiconductor chip 30 in the wire bonding step. The details of this step will be described later.

[0122] <Sealing Step>

[0123] Next, in Figure 4 In the sealing step shown, the semiconductor chip 10, a portion of the die pad 20, a portion of each of the plurality of leads 40 ( Figure 3 The inner lead portion 40M) shown in FIG. Figure 2 The plurality of wires 50 shown are sealed with insulating resin to form Figure 3 The sealing body 60 is shown.

[0124] In this step, for example, the sealing body 60 is formed by a so-called transfer molding method using a molding die including an upper die (first die) and a lower die (second die) (not shown). The lead frame LF is arranged so that Figure 5The die pad 20 in the device forming portion LFd shown and the inner lead portion 40M of each of the plurality of leads 40 (see Figure 3 ) is located in the cavity of the molding die. The lead frame LF is then sandwiched between the upper die and the lower die. When a softened (plasticized) thermosetting resin (insulating resin) is injected into the cavity of the molding die in this state, the insulating resin is molded into the shape of the cavity.

[0125] At this time, the upper surface 20t of the die pad 20 and a portion of the lower surface 20b of the die pad 20 are in close contact with the molding die. Figure 3 As shown, after this step, a portion of the upper surface 20 t and the lower surface 20 b of the die pad 20 are exposed from the sealing body 60 .

[0126] After the sealing body 60 is formed, heating is performed until a portion of the thermosetting resin contained in the sealing body 60 is cured (referred to as temporary curing). When the lead frame LF can be taken out from the molding die due to the temporary curing, the lead frame LF is taken out from the molding die. Then, the lead frame LF is transported to a heating furnace and further subjected to heat treatment (curing / baking). As a result, the remaining portion of the thermosetting resin is cured to obtain the sealing body 60.

[0127] <Solder Film Formation Step>

[0128] Next, in Figure 4 In the solder film forming step shown, the lead frame LF is immersed in a plating solution (not shown), and a metal film ( Figure 3 The metal film 22 and the metal film 48 are shown).

[0129] <Cutting steps>

[0130] Next, Figure 4 The cutting steps shown include cutting Figure 5 The tie bar cutting steps and cutting of the tie bar LFt1 shown Figure 5 The lead cutting step of the tip portion of each of the plurality of leads 40 is shown.

[0131] In the tie rod cutting step, cut Figure 5 The tie bar LFt1 is shown. In the tie bar cutting step, the tie bar LFt2 is also cut, and the plurality of die pads 20 connected via the tie bar LFt2 are separated. After this step, the plurality of leads 40 are connected via the frame portion LFf.

[0132] As a method of cutting the tie bars LFt1 and LFt2, punching (cutting) using a punch and a die (not shown) can be used. Since this step is performed after the solder film forming step, the side surface newly formed by cutting in this step is not covered by the metal film 48.

[0133] In the lead cutting step, the plurality of leads 40 are separated from each other by separating the plurality of leads 40 from the frame portion LFf. In this step, the tip portion of each of the plurality of leads 40 is cut by punching (cutting) using a punch and a die (not shown). The tip surface newly formed by cutting in this step is not covered with the metal film 48. By this step, Figure 5 The device forming part LFd shown is divided into blocks, and the Figure 1 The semiconductor device shown.

[0134] Through the above steps, we can obtain Figures 1 to 4 The semiconductor device PKG1 shown is shown. Thereafter, after performing a test or inspection (such as an electrical test or an appearance inspection) as required, the product determined to be a non-defective product is transported to the next step, such as a step of packaging the semiconductor device.

[0135] <Details of Wire Bonding Step>

[0136] Next, the details of the wire bonding step and the quality determination step will be described. Figure 2 The step shown is to connect the wire 51 to the source pad 10P1. Fig. 9 It is shown Figure 4 An explanatory diagram showing an example of detailed steps of the wire bonding step shown. Fig.10 It is schematically shown Figure 4 FIG. 1 is an explanatory diagram of a configuration example of a wire bonding device used in the wire bonding step shown.

[0137] like Fig. 9 As shown, the wire bonding step according to the present embodiment includes a semiconductor chip distinguishing step, an identification step of the position of the opening portion, an identification step of the bonding region, and a wire forming step.

[0138] exist Fig.10 In the example shown, the wire bonding device 700 includes a camera (image sensor or imaging processing unit) 701, a camera transmission unit 702, a monitor 703, a semiconductor chip distinguishing unit 704, a bonding processing unit 705, and a determination unit 706. Note that Fig.10 The wire bonding device 700 shown is an example, and various modifications may be applied. Fig.10In the case of the wire bonding device 700 shown, the camera 701 and the bonding processing unit 705 are configured to operate independently. Fig.10 In a variation of the present invention, there is a case where the camera 701 and the bonding processing unit 705 are driven by the same driving unit. In addition, for example, the monitor 703 is attached to Fig.10 The position of the monitor 703 is not limited to Fig.10 The example shown, and may be arranged, for example, at a location away from the wire bonding device 700.

[0139] The camera 701 is configured to be able to capture an image of a semiconductor chip mounted on a lead frame LF transferred onto a stage 707. The camera 701 is configured to be movable using a camera transfer unit 702. The image captured by the camera 701 is displayed on a monitor 703. The monitor 703 can display the image captured by the camera 701. In addition to the image captured by the camera 701, a line used as a guide for an operator to visually check the positional relationship between the opening portion and the wire can be displayed on the monitor 703.

[0140] exist Fig. 9 In the wire bonding step shown, first, a wire bonding device 700 (see Fig.10 ) in the camera 701 (see Fig.10 ) to identify the unique pattern on the semiconductor chip 10 (see Figure 6 ) to distinguish the semiconductor chips (semiconductor chip distinguishing step).

[0141] Fig.10 The semiconductor chip distinguishing unit 704 of the illustrated wire bonding device 700 is configured to distinguish semiconductor chips based on an image captured by the camera 701 and displayed on the monitor 703. For example, the semiconductor chip distinguishing unit 704 is configured to distinguish semiconductor chips by identifying a unique pattern from the image displayed on the monitor 703.

[0142] Examples of unique patterns include using Figure 6 The method of pre-forming a visible mark dedicated for differentiation on the upper surface 10t of the semiconductor chip 10 is shown as one or more of the plurality of pads 10P of the semiconductor chip 10. In the present embodiment, the opening portion of the source pad 10P1 can be used as a unique pattern.

[0143] Next, based on the coordinate data about the opening portion obtained in advance with the unique pattern defined as the origin, Figure 6 The position of the opening portion from which the portion of the source pad 10P1 of the semiconductor chip 10 is exposed is identified among the plurality of opening portions formed in the insulating film IF (an identification step of the position of the opening portion).

[0144] Next, the opening portion formed in the insulating film IF for connecting the wire 51 (see Figure 2 ) area (described later Fig.12 The bonding area BR shown in FIG. 1 is a step of identifying the bonding area. Figure 4 After the semiconductor chip preparation steps shown and Fig. 9 The wire forming step shown is performed before.

[0145] Formed in Figure 6 The source pad opening portion in the insulating film IF is formed to expose the bonding area of ​​the source pad 10P1 for the connecting wire 51 from the insulating film IF. However, considering the versatility of the semiconductor chip 10, the opening range of the opening portion does not necessarily match the bonding area, and the source pad 10P1 can be exposed in a wider range than the bonding area of ​​the connecting wire 51.

[0146] From the viewpoint of suppressing fluctuations in characteristics of the semiconductor device, it is preferable that the wire 51 is connected in a bonding region in the source pad 10P1 which is set in advance by design. Therefore, the wire bonding step preferably includes a step of identifying the bonding region.

[0147] The step of identifying the bonding area is called "teaching". From the perspective of suppressing the characteristic fluctuation of the semiconductor device due to the misalignment of the bonding position of the connecting bonding wire, "teaching" is performed to improve the accuracy of the position of the connecting wire 51. The details of "teaching" will be described later.

[0148] As reference Figure 4 As described above, this embodiment includes a quality determination step performed after the wire bonding step. Therefore, if the results of the quality determination can be fed back into the fine adjustment of the settings of the wire bonding device 700 (see Fig.10 ), the step of identifying the bonding area can be omitted.

[0149] Next, wire 51 (see Figure 2 )Connect to Figure 6 The source pad 10P1 shown in FIG. 10 is a wire forming step. When the bonding region identification step is performed before this step, the wire 51 (see FIG. 10A ) is placed in the wire forming step based on the information identified in the “teaching”. Figure 2 ) is connected to the bonding area of ​​the source pad 10P1. Figure 3 , Fig.11 as well as Fig.12 describe Fig. 9 Details of the wire forming steps are shown. Fig.11 is an enlarged cross-sectional view showing a first bonding step of a wire forming step. Fig.12 is a plan view schematically showing the operation of the wedge tool in the bent portion forming step of the wire forming step.

[0150] Fig.10 The bonding processing unit 705 of the wire bonding device 700 shown includes Fig.11 Wire guide 751 , cutting blade 752 , and wedge tool 753 are shown.

[0151] exist Fig. 9 In the wire forming steps shown, first, Fig.11 As shown, the end of wire 51 is brought into contact with a portion of source pad 10P1 exposed from insulating film IF in opening portion OP1, and wire 51 is sandwiched between wedge tool 753 and source pad 10P1. At this time, wedge tool 753 applies ultrasonic waves while pressing wire 51 in the direction of source pad 10P1 (first bonding step).

[0152] By the first bonding step, bonding portion 51B of the end portion of wire 51 is bonded to source pad 10P1. Note that bonding portion 51B is a portion of wire 51 including bonding surface 51Bb as a bonding interface with source pad 10P1 and a portion overlapping bonding surface 51Bb in the thickness direction of wire 51.

[0153] On the other hand, Fig.11 As shown, in the first bonding step, tip portion 51A of the end of wire 51 located closer to the tip than bonding portion 51B may not contact wedge tool 753. In this case, tip portion 51A not bonded to source pad 10P1 is formed at the tip of wire 51.

[0154] Next, while unwinding the wire 51 from the wire supply hole 751H formed in the wire guide 751, the wire 51 is pulled upward. Fig.11 Thereafter, as shown in FIG. Fig.12 As schematically shown by arrows in FIG. 1 , when the wire guide 751 (see Fig.11 ) is rotated along the XY plane, a bent portion (component) 51C is formed (bent portion forming step).

[0155] In this manual, Fig.12 The illustrated tip portion 51A, bonding portion 51B, and bent portion 51C are depicted as an end portion 51E of the wire 51 .

[0156] exist Fig.12, the dotted lines indicate the boundary between the bent portion 51C and the bonding portion 51B and the boundary between the bent portion 51C and the extension portion 51L so as to clearly specify these boundaries. In addition, the bent portion 51C extends in a direction different from any one of the X direction, the Y direction, and the θ direction. However, it is sometimes difficult to specify the boundary between the bent portion 51C and the extension portion 51L formed in the bent portion forming step. For example, when the bent portion 51C extends in the θ direction like the extension portion 51L, it is difficult to identify the boundary between the bent portion 51C and the extension portion 51L.

[0157] Next, in the Fig.11 While unwinding the wire 51 from the wire supply hole 751H in the guide member 751 as shown, move the wire guide member 751 toward Figure 3 The lead 47 shown is moved and bonded to the wire bonding portion 40W of the lead 47 (second bonding step). In the second bonding step, as in the first bonding step, a wedge tool 753 (see Fig.11 ) The wire 51 is pressed to the upper surface 40t of the lead 47 and bonded by applying ultrasonic waves.

[0158] Next, use Fig.11 The cutting blade 752 shown cuts the wire 51 (wire cutting step).

[0159] Through the above steps, we can obtain Figure 2 The wire 51 shown. Fig.12 As shown, the wire 51 includes an end 51E and an extension portion 51L, the end 51E includes a bonding portion 51B having a bonding surface, the bonding surface being a bonding interface with the pad 10P1, and the extension portion 51L is connected to the end 51E and extends in the θ direction intersecting each of the X direction and the Y direction in a plan view. In a plan view, the extension portion 51L intersects with the side OPS1. As described above, the end 51E of the wire 51 includes a tip portion 51A, a bonding portion 51B, and a bent portion 51C.

[0160] <Teaching>

[0161] Next, we will describe Fig. 9 Details of the "teach-in" performed during the identification step of the bonding area. Fig.13 It is shown in Fig. 9 This is an explanatory diagram of an example of an image displayed on the monitor when "teaching" is performed in the step of identifying the bonding area of ​​. Fig.13In the “teaching”, the outer edge of the bonding area BR and the outer edges of the corner portions OPC1, OPC2, OPC3, and OPC4 are indicated by double-dashed lines, but in the “teaching”, the lines of the bonding area BR and the corner portions OPC1, OPC2, OPC3, and OPC4 are not displayed on the monitor 703 (see Fig.10 )superior.

[0162] exist Fig.13 First, the lead frame LF on which the semiconductor chip 10 is mounted is adjusted (see Fig.10 ) and the camera 701, such that the opening portion OP1 (more specifically, the main opening portion OPM) including the bonding area BR is arranged just below the camera 701 (see Fig.10 ). As a result, Fig.13 As shown, the image of the opening portion OP1 captured by the camera 701 is displayed on the wire bonding device 700 (see Fig.10 ) of the monitor 703 (see Fig.10 ). For example, Fig.13 The opening portion OP1 shown has a main opening portion OPM including a bonding region BR.

[0163] Note that the bonding area BR is to be arranged Fig.12 The planned area of ​​the end 51E of the wire 51 is shown. Figure 4 In the mass determination step shown, in the plan view Fig.12 When at least the entirety of the bonding portion 51B of the wire 51 shown is within the range of the bonding region BR, it is determined to be a non-defective product. Preferably, when the entirety of the end portion 51E of the wire 51 including the bonding portion 51B and the bent portion 51C is within the range of the bonding region BR, it is determined to be a non-defective product.

[0164] In a plan view, the main opening portion OPM includes a side OPS1 extending in the X direction, a side OPS2 extending in the Y direction intersecting the X direction, a side OPS3 extending in the Y direction and located on a side opposite to the side OPS2, and a side OPS4 extending in the X direction and located on a side opposite to the side OPS1.

[0165] like Fig.12 As shown, in the wire bonding step, the wire 51 (more specifically, the extension portion 51L of the wire 51) is formed to cross the side OPS1 of the main opening portion OPM in a plan view.

[0166] In addition, the main opening portion OPM includes: a corner portion OPC1, including an intersection between the extension lines of the side OPS1 and the side OPS2; a corner portion OPC2, including an intersection between the side OPS1 and the side OPS3; a corner portion OPC3, including an intersection between the side OPS4 and the side OPS2; and a corner portion OPC4, including an intersection between the side OPS4 and the extension lines of the side OPS3.

[0167] exist Fig.12 In the case of the example shown, the definitions of the corner portions OPC1 to OPC4 are as described above, but the definitions of the corner portions are appropriately modified according to the positional relationship between the main opening portion OPM and the position determination opening pattern. Fig.16 In the variation shown, the main opening portion OPM includes: a corner portion OPC1 including the intersection between the side OPS1 and the side OPS2; a corner portion OPC2 including the intersection between the side OPS1 and the side OPS3; a corner portion OPC3 including the intersection between the side OPS4 and the side OPS2; and a corner portion OPC4 including the intersection between the side OPS4 and the side OPS3. In addition, for example, in the later described Fig.19 In the illustrated variation, the main opening portion OPM includes: a corner portion OPC1, including the intersection between side OPS1 and side OPS2; a corner portion OPC2, including the intersection between side OPS1 and the extension line of side OPS3; a corner portion OPC3, including the intersection between side OPS4 and the extension line of side OPS2; and a corner portion OPC4, including the intersection between side OPS4 and side OPS3.

[0168] In addition, although not shown, as Fig.12 In a variation of the present invention, there is a case where the position determination opening pattern AP1 is arranged at the corner portion OPC2 instead of being arranged at the corner portion OPC1. In this case, the corner portion OPC2 includes the intersection between the extension lines of the side OPS1 and the side OPS3. In addition, when Fig.12 When the position determination opening pattern AP2 shown is arranged at the corner portion OPC3, the corner portion OPC3 includes an intersection between the side OPS4 and the extension line of the side OPS2.

[0169] The planar shape of the main opening portion OPM is a rectangle having long and short sides, and the length of the long sides (side OPS2 and side OPS3) is about 1200 μm. On the other hand, the length of the short sides (side OPS1 and side OPS4) is about 600 μm.

[0170] Next, on viewing monitor 703 (see Fig.10 ) when the operator moves the camera 701 (see Fig.10) so that the bonding area BR is located at the center of the image, the position is visually adjusted, and the bonding area BR is identified.

[0171] like Fig.13 As shown, for example, a cross line consisting of a horizontal line 400A and a vertical line 400B is displayed on the monitor 703 (see Fig.10 ) and the bonding region BR is identified based on the cross line. Scale marks are given at regular intervals on each of the horizontal line 400A and the vertical line 400B, and the center position of the cross line is adjusted by moving the center of the cross line to the vicinity of the center of the main opening part OPM so that the number of scale marks from the center of the cross line to each of the upper side, the lower side, the left side, and the right side of the main opening part OPM becomes the same. For example, the interval of the scale marks given on each of the horizontal line 400A and the vertical line 400B constituting the cross line is, for example, about 100 μm.

[0172] However, when only the above-described “teaching” is performed, there is a limit to the accuracy of identifying the bonding region BR or the positional accuracy of the bonding portion 51B of the actually connected wire 51 .

[0173] For example, the size (width and length) of the main opening portion OPM of the source pad 10P1 to which the wire 51 is connected varies depending on the type of semiconductor device. Therefore, the size of the main opening portion OPM may not be given to the wire bonding device 700 (see Fig.10 ) is an integer multiple of the interval of the scale marks of each of the horizontal line 400A and the vertical line 400B of the cross line. In this case, the operator visually checks "1 scale mark × integer + α scale marks (α is a decimal)" and aligns the intersection of the cross lines with the center of the main opening part OPM. At this time, it is difficult for the operator to visually accurately adjust the center position of the cross lines to have the same "1 scale mark × integer + α scale marks" from the center of the cross lines to each of the upper side, lower side, left side, and right side of the main opening part OPM. Therefore, only by the above-mentioned "teaching", when the bonding area BR is identified, a misalignment of, for example, about 10% of one scale mark (about tens of micrometers) occurs.

[0174] In addition, for example, since "teaching" is in the wire 51 (see Fig.12 ) is connected to the source pad 10P1, so the position of the wire 51 after the actual bonding may vary depending on the wire bonding device 700 (see Fig.10 ) settings and characteristics and are not aligned with the planned position.

[0175] Therefore, although the position of the bonding region BR can be identified by “teaching”, there is a limit to the position accuracy of the bonding portion 51B of the wire 51 that is actually connected only by “teaching” as described above.

[0176] By the way, considering only the existence of electrical conduction, if Fig.12 It is sufficient that at least a portion of the wire 51 shown is connected to the source pad 10P1. In this case, if the bonding portion 51B of the wire 51 is arranged in the main opening portion OPM, electrical conduction can be obtained even if another portion of the wire 51 (for example, the tip portion 51A and the bent portion 51C) is located outside the main opening portion OPM in a plan view.

[0177] On the other hand, considering the characteristics of the semiconductor device, the characteristics may fluctuate depending on the position of the source pad 10P1 at which the bonding portion 51B of the wire 51 is arranged.

[0178] For example, in Figure 2 In the case of the semiconductor device PKG1 having the sensing transistor TrS shown in FIG. 1 , the bonding portion 51B (see FIG. 5B ) between the sensing transistor TrS and the wire 51 is Fig.12 ) is related to the detection value. As described above, the sensing transistor TrS has a function of detecting the current value of the current flowing through the main transistor TrM. The detected current value is related to the separation distance L1.

[0179] Therefore, even when the bonding portion 51B is arranged in the main opening portion OPM, different current values ​​are detected depending on the position of the bonding portion 51B in the main opening portion OPM. For this reason, in order to improve the accuracy of the current value detected by the sensing transistor TrS, it is preferable to improve the position accuracy of the bonding portion 51B in the main opening portion OPM. In other words, by improving the position accuracy of the bonding portion 51B in the main opening portion OPM, the accuracy of the current value detected by the sensing transistor TrS can be improved.

[0180] exist Figure 6 In the example shown, when the extended line obtained by extending the side OPS2 in the Y direction in the plan view is defined as the extended line VL1 and the extended line obtained by extending the side OPS3 in the Y-axis direction is defined as the extended line VL2, the sensing transistor TrS is located between the extended line VL1 and the extended line VL2 in the perspective plan view. Figure 6 The value of the separation distance L1 shown is set within the allowable range. Fig.13 Among the side BRS1 , the side BRS2 , the side BRS3 , and the side BRS4 of the bonding region BR shown, the positions of the side BRS4 and the side BRS1 are particularly important.

[0181] In addition, as described above, considering the versatility of the semiconductor chip 10, the opening range of the main opening portion OPM does not necessarily match the bonding region BR, and the source pad 10P1 may be exposed in a wider range than the bonding region BR to which the wire 51 is connected. For this reason, in order to improve the position accuracy of the bonding portion 51B in the main opening portion OPM, a technology for accurately arranging the bonding portion 51B in the bonding region BR having a small opening area of ​​the main opening portion OPM is required.

[0182] Based on the above understanding, the inventors of the present application have studied a technique for improving the positional accuracy of the bonding portion 51B in the actually connected wire 51 , and have found a method of manufacturing a semiconductor device according to the present embodiment.

[0183] <Details of quality determination steps>

[0184] Fig.14 It is shown in Figure 4 1 is an explanatory diagram of an example of an image displayed on a monitor in the quality determination step shown. Fig.14 In the embodiment, the outer edge of the bonding area BR and the outer edges of the corner portions OPC1, OPC2, OPC3 and OPC4 are indicated by double-dashed lines, but in the quality determination step, the line of the bonding area BR is not displayed on the monitor 703 (see Fig.10 ). In addition, Fig.14 In FIG. 5 , the dotted lines indicate the boundary between the tip portion 51A and the bonding portion 51B, the boundary between the bonding portion 51B and the bent portion 51C, and the boundary between the bent portion 51C and the extended portion 51L. Fig.14 The boundary lines represented by dashed lines in FIG. 1 are not shown in the quality determination step. Fig.15 It is shown Figure 4 An explanatory diagram showing details of the quality determination steps shown.

[0185] like Fig.15 As shown, the quality determination step includes a bonding position identification step, a quality determination step, and an adjustment step. First, in the bonding position identification step, based on the wire bonding device 700 (see Fig.10 ) of the monitor 703 (see Fig.10 ) on the image displayed, identifying the wire 51 (see Fig.14 ) of the bonding portion 51B (see Fig.14 ) or end 51E (see Fig.14 ) and the bonding area BR (see Fig.14 )’s positional relationship.

[0186] exist Fig.14, the semiconductor chip 10 includes a plurality of position determining opening patterns arranged in a region located around the main opening portion OPM in a plan view. In each of the sides OPS1 and OPS4 of the main opening portion OPM, when an extension line extending in a direction from the side OPS3 toward the side OPS2 in a plan view is defined as an extension line HL1 (see Figure 6 ) and an extension line extending in a direction from the side OPS2 toward the side OPS3 is defined as an extension line HL2 (see Figure 6 ), the positions of the plurality of position determining opening patterns may be defined as follows. That is, the plurality of position determining opening patterns include a position determining opening pattern AP1, which is located on an extension line HL1 of the side OPS1 in the Y direction (see Figure 6 ) and the extension line DL1 of the side OPS4 and is arranged at the position of the corner portion OPC1 among the corner portions OPC1, OPC2, OPC3 and OPC4 closest to the main opening portion OPM. In addition, the plurality of position determination opening patterns further include a position determination opening pattern AP2, which is located on the extension line HL2 of the side OPS1 in the Y direction (see Figure 6 ) and an extension line HLR of the side OPS4 and is arranged at a position of the corner portion OPC3 or the corner portion OPC4 among the corner portions OPC1, OPC2, OPC3 and OPC4 which are closest to the main opening portion OPM.

[0187] The bonding region BR has a rectangular shape whose area is smaller than the opening area of ​​the main opening portion OPM in a plan view. The bonding region BR is defined by the position determining opening pattern AP1, the position determining opening pattern AP2, the side OPS2, and the side OPS3.

[0188] like Fig.14 As shown, an image including the main opening portion OPM and the opening portion OP1 of the wire 51 is displayed on the monitor 703 (see Fig.10 ). When image processing or the like for displaying the bonding area BR is not particularly performed, the line indicating the outer edge of the bonding area BR is not displayed on the monitor 703. However, in the present embodiment, the position determination opening pattern AP1 and the position determination opening pattern AP2 for defining the range of the bonding area BR are provided for the corner portion OPC1 and the corner portion OPC4, respectively. Therefore, when the position determination opening pattern AP1 and the position determination opening pattern AP2 are used as a reference, the boundary of the bonding area BR can be easily identified visually.

[0189] Next, in the quality determination step, the quality is determined based on whether at least the entirety of the bonding portion 51B is located or not located in the bonding area BR. Preferably, the quality is determined based on whether the entirety of the end portion 51E including the bonding portion 51B and the bent portion 51C is located or not located in the bonding area BR. For example, when a portion of the end portion 51E (e.g., a portion of the bent portion 51C or a portion of the tip portion 51A) is located outside the bonding area BR, it is determined as "No" (i.e., defective), and the process proceeds to the adjustment step described later. On the other hand, when the entirety of the end portion 51E is located in the bonding area BR, it is determined as "Yes" (i.e., acceptable), and the process proceeds to the next step (e.g., bonding of another wire or Figure 4 Sealing steps shown).

[0190] As a variation of the present embodiment, the quality may be determined based on whether the entirety of the bonding portion 51B is located or not located in the bonding region BR in the quality determination step. In this case, when at least the entirety of the bonding portion 51B is arranged in the bonding region BR, even if a portion of the end portion 51E (e.g., a portion of the curved portion 51C or a portion of the tip portion 51A) is located outside the bonding region BR, it is determined to be "yes" (i.e., acceptable), and the process proceeds to the next step (e.g., bonding of another wire or Figure 4 On the other hand, when a part of the bonding portion 51B is arranged outside the bonding region BR, it is determined as "No" (ie, defective), and the process proceeds to an adjustment step described later.

[0191] However, from the perspective of further improving the accuracy of the current value detected by the sensing transistor TrS, it is preferred to perform quality determination based on whether the entire end 51E of the wire 51 is located or not located in the bonding area BR, as in the present embodiment, and the end 51E includes not only the bonding portion 51B but also the tip portion 51A and the bent portion 51C.

[0192] As mentioned above, in Fig.14 , the dotted lines indicate the boundary between the tip portion 51A and the bonding portion 51B, the boundary between the bonding portion 51B and the curved portion 51C, and the boundary between the curved portion 51C and the extension portion 51L. However, in the quality determination step, Fig.14 The boundary line indicated by the dotted line is not displayed on the monitor 703 (see Fig.10 ). Therefore, when the shape of the wire 51 is as Fig.14As shown, it is difficult to specify the boundary between the tip portion 51A and the bonding portion 51B and the boundary between the bonding portion 51B and the bent portion 51C in the end portion 51E of the wire 51 in a plan view based on the displayed image. On the other hand, the boundary between the bent portion 51C and the extended portion 51L can be easily specified from the plan image. For example, even when the operator visually checks the image on the monitor 703, the boundary between the bent portion 51C and the extended portion 51L can be specified.

[0193] As described in the bent portion forming step of the wire bonding step, it is sometimes difficult to specify the boundary between the bent portion 51C formed in the bent portion forming step and the extended portion 51L. In this case, the position range of the bent portion 51C is preferably set as follows.

[0194] That is to say, Fig.14 As shown, the length of the bent portion 51C in the Y direction is the length L51C. Then, the length L51C is 8% or more and 12% or less of the length L51B of the bonding portion 51B in the Y direction. More specifically, the length L51C is a value preset within the range of 8% or more and 12% or less of the length L51B.

[0195] When the curved portion 51C extends in the θ direction like the extending portion 51L, the curved portion 51C appears to be integral with the extending portion 51L. Therefore, it is difficult to specify the boundary between the curved portion 51C and the extending portion 51L. On the other hand, when the curved portion 51C extends in a direction different from the θ direction, the boundary between the curved portion 51C and the extending portion 51L can be easily specified.

[0196] Therefore, when it is difficult to specify the boundary between the bent portion 51C and the extended portion 51L, the length L51C proportional to the length L51B of the bonding portion 51B in the Y direction is set, and the portion of the wire 51 within the range of the length L51C is regarded as the bent portion 51C. In this way, even if the boundary between the bent portion 51C and the extended portion 51L is unclear, quality determination can be performed based on the same criteria as in the case where the boundary between the bent portion 51C and the extended portion 51L can be easily specified.

[0197] In addition, if the product is determined to be defective during the quality determination step, the adjustment Fig.10 Wire bonding device 700 is shown.

[0198] According to studies conducted by the inventors of the present application, in one of the following three cases, it tends to be detected that a portion of the bonding portion 51B or a portion of the end portion 51E of the wire 51 deviates from the range of the bonding region BR after the wire bonding step.

[0199] First, in a wire bonding device 700 (see Fig.10 ) is activated and the first wire is bonded, the misalignment of the end 51E can be detected. Next, the wire bonding device 700 (see FIG. 1 ) attached to the wire bonding device 700 is replaced in the wire bonding step. Fig.10 ) of the fixture (for example, Fig.11 After changing the wire bonding conditions for performing wire bonding in the wire bonding step, misalignment of the bonding portion 51B (or the end portion 51E) can be detected.

[0200] On the other hand, in cases other than the above three cases, it is unlikely that the misalignment of the bonding portion 51B (or the end portion 51E) is detected. In other words, the cause of the misalignment of the bonding portion 51B (or the end portion 51E) is mainly due to the wire bonding device 700 (see Fig.10 ) setting conditions and fixture attachment conditions.

[0201] Therefore, in the wire bonding device 700 (see Fig.10 ), one or more of the following items are adjusted. First, the adjustment of the wire bonding device 700 includes the adjustment of the setting of the wire bonding conditions. The setting of the wire bonding conditions includes, for example, the adjustment of the pressing force when bonding the wire, the adjustment of the setting of the ultrasonic output, the adjustment of the bonding processing unit 705 (see Fig.10 ) and the like. Adjustment of the wire bonding device 700 further includes attaching to the wire bonding device 700 (see Fig.10 ) of the fixture (for example, Fig.11 Inspection and adjustment of the attachment status of the wedge tool 753) shown.

[0202] After the adjustment step, the quality determination step is performed again after bonding another wire. By repeatedly performing the adjustment step and the quality determination step in this way, a setup can be achieved that achieves an "acceptable" result in the quality determination.

[0203] You can omit the execution confirmation Fig.15 The quality determination step shown in FIG. 1 is necessary for the quality determination step. In this case, the quality determination step is performed each time the wire bonding step is completed. However, from the perspective of improving manufacturing efficiency, Fig.15 The mode shown is more preferred.

[0204] exist Fig.15In the example shown, a step of determining whether to perform quality determination (a step of determining the necessity of performing quality determination) is included after the wire bonding step and before the quality determination step. In the step of determining the necessity of performing quality determination, determination is performed based on whether the wire bonding step performed immediately before corresponds to the timing of any one of the three cases mentioned above. When the wire bonding step corresponds to the timing of any one of the three cases mentioned above, it is determined as "Yes" (i.e., the quality determination step is necessary), and the process proceeds to the quality determination step. On the other hand, when the wire bonding step does not correspond to the timing of any one of the three cases mentioned above, it is determined as "No" (i.e., the quality determination step is unnecessary), the quality determination step is omitted, and the process proceeds to the next step (e.g., bonding of another wire or Figure 4 Sealing steps shown).

[0205] In other words, Fig.15 In the example shown, in a wire bonding device 700 (see Fig.10 ) is activated and the first wire is bonded, the wire bonding device 700 (see Fig.10 ) of the fixture (for example, Fig.11 The quality determination step is selectively performed after using a wedge tool 753 as shown, or after changing the wire bonding conditions for performing wire bonding in the wire bonding step.

[0206] If the quality determination step is performed at a timing corresponding to at least one of the three situations mentioned above, it is unlikely that a large number of defective products will be manufactured even if the quality determination step is omitted at other timings. In addition, even if defective products are manufactured, they can be Figure 4 After the cutting steps shown are completed, electrical testing is performed to eliminate defective products.

[0207] The quality determination step is considered to be a method for quickly correcting the quality of the wire bonded device 700 (see Fig.10 ) and the attachment condition of the fixture.

[0208] <Shape of the opening>

[0209] Next, we will describe Fig.14 The detailed structures of the main opening portion OPM, the position determining opening pattern AP1, and the position determining opening pattern AP2 and the positional relationship with the bonding region BR are shown, and include modifications.

[0210] like Fig.13As shown, in the plan view, the position determining opening pattern AP1 includes an inner side AS11 extending in the X direction and an outer side AS12 extending in the X direction and arranged at a position closer to the side OPS1 than the inner side AS11. In the plan view, the position determining opening pattern AP2 includes an inner side AS21 extending in the X direction and an outer side AS22 extending in the X direction and arranged at a position closer to the side OPS4 than the inner side AS21.

[0211] exist Fig.15 In the step of identifying the bonding position shown, the bonding region BR is defined by an extension line of the inner side AS11 of the position determining opening pattern AP1 , an extension line of the inner side AS21 of the position determining opening pattern AP2 , the side OPS2 , and the side OPS3 .

[0212] Fig.13 The structure shown can be expressed as follows. The bonding area BR includes a side BRS1 extending in the X direction; a side BRS2 extending in the Y direction and intersecting the side BRS1; a side BRS3 extending in the Y direction, intersecting the side BRS1 and located on the opposite side to the side BRS2; and a side BRS4 extending in the X direction, intersecting the side BRS2 and the side BRS3 and located on the opposite side to the side BRS1. The extension line of the side BRS1 overlaps with the inner side AS11 of the position determination opening pattern AP1. In addition, the extension line of the side BRS4 overlaps with the inner side AS21 of the position determination opening pattern AP2.

[0213] From the perspective of accurately identifying the position of the bonding region BR, it is more preferable to identify the position of the bonding region BR based on the positions of the inner side AS11 and the inner side AS21 rather than identifying the position of the bonding region BR based on any position of the position determination opening pattern AP1 and the position determination opening pattern AP2.

[0214] In this embodiment, since the position of the bonding region BR can be accurately identified based on the positions of the inner side AS11 and the inner side AS21, Fig. 9 In the step of identifying the bonding area shown, Fig.13 The cross lines shown (horizontal line 400A and vertical line 400B) may not be displayed on monitor 703 (see Fig.10 )superior.

[0215] In addition, if Fig.13 As shown, the opening area of ​​each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is smaller than the opening area of ​​the main opening portion OPM. This structure is preferable from the viewpoint of improving the accuracy of identifying the outer edge of the bonding region BR.

[0216] As reference Figure 8As described above, the insulating film IF may include the inorganic insulating film CF formed on the main surface 11 t and the organic insulating film OF formed on the inorganic insulating film CF. Fig.13 The main opening portion OPM shown is formed in Figure 8 In both the inorganic insulating film CF and the organic insulating film OF shown. In addition, for example, as will be described later Fig.17 As shown, each of the position determination opening pattern AP1 and the position determination opening pattern AP2 is formed in both the inorganic insulating film CF and the organic insulating film OF. Alternatively, as will be described later Fig.18 As shown, each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is formed only in the organic insulating film OF out of the inorganic insulating film CF and the organic insulating film OF.

[0217] Here, the organic insulating film OF is more likely to shrink due to heat than the inorganic insulating film CF. Therefore, when the opening end of the opening portion OPO formed in the organic insulating film OF is defined as Fig.13 When the outer edges (side OPS1, side OPS2, side OPS3, and side OPS4) of the main opening portion OPM are aligned, the positions of the outer edges of the main opening portion OPM may be misaligned due to thermal influence.

[0218] In this embodiment, Fig.17 and 18 Each of the position determining opening pattern AP1 and the position determining opening pattern AP2 shown is formed at least in the organic insulating film OF. Fig.13 As shown, the opening area of ​​each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is sufficiently smaller than the opening area of ​​the main opening portion OPM (for example, 5% or less). Therefore, even if the organic insulating film OF shrinks due to the influence of heat, the opening shapes of the position determining opening pattern AP1 and the position determining opening pattern AP2 are hardly deformed.

[0219] That is to say, Fig.13 In this embodiment, if each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is used as a mark for identifying the position of the bonding region BR, the positions of the side BRS1 and the side BRS4 which are particularly important among the sides of the bonding region BR can be accurately identified.

[0220] In addition, Fig.13 In the example shown, each of the position determining opening pattern AP1 and the position determining opening pattern AP2 forms an opening pattern connected to the main opening portion OPM. In other words, the opening portion OP1 includes the main opening portion OPM and a plurality of position determining opening patterns (position determining opening patterns AP1 and AP2) connected to the main opening portion OPN.

[0221] The position determining opening pattern AP1 is connected to the main opening portion OPM at a corner portion OPC1 of the main opening portion OPM. The position determining opening pattern AP2 is connected to the main opening portion OPM at a corner portion OPC4 of the main opening portion OPM.

[0222] When each of the plurality of position determination opening patterns is connected to the main opening portion OPM, the patterning of the opening shape is such as Fig.16 It is easier to separate each of the plurality of position determination opening patterns from the main opening portion OPM. Fig.16 yes Fig.13 variants.

[0223] Fig.16 is shown as Fig.13 An enlarged plan view of the area around the main opening portion of a semiconductor chip of a modification of the present invention. Note that Fig.16 Omitted Fig.13 An illustration of the intersecting lines (horizontal line 400A and vertical line 400B) is shown.

[0224] Fig.16 The semiconductor chip 10A shown is Fig.13 The semiconductor chip 10 shown is different in that each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is separated from the main opening portion OPM. Fig.13 The points of the semiconductor chip 10 shown are similar, and thus redundant descriptions thereof are omitted.

[0225] From the viewpoint of improving the accuracy of identifying the outer edge of the bonding region BR, it is preferable that each of the position determination opening pattern AP1 and the position determination opening pattern AP2 be separated from the main opening portion OPM as in the semiconductor chip 10A. That is, when the organic insulating film OF (see Figure 8 ) when the main opening portion OPM shrinks due to heat. Since each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is separated from the main opening portion OPM, even when the main opening portion OPM is deformed, Fig.13 The position determining opening pattern AP1 and the position opening pattern AP2 are also less likely to be affected by deformation than the example shown.

[0226] In addition, Fig.13 Examples and Fig.16In the example of FIG. 1 , the position determination opening pattern AP1 includes the intersection between the extension lines of the side OPS1 and the side OPS2. In other words, the outer side AS12 of the position determination opening pattern AP1 overlaps with the extension line of the side OPS1 of the main opening portion OPM. In this case, the distance from the opening end of the main opening portion OPM to the bonding area BR can be easily discerned visually. For this reason, when the operator Fig.15 The quality determination step shown is based on the monitor 703 (see Fig.10 ) when visually inspecting the product, the operator is less likely to mistakenly identify the positions of the side BRS1 and the side BRS2 of the bonding area BR.

[0227] Fig.17 It is along Figure 6 An enlarged cross-sectional view taken along line CC. Fig.18 It is shown Fig.17 An enlarged cross-sectional view of a variation of Fig.17 It is along Figure 6 The enlarged cross-sectional view taken along line CC is shown, but due to Fig.13 The position determining opening pattern AP1 and the position determining opening pattern AP2 shown have similar structures, so Fig.17 and 18 The reference symbols of the position determining opening pattern AP1 and the position determining opening pattern AP2 are given in FIG.

[0228] exist Fig.17 In the example shown, each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is formed in both the inorganic insulating film CF and the organic insulating film OF. Fig.18 The semiconductor chip 10B shown is Fig.17 The semiconductor chip 10B is different from the semiconductor chip 10 in that each of the position determining opening pattern AP1 and the position determining opening pattern AP2 is formed only in the organic insulating film OF. Therefore, in the position determining opening patterns AP1 and AP2, the source pad 10P1 is not exposed from the insulating film IF (more specifically, the inorganic insulating film CF). Since the semiconductor chip 10B is similar to the semiconductor chip 10 except for the above-mentioned difference, its redundant description is omitted.

[0229] Although the illustration is omitted, Fig.17 In another variation, there is a case where each of the position determination opening pattern AP1 and the position determination opening pattern AP2 is formed only in the inorganic insulating film CF. However, in this variation, when the fluidity of the organic insulating film OF is high when applied, the organic insulating film OF can be embedded in the opening portion OPC formed in the inorganic insulating film CF. Therefore, from improving the display of the monitor 703 (see Fig.10) from the perspective of the visibility level of the image displayed on Fig.17 The structure of the semiconductor chip 10 shown or Fig.18 The structure of the semiconductor chip 10B shown is preferred.

[0230] Fig.19 It is shown Fig.13 Another variation of the enlarged plan view. Note that Fig.19 Omitted Fig.13 An illustration of the intersecting lines (horizontal line 400A and vertical line 400B) is shown.

[0231] Fig.19 The semiconductor chip 10C shown is Fig.13 The semiconductor chip 10 shown is different in the following points. The plurality of position determination opening patterns of the semiconductor chip 10C include a position determination opening diagram AP2, which is located between the extension line of the side OPS1 and the extension line of the side OPS4 in the Y direction and is arranged at the position of the corner portion OPC3 among the corner portions OPC1, OPC2, OPC3, and OPC4 that are closest to the main opening portion OPM. In addition, the plurality of position determination opening patterns further include a position determination opening pattern AP3, which is located between the extension line of the side OPS1 and the extension line of the side OPS4 in the Y direction and is arranged at the position of the corner portion OPC2 among the corner portions OPC1, OPC2, OPC3, and OPC4 that are closest to the main opening portion OPM. In addition, the multiple position determining opening patterns further include a position determining opening pattern AP4, which is located between the extension line of the side OPS1 and the extension line of the side OPS4 in the Y direction and is arranged at the position of the corner portion OPC4 among the corner portion OPC1, corner portion OPC2, corner portion OPC3 and corner portion OPC4 which are closest to the main opening portion OPM.

[0232] The bonding region BR is defined by the position determining opening pattern AP1 , the position determining opening pattern AP2 , the position determining opening pattern AP3 , the position determining opening pattern AP4 , the side OPS2 , and the side OPS3 .

[0233] More specifically, if Fig.19 As shown, in the plan view, the position determining opening pattern AP3 includes an inner side AS31 extending in the X direction and an outer side AS32 extending in the X direction and arranged at a position closer to the side OPS1 than the inner side AS31. In the plan view, the position determining opening pattern AP4 includes an inner side AS41 extending in the X direction and an outer side AS42 extending in the X direction and arranged at a position closer to the side OPS4 than the inner side AS41.

[0234] exist Fig.15 In the bonding position identification step shown, the bonding area BR is defined by a virtual line connecting the inner side AS11 of the position determining opening pattern AP1 and the inner side AS31 of the position determining opening pattern AP3, a virtual line connecting the inner side AS21 of the position determining opening pattern AP2 and the inner side AS41 of the position determining opening pattern AP4, the side OPS2 and the side OPS3.

[0235] In this modification, the position determination opening pattern is provided at each of the four corner portions of the main opening portion OPM. Fig.13 Compared to the example shown, the visibility when the outer edge of the bonding area BR is identified from the image is further improved.

[0236] In addition, this modification is advantageous in the following aspects. Fig.12 In the example shown, the extension portion 51L of the conductive line 51 extends in a direction from the side OPS2 toward the side OPS3. At this time, when the position determination opening pattern is formed at the corner portion OPC2, the position determination opening pattern may be covered by the extension portion 51L of the conductive line 51 according to the bending angle of the bent portion 51C of the conductive line 51. In order to avoid this, the position determination opening pattern AP1 needs to be formed along the side opposite to the bending direction of the conductive line 51 (i.e., Fig.12 Side OPS2) setting in the example shown.

[0237] On the other hand, Fig.19 In the illustrated example, since the position determining opening pattern is provided at each of the four corner portions, at least three of the four position determining opening patterns can be visually discerned regardless of the bending direction of the conductive line 51 .

[0238] because Fig.19 The semiconductor chip 10C shown is similar to the Fig.13 The conductor chip 10 shown is similar, so its redundant description is omitted. Although not shown, Fig.19 The semiconductor chip 10C shown can be used in combination with the above-described various modifications.

[0239] For example, with Fig.16 As shown in the semiconductor chip 10A, there is Fig.19 The semiconductor chip 10C is shown in a state where each of the four position determination opening patterns is separated from the main opening portion OPM.

[0240] In addition, for example, Fig.17 The position determination opening patterns AP1 and AP2 of the semiconductor chip 10 shown in FIG. Fig.19Each of the four position determination opening patterns of the semiconductor chip 10C shown includes an opening portion OPC formed in the inorganic insulating film CF and an opening portion OPO formed in the organic insulating film OF. However, as a modification, Fig.18 Like the semiconductor chip 10B shown, there is a case where each of the four position determining opening patterns is formed only in the organic insulating film OF. Alternatively, there is a case where the organic insulating film OF is not formed.

[0241] Fig. 20 It is shown Fig.13 Another variation of the enlarged plan view. Note that Fig. 20 Omitted Fig.13 An illustration of the intersecting lines (horizontal line 400A and vertical line 400B) is shown.

[0242] Fig. 20 The semiconductor chip 10D shown is Fig.13 The semiconductor chip 10 shown is different in that the position determination opening pattern AP1 is arranged between the corner portion OPC1 and the center S2C of the side OPS2. Fig. 20 As shown, the semiconductor chip 10D is particularly effective when the area of ​​the bonding region BR is much smaller than the opening area of ​​the main opening portion OPM.

[0243] Since the position determining opening pattern AP1 is arranged between the corner portion OPC1 and the center S2C of the side OPS2, even when the separation distance between the bonding area BR and the side OPS1 is long, the opening area of ​​the position determining opening pattern AP1 can be made much smaller (for example, 5% or less) than the opening area of ​​the main opening portion OPM.

[0244] because Fig. 20 The semiconductor chip 10D shown is similar to the Fig.13 The conductor chips 10 shown are similar, so redundant description thereof is omitted. Fig. 20 The semiconductor chip 10D shown can be used in combination with the above-described various modifications.

[0245] In addition, Fig.12 , Fig.16 , Fig.19 as well as Fig. 20 In each of the above, a rectangular pattern extending in the X direction is shown as an example of the shape of the position determination opening pattern. The shape of the position determination opening pattern has various modifications. For example, it can be a square, a circle, an ellipse, or a combination of these shapes.

[0246] Fig.21 It is shown Fig.13 An enlarged plan view of another variation of . Fig.21The semiconductor chip 10E shown is Fig.13 The semiconductor chip 10 shown is different in that the semiconductor chip 10E has a mark for Fig. 9 The above-mentioned "teaching" is easily performed in the identification step of the bonding area shown.

[0247] The semiconductor chip 10E has a plurality of center position identification opening patterns CAP arranged at the center of at least three sides among the side OPS1 , the side OPS2 , the side OPS3 , and the side OPS4 and extending in a direction perpendicular to the extension of the three sides.

[0248] In the bonding area identification step, a plurality of center position identification opening patterns CAP are superimposed on the wire bonding device 700 (see Fig.10 ) of the monitor 703 (see Fig.10 ) the position of the bonding region BR can be easily identified on the cross lines (horizontal line 400A and vertical line 400B) shown in FIG.

[0249] because Fig.21 The semiconductor chip 10E shown is similar to the Fig.13 The conductor chips 10 shown are similar, so redundant description thereof is omitted. Fig.21 The semiconductor chip 10E shown can be used in combination with the above-described various modifications.

[0250] <Variation of Quality Determination Step>

[0251] Next, we will describe Figure 4 In the above description, an embodiment has been described in which the operator determines the quality of the product based on the quality of the product. Fig.10 The image displayed on the monitor 703 is shown to visually inspect the product.

[0252] Hereinafter, the Fig.10 The determination unit 706 in the illustrated wire bonding device 700 automatically performs a variation of the quality determination.

[0253] Fig. 22 It is shown Fig.10 A block diagram of an example configuration of a determination unit shown in FIG. Fig. 22 In the example shown, the determination unit 706 includes a start determination section 801 , a mark recognition section 802 , an area definition section 803 , a wire shape grasping section 804 , and a quality determination section 805 .

[0254] The start determination section 801 is configured to determine whether to start Fig. 9 More specifically, Fig. 22 The start determination section 801 shown is configured to be able to connect the wire 51 (see Figure 2 ) after determining whether to start the determination as to whether the connection position of the wire 51 is within the allowable range. For example, the start determination section 801 is configured to start the determination as to whether the connection position of the wire 51 is within the allowable range after activating the wire bonding device 700 and bonding the first wire 51, and after replacing the jig (e.g., Fig.11 The quality determination step is selectively started after using the wedge tool 753 shown in FIG. 1 , or after changing the wire bonding conditions for performing wire bonding in the wire bonding step.

[0255] For example, the marker recognition section 802 is configured to recognize the marker from the image captured by the camera 701 and displayed on the monitor 703 by using an image recognition technique. Fig.14 The shown positioning opening pattern AP1 and positioning opening pattern AP2.

[0256] Fig. 22 The region defining section 803 is configured to identify the region based on the region identified by the marker identifying section 802. Fig.14 The position determination opening pattern AP1 and the position determination opening pattern AP2 shown in the figure are used to define a rectangular bonding area BR used as a reference of the allowable range. The bonding area BR defined by the area defining section 803 can be shown in FIG. Fig. 22 On monitor 703 as shown.

[0257] The wire shape grabbing section 804 is configured to be based on the wire shape displayed on the monitor 703. Fig.14 The wire shape capture section 804 is configured to capture the position of the bonding portion 51B (or the end portion 51E) of the wire 51 based on the data about the identified boundary between the bending portion 51C and the extending portion 51L.

[0258] The quality determination section 805 is configured to determine whether the entire bonding portion 51B (or end 51E) of the wire 51 is located or not located in the bonding area BR based on the bonding area BR defined by the area definition section 803 and the position of the bonding portion 51B (or end 51E) of the wire 51 grasped by the wire shape grasping section 804.

[0259] Then, the quality determination section 805 is configured to: Fig.14 If the entire bonding portion 51B (or end portion 51E) of the wire 51 shown is within the bonding region BR, it is determined that the bonding position of the wire 51 is acceptable (in Fig.15On the other hand, the quality determination section 805 is configured to determine that the bonding position of the wire 51 is defective if a portion of the bonding portion 51B (or a portion of the end portion 51E) of the wire 51 is outside the bonding region BR.

[0260] The determination result is output to the monitor 703, and when the bonding position is determined to be defective, for example, the warning indicator lights up. The operator who recognizes the warning indicator temporarily stops the operation performed by the wire bonding device 700, and adjusts the settings of the wire bonding device 700.

[0261] On the other hand, if the bond position is determined to be acceptable, the next process is initiated automatically or based on an operator input command.

[0262] For example, Fig.12 , Fig.13 , Fig.17 The structural features of the semiconductor chip 10 shown in the figure are included in the Figure 2 and Figure 3 The semiconductor chip 10 in the finished semiconductor device PKG1 shown. Therefore, although redundant description is omitted, the structural features of the semiconductor chip 10 described in <Method of Manufacturing a Semiconductor Device> can be regarded as the structural features of the finished semiconductor device PKG1. The same applies to various variants, including Fig.16 The semiconductor chip 10A shown in FIG. Fig.18 The semiconductor chip 10B shown, Fig.19 The semiconductor chip 10C shown, Fig. 20 The semiconductor chip 10D shown and Fig.21 The semiconductor chip 10E is shown.

[0263] Although the invention made by the inventors of the present application has been specifically described based on the embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from the gist of the present invention.

[0264] As a summary of the technical ideas, the characteristics of the above-mentioned semiconductor device can be expressed as follows.

[0265] [Appendix 1]

[0266] A semiconductor device, comprising:

[0267] main surface;

[0268] a pad formed on the major surface;

[0269] an insulating film in which an opening portion for exposing a portion of the pad is formed; and

[0270] A plurality of position-determining opening patterns are arranged in a region located around the main opening portion in plan view,

[0271] The opening part includes a main opening part,

[0272] Among them, in the plan view, the main opening part includes:

[0273] a first side extending in a first direction;

[0274] a second side extending in a second direction intersecting the first direction;

[0275] a third side extending in the second direction and located on a side opposite to the second side;

[0276] a fourth side extending in the first direction and located on a side opposite to the first side;

[0277] a first corner portion including an intersection between extensions of the first side and the second side;

[0278] a second corner portion including an intersection between extensions of the first side and the third side;

[0279] a third corner portion including an intersection between the fourth side and an extension line of the second side; and

[0280] a fourth corner portion including an intersection between the fourth side and an extension line of the third side, and

[0281] wherein, in each of the first side and the fourth side of the main opening portion, when an extension line extending in a direction from the third side toward the second side in a plan view is defined as a first extension line and an extension line extending in a direction from the second side toward the third side in a plan view is defined as a second extension line, the plurality of position determination opening patterns include:

[0282] a first position determining opening pattern located between a first extension line of the first side and a first extension line of the fourth side in the second direction and arranged at a position closest to a first corner portion among a first corner portion, a second corner portion, a third corner portion, and a fourth corner portion of the main opening portion; and

[0283] The second position determines the opening pattern, which is located between the second extension line of the first side and the second extension line of the fourth side in the second direction and is arranged at the position of the third corner part or the fourth corner part among the first corner part, the second corner part, the third corner part and the fourth corner part which are closest to the main opening part.

[0284] [Appendix 2]

[0285] According to the semiconductor devices in Appendix 1,

[0286] Each of the first position determining opening pattern and the second position determining opening pattern forms an opening pattern communicating with the main opening portion.

[0287] [Appendix 3]

[0288] According to the semiconductor devices in Appendix 1,

[0289] The multiple positions determine the opening pattern including:

[0290] a second position determining opening pattern located between a second extension line of the first side and a second extension line of the fourth side in the second direction and arranged at a position closest to a third corner portion among the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion of the main opening portion;

[0291] a third position determining opening pattern located between the first extension line of the first side and the first extension line of the fourth side in the second direction and arranged at a position closest to the second corner portion among the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion of the main opening portion; and

[0292] The fourth position determines the opening pattern, which is located between the second extension line of the first side and the second extension line of the fourth side in the second direction and is arranged at the position of the fourth corner part among the first corner part, the second corner part, the third corner part and the fourth corner part closest to the main opening part.

[0293] [Appendix 4]

[0294] According to the semiconductor devices in Appendix 1,

[0295] The insulating films include:

[0296] an inorganic insulating film formed on the main surface; and

[0297] an organic insulating film formed on the inorganic insulating film, and

[0298] Each of the first positioning opening pattern and the second positioning opening pattern is formed in both the inorganic insulating film and the organic insulating film.

[0299] [Appendix 5]

[0300] According to the semiconductor devices in Appendix 1,

[0301] The insulating films include:

[0302] an inorganic insulating film formed on the main surface; and

[0303] An organic insulating film is formed on the inorganic insulating film.

[0304] wherein each of the first position determining opening pattern and the second position determining opening pattern is formed in at least the organic insulating film, and

[0305] wherein an opening area of ​​each of the first position determining opening pattern and the second position determining opening pattern is smaller than an opening area of ​​the main opening portion.

[0306] [Appendix 6]

[0307] The semiconductor device according to Appendix 1, further comprising:

[0308] A plurality of center position marking opening patterns are arranged at the center of at least three sides among the first side, the second side, the third side and the fourth side of the main opening portion and extend in a direction perpendicular to a direction in which the at least three sides extend.

[0309] [Appendix 7]

[0310] The semiconductor device according to Appendix 1, further comprising:

[0311] Power transistors, made from power MOSFETs or IGBTs; and

[0312] A sense transistor, which detects the current flowing through the power transistor,

[0313] Wherein the pad is the source pad of a power MOSFET or the emitter pad of an IGBT, and

[0314] wherein, when, in a plan view, an extension line obtained by extending the second side in a first direction from the first side toward the fourth side is defined as a third extension line and an extension line obtained by extending the third side in a second direction from the first side toward the fourth side is defined as a fourth extension line,

[0315] In the perspective plan view, the sensing transistor is located between the third extension line and the fourth extension line.

[0316] [Appendix 8]

[0317] The semiconductor device according to Appendix 1, further comprising:

[0318] The wires are connected to the bonding areas of the pads.

[0319] The wires include:

[0320] a first end portion including a bonding portion having a bonding surface, the bonding surface being a bonding interface with the pad; and

[0321] an extending portion connected to the first end portion, extending in a third direction intersecting each of the first direction and the second direction in a plan view, and intersecting the first side of the main opening portion in a plan view,

[0322] wherein the bonding area has a rectangular shape, the area of ​​the rectangular shape in a plan view being smaller than the opening area of ​​the main opening portion,

[0323] wherein the bonding area is defined by the first position determining opening pattern, the second position determining opening pattern, the second side and the third side, and

[0324] The entirety of the bonding portion including the bonding portion and the bending portion is located in the bonding area.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor chip including a main surface, a pad formed on the main surface, and an insulating film formed on the main surface; (b) bonding a wire to a bonding region of the pad, wherein the bonding region is exposed from the insulating film in an opening portion formed in the insulating film; as well as (c) after (b), determining the quality of whether the bonding portion of the wire is located within the bonding region or not in a plan view, wherein the opening portion includes a main opening portion, the main opening portion includes the bonding area, Wherein, in plan view, the main opening portion includes: a first side extending in a first direction; a second side extending in a second direction intersecting the first direction; a third side extending in the second direction and located on a side opposite to the second side; a fourth side extending in the first direction and located on a side opposite to the first side; a first corner portion including an intersection point between extension lines of the first side and the second side, or an intersection point between the first side and the second side; a second corner portion including an intersection point between the first side and the third side, or an intersection point between extension lines of the first side and the third side; a third corner portion including an intersection point between the fourth side and the second side, or an intersection point between the fourth side and an extension line of the second side; and a fourth corner portion, including an intersection point between the fourth side and an extension line of the third side, or an intersection point between the fourth side and the third side, wherein the insulating film includes a plurality of position determining opening patterns arranged in a region located around the main opening portion in a plan view, wherein, in each of the first side and the fourth side of the main opening portion, when an extension line extending in a direction from the third side toward the second side in a plan view is defined as a first extension line and an extension line extending in a direction from the second side toward the third side in a plan view is defined as a second extension line, the plurality of position determining opening patterns include: a first position determining opening pattern located between the first extension line of the first side and the first extension line of the fourth side in the second direction and arranged at a position closest to the first corner portion among the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion of the main opening portion; and a second position determining opening pattern located between the second extension line of the first side and the second extension line of the fourth side in the second direction, and arranged at a position closest to the third corner portion or the fourth corner portion among the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion of the main opening portion, The wires include: a first end portion including the bonding portion having a bonding surface, the bonding surface being a bonding interface with the pad; and an extending portion connected to the first end portion, extending in a third direction intersecting each of the first direction and the second direction in a plan view, and intersecting the first side of the main opening portion in a plan view, wherein the bonding region has a rectangular shape having an area smaller than an opening area of ​​the main opening portion in a plan view, wherein the bonding area is defined by the first position determining opening pattern, the second position determining opening pattern, the second side and the third side, and Wherein, in (c), the quality is determined based on whether all of the bonding portion is located within the bonding area or not.

2. The method for manufacturing a semiconductor device according to claim 1, in, In a plan view, the first position determining opening pattern includes a first inner side extending in the first direction, and a first outer side extending in the first direction and arranged at a position closer to the first side than the first inner side, wherein, in a plan view, the second position determining opening pattern includes a second inner side extending in the first direction, and a second outer side extending in the first direction and arranged at a position closer to the fourth side than the second inner side, The bonding area is defined by an extension line of the first inner side of the first position determining opening pattern, an extension line of the second inner side of the second position determining opening pattern, the second side, and the third side.

3. The method for manufacturing a semiconductor device according to claim 1, wherein each of the first position determining opening pattern and the second position determining opening pattern forms an opening pattern communicating with the main opening portion.

4. The method for manufacturing a semiconductor device according to claim 1, The plurality of position determination opening patterns include: The second position determining opening pattern is located between the second extension line of the first side and the second extension line of the fourth side in the second direction and is arranged at a position closest to the third corner portion among the first corner portion, the second corner portion, the third corner portion and the fourth corner portion of the main opening portion; a third position determining opening pattern located between the first extension line of the first side and the first extension line of the fourth side in the second direction and arranged at a position closest to the second corner portion among the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion of the main opening portion; as well as a fourth position determining opening pattern, which is located between the second extension line of the first side and the second extension line of the fourth side in the second direction and is arranged at a position closest to the fourth corner portion among the first corner portion, the second corner portion, the third corner portion and the fourth corner portion of the main opening portion, and The bonding area is defined by the first position determining opening pattern, the second position determining opening pattern, the third position determining opening pattern, the fourth position determining opening pattern, the second side, and the third side.

5. The method for manufacturing a semiconductor device according to claim 1, The insulating film comprises: an inorganic insulating film formed on the main surface; as well as an organic insulating film formed on the inorganic insulating film, and wherein each of the first positioning opening pattern and the second positioning opening pattern is formed in both the inorganic insulating film and the organic insulating film.

6. The method for manufacturing a semiconductor device according to claim 1, The insulating film comprises: an inorganic insulating film formed on the main surface; as well as an organic insulating film formed on the inorganic insulating film, wherein each of the first position determining opening pattern and the second position determining opening pattern is formed in at least the organic insulating film, and The opening area of ​​each of the first position determining opening pattern and the second position determining opening pattern is smaller than the opening area of ​​the main opening portion.

7. The method for manufacturing a semiconductor device according to claim 1, The insulating film comprises: an inorganic insulating film formed on the main surface; as well as an organic insulating film formed on the inorganic insulating film, and Each of the first positioning opening pattern and the second positioning opening pattern is formed in the organic insulating film among the inorganic insulating film and the organic insulating film.

8. The method for manufacturing a semiconductor device according to claim 1, Wherein (c) is selectively performed after a wire bonding device used to perform (b) is activated and a first wire is bonded, after a fixture attached to the wire bonding device in (b) is replaced, or after wire bonding conditions used to perform wire bonding in (b) are changed.

9. The method for manufacturing a semiconductor device according to claim 1, further comprising: (d) after (a) and before (b), identifying the bonding area in a portion of the pad, wherein the portion is exposed in the opening portion, wherein the semiconductor chip has a plurality of center position identification opening patterns, the plurality of center position identification opening patterns are arranged at the center of at least three sides among the first side, the second side, the third side and the fourth side, and extend in directions perpendicular to the directions in which the at least three sides extend, respectively; and Wherein, in (d), the bonding area is identified by superimposing the plurality of center position identification opening patterns on a cross line displayed on a monitor of the wire bonding device.

10. The method for manufacturing a semiconductor device according to claim 1, The semiconductor chip comprises: Power transistors, made of power MOSFETs or IGBTs; as well as a sense transistor for detecting the current flowing through the power transistor, and The pad is a source pad of the power MOSFET or an emitter pad of the IGBT.

11. The method for manufacturing a semiconductor device according to claim 10, in, When, in a plan view, an extension line obtained by extending the second side in the first direction from the first side toward the fourth side is defined as a third extension line, and an extension line obtained by extending the third side in the second direction from the first side toward the fourth side is defined as a fourth extension line, In a perspective plan view, the sensing transistor is located between the third extension line and the fourth extension line.

12. The method for manufacturing a semiconductor device according to claim 1, in, In (b), the conductive line is formed to straddle the first side of the main opening portion in a plan view.

13. The method for manufacturing a semiconductor device according to claim 1, in, In (c), the quality is determined based on whether all of the bonding portion and all of the first portion of the wire are located within or not located within the bonding region.

14. The method for manufacturing a semiconductor device according to claim 13, The length of the first portion in the second direction is not less than 8% and not more than 12% of the length of the bonding portion in the second direction.

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