Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device may include: a base insulating layer; a channel layer on the first surface of the base insulating layer; a first source / drain pattern and a second source / drain pattern spaced apart from each other in the first direction on the first surface of the base insulating layer, the channel layer interposed between the first source / drain pattern and the second source / drain pattern; a gate structure on the first surface of the base insulating layer and extending in a second direction crossing the first direction; a lower wiring structure on the second surface of the base insulating layer; and a through electrode spaced apart from the gate structure, the first source / drain pattern between the through electrode and the gate structure. The through electrode may penetrate the base insulating layer and electrically connect the first source / drain pattern to the lower wiring structure. The first direction may be parallel to the first surface of the base insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0144679 filed in the Korean Intellectual Property Office on October 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] Semiconductor devices are used in various electronic devices, such as storage devices for storing data and processors for calculating and processing data. With the development of the electronics industry, various methods for improving various characteristics (e.g., integration, reliability, speed, and functionality) of semiconductor devices are being studied. For example, semiconductor devices with three-dimensional structures have been proposed to overcome the limitations caused by the size reduction of semiconductor devices.

[0005] Recently, research is being conducted to improve routing congestion and scale the size of semiconductor devices by placing a power transmission network on the back side of a substrate to route signals provided to the semiconductor devices. Summary of the invention

[0006] The present disclosure attempts to provide a semiconductor device and a method of manufacturing the same that implements a backside power transmission network by using a simplified manufacturing process.

[0007] According to example embodiments, a semiconductor device may include: a base insulating layer including a first surface and a second surface opposite to each other; a channel layer on the first surface of the base insulating layer; a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction on the first surface of the base insulating layer, the channel layer being interposed between the first source / drain pattern and the second source / drain pattern, the first direction being parallel to the first surface of the base insulating layer; a gate structure extending in a second direction on the first surface of the base insulating layer, the second direction intersecting the first direction, and the gate structure surrounding the channel layer; a lower wiring structure on the second surface of the base insulating layer; and a through electrode spaced apart from the gate structure, the first source / drain pattern being between the through electrode and the gate structure, the through electrode penetrating the base insulating layer, and electrically connecting the first source / drain pattern to the lower wiring structure.

[0008] According to example embodiments, a method for manufacturing a semiconductor device may include: forming a channel layer, a first source / drain pattern, and a second source / drain pattern on a first surface of a substrate, the channel layer being between the first source / drain pattern and the second source / drain pattern in a first direction, the first direction being parallel to the first surface of the substrate; forming a gate structure extending in a second direction on the first surface of the substrate, the gate structure surrounding the channel layer in the second direction, the second direction intersecting the first direction; forming a base insulating layer, the forming of the base insulating layer including: removing a portion or all of the substrate, and forming the base insulating layer in a region where a portion or all of the substrate is removed; forming a through electrode spaced apart from the gate structure, the first source / drain pattern being between the through electrode and the gate structure, the through electrode penetrating the base insulating layer and being connected to the first source / drain pattern; and forming a lower wiring structure on a lower surface of the base insulating layer, the lower wiring structure being connected to the through electrode.

[0009] According to example embodiments, a semiconductor device may include: a base insulating layer including a first surface and a second surface opposite to each other; a channel layer on the first surface of the base insulating layer; a first source / drain pattern and a second source / drain pattern on the first surface of the base insulating layer, and the channel layer is between the first source / drain pattern and the second source / drain pattern in a first direction, the first direction being parallel to the first surface of the base insulating layer; a gate structure extending in a second direction on the first surface of the base insulating layer, the second direction intersecting the first direction, and the gate structure surrounding the channel layer in the second direction; an interlayer insulating layer covering the first source / drain pattern, the second source / drain pattern and the gate structure; an upper wiring structure on the interlayer insulating layer; a lower wiring structure on the second surface of the base insulating layer; a through electrode spaced apart from the gate structure, the first source / drain pattern being between the through electrode and the gate structure, the through electrode penetrating the base insulating layer and electrically connecting the first source / drain pattern to the lower wiring structure; and a contact electrode penetrating the interlayer insulating layer, the contact electrode having a first end connected to the second source / drain pattern, and a second end connected to the upper wiring structure.

[0010] According to an embodiment, some gate structures can be used as electrodes for connecting a back power transmission network and a source / drain pattern. According to an embodiment, a source / drain pattern and a back power transmission network of a semiconductor device can be connected by using a previously used structure and manufacturing process, and accordingly, the manufacturing process of the semiconductor device can be simplified and the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a top plan view showing a semiconductor device according to an embodiment.

[0012] Figure 2 is along Figure 1 A cross-sectional view of the semiconductor device taken along line II'.

[0013] Figure 3 is along Figure 1 sectional view of the semiconductor device taken along line II-II'.

[0014] Figure 4 is along Figure 1 1 is a cross-sectional view of the semiconductor device taken along line III-III'.

[0015] Figures 5 to 19 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment.

[0016] Fig. 20 is a top plan view showing a semiconductor device according to an embodiment.

[0017] Fig.21 is along Fig. 20 A cross-sectional view of the semiconductor device taken along line II'.

[0018] Fig. 22 is along Fig. 20 sectional view of the semiconductor device taken along line II-II'.

[0019] Fig.23 is along Fig. 20 1 is a cross-sectional view of the semiconductor device taken along line III-III'.

[0020] Figures 24 to 40 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment.

[0021] Fig.41 is a top plan view showing a semiconductor device according to an embodiment.

[0022] Fig.42 is along Fig.41 A cross-sectional view of the semiconductor device taken along line IV-IV'.

[0023] Fig.43 is along Fig.41 A cross-sectional view of the semiconductor device taken along line V-V'. DETAILED DESCRIPTION

[0024] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings which show embodiments of the present disclosure. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0025] The drawings and description should be regarded as illustrative in nature, rather than restrictive.Throughout the specification, like reference numerals designate like elements.

[0026] For better understanding and ease of description, the size and thickness of each constituent element in the drawings are arbitrarily shown, and the following embodiments are not limited thereto. In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. In the drawings, for ease of description, the thickness of some layers and regions is exaggerated.

[0027] Additionally, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "above" or "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, when an element is referred to as being "above" or "on" a reference element, it can be located above or below the reference element and is not necessarily referred to as being "above" or "on" in a direction opposite to gravity.

[0028] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0029] Although the term "equal to" is used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being "equal to" another element, it should be understood that the element or value can be "equal to" the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0030] Furthermore, throughout the specification, the phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0031] In the drawings for semiconductor devices according to the embodiments, a gate-all-around (GAA) and an MBCFET including nanowires or nanosheets are shown as examples only. TM (Multi-bridge channel field effect transistor), but not limited thereto. According to an embodiment, the semiconductor device may include a fin transistor (FinFET) having a channel region with a fin pattern shape, a tunneling transistor (tunneling FET), a 3D stacked field effect transistor (3DSFET) structure, a complementary field effect transistor (CFET) structure.

[0032] Hereinafter, semiconductor devices according to embodiments will be described with reference to the accompanying drawings.

[0033] Figure 1 is a top plan view showing a semiconductor device according to an embodiment. Figures 2 to 4 is a cross-sectional view showing a semiconductor device according to an embodiment. Specifically, Figure 2 is along Figure 1 A cross-sectional view of the semiconductor device taken along line II'. Figure 3 is along Figure 1 sectional view of the semiconductor device taken along line II-II'. Figure 4 is along Figure 1 1 is a cross-sectional view of the semiconductor device taken along line III-III'.

[0034] refer to Figures 1 to 4 According to the embodiment, the semiconductor device may include a base insulating layer 100, a channel layer CH located on a first surface of the base insulating layer 100, a source / drain pattern 150 located on both sides of the channel layer CH, gate structures M_GS and S_GS surrounding the channel layer CH, a lower wiring structure 220 located on a second surface of the base insulating layer 100, and a through electrode 190 inserted into the first source / drain pattern 151 and spaced apart from the gate structure GS.

[0035] The base insulating layer 100 may include a layer such as an oxide, a nitride, an oxynitride, or a combination thereof. The base insulating layer 100 may include an insulating material. For example, the base insulating layer 100 may include silicon nitride (SiN). Although the base insulating layer 100 is shown to be a single layer, this is only for ease of description and is not limited thereto. The first surface and the second surface of the base insulating layer 100 may be formed as a plane parallel to the first direction D1 and the second direction D2 intersecting the first direction D1. For example, the first surface of the base insulating layer 100 may be an upper surface, and the second surface may be a bottom surface. The upper surface of the base insulating layer 100 is a surface opposite to the bottom surface of the base insulating layer 100 in the third direction D3. The third direction D3 may be a direction perpendicular to the first direction D1 and the second direction D2. The bottom surface of the base insulating layer 100 may be referred to as the back side of the base insulating layer 100. In some embodiments, the logic circuit in the cell area may be implemented on the upper surface of the base insulating layer 100. The base insulating layer 100 may include a device isolation trench STI.

[0036] The channel layer CH may be disposed on the base insulating layer 100. In an embodiment, a plurality of channel layers 110a, 110b, 110c, and 110d may be disposed on the base insulating layer 100. For example, each of the plurality of channel layers 110a, 110b, 110c, and 110d may be a sheet-shaped semiconductor layer. Each semiconductor layer may be a nanosheet having a thickness of several nanometers along the third direction D3.

[0037] The channel layer CH may provide a path through which current flows between the two source / drain patterns 150. Figure 2 and Figure 3, the channel layers 110a, 110b, 110c, and 110d may be disposed on the source / drain pattern 150 and connected to the source / drain pattern 150. The channel layers 110a, 110b, 110c, and 110d may penetrate a portion of the gate structure GS in a direction (e.g., a first direction D1) intersecting a direction in which the gate structure GS extends. The channel layers 110a, 110b, 110c, and 110d may be arranged to be spaced apart from the upper surface of the base insulating layer 100 in a vertical direction (e.g., a third direction D3). Figure 2 and Figure 3 , four channel layers 110a, 110b, 110c and 110d are shown to be spaced apart, but are not limited thereto, and the number of stacked channel layers CH may be changed in various ways. The channel layer CH may include a semiconductor material. For example, the channel layer CH may include a group IV semiconductor such as Si and Ge, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc. In an embodiment, the lower pattern BP may also be disposed below the channel layer CH. Specifically, the lower pattern BP may be located between the base insulating layer 100 and the sub-gate structure S_GS located at the bottom among the plurality of sub-gate structures S_GS. The upper surface of the lower pattern BP may contact the lower surface of the sub-gate structure S_GS located at the bottom among the plurality of sub-gate structures S_GS. The lower pattern BP may include the same material as the channel layer CH. For example, the lower pattern BP may include a group IV semiconductor such as Si and Ge, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc. However, it is not limited thereto, and the lower pattern BP may include a material different from the channel layer CH.

[0038] As another example, Figure 2 and Figure 3 Unlike that shown in , the semiconductor device may not include the lower pattern BP. In this case, a lower surface of the sub-gate structure S_GS located at the lowermost among the sub-gate structures S_GS may directly contact the base insulating layer 100 .

[0039] As another example, Figure 2 and Figure 3 , a partial area of ​​the base insulating layer 100 overlapping with the sub-gate structure S_GS in the third direction D3 may extend into the interior of the lower pattern BP and directly contact the lower surface of the sub-gate structure S_GS located at the bottom among the sub-gate structures S_GS. At this time, the lower pattern BP may be in the lower part of the source / drain pattern 150 located at both sides of the sub-gate structure S_GS, and the lower patterns BP located in the lower parts of different source / drain patterns 150 may be separated by the base insulating layer 100. The base insulating layer 100 may be between the lower patterns BP located in the lower parts of different source / drain patterns 150.

[0040] The semiconductor device according to the embodiment may further include a field insulating layer 105. The field insulating layer 105 may be located on the lower pattern BP. The field insulating layer 105 may be a sidewall located on the lower pattern BP. The field insulating layer 105 may not be located on the upper surface of the lower pattern BP. The field insulating layer 105 may cover a portion of the sidewall of the lower pattern BP. In this case, a portion of the lower pattern BP may protrude from the upper surface of the field insulating layer 105 in the third direction D3. Unlike shown, the field insulating layer 105 may completely cover the side surface of the lower pattern BP. The field insulating layer 105 may include a layer of, for example, an oxide, a nitride, an oxynitride, or a combination thereof. Although the field insulating layer 105 is shown to be a single layer, this is only for ease of illustration and is not limited thereto.

[0041] The source / drain pattern 150 may be located on the base insulating layer 100. The source / drain pattern 150 may be located on both sides of the channel layer CH or the sub-gate structure S_GS. Specifically, the two source / drain patterns 150 may be arranged in a direction (e.g., a first direction D1) intersecting the direction in which the gate structure GS extends, and the channel layer CH or the sub-gate structure S_GS is inserted. The source / drain pattern 150 may directly contact the channel layer CH or the sub-gate structure S_GS. The source / drain pattern 150 may directly contact the sub-interface insulating layer 133S of the sub-gate structure S_GS. Although not shown in the drawings, an internal spacer may also be provided between the source / drain pattern 150 and the sub-interface insulating layer 133S. The internal spacer may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) and at least one of a combination thereof.

[0042] The source / drain pattern 150 may be formed on a sacrificial layer SC_L (see Figure 5 ) and the active pattern ACT_L (see Figure 5 ) is formed as an epitaxial layer formed by selective epitaxial growth (SEG) in a partially recessed region. That is, the source / drain pattern 150 may fill the sacrificial layer SC_L (see Figure 5 ) and the active pattern ACT_L (see Figure 5 ) is a recessed area.

[0043] The source / drain pattern 150 may include a first source / drain pattern 151, a second source / drain pattern 152, and a third source / drain pattern 153. The first to third source / drain patterns 151, 152, and 153 may include liner layers 151a, 152a, and 153a, and filling layers 151b, 152b, and 153b, respectively. The liner layers 151a, 152a, and 153a may be located on the side surfaces and bottom surfaces of the first to third source / drain patterns 151, 152, and 153. The liner layers 151a, 152a, and 153a may directly contact the sub-gate structure S_GS and the channel layer CH. That is, the liner layers 151a, 152a, and 153a may be formed along the source / drain recess RC1 described later (see Figure 6 ) surface contour positioning. The filling layers 151b, 152b and 153b may be located on the liner layers 151a, 152a and 153a. The filling layers 151b, 152b and 153b, and the liner layers 151a, 152a and 153a may have upper surfaces of substantially the same height. That is, the filling layers 151b, 152b and 153b may fill the source / drain recesses RC1 (see Figure 6 )’s interior.

[0044] The source / drain pattern 150 may include a semiconductor material. The source / drain pattern 150 may include, for example, silicon or germanium. In addition, the source / drain pattern 150 may include, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the source / drain pattern 150 may include silicon, silicon-germanium, germanium, silicon carbide, etc., but is not limited thereto. In an embodiment, the liner layers 151a, 152a, and 153a, and the filling layers 151b, 152b, and 153b may have different concentrations of silicon (Si) or germanium (Ge). For example, the concentration of silicon (Si) or germanium (Ge) included in the liner layers 151a, 152a, and 153a may be less than the concentration of silicon (Si) or germanium (Ge) included in the filling layers 151b, 152b, and 153b.

[0045] In an embodiment, the first source / drain pattern 151 and the third source / drain pattern 153 may be connected to the lower wiring structure 220. The first source / drain pattern 151 and the third source / drain pattern 153 may be connected to the lower wiring structure 220 through the through electrode 190. The through electrode 190 may include a lower conductive pattern 190b and an upper conductive pattern 190a. Partial areas of the first source / drain pattern 151 and the third source / drain pattern 153 may be penetrated by the lower conductive pattern 190b. For example, a portion of the side surface or bottom surface of the first source / drain pattern 151 and the third source / drain pattern 153 may be penetrated by the lower conductive pattern 190b. A portion of the side surface of the first source / drain pattern 151 and the third source / drain pattern 153 may be connected to the upper conductive pattern 190a described later. Accordingly, at least partial areas of the first source / drain pattern 151 and the third source / drain pattern 153 may contact the lower conductive pattern 190b and / or the upper conductive pattern 190a. The first source / drain pattern 151 and the third source / drain pattern 153 may receive power from the lower wiring structure 220 through the lower conductive pattern 190 b and / or the upper conductive pattern 190 a .

[0046] In an embodiment, the second source / drain pattern 152 may be connected to an upper wiring structure 210 to be described later. The second source / drain pattern 152 may be connected to the upper wiring structure 210 through the contact electrode 180. A portion of an upper surface of the second source / drain pattern 152 may be connected to a portion of the contact electrode 180. In an embodiment, a current having flowed through the channel layer CH may be transferred to the upper wiring structure 210 through the second source / drain pattern 152 and the contact electrode 180. Figure 2 Although the filling layer 152 b of the second source / drain pattern 152 is shown as being connected to the contact electrode 180 , the contact electrode 180 may also be connected to the liner layer 152 a of the second source / drain pattern 152 .

[0047] The gate structure GS may be disposed on the substrate insulating layer 100. The gate structure GS may include a sub-gate structure S_GS and a main gate structure M_GS. The sub-gate structure S_GS may be disposed on the substrate insulating layer 100, and the main gate structure M_GS may be disposed on the sub-gate structure S_GS. On the substrate insulating layer 100, the gate structure GS may extend in different directions other than the direction in which the source / drain pattern 150 is arranged. For example, on the substrate insulating layer 100, the gate structure GS may extend in a direction (e.g., a second direction D2) intersecting the direction in which the source / drain pattern 150 is arranged. The gate structure GS may be located on the substrate insulating layer 100. The gate structure GS may be arranged to be spaced apart in the first direction D1. The main gate structure M_GS may be on the uppermost channel layer 110a. The main gate structure M_GS may also be located on the side surface of the structure in which the channel layers 110a, 110b, 110c, and 110d and the sub-gate structure S_GS are stacked. That is, the main gate structure M_GS may surround each of the channel layers 110a, 110b, 110c, and 110d together with the sub-gate structure S_GS. However, the main gate structure M_GS may not be located on the surface of each of the channel layers 110a, 110b, 110c, and 110d contacting the source / drain pattern 150. Figure 2 and Figure 3 In FIG. 4 , four sub-gate structures S_GS are arranged in the third direction, but the number of arranged sub-gate structures S_GS is not limited thereto. For example, the gate structure GS may include three sub-gate structures S_GS.

[0048] The sub-gate structure S_GS may contact the source / drain pattern 150. For example, the sub-gate structure S_GS may directly contact the source / drain pattern 150. The sub-gate structure S_GS may be located on both sides of the source / drain pattern 150. The sub-gate structures S_GS may be formed as multiple layers. For example, the sub-gate structures S_GS may include a sub-gate electrode 131S, a sub-gate insulating layer 132S, and a sub-interface insulating layer 133S. The sub-gate structure S_GS and the channel layers 110a, 110b, 110c, and 110d may be alternately stacked in the third direction D3. The sub-gate structure S_GS may surround the surfaces of the channel layers 110a, 110b, 110c, and 110d except the surface connected to the source / drain pattern 150 together with the main gate structure M_GS.

[0049] The sub-gate electrode 131S may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The sub-gate electrode 131S may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAl ...N), tungsten aluminum nitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum nitride (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum nitride (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nit ), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and at least one of their combinations, but not limited thereto. The conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the above materials, but not limited thereto.

[0050] The sub-interface insulating layer 133S may be positioned along the periphery of the channel layer CH. For example, the sub-interface insulating layer 133S may surround the surface of the channel layer CH except for the surface connected to the source / drain pattern 150. The sub-interface insulating layer 133S may directly contact the source / drain pattern 150 and the channel layer CH. The sub-interface insulating layer 133S may be inserted between the channel layer CH and the sub-gate insulating layer 132S. The sub-interface insulating layer 133S may include, for example, silicon oxide (SiO 2 ).

[0051] The sub-gate insulating layer 132S may extend along the upper surface of the sub-interface insulating layer 133S. The sub-gate insulating layer 132S may surround the channel layer CH. For example, the sub-gate insulating layer 132S may surround the surface of the channel layer CH except the surface connected to the source / drain pattern 150. The sub-gate insulating layer 132S may be positioned along the periphery of the channel layer CH. The sub-gate insulating layer 132S may be inserted between the sub-gate electrode 131S and the sub-interface insulating layer 133S. The sub-gate insulating layer 132S may include, for example, a high dielectric constant material. The high dielectric constant material may include a dielectric having a dielectric constant greater than silicon oxide (SiO 2 ) Materials with high dielectric constants (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)).

[0052] The main gate structure M_GS may be located on the sub-gate structure S_GS and the channel layer CH. The main gate structure M_GS may be located on the upper surface of the channel layer CH. The main gate structure M_GS may be formed as a multilayer. For example, the main gate structure M_GS may include a main gate electrode 131M, a main interface insulating layer 133M, and a main gate insulating layer 132M. The main gate structure M_GS may surround the surface of at least one (e.g., 110a) of the channel layer CH together with the sub-gate structure S_GS except the surface connected to the source / drain pattern 150.

[0053] The main gate electrode 131M may be located on the sub-gate structure S_GS and the channel layer CH. The main gate electrode 131M may be located on the upper surface of the channel layer CH. The main gate electrode 131M may include the same material as the sub-gate electrode 131S. For example, the main gate electrode 131M may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0054] The main interface insulating layer 133M may extend along the upper surface of the channel layer CH. The main interface insulating layer 133M may include, for example, silicon oxide (SiO 2 ). The main gate insulating layer 132M may extend along the side surface and the bottom surface of the main gate electrode 131M. The main gate insulating layer 132M may include, for example, a high dielectric constant material.

[0055] The semiconductor device according to the embodiment may further include a capping layer 141 and a gate spacer 142. The gate spacer 142 may be located on the side surface of the main gate electrode 131M. The gate spacer 142 may not be disposed between the lower pattern BP and the channel layer CH. The gate spacer 142 may not be disposed between the channel layers CH adjacent to each other along the third direction D3. Although the gate spacer 142 is shown as a single layer, this is only for ease of explanation and is not limited thereto. The gate spacer 142 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) and at least one of a combination thereof.

[0056] The capping layer 141 may be located on the main gate structure M_GS and the gate spacer 142. Unlike shown, the capping layer 141 may be located between the gate spacers 142. The capping layer 141 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The capping layer 141 may include a material having an etching selectivity relative to the interlayer insulating layer 170 described later.

[0057] The through electrode 190 may be positioned to be spaced apart from the gate structure GS, interposing the first source / drain pattern 151. The through electrode 190 may penetrate the base insulating layer 100, and electrically connect a lower wiring structure 220 described later and the first source / drain pattern 151. In an embodiment, the through electrode 190 may include an upper conductive pattern 190a and a lower conductive pattern 190b.

[0058] The upper conductive pattern 190a may be located between two source / drain patterns 150. The upper conductive pattern 190a may contact the source / drain patterns 150 of two different semiconductor devices at the same time. Figure 2 , the upper conductive pattern 190a may contact the first source / drain pattern 151 and the third source / drain pattern 153 at the same time. The first source / drain pattern 151 and the third source / drain pattern 153 may be the source / drain pattern 150 of each of two adjacent different semiconductor devices. The upper conductive pattern 190a may extend in the third direction D3. The upper conductive pattern 190a may have an upper surface at substantially the same height as the upper surface of the main gate structure M_GS and the dummy gate spacer 160b described later. The upper surface of the upper conductive pattern 190a may contact the lower surface of the dummy capping layer 160a described later. The lower surface of the upper conductive pattern 190a may contact the upper surface of the lower conductive pattern 190b.

[0059] In an embodiment, the width of the upper conductive pattern 190a in the first direction D1 may be smaller than the width of the lower conductive pattern 190b in the first direction D1. The width of the upper conductive pattern 190a in the first direction D1 may be substantially the same as the width of the adjacent sub-gate structure S_GS in the first direction D1.

[0060] In an embodiment, the width of the upper conductive pattern 190a in the first direction D1 may be the same as the width of the channel layer CH in the first direction D1. However, it is not limited thereto, and the width of the upper conductive pattern 190a in the first direction D1 may be smaller than the width of the channel layer CH in the first direction D1. When the width of the upper conductive pattern 190a in the first direction D1 is smaller than the width of the channel layer CH in the first direction D1, residual semiconductor material may be located between the upper conductive pattern 190a and the source / drain pattern 150. When the process of forming the upper conductive pattern 190a described later (see Fig. 9 ), when the channel layer CH and the sacrificial layer SC_L are removed in the step of forming the channel layer CH, the remaining semiconductor material may be a portion of the channel layer CH that is not removed but remains between the source / drain pattern and the sidewall of the trench TR. The remaining semiconductor material may include the same material as the channel layer CH. For example, the remaining semiconductor material may include Si or SiGe.

[0061] The upper conductive pattern 190a may include a metal or a metal alloy. The upper conductive pattern 190a may include, for example, at least one of titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru), and platinum (Pt). In an embodiment, the upper conductive pattern 190a may include the same material as the lower conductive pattern 190b. The upper conductive pattern 190a may be integrally formed in the same process as the lower conductive pattern 190b.

[0062] The lower conductive pattern 190b may be located between the lower wiring structure 220 and the upper conductive pattern 190a. The lower conductive pattern 190b may penetrate the base insulating layer 100 and extend in the third direction D3. The first end of the lower conductive pattern 190b may be connected to the lower surface of the upper conductive pattern 190a, and the second end thereof may be connected to the lower wiring structure 220. The width of the lower conductive pattern 190b along the first direction D1 may be greater than the interval between the third source / drain pattern 153 and the source / drain pattern 150 (e.g., the first source / drain pattern 151). The lower conductive pattern 190b may overlap with a partial area of ​​the source / drain pattern 150. For example, the lower conductive pattern 190b may overlap with at least a portion of the first source / drain pattern 151 and at least a portion of the third source / drain pattern 153. The lower conductive pattern 190b may penetrate a portion of the lower surface and the side surface of the source / drain pattern 150 and extend to a partial area inside the source / drain pattern 150.

[0063] The upper surface of the lower conductive pattern 190b may be located between the upper surface of the source / drain pattern 150 and the lower surface of the source / drain pattern 150. The lower conductive pattern 190b may be located between two source / drain patterns 150. The lower conductive pattern 190b may contact the source / drain patterns 150 of two different semiconductor devices at the same time. For example, referring to Figure 2 , the lower conductive pattern 190b may simultaneously contact the first source / drain pattern 151 and the third source / drain pattern 153. The first source / drain pattern 151 and the third source / drain pattern 153 may be the source / drain pattern 150 of each of two adjacent different semiconductor devices. The upper surface of the lower conductive pattern 190b may contact the lower surface of the upper conductive pattern 190a.

[0064] The upper surface of the lower conductive pattern 190b may directly contact the lower surface of the upper conductive pattern 190a. In an embodiment, the interface between the lower conductive pattern 190b and the upper conductive pattern 190a may be located at a level higher than the lower surface of the lowermost sub-gate structure S_GS among the adjacent sub-gate structures S_GS in the third direction D3. The interface between the lower conductive pattern 190b and the upper conductive pattern 190a may be located at a level lower than the upper surface of the uppermost sub-gate structure S_GS among the adjacent sub-gate structures S_GS in the third direction D3.

[0065] In an embodiment, the interface between the lower conductive pattern 190b and the upper conductive pattern 190a may be located closer to the lowermost channel layer (eg, Figure 2 The interface between the lower conductive pattern 190b and the upper conductive pattern 190a may be located at a level higher than the uppermost channel layer (eg, Figure 2 110a) is at a lower level than the upper surface.

[0066] In an embodiment, the width of the lower conductive pattern 190b in the first direction D1 may be greater than the width of the upper conductive pattern 190a in the first direction D1. The width of the lower conductive pattern 190b in the first direction D1 may be greater than the width of the adjacent sub-gate structure S_GS in the first direction D1. The width of the lower conductive pattern 190b in the first direction D1 may be greater than the width of the channel layer CH in the first direction D1. The lower conductive pattern 190b may include a metal or a metal alloy. The lower conductive pattern 190b may include, for example, at least one of titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru) and platinum (Pt). In an embodiment, the lower conductive pattern 190b may include the same material as the upper conductive pattern 190a. The lower conductive pattern 190b may be integrally formed in the same process as the upper conductive pattern 190a. The semiconductor device according to an embodiment may also include a dummy capping layer 160a and a dummy gate spacer 160b. The dummy capping layer 160a may be located on the upper conductive pattern 190a and the dummy gate spacer 160b. The dummy capping layer 160a may cover the upper surface of the upper conductive pattern 190a and the dummy gate spacer 160b. The dummy capping layer 160a may be located in a layer substantially the same as the capping layer 141. The dummy capping layer 160a may have an upper surface at substantially the same height as the upper surface of the capping layer 141. The dummy capping layer 160a may have a lower surface at substantially the same height as the lower surface of the capping layer 141. The dummy capping layer 160a may include the same material as the capping layer 141. The dummy capping layer 160a may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and a combination thereof. The dummy capping layer 160a may include a material having an etching selectivity relative to the interlayer insulating layer 170. The dummy capping layer 160 a may be formed simultaneously with the capping layer 141 in the same process as the capping layer 141 .

[0067] The dummy gate spacer 160b may be located on the side surface of the upper conductive pattern 190a. Specifically, the dummy gate spacer 160b may be located between the interlayer insulating layer 170 and the upper conductive pattern 190a. The dummy gate spacer 160b may not be located on the interface between the upper conductive pattern 190a and the first source / drain pattern 151. That is, in the region adjacent to the source / drain pattern 150, the dummy gate spacer 160b may have a lower surface at substantially the same height as the upper surface of the source / drain pattern 150. The dummy gate spacer 160b may have an upper surface at substantially the same height as the upper surface of the main gate structure M_GS. The dummy gate spacer 160b may be located in substantially the same layer as the gate spacer 142. The dummy gate spacer 160b may have an upper surface at substantially the same height as the upper surface of the gate spacer 142. The dummy gate spacer 160b may have a lower surface at substantially the same height as the lower surface of the gate spacer 142. The dummy gate spacer 160b may include the same material as the gate spacer 142. For example, the dummy gate spacer 160b may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The dummy gate spacer 160 b may be formed simultaneously with the gate spacer 142 in the same process as the gate spacer 142 .

[0068] The lower wiring structure 220 may be disposed on the bottom surface of the base insulating layer 100. In an embodiment, the lower wiring structure 220 may be a component for supplying power to at least one of the source / drain patterns 150. For example, the lower wire structure 220 may be a power transmission network. The lower wiring structure 220 may include a lower wiring 221, a lower via 222, and a lower insulating layer 223. The lower wiring 221 and the lower via 222 may be located on the bottom surface of the base insulating layer 100. The lower wiring 221 and the lower via 222 may include a metal (e.g., copper). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may be disposed between the bottom surface of the base insulating layer 100, the lower wiring 221, and the lower via 222, and insulate them. That is, the lower insulating layer 223 may cover the lower wiring 221 and the bottom surface of the base insulating layer 100. The lower wiring 221 and the lower via 222 may be located in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0069] In an embodiment, the semiconductor device may further include an interlayer insulating layer 170 , an upper wiring structure 210 , and a contact electrode 180 .

[0070] The interlayer insulating layer 170 may cover the channel layer CH, the gate structure GS, the source / drain pattern 150, and the through electrode 190. The interlayer insulating layer 170 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylchlorotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethyl silicon phosphate (TMSP), polytetrafluoroethylene (PTFE), eastern burning silazane (TOSZ), fluorinated silicate glass (FSG), polyimide nanofoam (e.g., polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica or a combination thereof, but is not limited thereto. In an embodiment, the interlayer insulating layer 170 may include a material different from the base insulating layer 100.

[0071] The upper wiring structure 210 may be located on the interlayer insulating layer 170. The upper wiring structure 210 may include an upper wiring 211, an upper via 212, and an upper insulating layer 213. The upper wiring 211 and the upper via 212 may include a metal (e.g., copper). The upper insulating layer 213 may be disposed between the upper wiring 211 and the upper via 212 and insulate them. The upper insulating layer 213 may cover the interlayer insulating layer 170 and the upper wiring 211. The upper wiring 211 and the upper via 212 may be located within the upper insulating layer 213. The upper insulating layer 213 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0072] The contact electrode 180 may be located between the upper wiring structure 210 and the first source / drain pattern 150 among the source / drain patterns 150. The contact electrode 180 may include a first via 180a and a second via 180b. The contact electrode 180 may penetrate the interlayer insulating layer 170 in the third direction D3. The first via 180a may contact the upper surface of the second source / drain pattern 152. The first via 180a may extend in the third direction D3. The first via 180a may have an upper surface at a height that is the same as or higher than the upper surface of the capping layer 141. The second via 180b may be located on the first via 180a. The first end of the second via 180b may directly contact the first via 180a. The second end of the second via 180b may directly contact the upper wiring structure 210. The first via 180a and the second via 180b may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0073] Figures 5 to 24 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment.

[0074] like Figure 5 As shown in , a lower pattern BP and an upper pattern structure U_AP may be formed on a substrate 10. The substrate 10 may be a silicon on insulator (SOI) or bulk silicon. Alternatively, the substrate 10 may be a silicon substrate, and may include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The lower pattern BP may be a portion of the substrate 10.

[0075] The upper pattern structure U_AP may be located on the lower pattern BP. The upper pattern structure U_AP may include sacrificial layers SC_L and active patterns ACT_L alternately stacked on the lower pattern BP. For example, the sacrificial layers SC_L may include silicon germanium (SiGe). The active patterns ACT_L may include silicon (Si).

[0076] Subsequently, a preliminary gate insulating layer 132P, a preliminary main gate electrode 131MP, and a preliminary capping layer 141P are formed on the upper pattern structure U_AP. The preliminary gate insulating layer 132P may include, for example, silicon oxide (SiO 2), but not limited thereto. The preliminary main gate electrode 131MP may include, for example, polysilicon, but not limited thereto. The preliminary capping layer 141P may include, for example, silicon nitride, but not limited thereto. On both side surfaces of the preliminary main gate electrode 131MP, a preliminary gate spacer 142P may be formed.

[0077] like Figure 6 As shown in FIG. 1 , by using the preliminary capping layer 141P and the preliminary gate spacer 142P as a mask, a source / drain recess RC1 is formed by etching at least a portion of the upper pattern structure U_AP. As the source / drain recess RC1 is formed, at least a portion of the lower pattern BP may be etched. A portion of the source / drain recess RC1 may be formed in the substrate 10. At the same time, as shown in FIG. Figure 6 As shown in , after forming the source / drain recess RC1, a recess process relative to the sacrificial layer SC_L may be performed. In the recess process, the sacrificial layer SC_L is etched by a wet etching or dry etching method, and accordingly, the length of the sacrificial layer SC_L in the first direction D1 may be further reduced. Accordingly, the surface of the sacrificial layer SC_L contacting the source / drain recess RC1 may have a concave shape toward the source / drain recess RC1.

[0078] As the source / drain recess RC1 is formed, the active pattern ACT_L is separated so that channel layers 110a, 110b, 110c, and 110d can be formed. The channel layers 110a, 110b, 110c, and 110d can be located on both sides of the source / drain recess RC1. The channel layers 110a, 110b, 110c, and 110d and the sacrificial layers SC_L can be alternately stacked in the third direction D3. At this time, the lengths of the channel layers 110a, 110b, 110c, and 110d can be different or the same.

[0079] like Figure 7 As shown in , a source / drain pattern 150 may be formed in a source / drain recess RC1. The source / drain pattern 150 may be formed on a substrate 10. The source / drain pattern 150 may be formed by using an epitaxial growth method. At this time, the inner wall of the source / drain recess may be used as a seed crystal. The source / drain pattern 150 may directly contact the substrate 10 or the lower pattern BP. The source / drain pattern 150 may directly contact the channel layers 110a, 110b, 110c, and 110d and the sacrificial layer SC_L. The source / drain pattern 150 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The source / drain pattern 150 may be formed of several regions with different concentrations. For example, referring to Figure 7, each of the source / drain patterns 151, 152, and 153 may include liner layers 151a, 152a, and 153a, and filling layers 151b, 152b, and 153b. First, liner layers 151a, 152a, and 153a are formed along the sidewalls and bottom surfaces of the source / drain recess RC1, and filling layers 151b, 152b, and 153b may be formed on each of the liner layers 151a, 152a, and 153a. The liner layers 151a, 152a, and 153a, and the filling layers 151b, 152b, and 153b may be formed by using an epitaxial growth method, respectively. The liner layers 151a, 152a, and 153a, and the filling layers 151b, 152b, and 153b may include semiconductor materials. For example, the liner layers 151a, 152a and 153a, and the filling layers 151b, 152b and 153b may include silicon (Si) or germanium (Ge) as elemental semiconductor materials. In an embodiment, the liner layers 151a, 152a and 153a, and the filling layers 151b, 152b and 153b may have different concentrations of silicon (Si) or germanium (Ge). For example, the concentration of silicon (Si) or germanium (Ge) included in the liner layers 151a, 152a and 153a may be less than the concentration of silicon (Si) or germanium (Ge) included in the filling layers 151b, 152b and 153b.

[0080] like Figure 8 As shown in , an interlayer insulating layer 170 may be formed on the source / drain pattern 150. Subsequently, a portion of the interlayer insulating layer 170 and the preliminary capping layer 141P may be removed to expose the upper surface of the preliminary main gate electrode 131MP. At this time, a portion of the preliminary gate spacer 142P may be removed together so that the gate spacer 142 and the dummy gate spacer 160b may be formed. The gate spacer 142 and the dummy gate spacer 160b may be formed simultaneously.

[0081] like Fig. 9 As shown in , the trench TR can be formed by etching a portion of the channel layer CH and a portion of the sacrificial layer SC_L. The portion of the channel layer CH and the portion of the sacrificial layer SC_L that are removed may be a partial region of the channel layer CH and a partial region of the sacrificial layer SC_L located between the source / drain patterns 150 of two adjacent semiconductor devices. For example, in Fig. 9In the embodiment of the present invention, a partial region of the channel layer CH and a partial region of the sacrificial layer SC_L located between the first source / drain pattern 151 and the third source / drain pattern 153 may be removed. At this time, the preliminary gate insulating layer 132P and the preliminary main gate electrode 131MP located on the removed channel layer CH and the sacrificial layer SC_L may also be removed together. However, even in this case, the dummy gate spacer 160b may not be removed. The trench TR may penetrate the channel layer CH and the sacrificial layer SC_L and extend in the third direction D3. That is, the bottom surface of the trench TR may be positioned closer to the bottom surface of the substrate 10 than the bottom surface of the source / drain pattern 150. While removing a partial region of the channel layer CH, a partial region of the sacrificial layer SC_L, a portion of the preliminary gate insulating layer 132P, and a portion of the preliminary main gate electrode 131MP located between the source / drain patterns 150 of two adjacent semiconductor devices, the remaining area may be covered by a separate mask pattern. In an embodiment, the removed channel layer CH, the sacrificial layer SC_L, the preliminary gate insulating layer 132P, and the preliminary main gate electrode 131MP may be removed by a dry etching process. However, it is not limited thereto, and all or part of the removed channel layer CH, the sacrificial layer SC_L, the preliminary gate insulating layer 132P, and the preliminary main gate electrode 131MP may be removed by a wet etching process. Fig. 9 After forming the trench TR, a partial region of the channel layer CH may remain without being removed between the first source / drain pattern 151 and the sidewall of the trench TR and between the third source / drain pattern 153 and the sidewall of the trench TR.

[0082] like Fig.10 As shown in , the trench TR may be filled with a dummy insulating pattern DD. The dummy insulating pattern DD may include an insulating material. For example, the dummy insulating pattern DD may include silicon oxynitride (SiON) or silicon nitride (SiN). After the dummy insulating pattern DD is filled in the trench TR, a process for planarizing the upper surface of the dummy insulating pattern DD may be additionally performed. For example, the upper surface of the dummy insulating pattern DD may be planarized by a chemical mechanical polishing (CMP) process.

[0083] like Fig.11 As shown in FIG, after forming the dummy insulating pattern DD, the remaining preliminary gate insulating layer 132P and the preliminary main gate electrode 131MP may be removed so that the upper pattern structure U_AP between the gate spacers 142 may be exposed. Subsequently, the sacrificial layer SC_L between the channel layer CH and the lower pattern BP may be removed, and thereby the gate trench 130t may be formed.

[0084] like Fig.12As shown in , a sub-interface insulating layer 133S, a sub-gate insulating layer 132S, and a sub-gate electrode 131S can be sequentially formed in the gate trench 130t. In addition, a main interface insulating layer 133M, a main gate insulating layer 132M, a main gate electrode 131M, and a capping layer 141 can be sequentially formed. The sub-interface insulating layer 133S and the main interface insulating layer 133M can be formed simultaneously in the same process. The sub-gate insulating layer 132S and the main gate insulating layer 132M can be formed simultaneously in the same process. The sub-gate electrode 131S and the main gate electrode 131M can be formed simultaneously in the same process.

[0085] like Fig.13 As shown in , a portion of the interlayer insulating layer 170 may be patterned, and thereby a contact electrode 180 whose first end contacts the upper surface of the second source / drain pattern 152 may be formed. Specifically, after etching a portion of the interlayer insulating layer 170 overlapping with the second source / drain pattern 152 in the third direction D3, a first via 180a may be formed. At this time, a portion of the interlayer insulating layer 170 may be etched by using an etchant having a higher etching selectivity relative to the interlayer insulating layer 170 than the source / drain pattern 150. Accordingly, a portion of the upper surface of the second source / drain pattern 152 may be exposed. In another embodiment, a portion of the interlayer insulating layer 170 may be etched by a dry etching process. The first end of the first via 180a may directly contact the upper surface of the second source / drain pattern 152. The second end of the first via 180a may directly contact the second via 180b to be formed subsequently. Thereafter, the interlayer insulating layer 170 may be additionally formed at a level higher than the upper surface of the capping layer 141. At this time, the additionally formed interlayer insulating layer 170 may include the same insulating material as the interlayer insulating layer 170 already formed on the source / drain pattern 150. Accordingly, between the interlayer insulating layer 170 formed later and the already formed interlayer insulating layer 170, the boundary may not be visible. Thereafter, after etching a portion of the interlayer insulating layer 170 overlapping the first via 180a in the third direction D3, a second via 180b may be formed. A first end of the second via 180b may be connected to a second end of the first via 180a. A second end of the second via 180b may be connected to an upper wiring structure 210 (see FIG. 2 ) to be formed later. Fig.14 ).

[0086] like Fig.14As shown in , on the interlayer insulating layer 170 and the contact electrode 180, an upper wiring structure 210 may be formed. The upper wiring structure 210 may include an upper wiring 211, an upper via 212, and an upper insulating layer 213. In an embodiment, the upper wiring structure 210 may include upper wirings 211 of each layer formed by a plurality of repeated processes. First, after depositing a layer of upper insulating layer 213 on the upper surface of the interlayer insulating layer 170, it is patterned, and an upper wiring 211 connected to the second via 180b may be formed. Thereafter, after depositing a layer of upper insulating layer 213 again, it is patterned, and an upper via 212 may be formed on the upper wiring 211 connected to the second via 180b. Thereafter, an upper wiring 211 connected to the second end of the upper via 212 may be formed. The upper wiring 211 and the upper via 212 may include metal (e.g., copper). The upper insulating layer 213 may be located on the upper surface of the interlayer insulating layer 170. The upper insulating layer 213 may cover the upper wiring 211 and the upper via 212. That is, the upper wiring 211 and the upper via 212 may be disposed in the upper insulating layer 213. The upper insulating layer 213 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or at least one of a low-k dielectric layer.

[0087] like Fig.15 As shown in , the substrate 10 can be removed by performing an etching process. At this time, a process of thinning the substrate 10 by performing a chemical mechanical polishing (CMP) process relative to the lower surface of the substrate 10 can be additionally performed. For example, the etching process of removing the substrate 10 can be performed by a wet etching method. In this case, the substrate 10 can be etched by using an etchant having a higher etching selectivity relative to the substrate 10 than the dummy insulating pattern DD. However, but not limited to this, the substrate 10 can be removed by a dry etching process. When a partial area of ​​the substrate 10 is removed, the dummy insulating pattern DD can be exposed. Subsequently, in the area where the substrate 10 is removed, a base insulating layer 100 covering the dummy insulating pattern DD can be formed. In an embodiment, the base insulating layer 100 may include an insulating material different from the interlayer insulating layer 170. In an embodiment, the base insulating layer 100 may include an insulating material different from the dummy insulating pattern DD. For example, the base insulating layer 100 may include silicon oxide (SiOx).

[0088] like Fig.16As shown in , by performing photolithography and etching processes, the base insulating layer 100 overlapping with the dummy insulating pattern DD in the third direction D3, the lower pattern BP surrounding the dummy insulating pattern DD, and at least a portion of the source / drain pattern 150 can be etched. The base insulating layer 100, a portion of the lower pattern BP, and the source / drain pattern 150 can be removed sequentially. For example, the portion of the base insulating layer 100 overlapping with the dummy insulating pattern DD in the third direction D3 can be etched first, and accordingly, a portion of the dummy insulating pattern DD can be exposed. At this time, a portion of the base insulating layer 100 can be etched by using an etchant having a higher etching selectivity with respect to the base insulating layer 100 than the dummy insulating pattern DD. Subsequently, a portion of the lower pattern BP, the first source / drain pattern 151, and the third source / drain pattern 153 can be etched. At this time, a portion of the lower pattern BP, the first source / drain pattern 151, and the third source / drain pattern 153P can be etched by using an etchant having a higher etching selectivity with respect to the first source / drain pattern 151 and the third source / drain pattern 153 than the dummy insulating pattern DD. The etched portions of the first and third source / drain patterns 151 and 153 may respectively include portions of sidewalls and bottom surfaces of the first and third source / drain patterns 151 and 153. After etching is completed, an upper surface of the etched region may be located between upper surfaces of the first and third source / drain patterns 151 and 153 and lower surfaces of the first and third source / drain patterns 151 and 153. In an embodiment, a width of the etched region in the first direction D1 may be greater than a width of the dummy insulation pattern DD in the first direction.

[0089] like Fig.17 At this time, the dummy insulating pattern DD may be etched by using an etchant having a higher etching selectivity with respect to the dummy insulating pattern DD than the base insulating layer 100 , the lower pattern BP, and the source / drain pattern 150 .

[0090] like Fig.18 As shown in , upper and lower conductive patterns 190a and 190b may be formed in regions where the dummy insulating pattern DD is removed and where the base insulating layer 100, the lower pattern BP, and the first and third source / drain patterns 151 and 153 are removed. Fig.18, the upper conductive pattern 190a and the lower conductive pattern 190b are shown as if they are separate configurations, but the upper conductive pattern 190a and the lower conductive pattern 190b can be formed integrally in the same process. The upper conductive pattern 190a and the lower conductive pattern 190b may include the same material. The upper conductive pattern 190a and the lower conductive pattern 190b may include a metal or a metal alloy. For example, the upper conductive pattern 190a and the lower conductive pattern 190b may include at least one of titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru), and platinum (Pt).

[0091] like Fig.19 As shown in , a lower wiring structure 220 may be formed on the lower surface of the base insulating layer 100. In an embodiment, the lower wiring structure 220 may include lower wirings 221 of various layers formed by a plurality of repeated processes. First, after depositing a layer of lower insulating layer 223 on the bottom surface of the base insulating layer 100, it is patterned, and a lower wiring 221 connected to the lower conductive pattern 190b may be formed. Thereafter, after depositing a layer of lower insulating layer 223 again, it is patterned, and a lower via 222 may be formed on the lower wiring 221 connected to the lower conductive pattern 190b. Thereafter, a lower wiring 221 connected to the second end of the lower via 222 may be formed. The lower wiring 221 and the lower via 222 may include a metal (e.g., copper). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may cover the lower wiring 221 and the lower via 222. That is, the lower wiring 221 and the lower via 222 may be disposed in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or at least one of a low-k dielectric layer.

[0092] Fig. 20 is a top plan view showing a semiconductor device according to an embodiment. Figure 21 to Figure 23 is a cross-sectional view showing a semiconductor device according to an embodiment. Specifically, Fig.21 is along Fig. 20 A cross-sectional view of the semiconductor device taken along line II'. Fig. 22 is along Fig. 20 sectional view of the semiconductor device taken along line II-II'. Fig.23 is along Fig. 20 1 is a cross-sectional view of the semiconductor device taken along line III-III'. Figure 20 to Figure 23 The semiconductor device disclosed in Figures 1 to 4 The semiconductor device described herein, and in the following, the description focuses on Figure 20 to Figure 23 The semiconductor device disclosed in Figures 1 to 4Describe the differences between semiconductor devices.

[0093] refer to Figure 20 to Figure 23 According to the embodiment, the semiconductor device may include a base insulating layer 100, a channel layer CH located on a first surface of the base insulating layer 100, a source / drain pattern 150 located on both sides of the channel layer CH, gate structures M_GS and S_GS surrounding the channel layer CH, a lower wiring structure 220 located on a second surface of the base insulating layer 100, and a through electrode 190 inserted into the first source / drain pattern and spaced apart from the gate structure.

[0094] The base insulating layer 100 may include a layer such as an oxide, a nitride, an oxynitride, or a combination thereof. The base insulating layer 100 may include an insulating material. The base insulating layer 100 may include an insulating material different from the interlayer insulating layer 170. For example, the base insulating layer 100 may include silicon nitride (SiN). Although the base insulating layer 100 is shown to be a single layer, this is only for ease of description and is not limited thereto. The first surface and the second surface of the base insulating layer 100 may be formed as a plane parallel to the second direction D2 and the first direction D1 intersecting the first direction D1. For example, the first surface of the base insulating layer 100 may be an upper surface, and the second surface may be a bottom surface. The upper surface of the base insulating layer 100 is a surface opposite to the bottom surface of the base insulating layer 100 in the third direction D3. The third direction D3 may be a direction perpendicular to the first direction D1 and the second direction D2. The bottom surface of the base insulating layer 100 may be referred to as the back side of the base insulating layer 100. In some embodiments, the logic circuit in the cell area may be implemented on the upper surface of the base insulating layer 100. The base insulating layer 100 may include a device isolation trench STI.

[0095] The channel layer CH may be disposed on the base insulating layer 100. In an embodiment, a plurality of channel layers 110a, 110b, 110c, and 110d may be disposed on the base insulating layer 100. For example, each of the plurality of channel layers 110a, 110b, 110c, and 110d may be a sheet-shaped semiconductor layer. Each semiconductor layer may be a nanosheet having a thickness of several nanometers along the third direction D3.

[0096] In an embodiment, a plurality of channel layers 110a, 110b, 110c, and 110d may be disposed on the base insulating layer 100. The channel layer CH may provide a path through which current flows between the two source / drain patterns 150. Fig.21 and Fig. 22, the channel layers 110a, 110b, 110c, and 110d may be disposed on the source / drain pattern 150 and connected to the source / drain pattern 150. The channel layers 110a, 110b, 110c, and 110d may penetrate a portion of the gate structure GS in a direction (e.g., a first direction D1) intersecting a direction in which the gate structure GS extends. The channel layers 110a, 110b, 110c, and 110d may be arranged to be spaced apart from the upper surface of the base insulating layer 100 in a vertical direction (e.g., a third direction D3). Fig.21 and Fig. 22 , four channel layers 110a, 110b, 110c and 110d are shown to be spaced apart, but are not limited thereto, and the number of stacked channel layers CH may be changed in various ways. The channel layer CH may include a semiconductor material. For example, the channel layer CH may include a group IV semiconductor such as Si and Ge, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc. In an embodiment, the lower pattern BP may also be disposed below the channel layer CH. Specifically, the lower pattern BP may be located between the base insulating layer 100 and the sub-gate structure S_GS located at the bottom among the plurality of sub-gate structures S_GS. The upper surface of the lower pattern BP may contact the lower surface of the sub-gate structure S_GS located at the bottom among the plurality of sub-gate structures S_GS. The lower pattern BP may include the same material as the channel layer CH. For example, the lower pattern BP may include a group IV semiconductor such as Si and Ge, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc. However, it is not limited thereto, and the lower pattern BP may include a material different from the channel layer CH.

[0097] As another example, Fig.21 and Fig. 22 Unlike the example shown in , the semiconductor device may not include the lower pattern BP. In this case, a lower surface of the sub-gate structure S_GS located at the lowermost among the sub-gate structures S_GS may directly contact the base insulating layer 100 .

[0098] As another example, Fig.21 and Fig. 22 Different from that shown in , a portion of the base insulating layer 100 overlapping the sub-gate structure S_GS in the third direction D3 may extend to the inside of the lower pattern BP and directly contact a lower surface of the lowermost sub-gate structure S_GS among the sub-gate structures S_GS.

[0099] The semiconductor device according to the embodiment may further include a field insulating layer 105. The field insulating layer 105 may be located on the lower pattern BP. The field insulating layer 105 may be located on the sidewall of the lower pattern BP. The field insulating layer 105 may not be located on the upper surface of the lower pattern BP. The field insulating layer 105 may cover a portion of the sidewall of the lower pattern BP. In this case, a portion of the lower pattern BP may protrude from the upper surface of the field insulating layer 105 in the third direction D3. Unlike shown, the field insulating layer 105 may completely cover the side surface of the lower pattern BP. The field insulating layer 105 may include a layer of, for example, an oxide, a nitride, an oxynitride, or a combination thereof. Although the field insulating layer 105 is shown to be a single layer, this is only for ease of illustration and is not limited thereto.

[0100] The source / drain pattern 150 may be located on the base insulating layer 100. The source / drain pattern 150 may be located on both sides of the channel layer CH or the sub-gate structure S_GS. Specifically, the two source / drain patterns 150 may be arranged in a direction (e.g., a first direction D1) intersecting the direction in which the gate structure GS extends, and the channel layer CH or the sub-gate structure S_GS is inserted. The source / drain pattern 150 may directly contact the channel layer CH or the sub-gate structure S_GS. The source / drain pattern 150 may directly contact the sub-interface insulating layer 133S of the sub-gate structure S_GS. Although not shown in the drawings, an internal spacer may also be provided between the source / drain pattern 150 and the sub-interface insulating layer 133S. The internal spacer may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) and at least one of a combination thereof.

[0101] In the active pattern ACT_L described later (see Fig.24 ) and the sacrificial layer SC_L (see Fig.24 ), the source / drain pattern 150 may be formed as an epitaxial layer formed by selective epitaxial growth (SEG). That is, the source / drain pattern 150 may fill the sacrificial layer SC_L (refer to Fig.24 ) and the active pattern ACT_L (reference Fig.24 ) is a recessed area.

[0102] The source / drain pattern 150 may include a first source / drain pattern 151, a second source / drain pattern 152, and a third source / drain pattern 153. The first to third source / drain patterns 151, 152, and 153 may include liner layers 151a, 152a, and 153a and filling layers 151b, 152b, and 153b. The liner layers 151a, 152a, and 153a may be located on the side surfaces and the bottom surface of the source / drain pattern 150. The liner layers 151a, 152a, and 153a may directly contact the sub-gate structure S_GS and the channel layer CH. That is, the liner layers 151a, 152a, and 153a may be formed along the source / drain recess RC1 described later (see Fig.25 ) surface contour positioning. The filling layers 151b, 152b and 153b may be located on the liner layers 151a, 152a and 153a. The filling layers 151b, 152b and 153b, and the liner layers 151a, 152a and 153a may have upper surfaces of substantially the same height. That is, the filling layers 151b, 152b and 153b may fill the source / drain recesses RC1 (see Fig.25 )’s interior.

[0103] The source / drain pattern 150 may include a semiconductor material. The source / drain pattern 150 may include, for example, silicon or germanium. In addition, the source / drain pattern 150 may include, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the source / drain pattern 150 may include silicon, silicon-germanium, germanium, silicon carbide, etc., but is not limited thereto. In an embodiment, the liner layers 151a, 152a, and 153a and the filling layers 151b, 152b, and 153b may have different concentrations of silicon (Si) or germanium (Ge). For example, the concentration of silicon (Si) or germanium (Ge) included in the liner layers 151a, 152a, and 153a may be less than the concentration of silicon (Si) or germanium (Ge) included in the filling layers 151b, 152b, and 153b.

[0104] exist Figure 20 to Figure 23 In the case of the semiconductor device disclosed in the reference Figures 1 to 4 Unlike the semiconductor device described above, the source / drain pattern 150 may not directly contact the upper conductive pattern 190a or the lower conductive pattern 190b described later. The barrier layer 230 described later may be located between the sidewall of the upper conductive pattern 190a and the first source / drain pattern 151. The barrier layer 230 may include an insulating material. Accordingly, the first source / drain pattern 151 and the upper conductive pattern 190a may be electrically separated by the barrier layer 230. The first source / drain pattern 151 may be connected to the lower wiring structure 220 through the first contact electrode 181, the upper conductive pattern 190a, and the lower conductive pattern 190b. Figures 1 to 4Unlike the semiconductor device disclosed in , the first source / drain pattern 151 may not directly contact the lower conductive pattern 190b and the upper conductive pattern 190a. The upper surface of the first source / drain pattern 151 may contact the first end of the first contact electrode 181. The first source / drain pattern 151 may receive power from the lower wiring structure 220 through the lower conductive pattern 190b, the upper conductive pattern 190a, and the first contact electrode 181.

[0105] In an embodiment, the second source / drain pattern 152 may be connected to the upper wiring structure 210 described later. The second source / drain pattern 152 may be connected to the upper wiring structure 210 through the second contact electrode 182. A portion of the upper surface of the second source / drain pattern 152 may be connected to a portion of the second contact electrode 182. In an embodiment, the current having flowed through the channel layer CH may be transferred to the upper wiring structure 210 through the second source / drain pattern 152 and the second contact electrode 182. Fig.21 Although the filling layer 152 b of the second source / drain pattern 152 is shown as being connected to the second contact electrode 182 , the second contact electrode 182 may also be connected to the liner layer 152 a of the second source / drain pattern 152 .

[0106] The gate structure GS may be disposed on the substrate insulating layer 100. The gate structure GS may include a sub-gate structure S_GS and a main gate structure M_GS. The sub-gate structure S_GS may be disposed on the substrate insulating layer 100, and the main gate structure M_GS may be disposed on the sub-gate structure S_GS. On the substrate insulating layer 100, the gate structure GS may extend in different directions other than the direction in which the source / drain pattern 150 is arranged. For example, on the substrate insulating layer 100, the gate structure GS may extend in a direction (e.g., a second direction D2) intersecting the direction in which the source / drain pattern 150 is arranged. The gate structure GS may be located on the substrate insulating layer 100. The gate structure GS may be arranged to be spaced apart in the first direction D1. The main gate structure M_GS may be on the uppermost channel layer 110a. The main gate structure M_GS may also be located on the side surface of the structure in which the channel layers 110a, 110b, 110c, and 110d and the sub-gate structure S_GS are stacked. That is, the main gate structure M_GS may surround each of the channel layers 110a, 110b, 110c, and 110d together with the sub-gate structure S_GS. However, the main gate structure M_GS may not be located on the surface of each of the channel layers 110a, 110b, 110c, and 110d contacting the source / drain pattern 150. Fig.21 and Fig. 22 In FIG. 4 , four sub-gate structures S_GS are arranged in the third direction, but the number of arranged sub-gate structures S_GS is not limited thereto. For example, the gate structure GS may include three sub-gate structures S_GS.

[0107] The sub-gate structure S_GS may contact the source / drain pattern 150. For example, the sub-gate structure S_GS may directly contact the source / drain pattern 150. The sub-gate structure S_GS may be located on both sides of the source / drain pattern 150. The sub-gate structures S_GS may be formed as multiple layers. For example, the sub-gate structures S_GS may include a sub-gate electrode 131S, a sub-gate insulating layer 132S, and a sub-interface insulating layer 133S. The sub-gate structure S_GS and the channel layers 110a, 110b, 110c, and 110d may be alternately stacked in the third direction D3. The sub-gate structure S_GS may surround the surfaces of the channel layers 110a, 110b, 110c, and 110d except the surface connected to the source / drain pattern 150 together with the main gate structure M_GS.

[0108] The sub-gate electrode 131S may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The sub-gate electrode 131S may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAl ...N), tungsten aluminum nitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum nitride (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum nitride (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nit ), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and at least one of their combinations, but not limited thereto. The conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the above materials, but not limited thereto.

[0109] The sub-interface insulating layer 133S may be positioned along the periphery of the channel layer CH. For example, the sub-interface insulating layer 133S may surround the surface of the channel layer CH except for the surface connected to the source / drain pattern 150. The sub-interface insulating layer 133S may directly contact the source / drain pattern 150 and the channel layer CH. The sub-interface insulating layer 133S may be inserted between the channel layer CH and the sub-gate insulating layer 132S. The sub-interface insulating layer 133S may include, for example, silicon oxide (SiO 2 ).

[0110] The sub-gate insulating layer 132S may extend along the upper surface of the sub-interface insulating layer 133S. The sub-gate insulating layer 132S may surround the channel layer CH. For example, the sub-gate insulating layer 132S may surround the surface of the channel layer CH except the surface connected to the source / drain pattern 150. The sub-gate insulating layer 132S may be positioned along the periphery of the channel layer CH. The sub-gate insulating layer 132S may be inserted between the sub-gate electrode 131S and the sub-interface insulating layer 133S. The sub-gate insulating layer 132S may include, for example, a high dielectric constant material. The high dielectric constant material may include a dielectric having a dielectric constant greater than silicon oxide (SiO 2 ) Materials with high dielectric constants (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)).

[0111] The main gate structure M_GS may be located on the sub-gate structure S_GS and the channel layer CH. The main gate structure M_GS may be located on the upper surface of the channel layer CH. The main gate structure M_GS may be formed as a multilayer. For example, the main gate structure M_GS may include a main gate electrode 131M, a main interface insulating layer 133M, and a main gate insulating layer 132M. The main gate structure M_GS may surround the surface of at least one (e.g., 110a) of the channel layer CH together with the sub-gate structure S_GS except the surface connected to the source / drain pattern 150.

[0112] The main gate electrode 131M may be located on the sub-gate structure S_GS and the channel layer CH. The main gate electrode 131M may be located on the upper surface of the channel layer CH. The main gate electrode 131M may include the same material as the sub-gate electrode 131S. For example, the main gate electrode 131M may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0113] The main interface insulating layer 133M may extend along the upper surface of the channel layer CH. The main interface insulating layer 133M may include, for example, silicon oxide (SiO 2 ). The main gate insulating layer 132M may extend along the side surface and the bottom surface of the main gate electrode 131M. The main gate insulating layer 132M may include, for example, a high dielectric constant material.

[0114] The semiconductor device according to the embodiment may further include a capping layer 141 and a gate spacer 142. The gate spacer 142 may be located on the side surface of the main gate electrode 131M. The gate spacer 142 may not be disposed between the lower pattern BP and the channel layer CH. The gate spacer 142 may not be disposed between the channel layers CH adjacent to each other along the third direction D3. Although the gate spacer 142 is shown as a single layer, this is only for ease of explanation and is not limited thereto. The gate spacer 142 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) and at least one of a combination thereof.

[0115] The capping layer 141 may be located on the main gate structure M_GS and the gate spacer 142. Unlike shown, the capping layer 141 may be located between the gate spacers 142. The capping layer 141 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The capping layer 141 may include a material having an etching selectivity relative to the interlayer insulating layer 170 described later.

[0116] The through electrode 190 may be positioned to be spaced apart from the gate structure GS, interposing the first source / drain pattern 151. The through electrode 190 may penetrate the base insulating layer 100, and electrically connect a lower wiring structure 220 described later and the first source / drain pattern 151. In an embodiment, the through electrode 190 may include an upper conductive pattern 190a and a lower conductive pattern 190b.

[0117] The upper conductive pattern 190a may be located between two source / drain patterns 150. The upper conductive pattern 190a may be located between source / drain patterns 150 of two different semiconductor devices. Fig.21, the upper conductive pattern 190a may be located between the first source / drain pattern 151 and the third source / drain pattern 153. The first source / drain pattern 151 and the third source / drain pattern 153 may be the source / drain pattern 150 of each of two adjacent different semiconductor devices. The upper conductive pattern 190a may extend in the third direction D3. The upper conductive pattern 190a may have an upper surface at substantially the same height as the upper surface of the main gate structure M_GS and the dummy gate spacer 160b described later. The upper surface of the upper conductive pattern 190a may contact the lower surface of the dummy capping layer 160a described later. A portion of the upper surface of the upper conductive pattern 190a may also contact the lower surface of the first contact electrode 181. Specifically, a portion of the upper surface of the upper conductive pattern 190a may contact the lower surface of the first via 181a that penetrates a portion of the dummy capping layer 160a in the third direction D3. The lower surface of the upper conductive pattern 190a may contact the upper surface of the lower conductive pattern 190b. The interface between the upper conductive pattern 190a and the lower conductive pattern 190b may be positioned lower than the bottom surface of the source / drain pattern 150. The interface between the upper conductive pattern 190a and the lower conductive pattern 190b may be positioned higher than the interface between the lower pattern BP and the base insulating layer 100. That is, the interface between the upper conductive pattern 190a and the lower conductive pattern 190b may be located between the interface between the lower pattern BP and the base insulating layer 100 and the bottom surface of the source / drain pattern 150. However, but not limited to this, the interface between the upper conductive pattern 190a and the lower conductive pattern 190b may be positioned lower than the interface between the lower pattern BP and the base insulating layer 100. However, even in this case, the interface between the upper conductive pattern 190a and the lower conductive pattern 190b may be positioned lower than the bottom surface of the source / drain pattern 150.

[0118] In an embodiment, the width of the upper conductive pattern 190a in the first direction D1 may be less than or equal to the width of the lower conductive pattern 190b in the first direction D1. The width of the upper conductive pattern 190a in the first direction D1 may be substantially the same as the width of the adjacent sub-gate structure S_GS in the first direction D1.

[0119] In an embodiment, the width of the upper conductive pattern 190a in the first direction D1 may be the same as the width of the channel layer CH in the first direction D1. However, it is not limited thereto, and the width of the upper conductive pattern 190a in the first direction D1 may be smaller than the width of the channel layer CH in the first direction D1. When the width of the upper conductive pattern 190a in the first direction D1 is smaller than the width of the channel layer CH in the first direction D1, residual semiconductor material may be located between the upper conductive pattern 190a and the source / drain pattern 150. When the process of forming the upper conductive pattern 190a described later (see Fig.28), when the channel layer CH and the sacrificial layer SC_L are removed from the channel layer CH and the sacrificial layer SC_L, the residual semiconductor material may be a partial area of ​​the channel layer CH that is not removed but remains between the source / drain pattern and the sidewall of the trench TR. The residual semiconductor material may include the same material as the channel layer CH. For example, the residual semiconductor material may include Si or SiGe. The upper conductive pattern 190a may include a metal or a metal alloy. The upper conductive pattern 190a may include, for example, at least one of titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru) and platinum (Pt). In an embodiment, the upper conductive pattern 190a may include the same material as the lower conductive pattern 190b. The upper conductive pattern 190a may be formed integrally in the same process as the lower conductive pattern 190b.

[0120] The lower conductive pattern 190b may be located between the lower wiring structure 220 and the upper conductive pattern 190a. The lower conductive pattern 190b may penetrate the base insulating layer 100 and extend in the third direction D3. A first end of the lower conductive pattern 190b may be connected to a lower surface of the upper conductive pattern 190a, and a second end thereof may be connected to the lower wiring structure 220. Figure 20 to Figure 23 In the case of the semiconductor device disclosed in Figures 1 to 4 Unlike the semiconductor device disclosed in , the lower conductive pattern 190 b may not contact the source / drain pattern 150 .

[0121] The upper surface of the lower conductive pattern 190b may contact the lower surface of the upper conductive pattern 190a. In an embodiment, the width of the lower conductive pattern 190b in the first direction D1 may be greater than or equal to the width of the upper conductive pattern 190a in the first direction D1. The width of the lower conductive pattern 190b in the first direction D1 may be greater than or equal to the width of the adjacent sub-gate structure S_GS in the first direction D1. The width of the lower conductive pattern 190b in the first direction D1 may be greater than or equal to the width of the channel layer CH in the first direction.

[0122] The lower conductive pattern 190b may include a metal or a metal alloy. The lower conductive pattern 190b may include, for example, at least one of titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru), and platinum (Pt). In an embodiment, the lower conductive pattern 190b may include the same material as the upper conductive pattern 190a. The lower conductive pattern 190b may be integrally formed in the same process as the upper conductive pattern 190a.

[0123] The semiconductor device according to the embodiment may further include a barrier layer 230. The barrier layer 230 may extend along the contours of the two side surfaces of the upper conductive pattern 190a and the lower conductive pattern 190b. The barrier layer 230 may extend to the bottom surface of the dummy capping layer 160a. That is, the upper surface of the barrier layer 230 may contact the bottom surface of the dummy capping layer 160a. The barrier layer 230 may be located between the dummy gate spacer 160b and the upper conductive pattern 190a. A portion of the upper surface of the barrier layer 230 may contact the first contact electrode 181. Specifically, a portion of the upper surface of the barrier layer 230 may contact the lower surface of the second via 181b that penetrates the dummy capping layer 160a and contacts the upper surface of the upper conductive pattern 190a. The lower surface of the barrier layer 230 may contact the lower line structure 220. The barrier layer 230 may also be located between the first source / drain pattern 151 and the third source / drain pattern 153 and the upper conductive pattern 190a. The barrier layer 230 may also be located between the lower conductive pattern 190 b and the base insulating layer 100 .

[0124] The barrier layer 230 may include an insulating material. For example, the barrier layer 230 may include silicon oxide or silicon nitride. The barrier layer 230 may electrically separate the upper conductive pattern 190a from the source / drain pattern 150. The barrier layer 230 may electrically separate the lower conductive pattern 190b from the base insulating layer 100.

[0125] The semiconductor device according to the embodiment may further include a dummy capping layer 160a and a dummy gate spacer 160b. The dummy capping layer 160a may be located on the upper conductive pattern 190a and the dummy gate spacer 160b. The dummy capping layer 160a may cover the upper surfaces of the upper conductive pattern 190a and the dummy gate spacer 160b. The dummy capping layer 160a may be located in a layer substantially the same as the capping layer 141. The dummy capping layer 160a may have an upper surface at substantially the same height as the upper surface of the capping layer 141. The dummy capping layer 160a may have a lower surface at substantially the same height as the lower surface of the capping layer 141. The dummy capping layer 160a may include the same material as the capping layer 141. The dummy capping layer 160a may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The dummy capping layer 160a may include a material having an etching selectivity relative to the interlayer insulating layer 170. The dummy capping layer 160a may be formed simultaneously with the capping layer 141 in the same process as the capping layer 141.

[0126] The dummy gate spacer 160b may be located on the side surface of the upper conductive pattern 190a. Specifically, the dummy gate spacer 160b may be located between the interlayer insulating layer 170 and the upper conductive pattern 190a. The dummy gate spacer 160b may not be located on the interface between the upper conductive pattern 190a and the first source / drain pattern 151. That is, in the region adjacent to the source / drain pattern 150, the dummy gate spacer 160b may have a lower surface at substantially the same height as the upper surface of the source / drain pattern 150. The dummy gate spacer 160b may have an upper surface at substantially the same height as the upper surface of the main gate structure M_GS. The dummy gate spacer 160b may be located in substantially the same layer as the gate spacer 142. The dummy gate spacer 160b may have an upper surface at substantially the same height as the upper surface of the gate spacer 142. The dummy gate spacer 160b may have a lower surface at substantially the same height as the lower surface of the gate spacer 142. The dummy gate spacer 160b may include the same material as the gate spacer 142. For example, the dummy gate spacer 160b may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The dummy gate spacer 160 b may be formed simultaneously with the gate spacer 142 in the same process as the gate spacer 142 .

[0127] The lower wiring structure 220 may be disposed on the bottom surface of the base insulating layer 100. In an embodiment, the lower wiring structure 220 may be a component for supplying power to at least one of the source / drain patterns 150. For example, the lower wire structure 220 may be a power transmission network. The lower wiring structure 220 may include a lower wiring 221, a lower via 222, and a lower insulating layer 223. The lower wiring 221 and the lower via 222 may be located on the bottom surface of the base insulating layer 100. The lower wiring 221 and the lower via 222 may include a metal (e.g., copper). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may be disposed between the bottom surface of the base insulating layer 100, the lower wiring 221, and the lower via 222, and insulate them. That is, the lower insulating layer 223 may cover the lower wiring 221 and the bottom surface of the base insulating layer 100. The lower wiring 221 and the lower via 222 may be located in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0128] In an embodiment, the semiconductor device may further include an interlayer insulating layer 170 , an upper wiring structure 210 , and a contact electrode 180 . The contact electrode 180 may include a first contact electrode 181 and a second contact electrode 182 .

[0129] The interlayer insulating layer 170 may cover the channel layer CH, the gate structure GS, the source / drain pattern 150, and the through electrode 190. The interlayer insulating layer 170 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylchlorotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethyl silicon phosphate (TMSP), polytetrafluoroethylene (PTFE), eastern burning silazane (TOSZ), fluorinated silicate glass (FSG), polyimide nanofoam (e.g., polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica or a combination thereof, but is not limited thereto. In an embodiment, the interlayer insulating layer 170 may include a material different from the base insulating layer 100.

[0130] The upper wiring structure 210 may be located on the interlayer insulating layer 170. The upper wiring structure 210 may include an upper wiring 211, an upper via 212, and an upper insulating layer 213. The upper wiring 211 and the upper via 212 may include a metal (e.g., copper). The upper insulating layer 213 may be disposed between the upper wiring 211 and the upper via 212 and insulate them. The upper insulating layer 213 may cover the interlayer insulating layer 170 and the upper wiring 211. The upper wiring 211 and the upper via 212 may be located within the upper insulating layer 213. The upper insulating layer 213 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0131] The contact electrode 180 may be a configuration for connecting the source / drain pattern 150 to the upper wiring structure 210 or the lower wiring structure 220. In an embodiment, the first contact electrode 181 may be disposed between the first source / drain pattern 151 and the through electrode 190. In an embodiment, the first contact electrode 181 may electrically connect the first source / drain pattern 151 and the upper conductive pattern 190a. The first source / drain pattern 151 may be connected to the lower wiring structure 220 through the first contact electrode 181, the upper conductive pattern 190a, and the lower conductive pattern 190b.

[0132] The first contact electrode 181 may include a first via 181a and a second via 181b. The first via 181a may be disposed between the first source / drain pattern 151 and the second via 181b, and thereby the first source / drain pattern 151 and the second via 181b may be connected. The first via 181a may have an upper surface at substantially the same height as an upper surface of a third via 182a described later. In an embodiment, the first via 181a may be formed simultaneously in the same process as the third via 182a.

[0133] The second via 181b may be disposed between the first via 181a and the upper conductive pattern 190a, and connect the first via 181a and the upper conductive pattern 190a. In an embodiment, the second via 181b may have an upper surface at substantially the same height as an upper surface of a fourth via 182b described later. In this case, the second via 181b may be formed simultaneously in the same process as the fourth via 182b. However, but not limited to this, the second via 181b may be formed simultaneously in the same process as an electrode (not shown) for connecting the main gate electrode 131M and the upper wiring structure 210. Reference Fig.21 , showing that the upper surface of the second via 181b contacts the upper insulating layer 213 included in the upper wiring structure 210, but the height of the upper surface of the second via 181b is not limited to the present embodiment. For example, the second via 181b may have an upper surface at substantially the same height as the first via 181a, or may have an upper surface between the bottom surface of the upper wiring structure 210 and the upper surface of the first via 181a. Even if the upper surface of the second via 181b contacts the upper insulating layer 213, the upper surface of the second via 181b may not contact the upper wiring 211 or the upper via 212. The second via 181b may penetrate the dummy capping layer 160a and extend to the upper surface of the upper conductive pattern 190a in the third direction D3. Accordingly, a portion of the lower surface of the second via 181b may contact the upper surface of the upper conductive pattern 190a.

[0134] In an embodiment, the second contact electrode 182 may be disposed between the second source / drain pattern 152 and the upper wiring structure 210, and connect the second source / drain pattern 152 and the upper wiring structure 210. The second contact electrode 182 may include a third via 182a and a fourth via 182b. The second contact electrode 182 may penetrate the interlayer insulating layer 170 in the third direction D3. The third via 182a may contact the upper surface of the second source / drain pattern 152. The third via 182a may extend in the third direction D3. The third via 182a may have an upper surface at a height that is the same as or higher than the upper surface of the capping layer 141. The fourth via 182b may be located on the third via 182a. The first end of the fourth via 182b may directly contact the third via 182a in the third direction D3. The second end of the fourth via 182b may directly contact the upper wiring structure 210. The third via 182a and the fourth via 182b may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0135] Figures 24 to 40 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment.

[0136] like Fig.24 As shown in , a lower pattern BP and an upper pattern structure U_AP may be formed on a substrate 10. The substrate 10 may be a silicon on insulator (SOI) or bulk silicon. Alternatively, the substrate 10 may be a silicon substrate, and may include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The lower pattern BP may be a portion of the substrate 10.

[0137] The upper pattern structure U_AP may be located on the lower pattern BP. The upper pattern structure U_AP may include sacrificial layers SC_L and active patterns ACT_L alternately stacked on the lower pattern BP. For example, the sacrificial layers SC_L may include silicon germanium (SiGe). The active patterns ACT_L may include silicon (Si).

[0138] Subsequently, a preliminary gate insulating layer 132P, a preliminary main gate electrode 131MP, and a preliminary capping layer 141P are formed on the upper pattern structure U_AP. The preliminary gate insulating layer 132P may include, for example, silicon oxide (SiO 2), but not limited thereto. The preliminary main gate electrode 131MP may include, for example, polysilicon, but not limited thereto. The preliminary capping layer 141P may include, for example, silicon nitride, but not limited thereto. On both side surfaces of the preliminary main gate electrode 131MP, a preliminary gate spacer 142P may be formed.

[0139] like Fig.25 As shown in FIG. 1 , by using the preliminary capping layer 141P and the preliminary gate spacer 142P as a mask, a source / drain recess RC1 is formed by etching at least a portion of the upper pattern structure U_AP. As the source / drain recess RC1 is formed, at least a portion of the lower pattern BP may be etched. A portion of the source / drain recess RC1 may be formed in the substrate 10. At the same time, as shown in FIG. Fig.25 As shown in , after forming the source / drain recess RC1, a recess process relative to the sacrificial layer SC_L may be performed. In the recess process, the sacrificial layer SC_L is etched by a wet etching or dry etching method, and accordingly, the length of the sacrificial layer SC_L in the first direction D1 may be further reduced. Accordingly, the surface of the sacrificial layer SC_L contacting the source / drain recess RC1 may have a concave shape toward the source / drain recess RC1.

[0140] As the source / drain recess RC1 is formed, the active pattern ACT_L is separated so that channel layers 110a, 110b, 110c, and 110d can be formed. The channel layers 110a, 110b, 110c, and 110d can be located on both sides of the source / drain recess RC1. The channel layers 110a, 110b, 110c, and 110d and the sacrificial pattern SC_L can be alternately stacked in the third direction D3. At this time, the lengths of the channel layers 110a, 110b, 110c, and 110d can be different or the same.

[0141] like Fig.26 As shown in , a source / drain pattern 150 may be formed in a source / drain recess RC1. The source / drain pattern 150 may be formed on a substrate 10. The source / drain pattern 150 may be formed by using an epitaxial growth method. At this time, the inner wall of the source / drain recess may be used as a seed crystal. The source / drain pattern 150 may directly contact the substrate 10 or the lower pattern BP. The source / drain pattern 150 may directly contact the channel layers 110a, 110b, 110c, and 110d and the sacrificial layer SC_L. The source / drain pattern 150 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The source / drain pattern 150 may be formed of several regions with different concentrations. For example, referring to Fig.26, each of the source / drain patterns 151, 152, and 153 may include liner layers 151a, 152a, and 153a and filling layers 151b, 152b, and 153b. First, liner layers 151a, 152a, and 153a are formed along the sidewalls and bottom surfaces of the source / drain recess RC1, and filling layers 151b, 152b, and 153b may be formed on each of the liner layers 151a, 152a, and 153a. The liner layers 151a, 152a, and 153a, and the filling layers 151b, 152b, and 153b may be formed by using an epitaxial growth method, respectively. The liner layers 151a, 152a, and 153a, and the filling layers 151b, 152b, and 153b may include semiconductor materials. For example, the liner layers 151a, 152a and 153a, and the filling layers 151b, 152b and 153b may include silicon (Si) or germanium (Ge) as elemental semiconductor materials. In an embodiment, the liner layers 151a, 152a and 153a, and the filling layers 151b, 152b and 153b may have different concentrations of silicon (Si) or germanium (Ge). For example, the concentration of silicon (Si) or germanium (Ge) included in the liner layers 151a, 152a and 153a may be less than the concentration of silicon (Si) or germanium (Ge) included in the filling layers 151b, 152b and 153b.

[0142] like Fig. 27 As shown in , an interlayer insulating layer 170 may be formed on the source / drain pattern 150. Subsequently, a portion of the interlayer insulating layer 170 and the preliminary capping layer 141P may be removed to expose the upper surface of the preliminary main gate electrode 131MP. At this time, a portion of the preliminary gate spacer 142P may be removed together so that the gate spacer 142 and the dummy gate spacer 160b may be formed. The gate spacer 142 and the dummy gate spacer 160b may be formed simultaneously in the same process.

[0143] like Fig.28 As shown in , the trench TR can be formed by etching a portion of the channel layer CH and a portion of the sacrificial layer SC_L. The portion of the channel layer CH and the portion of the sacrificial layer SC_L that are removed may be a partial region of the channel layer CH and a partial region of the sacrificial layer SC_L located between the source / drain patterns 150 of two adjacent semiconductor devices. For example, in Fig.28In the embodiment of the present invention, a partial region of the channel layer CH and a partial region of the sacrificial layer SC_L located between the first source / drain pattern 151 and the third source / drain pattern 153 may be removed. At this time, the preliminary gate insulating layer 132P and the preliminary main gate electrode 131MP located on the removed channel layer CH and the sacrificial layer SC_L may also be removed together. However, even in this case, the dummy gate spacer 160b may not be removed. The trench TR may penetrate the channel layer CH and the sacrificial layer SC_L and extend in the third direction D3. That is, the bottom surface of the trench TR may be positioned closer to the bottom surface of the substrate 10 than the bottom surface of the source / drain pattern 150. While removing a partial region of the channel layer CH, a partial region of the sacrificial layer SC_L, a portion of the preliminary gate insulating layer 132P, and a portion of the preliminary main gate electrode 131MP located between the source / drain patterns 150 of two adjacent semiconductor devices, the remaining area may be covered by a separate mask pattern. In an embodiment, the removed channel layer CH, the sacrificial layer SC_L, the preliminary gate insulating layer 132P, and the preliminary main gate electrode 131MP may be removed by a dry etching process. However, it is not limited thereto, and all or part of the removed channel layer CH, the sacrificial layer SC_L, the preliminary gate insulating layer 132P, and the preliminary main gate electrode 131MP may be removed by a wet etching process. Fig.28 After forming the trench TR, a partial region of the channel layer CH may remain without being removed between the first source / drain pattern 151 and the sidewall of the trench TR and between the third source / drain pattern 153 and the sidewall of the trench TR.

[0144] like Fig.29 As shown in , the trench TR may be filled with a dummy insulating pattern DD. The dummy insulating pattern DD may include an insulating material. For example, the dummy insulating pattern DD may include silicon oxynitride (SiON) or silicon nitride (SiN). After the dummy insulating pattern DD is filled in the trench TR, a process for planarizing the upper surface of the dummy insulating pattern DD may be additionally performed. For example, the upper surface of the dummy insulating pattern DD may be planarized by a chemical mechanical polishing (CMP) process.

[0145] like Fig.30As shown in , after forming the dummy insulating pattern DD, the remaining preliminary gate insulating layer 132P and the preliminary main gate electrode 131MP can be removed so that the upper pattern structure U_AP between the gate spacers 142 can be exposed. Subsequently, the sacrificial layer SC_L between the channel layer CH and the lower pattern BP can be removed, and the gate trench 130t can be formed thereby. The sub-interface insulating layer 133S and the main interface insulating layer 133M can be formed simultaneously in the same process. The sub-gate insulating layer 132S and the main gate insulating layer 132M can be formed simultaneously in the same process. The sub-gate electrode 131S and the main gate electrode 131M can be formed simultaneously in the same process.

[0146] like Fig.31 As shown in FIG. 1 , a subinterface insulating layer 133S, a subgate insulating layer 132S, and a subgate electrode 131S may be sequentially formed in the gate trench 130t. In addition, a main interface insulating layer 133M, a main gate insulating layer 132M, a main gate electrode 131M, and a capping layer 141 may be sequentially formed.

[0147] like Fig.32 As shown in , a portion of the interlayer insulating layer 170 may be patterned, and thereby a first via 181a and a third via 182a may be formed. The first via 181a may contact the upper surface of the first source / drain pattern 151, and the third via 182a may contact the upper surface of the second source / drain pattern 152. Specifically, after each etching of the portion of the interlayer insulating layer 170 overlapping with the first source / drain pattern 151 and the second source / drain pattern 152 in the third direction D3, the first via 181a and the third via 182a may be formed, respectively. At this time, by using an etchant having a higher etching selectivity with respect to the interlayer insulating layer 170 than the source / drain pattern 150, a portion of the interlayer insulating layer 170 may be etched. Accordingly, a portion of the upper surface of the first source / drain pattern 151 and the second source / drain pattern 152 may be exposed. In another embodiment, a portion of the interlayer insulating layer 170 may be etched by a dry etching process. A first end of the first via 181a may directly contact the upper surface of the first source / drain pattern 151, and a second end of the first via 180a may directly contact a second via 180b formed later. A first end of the third via 182a may directly contact the upper surface of the second source / drain pattern 152, and a second end of the third via 182a may be connected to a fourth via 182b formed later. In an embodiment, the first via 181a and the third via 182a may be formed simultaneously in the same process.

[0148] like Fig.33As shown in , an interlayer insulating layer 170 may be additionally formed at a level higher than the upper surface of the capping layer 141. At this time, the additionally formed interlayer insulating layer 170 may include the same insulating material as the interlayer insulating layer 170 already formed on the source / drain pattern 150. Accordingly, between the interlayer insulating layer 170 formed later and the interlayer insulating layer 170 already formed, the boundary may be invisible. Thereafter, after etching a portion of the interlayer insulating layer 170 and the dummy capping layer 160a, a second via 181b may be formed. Specifically, by etching a partial area of ​​the first via 181a and the dummy capping layer 160a and a portion of the interlayer insulating layer 170 overlapping with them, the upper surface of the first via 181a and a portion of the upper surface of the dummy capping layer 160a may be exposed. Subsequently, a portion of the upper surface of the dummy insulation pattern DD may be exposed by etching a portion of the dummy capping layer 160a. The process of etching the interlayer insulating layer 170 and the dummy capping layer 160a may be simultaneously performed by the same process. Thereafter, a second via 181b contacting a portion of the upper surface of the first via 181a and the upper surface of the dummy capping layer 160a may be formed. After etching a portion of the interlayer insulating layer 170 overlapping the third via 182a in the third direction D3, a fourth via 182b may be formed. A first end of the fourth via 182b may be connected to a second end of the third via 182a, and a second end of the fourth via 182b may be connected to an upper wiring structure 210 (see FIG. 2 ) formed later. Fig.34 ). The processes of forming the second via hole 181b and the fourth via hole 182b may be performed simultaneously. However, but not limited thereto, the second via hole 181b and the fourth via hole 182b may be formed in separate processes, respectively.

[0149] like Fig.34As shown in , an upper wiring structure 210 may be formed on the interlayer insulating layer 170 and the first and second contact electrodes 181 and 182. The upper wiring structure 210 may include an upper wiring 211, an upper via 212, and an upper insulating layer 213. In an embodiment, the upper wiring structure 210 may include upper wirings 211 of various layers formed by a plurality of repeated processes. First, after depositing a layer of an upper insulating layer 213 on the upper surface of the interlayer insulating layer 170, it is patterned, and an upper wiring 211 connected to the fourth via 182b may be formed. Thereafter, after depositing a layer of an upper insulating layer 213 again, it may be patterned, and an upper via 212 may be formed on the upper wiring 211 connected to the fourth via 182b. Thereafter, an upper wiring 211 connected to the second end of the upper via 212 may be formed. The upper wiring 211 and the upper via 212 may include a metal (e.g., copper). The upper insulating layer 213 may be located on the upper surface of the interlayer insulating layer 170. The upper insulating layer 213 may cover the upper wiring 211 and the upper via 212. That is, the upper wiring 211 and the upper via 212 may be disposed in the upper insulating layer 213. The upper insulating layer 213 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or at least one of a low-k dielectric layer.

[0150] like Fig.35 As shown in , the substrate 10 can be removed by performing an etching process. At this time, a process of thinning the substrate 10 by performing a chemical mechanical polishing (CMP) process relative to the lower surface of the substrate 10 can be additionally performed. For example, the etching process of removing the substrate 10 can be performed by a wet etching method. In this case, the substrate 10 can be etched by using an etchant having a higher etching selectivity relative to the substrate 10 than the dummy insulating pattern DD. However, but not limited to this, the substrate 10 can be removed by a dry etching process. When a partial area of ​​the substrate 10 is removed, the dummy insulating pattern DD can be exposed. Subsequently, in the area where the substrate 10 is removed, a base insulating layer 100 covering the dummy insulating pattern DD can be formed. In an embodiment, the base insulating layer 100 may include an insulating material different from the interlayer insulating layer 170. In an embodiment, the base insulating layer 100 may include an insulating material different from the dummy insulating pattern DD. For example, the base insulating layer 100 may include silicon oxide (SiOx).

[0151] like Fig.36As shown in , by performing photolithography and etching processes, the base insulating layer 100 overlapping with the dummy insulating pattern DD in the third direction D3 and at least a portion of the lower pattern BP surrounding the dummy insulating pattern DD can be etched. The base insulating layer 100 and the lower pattern BP can be removed sequentially. For example, the portion of the base insulating layer 100 overlapping with the dummy insulating pattern DD in the third direction D3 can be etched first, and accordingly, a portion of the dummy insulating pattern DD can be exposed. At this time, a portion of the base insulating layer 100 can be etched by using an etchant having a higher etching selectivity relative to the base insulating layer 100 than the dummy insulating pattern DD. Subsequently, a portion of the lower pattern BP can be etched. At this time, a portion of the lower pattern BP can be etched by using an etchant having a higher etching selectivity relative to the lower pattern BP than the dummy insulating pattern DD. After etching is completed, the upper surface of the etched area can be located between the lower surfaces of the first source / drain pattern 151 and the third source / drain pattern 153 and the upper surface of the base insulating layer 100.

[0152] like Fig.37 At this time, the dummy insulating pattern DD may be etched by using an etchant having a higher etching selectivity with respect to the dummy insulating pattern DD than the base insulating layer 100 , the lower pattern BP, and the source / drain pattern 150 .

[0153] like Fig.38 As shown in , along the side surface profile of the region where the dummy insulating pattern DD is removed, and the region where the base insulating layer 100 and the lower pattern BP are removed, a barrier layer 230 may be formed. The barrier layer 230 may not be located on the upper surface of the region where the base insulating layer 100 and the lower pattern BP are removed (i.e., the bottom surface of the second via 181b and the dummy capping layer 160a). In order to form the barrier layer 230 only on the side surface of the region where the dummy insulating pattern DD is removed, and the region where the base insulating layer 100 and the lower pattern BP are removed, a plurality of photolithography processes and etching processes may be performed. For example, after the barrier layer 230 is formed on the entire side surface and upper surface of the region where the dummy insulating pattern DD is removed, and the region where the base insulating layer 100 and the lower pattern BP are removed, the barrier layer 230 formed on the upper surface may be removed alone by using an anisotropic etching process.

[0154] like Fig.39 As shown in , the upper conductive pattern 190a and the lower conductive pattern 190b may be formed in the region where the dummy insulating pattern DD is removed, and in the region where the base insulating layer 100 and the lower pattern BP are removed. Fig.39, the upper conductive pattern 190a and the lower conductive pattern 190b are shown as if they are separate configurations, but the upper conductive pattern 190a and the lower conductive pattern 190b can be formed integrally in the same process. The upper conductive pattern 190a and the lower conductive pattern 190b may include the same material. The upper conductive pattern 190a and the lower conductive pattern 190b may include a metal or a metal alloy. For example, the upper conductive pattern 190a and the lower conductive pattern 190b may include at least one of titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru), and platinum (Pt).

[0155] like Fig.40 As shown in , a lower wiring structure 220 may be formed on the lower surface of the base insulating layer 100. In an embodiment, the lower wiring structure 220 may include lower wirings 221 of various layers formed by a plurality of repeated processes. First, after depositing a layer of lower insulating layer 223 on the bottom surface of the base insulating layer 100, it is patterned, and a lower wiring 221 connected to the lower conductive pattern 190b may be formed. Thereafter, after depositing a layer of lower insulating layer 223 again, it is patterned, and a lower via 222 may be formed on the lower wiring 221 connected to the lower conductive pattern 190b. Thereafter, a lower wiring 221 connected to the second end of the lower via 222 may be formed. The lower wiring 221 and the lower via 222 may include a metal (e.g., copper). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may cover the lower wiring 221 and the lower via 222. That is, the lower wiring 221 and the lower via 222 may be disposed in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or at least one of a low-k dielectric layer.

[0156] In the following, reference Figure 41 to Figure 43 , a semiconductor device according to an embodiment will be described. Figure 41 to Figure 43 The semiconductor device disclosed in Figures 1 to 4 The semiconductor device described herein, and in the following, the description focuses on Figure 41 to Figure 43 The semiconductor device disclosed in Figures 1 to 4 Describe the differences between semiconductor devices.

[0157] Fig.41 is a top plan view showing a semiconductor device according to an embodiment. Fig.42 is along Fig.41 A cross-sectional view of the semiconductor device taken along line IV-IV'. Fig.43 is along Fig.41 A cross-sectional view of the semiconductor device taken along line V-V'.

[0158] refer to Figure 41 to Figure 43 According to the embodiment, the semiconductor device may include a base insulating layer 100, a channel layer CH located on a first surface of the base insulating layer 100, a source / drain pattern 150 located on both sides of the channel layer CH, gate structures M_GS and S_GS surrounding the channel layer CH, a lower wiring structure 220 located on a second surface of the base insulating layer 100, a through electrode 190 spaced apart from the gate structure GS and inserted into the first source / drain pattern, and a dummy gate structure D_GS located on the field insulating layer 105.

[0159] The dummy gate structure D_GS may include dummy gate electrodes 131D located at both sides of the through electrode 190 , a dummy interface insulating layer 133D located in a lower portion of the dummy gate electrode 131D, and a dummy gate insulating layer 132D.

[0160] A partial area of ​​the dummy gate electrode 131D may be penetrated by the through electrode 190 in the third direction D3. That is, the dummy gate electrode 131D may be located on both sides of the upper conductive pattern 190a and the lower conductive pattern 190b along the second direction D2. The dummy gate electrode 131D may be located on the field insulating layer 105. The dummy interface insulating layer 133D and the dummy gate insulating layer 132D may be located between the dummy gate electrode 131D and the field insulating layer 105. The upper surface of the dummy gate electrode 131D may contact the lower surface of the dummy capping layer 160c. The dummy gate electrode 131D may include a metal material. For example, the dummy gate electrode 131D may include a metal material that is similar to the reference dummy gate electrode 131D. Figure 2 The dummy gate electrode 131D may be made of the same material as the main gate electrode 131M described above. For example, the dummy gate electrode 131D may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The dummy gate electrode 131D may be electrically separated from other gate electrodes positioned to be spaced apart from the gate separation pattern CT in the first direction.

[0161] The dummy gate insulating layer 132D may extend along the bottom surface of the dummy gate electrode 131D. The dummy gate insulating layer 132D may include Figure 2 The dummy gate insulating layer 132D may include, for example, a high dielectric constant material.

[0162] The dummy interface insulating layer 133D may be located between the dummy gate insulating layer 132D and the field insulating layer 105. The dummy interface insulating layer 133D may also be located between the dummy gate insulating layer 132D and the lower conductive pattern 190b. The dummy interface insulating layer 133D may extend along the lower surface of the dummy gate insulating layer 132D. The dummy interface insulating layer 133D may include a dummy gate insulating layer 132D having a lower conductive pattern 190b. Figure 2The dummy interface insulating layer 133D may include the same material as the main interface insulating layer 133M described above. For example, the dummy interface insulating layer 133D may include silicon oxide (SiO 2 ).

[0163] The semiconductor device according to the embodiment may further include a gate separation pattern CT. The gate separation pattern CT may electrically separate a plurality of gate electrodes (or dummy gate electrodes) arranged in the first direction D1. Fig.41 and Fig.43 , the gate separation pattern CT may electrically separate the dummy gate electrode 131D from other gate electrodes (or other dummy gate electrodes) spaced apart in the first direction D1. The gate separation pattern CT may extend in the third direction D3. The upper surface of the gate separation pattern CT may contact the lower surface of the dummy capping layer 160a. The side surface of the gate separation pattern CT may contact the dummy gate electrode 131D. The lower surface of the gate separation pattern CT may be located at substantially the same height as the lower surface of the dummy gate electrode 131D or the dummy gate structure D_GS. However, it is not limited thereto and is not limited to the above. Fig.43 , the gate separation pattern CT may extend into the field insulation layer 105 or the lower pattern BP. In this case, the lower surface of the gate separation pattern CT may be located at a height lower than the lower surface of the dummy gate structure D_GS. In an embodiment, the gate separation pattern CT may include an insulating material. For example, the gate separation pattern CT may include silicon nitride (SiNx) and / or silicon oxide (SiOx). However, it is not limited thereto, and the gate separation pattern CT may include various insulating materials for electrically isolating the dummy gate structure D_GS from other gate electrodes.

[0164] refer to Figure 41 to Figure 43 , the semiconductor device according to the embodiment may have a hole-type electrode shape. Specifically, in reference Figures 1 to 4 In the semiconductor device described above, the lower conductive pattern 190b and the upper conductive pattern 190a have a linear electrode shape extending along the second direction D2 (see FIG. Figure 1 and Figure 4 ), and Fig.41 and Fig.42 In the case of the semiconductor device shown in , the lower conductive pattern 190 b and the upper conductive pattern 190 a may not extend in the second direction D2 .

[0165] refer to Figure 41 to Figure 43 , the widths of the lower conductive pattern 190b and the upper conductive pattern 190a in the second direction D2 may be smaller than the width w1 of the dummy gate structure D_GS in the second direction D2. The widths of the lower conductive pattern 190b and the upper conductive pattern 190a in the first direction D1 may be different. Fig.41 and Fig.43, the width of the lower conductive pattern 190b in the first direction D1 may be greater than the width of the upper conductive pattern 190a in the first direction. However, but not limited thereto, the widths of the lower conductive pattern 190b and the upper conductive pattern 190a in the first direction D1 may be the same.

[0166] While embodiments of the disclosure have been described in conjunction with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A base insulating layer including a first surface and a second surface opposite to each other; a channel layer on the first surface of the base insulating layer; a first source / drain pattern and a second source / drain pattern, spaced apart from each other in a first direction on the first surface of the base insulating layer, the channel layer being interposed between the first source / drain pattern and the second source / drain pattern, the first direction being parallel to the first surface of the base insulating layer; a gate structure extending in a second direction on the first surface of the base insulating layer, the second direction intersecting the first direction, and the gate structure surrounding the channel layer; a lower wiring structure on the second surface of the base insulating layer; as well as A through electrode is spaced apart from the gate structure, the first source / drain pattern is between the through electrode and the gate structure, the through electrode penetrates the base insulating layer and electrically connects the first source / drain pattern to the lower wiring structure.

2. The semiconductor device according to claim 1, wherein An upper surface of the through electrode is at the same level as an upper surface of the gate structure.

3. The semiconductor device according to claim 1, wherein The through electrode includes an upper conductive pattern and a lower conductive pattern below the upper conductive pattern. The upper conductive pattern is located on a first side of the first source / drain pattern, The width of the lower conductive pattern in the first direction is wider than the width of the upper conductive pattern in the first direction, and The lower conductive pattern is connected to the lower wiring structure.

4. The semiconductor device according to claim 3, wherein: A width of the upper conductive pattern in the first direction is equal to a width of the gate structure in the first direction.

5. The semiconductor device according to claim 3, further comprising: a gate spacer on a side surface of the gate structure; A capping layer, on the upper surface of the gate structure; a dummy gate spacer on a side surface of the upper conductive pattern; as well as a dummy capping layer, on the upper surface of the upper conductive pattern, wherein the dummy gate spacer and the gate spacer have the same material as each other and are part of the same layer, The dummy capping layer and the capping layer have the same material as each other and are parts of one layer.

6. The semiconductor device according to claim 1, further comprising: a third source / drain pattern on the first surface of the base insulating layer and spaced apart from the first source / drain pattern in the first direction, The through electrode is between the first source / drain pattern and the third source / drain pattern, and is electrically connected to the first source / drain pattern and the third source / drain pattern.

7. The semiconductor device according to claim 6, wherein: The through-electrodes extend in the second direction.

8. The semiconductor device according to claim 6, further comprising: The dummy gate electrodes are located on both sides of the through electrode along the second direction, wherein An upper surface of the dummy gate electrode is coplanar with an upper surface of the gate structure and an upper surface of the through electrode.

9. The semiconductor device according to claim 1, further comprising: A first contact electrode electrically connects the first source / drain pattern and the through electrode to each other.

10. The semiconductor device according to claim 9, further comprising: an interlayer insulating layer on the gate structure and the through electrode; an upper wiring structure, on the interlayer insulating layer; as well as a second contact electrode electrically connecting the second source / drain pattern and the upper wiring structure to each other, wherein The first contact electrode and the second contact electrode have the same material as each other and are parts of the same contact electrode layer.

11. A method for manufacturing a semiconductor device, the method comprising: forming a channel layer, a first source / drain pattern and a second source / drain pattern on a first surface of a substrate, wherein the channel layer is between the first source / drain pattern and the second source / drain pattern in a first direction, wherein the first direction is parallel to the first surface of the substrate; forming a gate structure extending in a second direction on the first surface of the substrate, the gate structure surrounding the channel layer in the second direction, the second direction intersecting the first direction; forming a base insulating layer, the forming of the base insulating layer comprising: removing a portion or all of the substrate, and forming the base insulating layer in a region where the portion or all of the substrate is removed; forming a through electrode spaced apart from the gate structure, the first source / drain pattern being between the through electrode and the gate structure, the through electrode penetrating the base insulating layer and being connected to the first source / drain pattern; and A lower wiring structure is formed on a lower surface of the base insulating layer, the lower wiring structure being connected to the through-electrodes.

12. The method according to claim 11, wherein: An upper surface of the through electrode is at the same level as an upper surface of the gate structure.

13. The method according to claim 11, wherein: The forming of the through-electrode includes: forming an upper conductive pattern and a lower conductive pattern below the upper conductive pattern, The upper conductive pattern is formed on a first side of the first source / drain pattern, The width of the lower conductive pattern in the first direction is wider than the width of the upper conductive pattern in the first direction, and The lower conductive pattern is connected to the lower wiring structure.

14. The method according to claim 13, wherein: A width of the upper conductive pattern in the first direction is equal to a width of the gate structure in the first direction.

15. The method according to claim 13, further comprising: forming a gate spacer on the substrate; forming a capping layer covering an upper surface of the gate structure; forming a dummy capping layer on the upper surface of the upper conductive pattern; as well as forming a dummy gate spacer on the substrate, Wherein, the gate spacer covers the side surface of the gate structure, Wherein, the dummy gate spacer covers the side surface of the upper conductive pattern, wherein the dummy gate spacer and the gate spacer have the same material as each other and are part of the same layer, and The dummy capping layer and the capping layer have the same material as each other and are parts of one layer.

16. The method according to claim 11, further comprising: A third source / drain pattern is formed, the third source / drain pattern is on the first surface of the substrate and is spaced apart from the first source / drain pattern in the first direction, wherein the operation of forming the through-electrode forms the through-electrode between the first source / drain pattern and the third source / drain pattern, and forms the through-electrode electrically connected to the first source / drain pattern and the third source / drain pattern.

17. The method according to claim 16, wherein: The through-electrodes extend in the second direction.

18. The method according to claim 11, further comprising: A first contact electrode electrically connecting the first source / drain pattern and the through electrode to each other is formed.

19. The method according to claim 18, further comprising: forming an interlayer insulating layer covering the gate structure and the through electrode; forming a second contact electrode passing through the interlayer insulating layer and electrically connected to the second source / drain pattern; as well as forming an upper wiring structure on the interlayer insulating layer and electrically connected to the second contact electrode, The first contact electrode and the second contact electrode have the same material as each other and are parts of the same contact electrode layer.

20. A semiconductor device comprising: A base insulating layer including a first surface and a second surface opposite to each other; a channel layer on the first surface of the base insulating layer; a first source / drain pattern and a second source / drain pattern, spaced apart from each other on the first surface of the base insulating layer and in a first direction, the channel layer being interposed between the first source / drain pattern and the second source / drain pattern, the first direction being parallel to the first surface of the base insulating layer; a gate structure extending in a second direction on the first surface of the base insulating layer, the second direction intersecting the first direction, and the gate structure surrounding the channel layer in the second direction; an interlayer insulating layer, covering the first source / drain pattern, the second source / drain pattern and the gate structure; an upper wiring structure, on the interlayer insulating layer; a lower wiring structure on the second surface of the base insulating layer; a through electrode spaced apart from the gate structure, the first source / drain pattern being between the through electrode and the gate structure, the through electrode penetrating the base insulating layer and electrically connecting the first source / drain pattern to the lower wiring structure; as well as A contact electrode penetrates the interlayer insulating layer, the contact electrode having a first end connected to the second source / drain pattern and a second end connected to the upper wiring structure.

Images