Semiconductor light-emitting structure and preparation method thereof

Abstract

The invention provides a semiconductor light-emitting structure and a preparation method thereof, the semiconductor light-emitting structure comprises a photonic crystal layer, the photonic crystal layer comprises a first semiconductor layer, the first semiconductor layer is provided with a groove, the first semiconductor layer comprises a plurality of sub-semiconductor layers stacked in a direction perpendicular to a semiconductor substrate layer, and the plurality of sub-semiconductor layers are stacked in a direction perpendicular to the semiconductor substrate layer. The adjacent sub-semiconductor layers are made of different materials, and the thickness of each sub-semiconductor layer is smaller than or equal to 100 nm; wherein the width of the groove has a minimum value at a first position in the direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is larger than the spacing distance from one end, facing the semiconductor substrate layer, of the groove to the semiconductor substrate layer; or, the width of the groove has the maximum value at a second position in the direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is smaller than the spacing distance from one end, away from the semiconductor substrate layer, of the groove to the semiconductor substrate layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor light-emitting structure and a preparation method thereof. Background Art

[0002] Semiconductor lasers are widely used in the modern optoelectronics industry. Introducing embedded periodic photonic crystals in semiconductor lasers is a general method to effectively control the light field mode and manufacture various high-performance semiconductor lasers. In principle, by preparing a periodic air hole structure with high refractive index contrast on semiconductor epitaxial materials, the photon localization effect of nanoscale photonic crystals is used to form a standing wave cavity to generate laser output. Summary of the invention

[0003] Therefore, the technical problem to be solved by the present invention is how to improve the light field mode control capability of a semiconductor light emitting structure, thereby providing a semiconductor light emitting structure and a preparation method thereof.

[0004] The present application provides a semiconductor light-emitting structure, comprising: a semiconductor substrate layer; an active layer located on one side of the semiconductor substrate layer; and a photonic crystal layer located on the side of the active layer away from the semiconductor substrate layer, wherein the photonic crystal layer comprises a first semiconductor layer, wherein the first semiconductor layer comprises a plurality of spaced grooves, the plurality of grooves are arranged periodically, and the grooves extend from a surface of the first semiconductor layer away from the active layer to the first semiconductor layer; wherein the first semiconductor layer comprises a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, wherein adjacent sub-semiconductor layers are made of different materials, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm; wherein the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from one end of the groove away from the semiconductor substrate layer to the semiconductor substrate layer.

[0005] Optionally, the photonic crystal layer also includes: a second semiconductor layer, which is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to an inner wall of the groove; an area of ​​the groove surrounded by a surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

[0006] Optionally, the width of the groove decreases in a direction from the semiconductor substrate layer to the active layer, and the first position passes through an end of the groove away from the semiconductor substrate layer.

[0007] Optionally, the width of the groove first decreases and then increases in a direction from the semiconductor substrate layer to the active layer, and the first position is located between an end of the groove away from the semiconductor substrate layer and an end of the groove facing the semiconductor substrate layer.

[0008] Optionally, the width of the groove first increases and then decreases in the direction from the semiconductor substrate layer to the active layer, and the second position is located between an end of the groove away from the semiconductor substrate layer and an end of the groove facing the semiconductor substrate layer.

[0009] Optionally, the material of the sub-semiconductor layer includes one of a III-V compound semiconductor material, an insulating dielectric material and a metal material.

[0010] The present application also provides a method for preparing a semiconductor light-emitting structure, comprising: forming an active layer on one side of a semiconductor substrate layer; forming a photonic crystal layer on a side of the active layer away from the semiconductor substrate layer; wherein the step of forming the photonic crystal comprises: forming a first semiconductor layer on a side of the active layer away from the semiconductor substrate layer, the first semiconductor layer comprising a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and adjacent sub-semiconductor layers are made of different materials; forming a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer on a side away from the active layer to the first semiconductor layer, and forming the grooves During the etching process, the etching rates of adjacent sub-semiconductor layers are different, and the thickness of each sub-semiconductor layer is less than or equal to 100nm; wherein the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from the end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from the end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

[0011] Optionally, the step of forming the groove includes: forming a patterned mask layer on a side of the first semiconductor layer away from the active layer; etching the first semiconductor layer using the mask layer as a mask layer; removing the mask layer; wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer decreases from the semiconductor substrate layer to the active layer, or the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases from the semiconductor substrate layer to the active layer; wherein, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases from the semiconductor substrate layer to the active layer.

[0012] Optionally, forming the photonic crystal layer also includes: forming a second semiconductor layer, wherein the second semiconductor layer is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to an inner wall of the groove; an area of ​​the groove surrounded by a surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

[0013] Optionally, for adjacent sub-semiconductor layers, a ratio of an absolute value of a difference between etching rates of adjacent sub-semiconductor layers to an etching rate of any one of the sub-semiconductor layers is greater than or equal to 20%.

[0014] The technical solution of the present invention has the following beneficial effects: In the semiconductor light-emitting structure provided by the technical solution of the present invention, the first semiconductor layer includes multiple sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, the adjacent sub-semiconductor layers are made of different materials, and the thickness of each sub-semiconductor layer is less than or equal to 100nm. By regulating the etching rates of different sub-semiconductor layers, the morphology of the grooves can be regulated, thereby improving the light field mode regulation capability.

[0015] Further, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from the end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from the end of the groove away from the semiconductor substrate layer to the semiconductor substrate layer. Based on the groove with special morphology, the volume of the gap is increased, the duty cycle of the gap is improved, and the light field mode control capability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic structural diagram of a semiconductor light emitting structure according to an embodiment of the present application; Figure 2 A schematic structural diagram of a semiconductor light emitting structure according to another embodiment of the present application; Figure 3 A schematic structural diagram of a semiconductor light emitting structure according to another embodiment of the present application; Figure 4 is a schematic structural diagram of a semiconductor light-emitting structure after forming a first semiconductor layer; Figure 5 for Figure 4 A schematic structural diagram of the first semiconductor layer; Figure 6 For Figure 4 A schematic diagram of a structure after a groove is formed on the basis of the present invention; Figure 7 For Figure 6 A schematic diagram of a structure after a second semiconductor layer is formed on the basis of the above; Figure 8 For Figure 7 Schematic diagram of the structure after the Bragg reflector is formed on the basis of. DETAILED DESCRIPTION

[0018] In order to enhance the longitudinal radiation constant of the photonic crystal and thus improve the output power of the semiconductor laser, a scheme is proposed. Specifically, the longitudinal asymmetry of the air hole is regulated, and the air hole after etching is buried by the secondary epitaxial technology. However, for a single semiconductor material, the overall etching rate of the semiconductor material is similar. Since the top and bottom of the semiconductor material have the same etching selectivity, and the top etching time is long and the bottom etching time is short, the morphology of the air hole after etching will be wide at the top and narrow at the bottom. A thicker secondary epitaxial growth is required to completely bury the wide air hole at the top. The longer epitaxial growth time causes the semiconductor material to be deposited again inside the air hole, resulting in a reduction in the hole volume after the secondary epitaxy of the photonic crystal. The volume reduction will affect the duty cycle and morphology of the photonic crystal, causing changes in the energy band and output spectrum, and reducing the ability to control the light field mode.

[0019] On this basis, the present invention provides a semiconductor light-emitting structure and a preparation method thereof, which improves the light field mode control capability of the semiconductor light-emitting structure.

[0020] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0022] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] An embodiment of the present invention provides a semiconductor light emitting structure, referring to Figure 1 , Figure 2 and Figure 3 ,include: Semiconductor substrate layer 100; An active layer 120 located on one side of the semiconductor substrate layer 100; The photonic crystal layer 130 is located on the side of the active layer 120 away from the semiconductor substrate layer 100. The photonic crystal layer 130 includes a first semiconductor layer 1300. The first semiconductor layer 1300 has a plurality of spaced grooves 1301 (see Figure 6 ), a plurality of grooves 1301 are arranged periodically, and the grooves 1301 extend from a surface of the first semiconductor layer 1300 away from the active layer 120 to the first semiconductor layer 1300; wherein the first semiconductor layer 1300 includes a plurality of sub-semiconductor layers 1300a stacked in a direction perpendicular to the semiconductor substrate layer 100 (refer to Figure 5 ), the materials of adjacent sub-semiconductor layers 1300a are different, and the thickness of each sub-semiconductor layer 1300a is less than or equal to 100nm.

[0024] In which, the width of the groove 1301 has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer 100, and the spacing distance from the first position to the semiconductor substrate layer 100 is greater than the spacing distance from one end of the groove 1301 facing the semiconductor substrate layer 100 to the semiconductor substrate layer 100; or, the width of the groove 1301 has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer 100, and the spacing distance from the second position to the semiconductor substrate layer 100 is less than the spacing distance from one end of the groove 1301 facing away from the semiconductor substrate layer 100 to the semiconductor substrate layer 100.

[0025] In this embodiment, the first semiconductor layer 1300 includes a plurality of sub-semiconductor layers 1300a stacked in a direction perpendicular to the semiconductor substrate layer 100, and the materials of adjacent sub-semiconductor layers 1300a are different, and the thickness of each sub-semiconductor layer is less than or equal to 100nm. By regulating the etching rate of different sub-semiconductor layers 1300a, the morphology of the groove is precisely regulated, and the light field mode regulation capability is improved.

[0026] In this embodiment, the semiconductor light emitting structure includes a surface emitting semiconductor laser.

[0027] In this embodiment, the photonic crystal layer further includes: a second semiconductor layer 1302 , which is located on a surface of the first semiconductor layer 1300 between adjacent grooves, facing away from the active layer 120 and extending to an inner wall of the groove 1301 .

[0028] In one embodiment, the material of the second semiconductor layer 1302 is different from the material of the first semiconductor layer 1300 .

[0029] In one embodiment, the refractive index of the second semiconductor layer 1302 is higher than the refractive index of the first semiconductor layer 1300. In other embodiments, the refractive index of the second semiconductor layer is lower than or equal to the refractive index of the first semiconductor layer.

[0030] The area of ​​the groove 1301 surrounded by the surface of the second semiconductor layer 1302 away from the first semiconductor layer 1300 is called a gap W. A plurality of gaps W are periodically arranged in a direction parallel to the surface of the semiconductor substrate layer 100. The gaps W are used to transmit light of a specific wavelength, so that the wavelength of the light emitted by the semiconductor light-emitting structure is more concentrated. Due to the precise control of the morphology of the groove, the volume of the gap W is increased based on the groove with a special morphology, the duty cycle of the gap W is improved, and the light field mode control capability is improved.

[0031] In one embodiment, the material of the sub-semiconductor layer 1300a includes one of a III-V compound semiconductor material, an insulating dielectric material and a metal material. The III-V compound semiconductor material includes but is not limited to GaAs, InP, GaN and GaSb. The insulating dielectric material is, for example, silicon oxide or silicon nitride. The metal material is, for example, titanium, platinum or gold.

[0032] In one embodiment, the thickness of each semiconductor sub-layer 1300a is less than or equal to 100 nm, such as 1 nm, 10 nm, 50 nm or 100 nm. By reducing the thickness of each semiconductor sub-layer 1300a, the ability to control the morphology of the groove 1301 can be improved. The thickness of the semiconductor sub-layer 1300a is the dimension in the direction perpendicular to the semiconductor substrate layer.

[0033] In one embodiment, the material of the second semiconductor layer 1302 includes Al x1 Ga 1-x1 In other embodiments, the second semiconductor layer may also be made of other materials.

[0034] In one embodiment, reference Figure 1 and Figure 3 The width of the groove 1301 has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer 100 , and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove 1301 toward the semiconductor substrate layer 100 to the semiconductor substrate layer 100 .

[0035] When the width of the groove 1301 has a minimum value at the first position in the direction perpendicular to the semiconductor substrate layer 100, in a specific embodiment, Figure 1 and Figure 3, the width of the gap W has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer 100, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the gap W toward the semiconductor substrate layer 100 to the semiconductor substrate layer 100; in another specific embodiment, the width of the gap W first increases and then decreases in the direction from the semiconductor substrate layer 100 to the active layer 120.

[0036] In one embodiment, reference Figure 1 The width of the groove 1301 decreases in a direction from the semiconductor substrate layer 100 to the active layer 120 , and the first position passes through an end of the groove 1301 away from the semiconductor substrate layer 100 .

[0037] In one embodiment, reference Figure 3 The width of the groove 1301 first decreases and then increases in the direction from the semiconductor substrate layer 100 to the active layer 120 , and the first position is located between one end of the groove 1301 away from the semiconductor substrate layer 100 and one end of the groove 1301 toward the semiconductor substrate layer 100 .

[0038] In one embodiment, reference Figure 2 The width of the groove 1301 has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer 100, and the spacing distance from the second position to the semiconductor substrate layer 100 is smaller than the spacing distance from one end of the groove 1301 away from the semiconductor substrate layer 100 to the semiconductor substrate layer 100.

[0039] When the width of the groove 1301 has a minimum value at the first position in the direction perpendicular to the semiconductor substrate layer 100, in a specific embodiment, Figure 2 , the width of the gap W has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer 100, and the spacing distance from the second position to the semiconductor substrate layer 100 is smaller than the spacing distance from one end of the gap W away from the semiconductor substrate layer 100 to the semiconductor substrate layer 100; in another specific embodiment, the width of the gap W first increases and then decreases in the direction from the semiconductor substrate layer 100 to the active layer 120.

[0040] In one embodiment, the width of the gap W at one end away from the semiconductor substrate layer 100 is 100 nanometers to 200 nanometers, such as 100 nanometers, 150 nanometers or 200 nanometers.

[0041] refer to Figure 2The width of the groove 1301 first increases and then decreases in the direction from the semiconductor substrate layer 100 to the active layer 120, and the second position is located between one end of the groove 1301 away from the semiconductor substrate layer 100 and one end of the groove 1301 toward the semiconductor substrate layer 100.

[0042] In one embodiment, a minimum value of the width of the groove 1301 at a first position in a direction perpendicular to the semiconductor substrate layer 100 is 100 nanometers to 200 nanometers, for example, 100 nanometers, 150 nanometers or 200 nanometers.

[0043] refer to Figure 1 The shape of the groove 1301 in the cross section perpendicular to the semiconductor substrate layer 100 is a trapezoid.

[0044] refer to Figure 2 The shape of the groove 1301 in the cross section perpendicular to the semiconductor substrate layer 100 is a convex hexagon.

[0045] refer to Figure 3 The shape of the groove 1301 in the cross section perpendicular to the semiconductor substrate layer 100 is a dumbbell shape.

[0046] In other embodiments, the shape of the groove in the cross section perpendicular to the semiconductor substrate layer 100 may be circular.

[0047] In other embodiments, the shape of the groove in the cross section perpendicular to the semiconductor substrate layer 100 may be an ellipse.

[0048] In this embodiment, the semiconductor light emitting structure further includes: a Bragg reflector 140 located on the side of the photonic crystal layer 130 away from the active layer 120; and a carrier transport layer 110 located between the semiconductor substrate layer 100 and the active layer 120, wherein the doping type of the carrier transport layer 110 is opposite to the doping type of the Bragg reflector 140. For example, the doping type of the Bragg reflector 140 is P-type, and the doping type of the carrier transport layer 110 is N-type.

[0049] In this embodiment, there is no Bragg reflector between the semiconductor substrate layer 100 and the active layer 120. The light emitted by the active layer 120 is transmitted to the Bragg reflector 140 and reflected by the Bragg reflector 140, and then emitted from the semiconductor substrate 100 to the side of the semiconductor substrate 100 away from the active layer 120, and the photonic crystal layer 130 selects the wavelength of the light.

[0050] In other embodiments, the semiconductor light emitting structure further includes: a bottom Bragg reflector located between the semiconductor substrate layer and the active layer, and the reflectivity of the bottom Bragg reflector is greater than the reflectivity of the Bragg reflector.

[0051] The present application also provides a method for preparing a semiconductor light-emitting structure, comprising: forming an active layer on one side of a semiconductor substrate layer; forming a photonic crystal layer on a side of the active layer away from the semiconductor substrate layer; wherein the step of forming the photonic crystal comprises: forming a first semiconductor layer on a side of the active layer away from the semiconductor substrate layer, the first semiconductor layer comprising a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and adjacent sub-semiconductor layers are made of different materials; forming a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer on a side away from the active layer to the first semiconductor layer, and forming the grooves During the etching process, the etching rates of adjacent sub-semiconductor layers are different, and the thickness of each sub-semiconductor layer is less than or equal to 100nm; wherein the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from the end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from the end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

[0052] In this embodiment, the etching rates of adjacent sub-semiconductor layers are different, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm. By adjusting the arrangement of the sub-semiconductor layers, selective etching of the grooves can be achieved. The groove morphology can be controlled with high precision and simple operation, which can meet the advantages of rapid preparation of photonic crystal layers.

[0053] In one embodiment, the step of forming the groove includes: forming a patterned mask layer on a side of the first semiconductor layer away from the active layer; etching the first semiconductor layer using the mask layer as a mask layer; removing the mask layer; wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, in the process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer decreases from the semiconductor substrate layer to the active layer, or the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases from the semiconductor substrate layer to the active layer; wherein, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, in the process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases from the semiconductor substrate layer to the active layer.

[0054] In one embodiment, forming the photonic crystal layer further comprises: forming a second semiconductor layer, the second semiconductor layer being located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extending to the inner wall of the groove; the area of ​​the groove surrounded by the surface of the second semiconductor layer facing away from the first semiconductor layer is a gap. Since the width of the groove has the above characteristics, the amount of the second semiconductor layer filled in the groove is small, which can achieve rapid formation of the second semiconductor layer and improve the duty ratio of the gap.

[0055] Reference below Figures 4 to 8 Introduces the preparation process for forming semiconductor structures.

[0056] refer to Figure 4 , a carrier transport layer 110 is formed on one side of the semiconductor substrate layer 100 ; and an active layer 120 is formed on a side of the carrier transport layer 110 that is away from the semiconductor substrate layer 100 .

[0057] In this embodiment, it also includes: forming a photonic crystal layer on the side of the active layer away from the semiconductor substrate layer; wherein the step of forming the photonic crystal includes: forming a first semiconductor layer on the side of the active layer away from the semiconductor substrate layer, the first semiconductor layer includes a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and the materials of adjacent sub-semiconductor layers are different.

[0058] refer to Figure 4 A first semiconductor layer 1300 is formed on a side of the active layer 120 away from the semiconductor substrate layer 100 .

[0059] In one embodiment, the process for forming the first semiconductor layer 1300 is a deposition process, such as a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a plasma enhanced chemical vapor deposition process, and an atomic layer deposition process.

[0060] refer to Figure 5 The first semiconductor layer 1300 includes a plurality of sub-semiconductor layers 1300a stacked in a direction perpendicular to the semiconductor substrate layer 100, adjacent sub-semiconductor layers 1300a are made of different materials, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm.

[0061] In one embodiment, multiple layers of semiconductor sub-layers 1300a are formed continuously in the same chamber.

[0062] refer to Figure 6, forming a plurality of spaced grooves 1301, the plurality of grooves 1301 are arranged periodically, the grooves 1301 extend from a surface of the first semiconductor layer 1300 that is away from the active layer 120 to the first semiconductor layer 1300, and in the process of forming the grooves 1301, the etching rates of adjacent sub-semiconductor layers 1300a are different, and the thickness of each layer of the sub-semiconductor 1300a is less than or equal to 100nm.

[0063] In one embodiment, the process for forming the groove 1301 is an etching process, and the etching process includes a combination of one or more of a wet etching process and a dry etching process. The wet etching process may be, for example, an acid etching process or an alkaline etching process.

[0064] Figure 6 In the embodiment, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from the end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer as an example. In other embodiments, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from the end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

[0065] The description of the groove refers to the description of the aforementioned embodiment and will not be described in detail.

[0066] In one embodiment, the step of forming the groove includes: forming a patterned mask layer on the side of the first semiconductor layer 1300 away from the active layer 120; etching the first semiconductor layer 1300 using the mask layer as a mask layer; removing the mask layer; wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer 1300 using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer 1300a relative to the mask layer decreases in the direction from the semiconductor substrate layer 100 to the active layer 120.

[0067] In other embodiments, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer 1300 using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases from the semiconductor substrate layer to the active layer; in other embodiments, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases from the semiconductor substrate layer to the active layer.

[0068] In one embodiment, for adjacent sub-semiconductor layers, a ratio of an absolute value of a difference between etching rates of adjacent sub-semiconductor layers to an etching rate of any one of the sub-semiconductor layers is greater than or equal to 20%.

[0069] refer to Figure 7 , forming a second semiconductor layer 1302, wherein the second semiconductor layer 1302 is located on a surface of the first semiconductor layer 1300 between adjacent grooves that is away from the active layer 120 and extends to the inner wall of the groove; the area of ​​the groove surrounded by the surface of the second semiconductor layer 1302 that is away from the first semiconductor layer 1300 is a gap W.

[0070] In one embodiment, the process of forming the second semiconductor layer 1302 includes an epitaxial growth process. In one embodiment, the process of forming the second semiconductor layer 1302 is, for example, an organic metal chemical vapor deposition process. The material and refractive index of the second semiconductor layer 1302 are described with reference to the description of the previous embodiment.

[0071] Since the morphology of the grooves is precisely controlled, the volume of the gap W is increased based on the grooves with special morphology, and the duty cycle of the gap W is improved, thereby improving the light field mode control capability.

[0072] refer to Figure 8 A Bragg reflector 140 is formed on the side of the photonic crystal layer 130 away from the active layer 120 .

[0073] Regarding the material of the Bragg reflector 140 , refer to the above-mentioned embodiment.

[0074] In other embodiments, the semiconductor light emitting structure further includes: a bottom Bragg reflector located between the semiconductor substrate layer and the active layer, and the reflectivity of the bottom Bragg reflector is greater than the reflectivity of the Bragg reflector.

[0075] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A semiconductor light emitting structure, characterized in that: include: Semiconductor substrate layer; an active layer located on one side of the semiconductor substrate layer; A photonic crystal layer located on a side of the active layer away from the semiconductor substrate layer, the photonic crystal layer comprising a first semiconductor layer, the first semiconductor layer having a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer away from the active layer into the first semiconductor layer; Wherein, the first semiconductor layer comprises a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, adjacent sub-semiconductor layers are made of different materials, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm; Wherein, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from one end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

2. The semiconductor light emitting structure according to claim 1, characterized in that: The photonic crystal layer also includes: a second semiconductor layer, which is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to the inner wall of the groove; the area of ​​the groove surrounded by the surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

3. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the groove decreases in a direction from the semiconductor substrate layer to the active layer, and the first position passes through an end of the groove away from the semiconductor substrate layer.

4. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the groove first decreases and then increases in a direction from the semiconductor substrate layer to the active layer, and the first position is located between an end of the groove away from the semiconductor substrate layer and an end of the groove toward the semiconductor substrate layer.

5. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the groove increases first and then decreases in a direction from the semiconductor substrate layer to the active layer, and the second position is located between an end of the groove away from the semiconductor substrate layer and an end of the groove toward the semiconductor substrate layer.

6. The semiconductor light emitting structure according to claim 1, characterized in that: The material of the sub-semiconductor layer includes one of a III-V compound semiconductor material, an insulating dielectric material and a metal material.

7. A method for preparing a semiconductor light-emitting structure, characterized in that: include: forming an active layer on one side of the semiconductor substrate layer; forming a photonic crystal layer on a side of the active layer away from the semiconductor substrate layer; Wherein, the step of forming the photonic crystal comprises: forming a first semiconductor layer on a side of the active layer away from the semiconductor substrate layer, the first semiconductor layer comprising a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and adjacent sub-semiconductor layers are made of different materials; forming a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer away from the active layer to the first semiconductor layer, in the process of forming the grooves, etching rates of adjacent sub-semiconductor layers are different, and the thickness of each layer of the sub-semiconductor is less than or equal to 100 nm; Wherein, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from one end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

8. The method for preparing a semiconductor light emitting structure according to claim 7, characterized in that: The step of forming the groove includes: forming a patterned mask layer on a side of the first semiconductor layer away from the active layer; etching the first semiconductor layer using the mask layer as a mask layer; and removing the mask layer; Wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, in a process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer decreases from the semiconductor substrate layer to the active layer, or the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases from the semiconductor substrate layer to the active layer; Among them, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, in a process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases in a direction from the semiconductor substrate layer to the active layer.

9. The method for preparing a semiconductor light emitting structure according to claim 7, characterized in that: Forming the photonic crystal layer also includes: forming a second semiconductor layer, wherein the second semiconductor layer is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to the inner wall of the groove; the area of ​​the groove surrounded by the surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

10. The method for preparing a semiconductor light emitting structure according to claim 7, characterized in that: For adjacent sub-semiconductor layers, a ratio of an absolute value of a difference between etching rates of adjacent sub-semiconductor layers to an etching rate of any one of the sub-semiconductor layers is greater than or equal to 20%.

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