Charge pump circuit

Abstract

The invention provides a charge pump circuit. The charge pump circuit includes a first transistor, a first capacitor, a second transistor, and a second capacitor. The first transistor has a first terminal and a second terminal. The first capacitor has a first end and a second end. A second terminal of the first capacitor is electrically connected to a second terminal of the first transistor. The second transistor has a first terminal and a second terminal. A first terminal of the second transistor is electrically connected to a second terminal of the first transistor. The second capacitor has a first end and a second end. A first terminal of the second capacitor is electrically connected to a second terminal of the second transistor.

Description

[0001] The present invention is a divisional application of the invention patent application with application number 202210014161.0 filed on January 6, 2022 and invention name “Charge Pump Circuit”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 142,498, filed on January 28, 2021. The entire contents of the above-mentioned patent application are hereby incorporated by reference herein and constitute a part of this specification. Technical Field

[0004] The present disclosure relates to circuits; in particular, the present disclosure relates to charge pump circuits. Background Art

[0005] The display device generally includes a display panel and a driving circuit. Due to the limitation of the material of the display panel, some parts of the driving circuit are usually placed on the driving integrated circuit rather than on the display panel. For example, the scanning signal generator is placed on the driving integrated circuit to provide scanning signals for the pixels on the display panel.

[0006] However, in order to provide the scan signal from the driver integrated circuit to the display panel, low impedance transmission is required. In addition, in order to optimize the area overhead, the scan signal is used to provide to all pixels. Therefore, the low resistance and low parasitic capacitance of the transmission line and the condition of the scan signal introduce some limitations to the display device.

[0007] In addition, voltage regulators usually use charge pump circuits, which are not suitable for signal generators because the output of the charge pump circuits is not linear. Summary of the invention

[0008] The present disclosure is directed to a charge pump circuit for implementing an in-pixel sweep signal generator.

[0009] In the present disclosure, a charge pump circuit includes a first transistor, a first capacitor, a second transistor, and a second capacitor. The first transistor has a first end and a second end. The first capacitor has a first end and a second end. The second end of the first capacitor is electrically connected to the second end of the first transistor. The second transistor has a first end and a second end. The first end of the second transistor is electrically connected to the second end of the first transistor. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically connected to the second end of the second transistor.

[0010] Based on the above, according to the charge pump circuit disclosed in the present invention, multiple output signals are obtained by applying multiple input signals to the charge pump circuit. Since the charge pump circuit has a simple structure, it can be placed on a substrate and thus an in-pixel scan signal generator can be implemented.

[0011] In order that the foregoing may be better understood, several embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0013] Figure 1 is a schematic diagram of a charge pump circuit according to a first embodiment of the present disclosure;

[0014] Figure 2 is a schematic signal timing diagram of a charge pump circuit according to a first embodiment of the present disclosure;

[0015] Figure 3 is a schematic diagram of a charge pump circuit according to a second embodiment of the present disclosure;

[0016] Figure 4 is a schematic signal timing diagram of a charge pump circuit according to a second embodiment of the present disclosure;

[0017] Figure 5 is a schematic diagram of a charge pump circuit according to a modification of the second embodiment of the present disclosure;

[0018] Figure 6 is a schematic diagram of a charge pump circuit according to a third embodiment of the present disclosure;

[0019] Figure 7 is a schematic diagram of a charge pump circuit according to a modification of the third embodiment of the present disclosure;

[0020] Figure 8 is a schematic diagram of a charge pump circuit according to a fourth embodiment of the present disclosure;

[0021] Fig. 9 is a schematic signal timing diagram of a charge pump circuit according to a fourth embodiment of the present disclosure;

[0022] Fig.10 is a schematic diagram of a charge pump circuit according to a modification of the fourth embodiment of the present disclosure;

[0023] Fig.11A is a schematic block diagram of a pixel circuit for an AM-LED display panel according to an embodiment of the present disclosure;

[0024] Fig. 11B is a schematic signal timing diagram of a pixel circuit for an AM-LED display panel according to an embodiment of the present disclosure;

[0025] Fig. 12A is a schematic block diagram of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure;

[0026] Fig. 12B is a schematic input signal of a comparator of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure;

[0027] Fig. 12C is a schematic output signal of a comparator of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure;

[0028] Fig.12D is a schematic output signal of a counter of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure;

[0029] Fig.13 is a schematic diagram of an arbitrary waveform generator according to an embodiment of the present disclosure.

[0030] Description of Figure Numbers

[0031] 100, 300, 500, 600, 700, 800, 1000, 1103: charge pump circuit;

[0032] 110: boost circuit;

[0033] 120: reset circuit;

[0034] 1100, 1200: pixel circuit;

[0035] 1101: scanning transistor;

[0036] 1102: Capacitor;

[0037] 1104: comparator;

[0038] 1105: current generator;

[0039] 1106: light emitting diode;

[0040] 1110: Transmission time period;

[0041] 1201: light detector;

[0042] 1202: pulse shaper;

[0043] 1203: first comparator;

[0044] 1204: second comparator;

[0045] 1205: first counter;

[0046] 1206: second counter;

[0047] 1207: a first scanning transistor;

[0048] 1208: a second transistor;

[0049] 1210, Vi, Vi3, Vi5, Vi6, Vi7, Vi8, Vi10: input signal;

[0050] 1220: first comparison signal;

[0051] 1230: second comparison signal;

[0052] 1240: first counting signal;

[0053] 1250: second counting signal;

[0054] 1300: Arbitrary waveform generator;

[0055] C1, C31, C51, C61, C71, C81, C101: first capacitor;

[0056] C1D: first step-down capacitor;

[0057] C1U: first upper adjustment capacitor;

[0058] C2, C32, C52, C62, C72, C82, C102, C132: second capacitor;

[0059] C33, C53, C63, C73, C83, C103: third capacitor;

[0060] COMP3, COMP5: compensation signals;

[0061] COMP81, COMP101: first compensation signal;

[0062] COMP82, COMP102: second compensation signal;

[0063] Data (m): data line;

[0064] D_PWM: pulse width modulation data;

[0065] E_C: transmission control signal;

[0066] INIT3, INIT5, INIT6, INIT7: initialization signals;

[0067] I_C32, I_C62, I_C72, I_C82, I_C102: second capacitor current;

[0068] I_PD: photodetector current;

[0069] I_T1, I_T31, I_T51, I_T61, I_T71, I_T81, I_T101: first transistor current;

[0070] I_T2, I_T32, I_T52, I_C62, I_T72, I_T82, I_T102: second transistor current;

[0071] I_T33, I_T53, I_T83, I_T103: third transistor current;

[0072] I_T34, I_T64, I_T74, I_T84, I_T104: fourth transistor current;

[0073] I_T35, I_T65, I_T75, I_T85, I_T105: fifth transistor current;

[0074] I_T36, I_T66, I_T86, I_T106: sixth transistor current;

[0075] I_T88_1, I_108_1: current of the eighth transistor step 1;

[0076] I_T88_3, I_T108_3: current of the eighth transistor step three;

[0077] I_T88_4: current of the eighth transistor in step 4;

[0078] I_T89, I_T109: ninth transistor current;

[0079] L: light;

[0080] N1, N31, N51, N61, N71, N81, N101: first node;

[0081] N32, N52, N62, N72, N82, N102: second node;

[0082] N33, N53, N63, N73, N83, N103: the third node;

[0083] Q: extra charge;

[0084] Q': insufficient charge;

[0085] RES, RES3, RES5, RES6, RES7, RES8, RES10, RES13: reset signals;

[0086] Ref1: first reference signal;

[0087] Ref2: second reference signal;

[0088] Scan(n): scan line;

[0089] Scan1(n): first scan line;

[0090] Sense(m): sensing line;

[0091] SW: scanning signal;

[0092] T1, T31, T51, T61, T71, T81, T101: first transistor;

[0093] T2, T32, T52, T62, T72, T82, T102: second transistor;

[0094] T33, T53, T63, T73, T83, T103: third transistor;

[0095] T34, T54, T64, T74, T84, T104: fourth transistor;

[0096] T35, T55, T65, T75, T85, T105: fifth transistor;

[0097] T36, T56, T66, T76, T86, T106: sixth transistor;

[0098] T87, T107: seventh transistor;

[0099] T88, T108: eighth transistor;

[0100] T89, T109: ninth transistor;

[0101] Tr, T13r: reset transistor;

[0102] T_D1: first step-down transistor;

[0103] T_D2: second step-down transistor;

[0104] T_U1: first up-regulation transistor;

[0105] T_U2: second up-regulation transistor;

[0106] t_1, t_2, t_3, t_31, t_32, t_33, t_34, t_t35, t_36, t_37, t_38, t_39, t_4, t_5, t_6, t_7: time;

[0107] V1: first voltage;

[0108] V2: second voltage;

[0109] VDD, VH: first reference voltage;

[0110] Vid: input down-regulation signal;

[0111] Vin: input voltage;

[0112] Viu: input up-regulation signal;

[0113] VL, VSS: second reference voltage;

[0114] Vo, Vo3, Vo5, Vo6, Vo7, Vo8, Vo10, Vo13: output signal;

[0115] Vrst, Vrst3, Vrst5, Vrst6, Vrst7, Vrst8, Vrst10, Vrst13: reset voltage;

[0116] Vstep, Vstep3, Vstep5, Vstep6, Vstep7, Vstep8, Vstep10: step voltage;

[0117] Vth1, Vth31, Vth51, Vth61, Vth71, Vth81, Vth101: first threshold voltage;

[0118] Vth2, Vth32, Vth52, Vth62, Vth72, Vth82, Vth102: second threshold voltage;

[0119] Vth63, Vth73, Vth83, Vth103: third threshold voltage;

[0120] Vth64, Vth74: fourth threshold voltage. DETAILED DESCRIPTION

[0121] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like components.

[0122] Throughout this specification and the appended claims of the present disclosure, specific terms are used to refer to specific components. It will be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. It is not intended herein to distinguish between components that have the same function but different names. In the following description and claims, words such as "including" and "comprising" are open-ended terms and should be interpreted as "including but not limited to ...".

[0123] The term "coupling (or connection)" used throughout the entire specification of this application (including the attached claims) may refer to any direct or indirect connection member. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connecting members. The terms "first", "second" and similar terms mentioned throughout the entire specification of this application (including the attached claims) are only used to name discrete elements or to distinguish different embodiments or scopes. Therefore, the terms should not be regarded as limiting the upper or lower limits of the number of elements and should not be used to limit the arrangement order of elements. In addition, where possible, the elements / components / steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. The same reference numerals or the same terms can be used to refer to the relevant descriptions of the elements / components / steps in different embodiments.

[0124] The light-emitting device of the present disclosure may be suitable for liquid crystal, light-emitting diode, quantum dot (quantum dot; QD), fluorescence, phosphor, other suitable materials or combinations of the foregoing materials, but the present disclosure is not limited thereto. The light-emitting diode may include, for example, an organic light-emitting diode (organic light emitting diode; OLED), a submillimeter light-emitting diode (micro LED), a micro light-emitting diode (micro LED) or a quantum dot light-emitting diode (quantum dot light emitting diode; QLED or QDLED) or other suitable materials. The materials may be arranged and combined arbitrarily, but the present disclosure is not limited thereto. The light-emitting device of the present disclosure may include peripheral systems that support the light-emitting device, such as a drive system, a control system, a light source system, a chassis system, and the like.

[0125] It should be noted that in the following embodiments, the technical features of several different embodiments may be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the present disclosure. As long as the features of each embodiment do not violate the spirit of the present disclosure or conflict with each other, they may be mixed and used together at will.

[0126] Figure 1 is a schematic diagram of a charge pump circuit according to a first embodiment of the present disclosure. Figure 1, the charge pump circuit 100 may include a boost circuit 110 and a reset circuit 120. The boost circuit 110 may include a first transistor T1, a second transistor T2, a first capacitor C1, and a second capacitor C2. Specifically, the first transistor T1 may have a first end and a second end. In one embodiment, the first end of the first transistor T1 may be a source terminal, and the second end of the first transistor T1 may be a drain terminal, but the present disclosure is not limited thereto. In another embodiment, the first end of the first transistor T1 may be a drain terminal, and the second end of the first transistor T1 may be a source terminal. In an embodiment, the first capacitor C1 may have a first end and a second end. The second end of the first capacitor C1 may be electrically connected to the second end of the first transistor T1 at a first node N1. The second transistor T2 may have a first end and a second end. In an embodiment, the first end of the second transistor T2 may be electrically connected to the second end of the first transistor T1 at a first node N1. The second capacitor C2 may have a first end and a second end. The first end of the second capacitor C2 may be electrically connected to the second end of the second transistor T2.

[0127] In addition, the reset circuit 120 may include a reset transistor Tr. The reset transistor may have a first terminal and a second terminal. The first terminal of the reset transistor Tr may be electrically connected to the first terminal of the second capacitor C2. The second terminal of the reset transistor Tr may receive a reset voltage. The reset transistor Tr may further have a control terminal. The control terminal of the reset transistor Tr may receive a reset signal RES.

[0128] In an embodiment, the reset circuit 120 may be disposed in the charge pump circuit 100. The reset circuit 120 and the boost circuit 110 may be integrated in an electronic device (e.g., a pixel of a display device). In an embodiment, the electronic device may include a light emitting device or a display device, but the present disclosure is not limited thereto. In an embodiment, the display device may include an active matrix light emitting diode (AM-LED) display panel, but the present disclosure is not limited thereto.

[0129] In addition, in one embodiment, the reset circuit 120 may be disposed outside the charge pump circuit 100. In an embodiment, the reset circuit 120 may be disposed on a driver integrated circuit of a pixel of a display device to provide a reset signal RES to the boost circuit 110. That is, the charge pump circuit 100 may not include the reset circuit 120, but the present disclosure is not limited thereto.

[0130] Figure 2 is a schematic signal timing diagram of a charge pump circuit according to a first embodiment of the present disclosure. Figure 1 and Figure 2, the first end of the first capacitor C1 may receive an input signal Vi, and the first end of the second capacitor C2 may provide an output signal Vo. In an embodiment, the first end of the transistor T1 receives a first voltage V1, and the control end of the second transistor T2 receives a second voltage V2. The first voltage V1 may be lower than the second voltage V2, but the present disclosure is not limited thereto. The second end of the second capacitor C2 receives a reset voltage Vrst. The first transistor T1 may have a first threshold voltage Vth1, and the second transistor T2 may have a second threshold voltage Vth2. The first end of the first transistor T1 is electrically connected to the control end of the first transistor. That is, the first transistor T1 may act as a diode. In an embodiment, the first transistor T1 may be an N-type transistor, and the second transistor T2 may be a P-type transistor, but the present disclosure is not limited thereto. In one embodiment, the first transistor T1 may be a P-type transistor, and the second transistor T2 may be an N-type transistor.

[0131] In an embodiment, for ease of understanding, for example, the first voltage V1 may be 7 volts. The second voltage V2 may be 9 volts. The absolute values ​​of the first threshold voltage Vth1 and the second threshold voltage Vth2 may be 1 volt, but the present disclosure is not limited thereto. At time t_1, the reset signal RES may be switched from a low voltage level to a high voltage level. After the high voltage level is applied to the control end of the reset transistor Tr, the reset transistor Tr is turned on, and the first end of the second capacitor C2 is reset to the reset voltage Vrst. That is, the output signal Vo is reset to the reset voltage Vrst. Before time t_2, the reset signal RES may be switched from a high voltage level to a low voltage level. In addition, the voltage of the first node N1 may be obtained by subtracting the first threshold voltage Vth1 from the first voltage V1, so the voltage of the first node N1 may be expressed as V1-|Vth1|.

[0132] At time t_2, the input signal Vi may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. In an embodiment, it is assumed that the input voltage Vin is 5 volts, but the present disclosure is not limited thereto. Since the voltage difference between the first end and the second end of the first capacitor C1 may maintain a constant value, the voltage of the first node N1 may change from V1-|Vth1| to V1-|Vth1|+Vin. However, since the first node N1 is electrically connected to the first end of the second transistor T2, the voltage value of the first node N1 may be constrained by the second transistor T2. That is, at time t_2, the voltage value of the first node N1 may be V2+|Vth2|( Figure 2 The solid line of N1 in the figure) rather than V1-|Vth1|+Vin( Figure 2 ), and the second transistor T2 may be turned on. Therefore, the additional charge Q may be discharged from the first capacitor C1 based on the voltage difference and may be calculated by the following equation (1).

[0133] Q=C1×{(V1-|Vth1|)+Vin-(V2+|Vth2|)}…………(1)

[0134] In an embodiment, the extra charge Q can be transferred from the first capacitor C1 to the second capacitor C2 through the second transistor current I_T2, and thus the second capacitor C2 can be charged. That is, the value of the output signal Vo can increase the value of the step voltage Vstep, and the value of the step voltage Vstep can be calculated by the following equation (2).

[0135]

[0136] In an embodiment, the ratio of the first capacitor C1 to the second capacitor C2 may be 1 / 100. That is, the value of the step voltage Vstep may be 10 mV. Therefore, the value of the output signal Vo may increase from the reset voltage Vrst to Vrst+Vstep.

[0137] At time t_3, the input signal Vi may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C1 may maintain a constant value, the voltage of the first node N1 may change from V2+|Vth2| to V2+|Vth2|-Vin. However, since the first node N1 is electrically connected to the second end of the first transistor T1, the voltage value of the first node N1 may be constrained by the first transistor T1. That is, at time t_3, the voltage value of the first node N1 may be V1-|Vth1|( Figure 2 The solid line of N1 in the figure) rather than V2+|Vth2|-Vin( Figure 2 ), and the first transistor T1 may be turned on. Therefore, insufficient charge Q' may be charged into the first capacitor C1 through the first transistor current I_T1 based on the voltage difference, and may be calculated by the following equation (3).

[0138] Q ′ =C1×{(V2+|Vth2|)-Vin-(V1+|Vth1|)}=-Q…………(3)

[0139] At time t_4, the input signal Vi may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Referring to time t_2, the additional charge Q may be discharged from the first capacitor C1. In addition, the additional charge Q may be transferred from the first capacitor C1 to the second capacitor C2 through the second transistor current I_T2, and thereby the second capacitor C2 may be charged. That is, the value of the output signal Vo may increase the value of the step voltage Vstep. Therefore, the value of the output signal Vo may increase from Vrst+Vstep to Vrst+(2×Vstep).

[0140] At time t_5 , the input signal Vi may switch from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Referring to time t_3 , insufficient charge Q′ may be charged into the first capacitor C1 by the first transistor current I_T1 .

[0141] At time t_6, the input signal Vi may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Referring to time t_2 and time t_4, the additional charge Q may be discharged from the first capacitor C1. In addition, the additional charge Q may be transferred from the first capacitor C1 to the second capacitor C2 through the second transistor current I_T2, and thereby the second capacitor C2 may be charged. That is, the value of the output signal Vo may increase the value of the step voltage Vstep. Therefore, the value of the output signal Vo may increase from Vrst+(2×Vstep) to Vrst+(3×Vstep).

[0142] At time t_7, the input signal Vi may switch from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Referring to time t_3 and time t_5, insufficient charge Q' may be charged into the first capacitor C1 by the first transistor current I_T1.

[0143] It should be noted that at time t_2, time t_4 and time t_6, the output signal Vo can increase the value of the step voltage Vstep respectively. That is, by repeatedly switching the input signal Vi between the high voltage level and the low voltage level, the value of the output signal Vo can be increased to a plurality of different values. In addition, the plurality of different values ​​can be proportional to the number of repetitions of the switching input signal Vi. In other words, various waveforms can be output by the charge pump circuit 100, and the output is substantially linear. Therefore, the charge pump circuit 100 can be used as a signal generator. In one embodiment, the charge pump circuit 100 can be used as a scan signal generator for the pixel of the display device to implement a scan signal generator in the pixel. In addition, since the structure of the charge pump circuit 100 is simple, the charge pump circuit 100 can be placed on a substrate and thus a scan signal generator in the pixel can be implemented. In one embodiment, the substrate may include glass or polyimide or other suitable materials, but the present disclosure is not limited thereto.

[0144] In an embodiment, the second transistor T2 is a P-type transistor, but the present disclosure is not limited thereto. In an embodiment, the second transistor T2 can provide a charging current (second transistor current I_T2) of the second capacitor C2, and thus the charge pump circuit 100 can be a boost circuit. In another embodiment, the second transistor T2 can be an N-type transistor, and thus a discharge current of the second capacitor C2 can be provided. Therefore, the charge pump circuit 100 can become a step-down circuit.

[0145] Figure 3 is a schematic diagram of a charge pump circuit according to a second embodiment of the present disclosure. Figure 1 and Figure 3 , the charge pump circuit 300 may have a similar structure to the charge pump circuit 100. The charge pump circuit 300 may include a first transistor T31, a second transistor T32, a first capacitor C31, and a second capacitor C32. These elements may be referred to as the charge pump circuit 100 and the details are not redundantly described one by one herein.

[0146] In an embodiment, the charge pump circuit 300 may further include a third transistor T33, a fourth transistor T34, a fifth transistor T35, a sixth transistor T36 and a third capacitor C33. In an embodiment, the third transistor T33 may have a first end and a second end. The third transistor T33 may be electrically connected between the second end of the second transistor T32 and the first end of the second capacitor C32. The third capacitor C33 may have a first end and a second end. The first end of the third capacitor C33 may be electrically connected to the control end of the second transistor T32. The fourth transistor T34 may have a first end and a second end. The fourth transistor T34 may be electrically connected between the second end of the second transistor T32 and the first end of the third capacitor C33. The fifth transistor T35 may have a first end and a second end. The fifth transistor T35 may be electrically connected between the second end of the fourth transistor T34 and the second end of the third capacitor C33. The sixth transistor T36 may have a first end and a second end. The sixth transistor T36 may be electrically connected between the second end of the third transistor T33 and the second end of the second capacitor C32. In an embodiment, the second end of the first capacitor C31 may be indicated as a first node N31, the first end of the third capacitor C33 may be indicated as a second node N32, and the first end of the second capacitor C32 may be indicated as a third node N33. In an embodiment, the first transistor T31 may have a first threshold voltage Vth31, and the second transistor T32 may have a second threshold voltage Vth32, but the present disclosure is not limited thereto.

[0147] In an embodiment, a first end of the first transistor T31 receives a first reference voltage VH. A second end of the second capacitor C32 receives a second reference voltage VL. A second end of the third capacitor C33 receives a reset voltage Vrst3. In an embodiment, a control end of the fifth transistor T35 may receive a reset signal RES3. A control end of the sixth transistor T36 may receive an initialization signal INIT3. In an embodiment, a control end of the third transistor T33 and a control end of the fourth transistor T34 receive a compensation signal COMP3. In an embodiment, a first end of the first capacitor C31 may receive an input signal Vi3. A first end of the second capacitor C32 may provide an output signal Vo3.

[0148] Figure 4 is a schematic signal timing diagram of a charge pump circuit according to a second embodiment of the present disclosure. Figure 3 and Figure 4 , the circled numbers in the drawings may respectively indicate different steps of the operation of the charge pump circuit 300. The arrows with the circled numbers in the drawings may respectively indicate the current during a certain step of the operation of the charge pump circuit 300. The arrows toward the first capacitor C31 may indicate charging the first capacitor C31, and the arrows away from the first capacitor C31 may indicate discharging the first capacitor C31.

[0149] During the time period (step 1) from time t_31 to time t_32, the reset signal RES3 may be switched from a low voltage level to a high voltage level, and the compensation signal COMP3 and the initialization signal INIT3 may be maintained at a low voltage level. After the high voltage level is applied to the control terminal of the fifth transistor T35, the fifth transistor T35 is turned on. Therefore, the first end of the third capacitor C33 is reset to the reset voltage Vrst3 by the fifth transistor current I_T35. That is, the second node N32 is reset to the reset voltage Vrst3. Since the reset voltage Vrst3 is at a low voltage level, the second transistor T32 may be turned on. In addition, the first transistor T31 is turned on due to the high voltage level of the first reference voltage VH, and the third transistor T33 is turned on due to the low voltage level of the compensation signal COMP3. Therefore, the first node N31 and the third node N33 are both reset to VH-|Vth31| by the second capacitor current I_C32. Before time t_32, the reset signal RES may be switched from a high voltage level to a low voltage level.

[0150] During the time period from time t_32 to time t_33 (step 2), the compensation signal COMP3 may be switched from a low voltage level to a high voltage level. After the high voltage level is applied to the control terminals of the third transistor T33 and the fourth transistor T34, the third transistor T33 is switched from on to off, and the fourth transistor T34 is switched from off to on. The second node N32 is then compensated to VH-|Vth31|-|Vth32| by the fourth transistor current I_T34. Before time t_33, the compensation signal COMP3 may be switched from a high voltage level to a low voltage level.

[0151] During the time period from time t_33 to time t_34 (step 3), the initialization signal INIT3 may be switched from a low voltage level to a high voltage level. After the high voltage level is applied to the control terminal of the sixth transistor T36, the sixth transistor T36 is switched from disconnection to connection. The node N33 is reset to the second reference voltage VL by the sixth transistor current I_T36. Before time t_34, the initialization signal INIT3 may be switched from a high voltage level to a low voltage level.

[0152] During the time period from time t_t34 to time t_t35 (step 4), the input signal Vi3 may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C1 may maintain a constant value, the voltage of the first node N31 may change from VH-|Vth31| to VH-|Vth31|+Vin. However, since the first node N31 is electrically connected to the first end of the second transistor T32, the voltage value of the first node N31 may be constrained by the second transistor T32. That is, at time t_34, the voltage value of the first node N31 may be maintained at VH-|Vth31|( Figure 4 The solid line of N31 in the figure) rather than VH-|Vth31|+Vin( Figure 4 The second transistor T32 and the third transistor T33 may be turned on. Therefore, the additional charge Q may be discharged from the first capacitor C31 based on the voltage difference and may be calculated by the following equation (4).

[0153] Q=C31×{(VH-|Vth31|+Vin)-(VH-|Vth31|)}=C31×Vin…(4)

[0154] In an embodiment, the extra charge Q can be transferred from the first capacitor C31 to the second capacitor C32 through the second transistor current I_T32 and the third transistor current I_T33 and thus the second capacitor C32 can be charged. That is, the value of the output signal Vo3 can increase the value of the step voltage Vstep3, and the value of the step voltage Vstep3 can be calculated by the following equation (5).

[0155]

[0156] Therefore, the value of the output signal Vo3 may increase from the second reference voltage VL to VL+Vstep3.

[0157] During the time period from time t_35 to time t_36 (step 5), the input signal Vi3 may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C1 may maintain a constant value, the voltage of the first node N31 may change from VH-|Vth31| to VH-|Vth31|-Vin. However, since the first node N31 is electrically connected to the second end of the first transistor T31, the voltage value of the first node N31 may be constrained by the first transistor T31. That is, at time t_34, the voltage value of the first node N31 may be maintained at VH-|Vth31|( Figure 4The solid line of N31 in the figure) rather than VH-|Vth31|-Vin( Figure 4 The first transistor T31 may be turned on. Therefore, the insufficient charge Q' may be charged into the first capacitor C31 through the first transistor current I_T31 based on the voltage difference, and may be calculated by the following equation (6).

[0158] Q ′ =C31×{(VH-|Vth31|-Vin)-(VH-|Vth31|)}=C31×(-Vin)=-Q…………(6)

[0159] During the time period from time t_36 to time t_37, the charging operation may be repeated again as step 4. The extra charge Q may be discharged from the first capacitor C31. In addition, the extra charge Q may be transferred from the first capacitor C31 to the second capacitor C32 through the second transistor current I_T32 and the third transistor current I_T33 and the second capacitor C32 may be charged thereby. Therefore, the value of the output signal Vo3 may increase from VL+Vstep3 to VL+(2×Vstep3). During the time period from time t_37 to time t_38, the charging operation may be repeated again as step 5. The insufficient charge Q' may be charged into the first capacitor C31 through the first transistor current I_T31.

[0160] During the time period from time t_38 to time t_39, the charging operation may be repeated again as step 4. The extra charge Q may be discharged from the first capacitor C31. In addition, the extra charge Q may be transferred from the first capacitor C31 to the second capacitor C32 through the second transistor current I_T32 and the third transistor current I_T33 and the second capacitor C32 may be charged thereby. Therefore, the value of the output signal Vo3 may increase from VL+(2×Vstep3) to VL+(3×Vstep3). After time t_39, the charging operation may be repeated again as step 5. The insufficient charge Q' may be charged into the first capacitor C31 through the first transistor current I_T31.

[0161] It should be noted that the value of the output signal Vo3 can be increased by the value of the step voltage Vstep3 at time t_34, time t_36 and time t_38, respectively. That is, by repeating steps 4 and 5, the value of the output signal Vo3 can be increased to a plurality of different values. In addition, the plurality of different values ​​are proportional to the number of repetitions of steps 4 and 5. In other words, various waveforms can be output by the charge pump circuit 300, and the output is substantially linear. Therefore, the charge pump circuit 300 can be used as a signal generator. In one embodiment, the charge pump circuit 300 can be used as a scan signal generator for a pixel of a display device to implement a scan signal generator in a pixel. In addition, since the structure of the charge pump circuit 300 is simple, the charge pump circuit 300 can be disposed on a substrate, and thus a scan signal generator in a pixel can be implemented.

[0162] In an embodiment, the second transistor T32 is a P-type transistor, but the present disclosure is not limited thereto. In an embodiment, the second transistor T32 can provide a charging current (second transistor current I_T32) of the second capacitor C32 and thus the charge pump circuit 300 can be a boost circuit. In another embodiment, the second transistor T32 can be an N-type transistor and thus can provide a discharge current of the second capacitor C32. Therefore, the charge pump circuit 300 can be changed into a buck circuit.

[0163] Figure 5 is a schematic diagram of a charge pump circuit according to a modification of the second embodiment of the present disclosure. Figure 5 , Figure 3 and Figure 5 The main difference between the two is that the second transistor T32 of the charge pump circuit 300 is a P-type transistor and the second transistor T52 of the charge pump 500 is an N-type transistor. In an embodiment, the charge pump circuit 500 may include a first transistor T51, a second transistor T52, a first capacitor C51, and a second capacitor C52. These elements may be referred to as the charge pump circuit 100 and the details are not redundantly described one by one herein.

[0164] In an embodiment, the charge pump circuit 500 may further include a third transistor T53, a fourth transistor T54, a fifth transistor T55, a sixth transistor T56 and a third capacitor C53. In an embodiment, the third transistor T53 may have a first end and a second end. The third transistor T53 may be electrically connected between the second end of the second transistor T52 and the first end of the second capacitor C52. The third capacitor C53 may have a first end and a second end. The first end of the third capacitor C53 may be electrically connected to the control end of the second transistor T52. The fourth transistor T54 may have a first end and a second end. The fourth transistor T54 may be electrically connected between the second end of the second transistor T52 and the first end of the third capacitor C53. The fifth transistor T55 may have a first end and a second end. The fifth transistor T55 may be electrically connected between the second end of the fourth transistor T54 and the second end of the third capacitor C53. The sixth transistor T56 may have a first end and a second end. The sixth transistor T56 may be electrically connected between the second end of the third transistor T53 and the second end of the second capacitor C52.

[0165] In an embodiment, the second end of the first capacitor C51 may be indicated as a first node N51, the first end of the third capacitor C53 may be indicated as a second node N52, and the first end of the second capacitor C52 may be indicated as a third node N53. In an embodiment, the first transistor T51 may have a first threshold voltage Vth51, and the second transistor T52 may have a second threshold voltage Vth52, but the present disclosure is not limited thereto. In an embodiment, the first end of the first transistor T51 receives a second reference voltage VL. The second end of the second capacitor C52 receives a first reference voltage VH. The second end of the third capacitor C53 receives a reset voltage Vrst5.

[0166] In an embodiment, the control end of the fifth transistor T55 may receive a reset signal RES5. The control end of the sixth transistor T56 may receive an initialization signal INIT5. In an embodiment, the control end of the third transistor T53 and the control end of the fourth transistor T54 may receive a compensation signal COMP5. In an embodiment, the first end of the first capacitor C51 may receive an input signal Vi5. The first end of the second capacitor C52 may provide an output signal Vo5.

[0167] In an embodiment, the circled numbers in the drawings may respectively indicate different steps of the operation of the charge pump circuit 500. The arrows with the circled numbers in the drawings may respectively indicate the current flow during a certain step of the operation of the charge pump circuit 500. The arrows toward the first capacitor C51 may indicate charging the first capacitor C51, and the arrows away from the first capacitor C51 may indicate discharging the first capacitor C51.

[0168] In an embodiment, steps 1 to 3 may refer to steps 1 to 3 of the second embodiment, and the details are not redundantly described one by one herein. It should be noted that the reset signal RES5, the compensation signal COMP5, and the initialization signal INIT5 may be switched from a high voltage level to a low voltage level during steps 1, 2, and 3, respectively. Therefore, during step 1, the first node N51 and the third node N53 may be reset to VL+|Vth51|, and the second node N52 may be reset to the reset voltage Vrst5. During step 2, the second node N52 may be compensated to VL+|Vth51|+|Vth52|. During step 3, the third node N53 may be initialized to the first reference voltage VH.

[0169] During the time period of step 4, the input signal Vi5 may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C51 may maintain a constant value, the voltage of the first node N51 may change from VL+|Vth51| to VL+|Vth51|-Vin. However, since the first node N51 is electrically connected to the first end of the second transistor T52, the voltage value of the first node N51 may be constrained by the second transistor T52. That is, during step 4, the voltage value of the first node N51 may be maintained at VL+|Vth51| rather than VL+|Vth51|-Vin. The second transistor T52 and the third transistor T53 may be turned on. Therefore, insufficient charge Q' may be charged into the first capacitor C51 based on the voltage difference. The value of insufficient charge Q' may be equal to C51×(-Vin).

[0170] In an embodiment, insufficient charge Q' may be transferred from the second capacitor C52 to the first capacitor C51 through the second transistor current I_T52 and the third transistor current I_T53, and thereby the second capacitor C52 may be discharged. That is, the value of the output signal Vo5 may be reduced by the value of the step voltage Vstep5, and the value of the step voltage Vstep5 may be equal to (C51 / C52)×Vin. Therefore, the value of the output signal Vo5 may be reduced from the first reference voltage VH to VH-Vstep5.

[0171] During the time period of step 5, the input signal Vi5 may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C51 may maintain a constant value, the voltage of the first node N51 may change from VL+|Vth51| to VL+|Vth51|+Vin. However, since the first node N51 is electrically connected to the second end of the first transistor T51, the voltage value of the first node N51 may be constrained by the first transistor T51. That is, during the time period of step 5, the voltage value of the first node N51 may be maintained at VL+|Vth51| rather than VL+|Vth51|+Vin, and the first transistor T51 may be turned on. Therefore, the extra charge Q may be discharged from the first capacitor C51 through the first transistor current I_T51 based on the voltage difference and may be equal to (-Q').

[0172] It should be noted that the value of the output signal Vo5 can reduce the value of the step voltage Vstep5 during step 4. That is, by repeating steps 4 and 5, the value of the output signal Vo5 can be reduced to a plurality of different values. In addition, the plurality of different values ​​are proportional to the number of repetitions of steps 4 and 5. In other words, various waveforms can be output by the charge pump circuit 500, and the output is linear. Therefore, the charge pump circuit 500 can be used as a signal generator. In one embodiment, the charge pump circuit 500 can be used as a scan signal generator for a pixel of a display device to implement a scan signal generator in a pixel. In addition, since the structure of the charge pump circuit 500 is simple, the charge pump circuit 500 can be disposed on a substrate and thus a scan signal generator in a pixel can be implemented.

[0173] Figure 6 is a schematic diagram of a charge pump circuit according to a third embodiment of the present disclosure. Figure 1 and Figure 6 , the charge pump circuit 600 may have a similar structure to the charge pump circuit 100. The charge pump circuit 600 may include a first transistor T61, a second transistor T62, a first capacitor C61, and a second capacitor C62. These elements may be referred to as the charge pump circuit 100 and the details are not redundantly described one by one herein.

[0174] In an embodiment, the charge pump circuit 600 may further include a third transistor T63, a fourth transistor T64, a fifth transistor T65, a sixth transistor T66, and a third capacitor C63. In an embodiment, the third transistor T63 may have a first end and a second end. The fourth transistor T64 may have a first end and a second end. The second end of the fourth transistor T64 may be electrically connected to the first end of the third transistor T63. The fifth transistor T65 may have a first end and a second end. The first end of the fifth transistor T65 may be electrically connected to the first end of the fourth transistor T64. The sixth transistor T66 may have a first end and a second end. The first end of the sixth transistor T65 may be electrically connected to the first end of the second capacitor C62. The second end of the sixth transistor T66 may be electrically connected to the second end of the second capacitor C62. The third capacitor C63 may have a first end and a second end. The first end of the third capacitor C63 may be electrically connected to the first end of the fifth transistor C65. The second end of the third capacitor C63 may be electrically connected to the second end of the fifth transistor C65.

[0175] In an embodiment, the second end of the first capacitor C61 may be indicated as the first node N61, the first end of the third capacitor C63 may be indicated as the second node N62, and the first end of the second capacitor C62 may be indicated as the third node N63. In an embodiment, the first transistor T61 may have a first threshold voltage Vth61, the second transistor T62 may have a second threshold voltage Vth62, the third transistor T63 may have a third threshold voltage Vth63, and the fourth transistor T64 may have a fourth threshold voltage Vth64. In an embodiment, the first threshold voltage Vth61 may be equal to the third threshold voltage Vth63, and the second threshold voltage Vth62 may be equal to the fourth threshold voltage Vth64, but the present disclosure is not limited thereto. In an embodiment, the first end of the first transistor T61 and the second end of the third transistor T63 receive a first reference voltage VH. The second end of the second capacitor C62 receives a second reference voltage VL. The second end of the third capacitor C63 receives a reset voltage Vrst6.

[0176] In an embodiment, the control terminal of the fifth transistor T65 may receive a reset signal RES6. The control terminal of the sixth transistor T66 may receive an initialization signal INIT6. In an embodiment, the second end of the third transistor T63 may be electrically connected to the control terminal of the third transistor T63. The first end of the fourth transistor T64 may be electrically connected to the control terminal of the fourth transistor T64. In an embodiment, the first end of the first capacitor C61 may receive an input signal Vi6. The first end of the second capacitor C62 may provide an output signal Vo6.

[0177] In an embodiment, the circled numbers in the accompanying drawings may indicate different steps of the operation of the charge pump circuit 600, respectively. The arrows with circled numbers in the accompanying drawings may indicate the current during a certain step of the operation of the charge pump circuit 600, respectively. The arrow toward the first capacitor C61 may indicate that the first capacitor C61 is charged, and the arrow away from the first capacitor C61 may indicate that the first capacitor C61 is discharged. In an embodiment, step 1 and step 3 may refer to step 1 and step 3 of the second embodiment, and the details are not redundantly described one by one herein. It should be noted that step 2 in the embodiment is not required due to the specified conditions of the threshold voltage of the first transistor T61 to the fourth transistor T64. That is, the third transistor T63 and the fourth transistor T64 are specified to provide a fourth transistor current I_T64 for compensation. In addition, the reset signal RES6 and the initialization signal INIT6 may be switched from a low voltage level to a high voltage level during the time period of step 1 and step 3, respectively. Therefore, during the time period of step 1, the first node N61 and the third node N63 can be reset to VH-|Vth61| by the second capacitor current I_C62, and the second node N62 can be reset to the reset voltage Vrst6 by the fifth transistor current I_T65. During the time period of step 3, the third node N63 can be initialized to the second reference voltage VL by the sixth transistor current I_T66, and the second node N62 can be initialized to VH-|Vth61|-|Vth62|.

[0178] During the time period of step 4, the input signal Vi6 may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C61 may maintain a constant value, the voltage of the first node N61 may change from VH-|Vth61| to V1-|Vth61|+Vin. However, since the first node N61 is electrically connected to the first end of the second transistor T62, the voltage value of the first node N61 may be constrained by the second transistor T62. That is, during the time period of step 4, the voltage value of the first node N61 may be maintained at VH-|Vth61| rather than VH-|Vth61|+Vin. The second transistor T62 may be turned on. Therefore, the additional charge Q may be discharged from the first capacitor C61 based on the voltage difference and may be equal to C61×Vin.

[0179] In an embodiment, the extra charge Q can be transferred from the first capacitor C61 to the second capacitor C62 through the second transistor current I_T62, and thus the second capacitor C62 can be charged. That is, the value of the output signal Vo6 can increase the value of the step voltage Vstep6, and the value of the step voltage Vstep6 can be equal to (C61 / C62)×Vin. Therefore, the value of the output signal Vo6 can increase from the second reference voltage VL to VL+Vstep6.

[0180] During the time period of step 5, the input signal Vi6 may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C61 may maintain a constant value, the voltage of the first node N61 may change from VH-|Vth61| to VH-|Vth61|-Vin. However, since the first node N61 is electrically connected to the second end of the first transistor T61, the voltage value of the first node N61 may be constrained by the first transistor T61. That is, during the time period of step 5, the voltage value of the first node N61 may be maintained at VH-|Vth61| rather than VH-|Vth61|-Vin, and the first transistor T61 may be turned on. Therefore, insufficient charge Q' may be charged into the first capacitor C61 by the first transistor current I_T61 based on the voltage difference and may be equal to (-Q).

[0181] It should be noted that the value of the output signal Vo6 can increase the value of the step voltage Vstep6 during step 4. That is, by repeating steps 4 and 5, the value of the output signal Vo4 can be increased to a plurality of different values. In addition, the plurality of different values ​​are proportional to the number of repetitions of steps 4 and 5. In other words, various waveforms can be output by the charge pump circuit 600, and the output is linear. Therefore, the charge pump circuit 600 can be used as a signal generator. In one embodiment, the charge pump circuit 600 can be used as a scan signal generator for a pixel of a display device to implement a scan signal generator in a pixel. In addition, since the structure of the charge pump circuit 600 is simple, the charge pump circuit 600 can be disposed on a substrate and thus a scan signal generator in a pixel can be implemented.

[0182] In an embodiment, the second transistor T62 is a P-type transistor, but the present disclosure is not limited thereto. In an embodiment, the second transistor T62 can provide a charging current (second transistor current I_T62) of the second capacitor C62, and thus the charge pump circuit 600 can be a boost circuit. In another embodiment, the second transistor T62 can be an N-type transistor, and thus a discharge current of the second capacitor C62 can be provided. Therefore, the charge pump circuit 600 can be changed into a buck circuit.

[0183] Figure 7is a schematic diagram of a charge pump circuit according to a modification of the third embodiment of the present disclosure. Figure 7 , Figure 6 and Figure 7 The main difference between the two is that the second transistor T62 of the charge pump circuit 600 is a P-type transistor and the second transistor T72 of the charge pump 700 is an N-type transistor. In an embodiment, the charge pump circuit 700 may include a first transistor T71, a second transistor T72, a first capacitor C71, and a second capacitor C72. These elements may be referred to as the charge pump circuit 100 and the details are not redundantly described one by one herein.

[0184] In an embodiment, the charge pump circuit 700 may further include a third transistor T73, a fourth transistor T74, a fifth transistor T75, a sixth transistor T76, and a third capacitor C73. In an embodiment, the third transistor T73 may have a first end and a second end. The first end of the third transistor T73 may be electrically connected to the second end of the fourth transistor T74. The third capacitor C73 may have a first end and a second end. The first end of the third capacitor C73 may be electrically connected to the control end of the second transistor T72. The fourth transistor T74 may have a first end and a second end. The fourth transistor T74 may be electrically connected between the control end of the second transistor T72 and the first end of the third transistor T73. The fifth transistor T75 may have a first end and a second end. The fifth transistor T75 may be electrically connected between the first end of the fourth transistor T74 and the second end of the third capacitor C73. The sixth transistor T76 may have a first end and a second end. The sixth transistor T76 may be electrically connected between the first end of the second capacitor C72 and the second end of the second capacitor C72.

[0185] In an embodiment, the second end of the first capacitor C71 may be indicated as a first node N71, the first end of the third capacitor C73 may be indicated as a second node N72, and the first end of the second capacitor C72 may be indicated as a third node N73. In an embodiment, the first transistor T71 may have a first threshold voltage Vth71, the second transistor T72 may have a second threshold voltage Vth72, the third transistor T73 may have a third threshold voltage Vth73, and the fourth transistor T74 may have a fourth threshold voltage Vth74. In an embodiment, the first threshold voltage Vth71 may be equal to the third threshold voltage Vth73, and the second threshold voltage Vth72 may be equal to the fourth threshold voltage Vth74, but the present disclosure is not limited thereto.

[0186] In an embodiment, the first end of the first transistor T71, the control end of the third transistor T73, and the second end of the third transistor T73 receive the second reference voltage VL. The second end of the second capacitor C72 receives the first reference voltage VH. The second end of the third capacitor C73 receives the reset voltage Vrst7. In an embodiment, the control end of the fifth transistor T75 may receive a reset signal RES7. The control end of the sixth transistor T76 may receive an initialization signal INIT7. In an embodiment, the first end of the first capacitor C71 may receive an input signal Vi7. The first end of the second capacitor C72 may provide an output signal Vo7.

[0187] In an embodiment, the arrows with circled numbers in the accompanying drawings may indicate the current during a certain step of the operation of the charge pump circuit 700, respectively. The arrow toward the first capacitor C71 may indicate that the first capacitor C71 is charged, and the arrow away from the first capacitor C71 may indicate that the first capacitor C71 is discharged. In an embodiment, steps 1 to 3 may refer to the time period of steps 1 to 3 of the second embodiment, and the details are not redundantly described one by one herein. It should be noted that step 2 in the embodiment is not required due to the specified conditions of the threshold voltages of the first transistor T71 to the fourth transistor T74. That is, the third transistor T73 and the fourth transistor T74 are specified to provide a fourth transistor current I_T74 for compensation. In addition, the reset signal RES7 and the initialization signal INIT7 may be switched from a high voltage level to a low voltage level during the time periods of steps 1 and 3, respectively. Therefore, during the time period of step 1, the first node N71 and the third node N73 can be reset to VL+|Vth71| by the second capacitor current I_C72, and the second node N72 can be reset to the reset voltage Vrst7 by the fifth transistor current I_T75. During the time period of step 3, the second node N72 can be initialized to VL+|Vth1|+|Vth2|.

[0188] During the time period of step 4, the input signal Vi7 may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C71 may maintain a constant value, the voltage of the first node N71 may change from VL+|Vth71| to VL+|Vth71|-Vin. However, since the first node N71 is electrically connected to the first end of the second transistor T72, the voltage value of the first node N71 may be constrained by the second transistor T72. That is, during step 4, the voltage value of the first node N71 may be maintained at VL+|Vth71| rather than VL+|Vth71|-Vin. The second transistor T72 may be turned on. Therefore, insufficient charge Q' may be charged into the first capacitor C71 based on the voltage difference. The value of insufficient charge Q' may be equal to C71×(-Vin).

[0189] In an embodiment, insufficient charge Q' may be transferred from the second capacitor C72 to the first capacitor C71 through the second transistor current I_T72 and thereby the second capacitor C72 may be discharged. That is, the value of the output signal Vo7 may be reduced by the value of the step voltage Vstep7, and the value of the step voltage Vstep7 may be equal to (C71 / C72)×Vin. Therefore, the value of the output signal Vo7 may be reduced from the first reference voltage VH to VH-Vstep7.

[0190] During the time period of step 5, the input signal Vi7 may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C71 may maintain a constant value, the voltage of the first node N71 may change from VL+|Vth71| to VL+|Vth71|+Vin. However, since the first node N71 is electrically connected to the second end of the first transistor T71, the voltage value of the first node N71 may be constrained by the first transistor T71. That is, during step 5, the voltage value of the first node N71 may be maintained at VL+|Vth71| instead of VL+|Vth71|+Vin, and the first transistor T71 may be turned on. Therefore, the additional charge Q may be discharged from the first capacitor C71 through the first transistor current I_T71 based on the voltage difference and may be equal to (-Q').

[0191] It should be noted that the value of the output signal Vo7 can reduce the value of the step voltage Vstep7 during the time period of step 4. That is, by repeating steps 4 and 5, the value of the output signal Vo7 can be reduced to a plurality of different values. In addition, the plurality of different values ​​are proportional to the number of repetitions of steps 4 and 5. In other words, various waveforms can be output by the charge pump circuit 700, and the output is linear. Therefore, the charge pump circuit 700 can be used as a signal generator. In one embodiment, the charge pump circuit 700 can be used as a scan signal generator for a pixel of a display device to implement a scan signal generator in a pixel. In addition, since the structure of the charge pump circuit 700 is simple, the charge pump circuit 700 can be disposed on a substrate and thus a scan signal generator in a pixel can be implemented.

[0192] Figure 8 is a schematic diagram of a charge pump circuit according to a fourth embodiment of the present disclosure. Figure 1 and Figure 8 , the charge pump circuit 800 may have a similar structure to the charge pump circuit 100. The charge pump circuit 800 may include a first transistor T81, a second transistor T82, a first capacitor C81, and a second capacitor C82. These elements may be referred to as the charge pump circuit 100 and the details are not redundantly described one by one herein.

[0193] In an embodiment, the charge pump circuit 800 may further include a third transistor T83, a fourth transistor T84, a fifth transistor T85, a sixth transistor T86, a seventh transistor T87, an eighth transistor T88, a ninth transistor T89 and a third capacitor C83. In an embodiment, the third transistor T83 may have a first end and a second end. The third transistor T83 may be electrically connected between the second end of the second transistor T82 and the first end of the second capacitor C82. The third capacitor C83 may have a first end and a second end. The first end of the third capacitor C83 may be electrically connected to the control end of the second transistor T82. The fourth transistor T84 may have a first end and a second end. The fourth transistor T84 may be electrically connected between the second end of the second transistor T82 and the first end of the third capacitor C83. The fifth transistor T85 may have a first end and a second end. The fifth transistor T85 may be electrically connected between the second end of the fourth transistor T84 and the second end of the third capacitor C83. The sixth transistor T86 may have a first end and a second end. The first end of the sixth transistor T86 may be electrically connected to the first end of the second capacitor C82. The seventh transistor T87 may have a first end and a second end. The second end of the seventh transistor T87 may be electrically connected to the second end of the sixth transistor T86. The eighth transistor T88 may have a first end and a second end. The first end of the eighth transistor T88 may be electrically connected to the second end of the seventh transistor T87. The ninth transistor T89 may have a first end and a second end. The first end of the ninth transistor T89 may be electrically connected to the second end of the eighth transistor T88.

[0194] In an embodiment, the second end of the first capacitor C81 may be indicated as a first node N81, the first end of the third capacitor C83 may be indicated as a second node N82, and the first end of the second capacitor C82 may be indicated as a third node N83. In an embodiment, the first transistor T81 may have a first threshold voltage Vth81, the second transistor T82 may have a second threshold voltage Vth82, and the eighth transistor T88 may have a third threshold voltage Vth83. In an embodiment, the first end of the first transistor T81 and the first end of the seventh transistor T87 receive a first reference voltage VH. The second end of the second capacitor C82 and the second end of the ninth transistor T89 receive a second reference voltage VL. The second end of the third capacitor C83 receives a reset voltage Vrst8.

[0195] In an embodiment, the control end of the fifth transistor T85 may receive a reset signal RES8. In an embodiment, the control end of the third transistor T83 and the control end of the fourth transistor T84 may receive a first compensation signal COMP81. The control end of the sixth transistor T86, the control end of the seventh transistor T87, and the control end of the ninth transistor T89 may receive a second compensation signal COMP82. In an embodiment, the first end of the first capacitor C81 may receive an input signal Vi8. The second end of the eighth transistor T88 may provide an output signal Vo8.

[0196] Fig. 9 is a schematic signal timing diagram of a charge pump circuit according to a fourth embodiment of the present disclosure. Figure 8 and Fig. 9 , the circled numbers in the accompanying drawings may respectively indicate different steps of the operation of the charge pump circuit 800. The arrows with circled numbers in the accompanying drawings may respectively indicate the current during a certain step of the operation of the charge pump circuit 800. The arrows toward the first capacitor C81 may indicate that the first capacitor C81 is charged, and the arrows away from the first capacitor C81 may indicate that the first capacitor C81 is discharged. In an embodiment, step 1 and step 2 may refer to step 1 and step 2 of the second embodiment, and the details are not redundantly described one by one herein. In an embodiment, the reset signal RES8, the first compensation signal COMP81, and the second compensation signal COMP82 may be switched from a low voltage level to a high voltage level during the time periods of step 1, step 2, and step 3, respectively. Therefore, during the time period of step 1, the first node N81 and the third node N83 can be reset to VH-|Vth81| by the second capacitor current I_C82, the second node N82 can be reset to the reset voltage Vrst8 by the fifth transistor current I_T85, and the output signal Vo8 can be reset to VH-|Vth81|-|Vth83| by the eighth transistor step one current I_T88_1. During the time period of step 2, the second node N82 can be compensated to VH-|Vth81|-|Vth82| by the fourth transistor current I_T84. During the time period of step 3, the third node N83 can be compensated to VL+|Vth83| by the sixth transistor current I_T86, and the output signal Vo8 can be compensated to the second reference voltage VL by the eighth transistor step three current I_T88_3 and the ninth transistor current I_T89.

[0197] During the time period of step 4, the input signal Vi8 may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C81 may maintain a constant value, the voltage of the first node N81 may change from VH-|Vth81| to VH-|Vth81|+Vin. However, since the first node N81 is electrically connected to the first end of the second transistor T82, the voltage value of the first node N81 may be constrained by the second transistor T82. That is, during the time period of step 4, the voltage value of the first node N81 may be maintained at VH-|Vth81|( Fig. 9 The solid line of N81 in the figure) rather than VH-|Vth81|+Vin( Fig. 9 The second transistor T82 and the third transistor T83 may be turned on. Therefore, the additional charge Q may be discharged from the first capacitor C81 based on the voltage difference and may be equal to C81×Vin.

[0198] In an embodiment, the extra charge Q can be transferred from the first capacitor C81 to the second capacitor C82 through the second transistor current I_T82 and the third transistor current I_T83, and thus the second capacitor C82 can be charged. In addition, the voltage value of the output signal Vo8 can be obtained by subtracting the third threshold voltage Vth83 from the voltage value of the third node N83. That is, the value of the output signal Vo8 can increase the value of the step voltage Vstep8, and the value of the step voltage Vstep8 can be equal to (C81 / C82)×Vin. Therefore, the value of the output signal Vo8 can be increased from the second reference voltage VL to VL+Vstep8 through the eighth transistor step four current I_T88_4.

[0199] During the time period of step 5, the input signal Vi8 may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C81 may maintain a constant value, the voltage of the first node N81 may change from VH-|Vth81| to VH-|Vth81|-Vin. However, since the first node N81 is electrically connected to the second end of the first transistor T81, the voltage value of the first node N81 may be constrained by the first transistor T81. That is, during the time period of step 5, the voltage value of the first node N81 may be maintained at VH-|Vth81| rather than VH-|Vth81|-Vin, and the first transistor T81 may be turned on. Therefore, insufficient charge Q' may be charged into the first capacitor C81 by the first transistor current I_T81 based on the voltage difference and may be equal to (-Q).

[0200] It should be noted that the value of the output signal Vo8 can increase the value of the step voltage Vstep8 during step 4. That is, by repeating steps 4 and 5, the value of the output signal Vo8 can be increased to a plurality of different values. In addition, the plurality of different values ​​are proportional to the number of repetitions of steps 4 and 5. In other words, various waveforms can be output by the charge pump circuit 800, and the output is linear. Therefore, the charge pump circuit 800 can be used as a signal generator. In one embodiment, the charge pump circuit 800 can be used as a scan signal generator for a pixel of a display device to implement a scan signal generator in a pixel. In addition, since the structure of the charge pump circuit 800 is simple, the charge pump circuit 800 can be placed on a substrate and thus a scan signal generator in a pixel can be implemented.

[0201] In an embodiment, the second transistor T82 is a P-type transistor, but the present disclosure is not limited thereto. In an embodiment, the second transistor T82 can provide a charging current (second transistor current I_T82) of the second capacitor C82, and thus the charge pump circuit 800 can be a boost circuit. In another embodiment, the second transistor T82 can be an N-type transistor, and thus a discharge current of the second capacitor C82 can be provided. Therefore, the charge pump circuit 800 can be changed into a buck circuit.

[0202] In an embodiment, Figure 3 and Figure 8 The difference between them is that the output signal Vo3 can be provided through the first end of the second capacitor C32, but the output signal Vo8 can be provided through the second end of the eighth transistor T88. That is, the output signal Vo8 can depend on the eighth transistor T88 instead of the capacitor.

[0203] Fig.10 is a schematic diagram of a charge pump circuit according to a modification of the fourth embodiment of the present disclosure. Figure 8 , Figure 8 and Fig.10 The main difference between the two is that the second transistor T82 of the charge pump circuit 800 is a P-type transistor and the second transistor T102 of the charge pump 1000 is an N-type transistor. In an embodiment, the charge pump circuit 1000 may include a first transistor T101, a second transistor T102, a first capacitor C101, and a second capacitor C102. These elements may be referred to as the charge pump circuit 100 and the details are not redundantly described one by one herein.

[0204] In an embodiment, the charge pump circuit 1000 may further include a third transistor T103, a fourth transistor T104, a fifth transistor T105, a sixth transistor T106, a seventh transistor T107, an eighth transistor T108, a ninth transistor T109 and a third capacitor C103. In an embodiment, the third transistor T103 may have a first end and a second end. The third transistor T103 may be electrically connected between the second end of the second transistor T102 and the first end of the second capacitor C102. The third capacitor C103 may have a first end and a second end. The first end of the third capacitor C103 may be electrically connected to the control end of the second transistor T102. The fourth transistor T104 may have a first end and a second end. The fourth transistor T104 may be electrically connected between the control end of the second transistor T102 and the first end of the third transistor T103. The fifth transistor T105 may have a first end and a second end. The fifth transistor T105 may be electrically connected between the second end of the fourth transistor T104 and the second end of the third capacitor C103. The sixth transistor T106 may have a first end and a second end. The first end of the sixth transistor T106 may be electrically connected to the first end of the second capacitor C102. The seventh transistor T107 may have a first end and a second end. The second end of the seventh transistor T107 may be electrically connected to the second end of the sixth transistor T106. The eighth transistor T108 may have a first end and a second end. The first end of the eighth transistor T108 may be electrically connected to the second end of the seventh transistor T107. The ninth transistor T109 may have a first end and a second end. The first end of the ninth transistor T109 may be electrically connected to the second end of the eighth transistor T108.

[0205] In an embodiment, the second end of the first capacitor C101 may be indicated as the first node N101, the first end of the third capacitor C103 may be indicated as the second node N102, and the first end of the second capacitor C102 may be indicated as the third node N103. In an embodiment, the first transistor T101 may have a first threshold voltage Vth101, the second transistor T102 may have a second threshold voltage Vth102, and the eighth transistor T108 may have a third threshold voltage Vth103. In an embodiment, the first end of the first transistor T101 and the first end of the seventh transistor T107 receive the second reference voltage VL. The second end of the second capacitor C102 and the second end of the ninth transistor T109 receive the first reference voltage VH. The second end of the third capacitor C103 receives the reset voltage Vrst10.

[0206] In an embodiment, the control terminal of the fifth transistor T105 may receive a reset signal RES10. In an embodiment, the control terminal of the third transistor T103 and the control terminal of the fourth transistor T104 may receive a first compensation signal COMP101. The control terminal of the sixth transistor T106, the control terminal of the seventh transistor T107, and the control terminal of the ninth transistor T109 may receive a second compensation signal COMP102. In an embodiment, the first terminal of the first capacitor C101 may receive an input signal Vi10. The first terminal of the eighth transistor T108 may provide an output signal Vo10.

[0207] In an embodiment, the circled numbers in the drawings may respectively indicate different steps of the operation of the charge pump circuit 1000. The arrows with the circled numbers in the drawings may respectively indicate the current flow during a certain step of the operation of the charge pump circuit 1000. The arrows toward the first capacitor C101 may indicate charging the first capacitor C101, and the arrows away from the first capacitor C101 may indicate discharging the first capacitor C101.

[0208] In an embodiment, step 1 and step 2 may refer to step 1 and step 2 of the second embodiment, and the details are not redundantly described one by one herein. In an embodiment, the reset signal RES10, the first compensation signal COMP101, and the second compensation signal COMP102 may be switched from a high voltage level to a low voltage level during the time periods of step 1, step 2, and step 3, respectively. Therefore, during the time period of step 1, the first node N101 and the third node N103 may be reset to VL+|Vth101| by the second capacitor current I_C102, the second node N102 may be reset to the reset voltage Vrst10 by the fifth transistor current I_T105, and the output signal Vo10 may be reset to VL+|Vth01|+|Vth103| by the eighth transistor step one current I_108_1. During the time period of step 2, the second node N102 may be compensated to VL+|Vth101|+|Vth102| by the fourth transistor current I_T104. During the step 3 period, the third node N103 may be compensated to VH-|Vth103| by the sixth transistor current I_T106, and the output signal may be compensated to the first reference voltage VH by the eighth transistor step three current I_T108_3 and the ninth transistor current I_T109.

[0209] During the time period of step 4, the input signal Vi10 may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C101 may maintain a constant value, the voltage of the first node N101 may change from VL+|Vth101| to V1+|Vth101|-Vin. However, since the first node N101 is electrically connected to the first end of the second transistor T102, the voltage value of the first node N101 may be constrained by the second transistor T102. That is, during step 4, the voltage value of the first node N101 may be maintained at VL+|Vth101| rather than VL+|Vth101|-Vin. The second transistor T102 and the third transistor T103 may be turned on. Therefore, insufficient charge Q may be charged into the first capacitor C101 based on the voltage difference and may be equal to C101×(-Vin).

[0210] In an embodiment, insufficient charge Q may be transferred from the second capacitor C102 to the first capacitor C101 through the second transistor current I_T102 and the third transistor current I_T103, and thereby the second capacitor C102 may be discharged. In addition, the voltage value of the output signal Vo10 may be obtained by adding the third threshold voltage Vth103 to the voltage value of the third node N103. That is, the value of the output signal Vo10 may be reduced by the value of the step voltage Vstep10, and the value of the step voltage Vstep10 may be equal to (C101 / C102)×Vin. Therefore, the value of the output signal Vo10 may be reduced from the second reference voltage VL to VL-Vstep10.

[0211] During the time period of step 5, the input signal Vi10 may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may also be the input voltage Vin. Since the voltage difference between the first end and the second end of the first capacitor C101 may maintain a constant value, the voltage of the first node N101 may change from VL+|Vth101| to VL+|Vth101|+Vin. However, since the first node N101 is electrically connected to the second end of the first transistor T101, the voltage value of the first node N101 may be constrained by the first transistor T101. That is, during the time period of step 5, the voltage value of the first node N101 may be maintained at VL+|Vth101| rather than VL+|Vth101|+Vin and the first transistor T101 may be turned on. Therefore, the additional charge Q' may be discharged from the first capacitor C101 through the first transistor current I_T101 based on the voltage difference and may be equal to (-Q).

[0212] It should be noted that the value of the output signal Vo10 can reduce the value of the step voltage Vstep10 during the time period of step 4. That is, by repeating steps 4 and 5, the value of the output signal Vo10 can be reduced to a plurality of different values. In addition, the plurality of different values ​​are proportional to the number of repetitions of steps 4 and 5. In other words, various waveforms can be output by the charge pump circuit 1000, and the output is linear. Therefore, the charge pump circuit 1000 can be used as a signal generator. In one embodiment, the charge pump circuit 1000 can be used as a scan signal generator for a pixel of a display device to implement a scan signal generator in a pixel. In addition, since the structure of the charge pump circuit 1000 is simple, the charge pump circuit 1000 can be disposed on a substrate and thus a scan signal generator in a pixel can be implemented.

[0213] Fig.11A is a schematic block diagram of a pixel circuit for an AM-LED display panel according to an embodiment of the present disclosure. Fig.11A , the pixel circuit 1100 may include a charge pump circuit 1103, a comparator 1104, a current generator 1105, a light emitting diode 1106, a capacitor 1102, and a scanning transistor 1101. In an embodiment, the current generator 1105 may receive a first reference voltage VDD. The capacitor 1102 may have a first end and a second end. The scanning transistor 1101 may have a first end and a second end. The first end of the capacitor 1102 may be electrically connected to the second end of the scanning transistor 1101. The second end of the capacitor 1102 may receive a second reference voltage VSS. The first end of the scanning transistor 1101 may be electrically connected to a data line Data(m) of a plurality of data lines. The control end of the scanning transistor 1101 may be electrically connected to a scanning line Scan(n) of a plurality of scanning lines. The comparator 1104 may have a positive terminal and a negative terminal. The second end of the scanning transistor 1101 may be electrically connected to the positive terminal of the comparator 1104 to provide pulse width modulation data D_PWM. The charge pump circuit 1103 can be electrically connected to the negative terminal of the comparator 1104 to provide the scan signal SW. The output terminal of the comparator 1104 can be electrically connected to the current generator 1105 to provide the emission control signal E_C. The light emitting diode 1106 can receive the second reference voltage VSS and be electrically connected to the current generator 1105.

[0214] Fig. 11B is a schematic signal timing diagram of a pixel circuit for an AM-LED display panel according to an embodiment of the present disclosure. Fig.11A and Fig. 11B, the comparator 1104 may be configured to output the emission control signal E_C according to the pulse width modulation data D_PWM and the scanning signal SW. In an embodiment, before the emission time period 1110, the comparator 1104 may be configured to output a low voltage level, while there is no input of the scanning signal SW. During the emission time period 1110, the comparator 1104 may be configured to output a high voltage level, while the value of the pulse width modulation data D_PWM is greater than the value of the scanning signal SW. After the emission time period 1110, the comparator 1104 may be configured to output a low voltage level, while the value of the pulse width modulation data D_PWM is less than the value of the scanning signal SW. In an embodiment, the scanning signal SW may be a linear signal that increases over time, and the linear signal may have a specific slope. In an embodiment, the charge pump circuit 1103 may be composed of Figure 1 , Figure 3 , Figures 5 to 8 as well as Fig.10 The charge pump circuit 1103 is implemented by one of the charge pump circuits 100, 300, 500, 600, 700, 800, and 1000 of the above embodiments. Therefore, the specific slope can be determined by the step voltage of the charge pump circuit 1103. Since the structure of the charge pump circuit 1103 is simple, the charge pump circuit 1103 can be disposed on the substrate of the AM-LED display panel and thus the in-pixel scan signal generator can be implemented.

[0215] Fig. 12A is a schematic block diagram of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure. Fig. 12A , a pixel circuit for a photon counting detector may include a photodetector 1201, a pulse shaper 1202, a first comparator 1203, a second comparator 1204, a first counter 1205, a second counter 1206, a first scanning transistor 1207, and a second transistor 1208. In an embodiment, the photodetector 1201 may be configured to detect light L and generate a photodetector current I_PD according to the light L. In an embodiment, the light L may be an X-ray for computer tomography, but the present disclosure is not limited thereto.

[0216] In an embodiment, the pulse shaper 1202 may be configured to generate an input signal 1210 based on the photodetector current I_PD. The first comparator 1203 may have a positive terminal and a negative terminal. The second comparator 1204 may have a positive terminal and a negative terminal. The positive terminal of the first comparator 1203 and the positive terminal of the second comparator 1204 may receive the input signal 1210. The negative terminal of the first comparator 1203 may receive the first reference signal Ref1. The negative terminal of the second comparator 1204 may receive the second reference signal Ref2. The first comparator 1203 may be configured to output a first comparison signal 1220 based on the input signal and the first reference signal Ref1. The second comparator 1204 may be configured to output a second comparison signal 1230 based on the input signal and the second reference signal Ref2.

[0217] In an embodiment, the first counter 1205 may be configured to output a first count signal 1240 according to the first comparison signal. The second counter 1206 may be configured to output a second count signal 1250 according to the second comparison signal. The first scan transistor 1207 may have a first end and a second end. The second scan transistor 1208 may have a first end and a second end. The control end of the first scan transistor 1207 may be electrically connected to a first scan line Scan1(n) of a plurality of scan lines. The control end of the second scan transistor 1208 may be electrically connected to a second scan line Scan2(n) of a plurality of scan lines. The second end of the first scan transistor 1207 and the second end of the second scan transistor 1208 may be electrically connected to a sense line Sense(m) of a plurality of sense lines.

[0218] Fig. 12B is an exemplary input signal of a comparator of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure. Fig. 12C is a schematic output signal of a comparator of a pixel circuit for a photon counting detector according to one embodiment of the present disclosure. Fig.12D is a schematic output signal of a counter of a pixel circuit for a photon counting detector according to an embodiment of the present disclosure. FIG. 12A to FIG. 12D , the pulse shaper 1202 may be configured to generate an input signal 1210 according to the photodetector current I_PD. The input signal 1210 may be compared with the first reference signal Ref1 by the first comparator 1203 to obtain a first comparison signal 1220. The input signal 1210 may be compared with the second reference signal Ref2 by the second comparator 1204 to obtain a second comparison signal 1230.

[0219] In an embodiment, the first comparator 1203 and the second comparator 1204 may respectively output a high voltage level, while the input signal 1210 is greater than the value of the first reference signal Ref1 or the second reference signal Ref2. The first comparator 1203 and the second comparator 1204 may respectively output a low voltage level, while the input signal 1210 is less than the value of the first reference signal Ref1 or the second reference signal Ref2.

[0220] In an embodiment, the peak value of the input signal 1210 has only one value greater than the value of the first reference signal Ref1. Therefore, the first comparison signal 1220 may include one square wave. In an embodiment, the peak value of the input signal 1210 has three values ​​greater than the value of the second reference signal Ref2. Therefore, the second comparison signal 1230 may include three square waves. That is, the number of square waves of the first comparison signal 1220 and the number of square waves of the second comparison signal 1230 are determined according to the input signal 1210, the first reference signal Ref1, and the second reference signal Ref2, respectively.

[0221] In an embodiment, the first counter 1205 and the second counter 1206 may be respectively Figure 1 , Figure 3 , Figures 5 to 8 as well as Fig.10 The pixel circuit 1200 is implemented in one of the charge pump circuits 100, 300, 500, 600, 700, 800, and 1000 of the above embodiments. The first counter 1205 may be configured to output a first counting signal 1240 according to the number of square waves of the first comparison signal 1220. The second counter 1206 may be configured to output a second counting signal 1250 according to the number of square waves of the second comparison signal 1230. Therefore, the pixel circuit 1200 may detect the number of photos of the light L, and may implement a light counting detector in a pixel.

[0222] Fig.13 is a schematic diagram of an arbitrary waveform generator according to an embodiment of the present disclosure. Fig.13, the arbitrary waveform generator 1300 may include a first up transistor T_U1, a second up transistor T_U2, a first down transistor T_D1, a second down transistor T_D2, a reset transistor T13r, a first up capacitor C1U, a first down capacitor C1D, and a second capacitor C132. In an embodiment, the first up transistor T_U1 may have a first end and a second end. The second up transistor T_U2 may have a first end and a second end. The first down transistor T_D1 may have a first end and a second end. The second down transistor T_D2 may have a first end and a second end. The reset transistor T13r may have a first end and a second end. The first up capacitor C1U may have a first end and a second end. The first down capacitor C1D may have a first end and a second end. The second capacitor C132 may have a first end and a second end.

[0223] In an embodiment, a first end of the first up-regulating capacitor C1U may receive an input up-regulating signal Viu. A second end of the first up-regulating capacitor C1U may be electrically connected to a second end of the first up-regulating transistor T_U1. A first end and a control end of the first up-regulating transistor T_U1 may receive a first reference voltage VH. A first end of the second up-regulating transistor T_U2 may be electrically connected to a second end of the first up-regulating transistor T_U1. A control end of the second up-regulating transistor T_U2 may receive a first reference voltage VH. A second end of the second up-regulating transistor T_U2 may be electrically connected to a first end of the second capacitor C132.

[0224] In an embodiment, a first end of the first down-regulation capacitor C1D may receive an input down-regulation signal Vid. A second end of the first down-regulation capacitor C1D may be electrically connected to a first end of the first down-regulation transistor T_D1. A second end and a control end of the first down-regulation transistor T_D1 may receive a second reference voltage VL. A first end of the second down-regulation transistor T_D2 may be electrically connected to a first end of the first down-regulation transistor T_D1. A control end of the second up-regulation transistor T_D2 may receive a second reference voltage VL. A second end of the second down-regulation transistor T_D2 may be electrically connected to a first end of a second capacitor C132. A first end of the second capacitor C132 may provide an output signal Vo13. In an embodiment, a first end of a reset transistor T13r may receive a reset voltage Vrst13. A control end of the reset transistor T13r may receive a reset signal RES13. A second end of the reset transistor T13r may provide an output signal Vo13.

[0225] refer to Figure 1 and Fig.13The first up-regulating transistor T_U1, the second up-regulating transistor T_U2, the reset transistor T13r, the first up-regulating capacitor C1U and the second capacitor C132 can form a boost circuit as Figure 1 The charge pump circuit 100 of FIG. 100 includes a first down-regulation transistor T_D1, a second down-regulation transistor T_D2, a reset transistor T13r, a first down-regulation capacitor C1D, and a second capacitor C132 that can form a step-down circuit. That is, the output signal Vo13 can include a plurality of boost signals and a plurality of step-down signals according to the input up-regulation signal Viu and the input down-regulation signal Vid. By changing the combination of the input up-regulation signal Viu and the input down-regulation signal Vid, various output signals Vo13 can be obtained. Therefore, the arbitrary waveform generator 1300 can output an arbitrary waveform.

[0226] In summary, according to the charge pump circuit disclosed in the present invention, through the above circuit design of the charge pump circuit, the charge pump can output multiple waveforms according to the input signal and the output of the charge pump is linear. In addition, since the structure of the charge pump circuit is simple, the charge pump circuit can be placed on the substrate of the AM-LED display panel, and thus the pixel scanning signal generator can be implemented.

[0227] It will be apparent to those skilled in the art that various modifications and variations of the disclosed embodiments may be made without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and variations of the present disclosure that fall within the scope of the appended claims and their equivalents.

Claims

1. A charge pump circuit, characterized in that: include: A first transistor having a first terminal and a second terminal; a first capacitor having a first end and a second end, wherein the second end of the first capacitor is electrically connected to the second end of the first transistor; a second transistor having a first terminal and a second terminal, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor; a second capacitor having a first end and a second end, wherein the first end of the second capacitor is electrically connected to the second end of the second transistor; A third transistor has a first terminal and a second terminal, a fourth transistor having a first terminal and a second terminal, wherein the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor; a fifth transistor having a first terminal and a second terminal, wherein the first terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor; and A third capacitor has a first end and a second end, wherein the first end of the third capacitor is electrically connected to the first end of the fifth transistor, and the second end of the third capacitor is electrically connected to the second end of the fifth transistor.

2. The charge pump circuit according to claim 1, characterized in that: The first end of the first capacitor receives an input signal.

3. The charge pump circuit according to claim 1, characterized in that: The first end of the second capacitor provides an output signal.

4. The charge pump circuit according to claim 1, characterized in that: Also includes: A reset transistor has a first terminal and a second terminal, wherein the first terminal of the reset transistor is electrically connected to the first terminal of the second capacitor, the second terminal of the reset transistor receives a reset voltage, and the control terminal of the reset transistor receives a reset signal.

5. The charge pump circuit according to claim 1, characterized in that: The first end of the first transistor is electrically connected to the control end of the first transistor.

6. The charge pump circuit according to claim 1, characterized in that: Also includes: A sixth transistor has a first terminal and a second terminal, wherein the first terminal of the sixth transistor is electrically connected to the first terminal of the second capacitor, and the second terminal of the sixth transistor is electrically connected to the second terminal of the second capacitor.

7. The charge pump circuit according to claim 6, characterized in that: The control terminal of the fifth transistor receives a reset signal. The control terminal of the sixth transistor receives an initialization signal.

8. The charge pump circuit according to claim 6, characterized in that: wherein the second terminal of the third transistor is electrically connected to the control terminal of the third transistor, The first terminal of the fourth transistor is electrically connected to the control terminal of the fourth transistor.

9. The charge pump circuit according to claim 6, characterized in that: wherein a threshold voltage of the first transistor is the same as a threshold voltage of the third transistor, The threshold voltage of the second transistor is the same as the threshold voltage of the fourth transistor.

10. A charge pump circuit, characterized in that: include: A first transistor having a first terminal and a second terminal; a first capacitor having a first end and a second end, wherein the second end of the first capacitor is electrically connected to the second end of the first transistor; a second transistor having a first terminal and a second terminal, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor; a second capacitor having a first end and a second end, wherein the first end of the second capacitor is electrically connected to the second end of the second transistor; a third transistor having a first terminal and a second terminal, wherein the third transistor is electrically connected between the second terminal of the second transistor and the first terminal of the second capacitor; a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is electrically connected to the control terminal of the second transistor; a fourth transistor having a first terminal and a second terminal, wherein the fourth transistor is electrically connected between the second terminal of the second transistor and the first terminal of the third capacitor; a fifth transistor having a first terminal and a second terminal, wherein the fifth transistor is electrically connected between the second terminal of the fourth transistor and the second terminal of the third capacitor; a sixth transistor having a first terminal and a second terminal, wherein the first terminal of the sixth transistor is electrically connected to the first terminal of the second capacitor; a seventh transistor having a first terminal and a second terminal, wherein the second terminal of the seventh transistor is electrically connected to the second terminal of the sixth transistor; an eighth transistor having a first terminal and a second terminal, wherein the first terminal of the eighth transistor is electrically connected to the second terminal of the seventh transistor; and A ninth transistor has a first terminal and a second terminal, wherein the first terminal of the ninth transistor is electrically connected to the second terminal of the eighth transistor.

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