High-frequency oscillator

Abstract

The invention discloses a high-frequency oscillator. A circuit of the high-frequency oscillator comprises a first current mirror branch, a second current mirror branch, a third current mirror branch and an overturning control unit, wherein the first current mirror branch comprises a first PMOS (P-channel Metal Oxide Semiconductor) switching tube and a current source; the second current mirror branch comprises a second PMOS switch tube, a first NMOS switch tube and a resistor; the third current mirror branch comprises a third PMOS switch tube, a second NMOS switch tube and a capacitor; the overturning control unit comprises a voltage detection unit, a first switch and a second switch. The voltage detection unit generates an oscillation clock signal and controls the opening and closing of the first switch and the second switch. As a high-performance comparator does not need to be used, the precision of the oscillation period is improved, and the manufacturing cost of a chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits, and in particular to a high-frequency oscillator. Background Art

[0002] With the development of integrated circuit technology, oscillators (OSC) are widely used as on-chip clock sources in various chips. They have the functions of system timing, system wake-up or network synchronization. In order to ensure accurate timing or synchronization, the error of the output oscillation frequency of the above oscillator should be controlled within a certain range and should not differ too much from the predetermined frequency.

[0003] like Figure 1 The oscillator circuit structure shown in the prior art is that a current source I charges a fixed capacitor C. When the capacitor C is charged to a preset value V of a comparator, ref When the value is reached, the comparator result flips and controls the switch SW to close, starting to discharge the capacitor. The total time of the entire charging and discharging is the oscillator period. Because the discharge is to ground through a switch with a very small on-resistance, the discharge time is very short and can be basically ignored. The period can be roughly calculated as T = C*V ref / I.

[0004] like Figure 2 As shown in the figure, when the frequency requirement of the oscillator is relatively high, the oscillator period is relatively short, and the comparator's offset voltage, gain factor and response speed have a greater impact on the oscillator period. ramp Equal to V ref When the comparator is turned on, the offset voltage, gain factor and response speed of the comparator will cause the comparator to fail to flip immediately. The resulting time difference will cause the oscillator period error to become larger. Figure 2 Medium time T d The expected period T p The actual period T p 'The error value between.

[0005] It can be seen that an oscillator with better accuracy is needed in the prior art to meet the requirements of high-frequency oscillation period. Summary of the invention

[0006] The present invention provides a high-frequency oscillator, which can achieve a higher-precision and better high-frequency oscillation period and avoid the use of a high-frequency comparator to save chip manufacturing costs.

[0007] Based on the above technical purpose, the present invention provides a high-frequency oscillator, wherein the high-frequency oscillator circuit includes a first current mirror branch, a second current mirror branch, a third current mirror branch and a flip control unit;

[0008] Wherein, the first current mirror branch includes a first PMOS switch tube and a current source; the second current mirror branch includes a second PMOS switch tube, a first NMOS switch tube and a resistor; the third current mirror branch includes a third PMOS switch tube, a second NMOS switch tube and a capacitor; the flip control unit includes a voltage detection unit, a first switch and a second switch;

[0009] The source of the first PMOS switch tube is connected to the external power supply VDD, the drain of the first PMOS switch tube is connected to one end of the current source, and the other end of the current source is grounded; the gate of the first PMOS switch tube is connected to the gate of the second PMOS switch tube;

[0010] The source of the second PMOS switch tube is connected to the external power supply VDD, the drain of the second PMOS switch tube is connected to the drain of the first NMOS switch tube, and the voltage value of the source of the first NMOS switch tube is stabilized at a predetermined voltage value;

[0011] The source of the third PMOS switch tube is connected to the external power supply VDD, the drain of the third PMOS switch tube is connected to the drain of the second NMOS switch tube, the source of the second NMOS switch tube is connected to one end of the capacitor, and the other end of the capacitor is grounded; the gate of the third PMOS switch tube is connected to the gate of the first PMOS switch tube and the gate of the second PMOS switch tube;

[0012] The gate of the first NMOS switch tube is connected to the gate of the second NMOS switch tube, and the gate and drain of the first NMOS switch tube 21 are short-circuited;

[0013] The first switch is connected between the drain of the second NMOS switch tube and the ground, and the second switch is connected between the source of the second NMOS switch tube and the ground; the input end of the voltage detection unit is connected to the drain of the second NMOS switch tube, and the output end of the voltage detection unit controls the opening and closing states of the first switch and the second switch; the oscillation clock signal is output by the output end of the voltage detection unit.

[0014] In one embodiment, the voltage detection unit is a two-stage inverter structure or a single-ended amplifier structure.

[0015] Compared with the prior art, one or more embodiments of the present invention may have the following advantages:

[0016] The high-frequency oscillator circuit of the present invention avoids the use of a so-called voltage flip trigger judgment mechanism of a comparator, so that the comparator's own bias voltage offset, gain coefficient and response speed factors no longer become constraints on generating an accurate oscillation clock. In addition, since a high-performance comparator is not used, the chip manufacturing cost can be significantly reduced.

[0017] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0019] Figure 1 It is a schematic diagram of the structure of a high-frequency oscillator circuit in the prior art;

[0020] Figure 2 It is a schematic diagram of the oscillation cycle timing formed by a high-frequency oscillator circuit in the prior art;

[0021] Figure 3 It is a schematic diagram of the high-frequency oscillator circuit structure of the present invention;

[0022] Figure 4 It is a schematic diagram of the oscillation cycle timing of the high-frequency oscillator circuit of the present invention;

[0023] Figure 5 It is a schematic diagram of the circuit structure of a voltage detection unit in the high-frequency oscillator circuit of the present invention. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0025] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0026] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0027] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] Example 1

[0029] like Figure 3-4As shown, the high-frequency oscillator circuit of the present invention includes a first current mirror branch 1 , a second current mirror branch 2 , a third current mirror branch 3 and a flip control unit 4 .

[0030] Among them, the first current mirror branch 1 includes a first PMOS switch tube 10 and a current source 11; the second current mirror branch 2 includes a second PMOS switch tube 20, a first NMOS switch tube 21 and a resistor 22; the third current mirror branch 3 includes a third PMOS switch tube 30, a second NMOS switch tube 31 and a capacitor 32; the flip control unit 4 includes a voltage detection unit 40, a first switch 41 and a second switch 42.

[0031] The source of the first PMOS switch tube 10 is connected to the external power supply VDD, the drain of the first PMOS switch tube 10 is connected to one end of the current source 11, and the other end of the current source 11 is grounded. The gate of the first PMOS switch tube 10 is connected to the gate of the second PMOS switch tube 20.

[0032] The source of the second PMOS switch tube 20 is connected to the external power supply VDD, the drain of the second PMOS switch tube 20 is connected to the drain of the first NMOS switch tube 21, the source of the first NMOS switch tube 21 is connected to one end of the resistor 22, and the other end of the resistor 22 is grounded.

[0033] The source of the third PMOS switch tube 30 is connected to the external power supply VDD, the drain of the third PMOS switch tube 30 is connected to the drain of the second NMOS switch tube 31, the source of the second NMOS switch tube 31 is connected to one end of the capacitor 32, and the other end of the capacitor 32 is grounded. The gate of the third PMOS switch tube 30 is connected to the gate of the first PMOS switch tube 10 and the gate of the second PMOS switch tube 20.

[0034] The gate of the first NMOS switch tube 21 is connected to the gate of the second NMOS switch tube 31 , and the gate and drain of the first NMOS switch tube 21 are short-circuited.

[0035] The first switch 41 is connected between the drain of the second NMOS switch tube 31 and the ground, and the second switch 42 is connected between the source of the second NMOS switch tube 31 and the ground. The input end of the voltage detection unit 40 is connected to the drain of the second NMOS switch tube 31, and the output end of the voltage detection unit 40 controls the on / off state of the first switch 41 and the second switch 42. At the same time, the output end of the voltage detection unit 40 outputs an oscillation clock signal.

[0036] In the oscillator circuit of this embodiment, the currents of the first current mirror branch 1 , the second current mirror branch 2 and the third current mirror branch 3 are all current source currents I. When the first current mirror branch 1, the second current mirror branch 2 and the third current mirror branch 3 are all turned on, the third current mirror branch 3 charges the capacitor C. When the source voltage Vb of the second NMOS switch tube 31 is less than the source voltage Va of the first NMOS switch tube 21, the capacitor C is charged with the current I. At this time, the second NMOS switch tube 31 operates in the linear region, and its voltage difference is small. The drain voltage Vr of the second NMOS switch tube 31 is approximately equal to the source voltage Vb. When the source voltage Vb of the second NMOS switch tube 31 increases to the source voltage Va of the first NMOS switch tube 21, the source voltage Vb of the second NMOS switch tube 31 will be clamped to the voltage value of the source voltage Va of the first NMOS switch tube 21 (because the gate of the second NMOS switch tube 31 is clamped), and the drain voltage Vr of the second NMOS switch tube 31 will be quickly charged (the current is shunted to the voltage detection unit 40). When the drain voltage Vr of the second NMOS switch tube 31 quickly increases, the output of the subsequent voltage detection unit 40 will immediately flip, and the drain voltage Vr of the second NMOS switch tube 31 and the source voltage Vb of the second NMOS switch tube 31 will be quickly discharged to the ground through the closing and conduction of the first switch 41 and the second switch 42.

[0037] In this embodiment, the flip threshold V ref 'It only needs to be greater than the set flip voltage V ref It can be done. Since the slope of the second stage charging is very large, the change of the threshold of the subsequent level detection circuit has little effect on the cycle accuracy. Figure 4 shown.

[0038] Since the drain voltage Vr of the second NMOS switch tube 31 is relatively large over the driving voltage, the amplification factor of the level detection circuit can be made relatively small, for example, a two-stage inverter or a simple single-ended amplifier can be used. Figure 5 As shown, a high-performance comparator implementation is not required.

[0039] In the present invention, the resistor 22 may be replaced by other devices capable of achieving voltage clamping or voltage stabilization, as long as the source voltage Va is stabilized at a predetermined voltage, the requirements of the present invention can be met.

[0040] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A high frequency oscillator, characterized in that: The high-frequency oscillator circuit comprises a first current mirror branch, a second current mirror branch, a third current mirror branch and a flip control unit; Wherein, the first current mirror branch includes a first PMOS switch tube and a current source; the second current mirror branch includes a second PMOS switch tube, a first NMOS switch tube and a resistor; the third current mirror branch includes a third PMOS switch tube, a second NMOS switch tube and a capacitor; the flip control unit includes a voltage detection unit, a first switch and a second switch; The source of the first PMOS switch tube is connected to the external power supply VDD, the drain of the first PMOS switch tube is connected to one end of the current source, and the other end of the current source is grounded; the gate of the first PMOS switch tube is connected to the gate of the second PMOS switch tube; The source of the second PMOS switch tube is connected to the external power supply VDD, the drain of the second PMOS switch tube is connected to the drain of the first NMOS switch tube, and the voltage value of the source of the first NMOS switch tube is stabilized at a predetermined voltage value; The source of the third PMOS switch tube is connected to the external power supply VDD, the drain of the third PMOS switch tube is connected to the drain of the second NMOS switch tube, the source of the second NMOS switch tube is connected to one end of the capacitor, and the other end of the capacitor is grounded; the gate of the third PMOS switch tube is connected to the gate of the first PMOS switch tube and the gate of the second PMOS switch tube; The gate of the first NMOS switch tube is connected to the gate of the second NMOS switch tube, and the gate and drain of the first NMOS switch tube 21 are short-circuited; The first switch is connected between the drain of the second NMOS switch tube and the ground terminal, and the second switch is connected between the source of the second NMOS switch tube and the ground terminal; the input end of the voltage detection unit is connected to the drain of the second NMOS switch tube, and the output end of the voltage detection unit controls the opening and closing states of the first switch and the second switch; the oscillation clock signal is output by the output end of the voltage detection unit.

2. The high frequency oscillator according to claim 1, characterized in that: The voltage detection unit is a two-stage inverter structure or a single-ended amplifier structure.

Images