Constant transconductance input stage circuit for operational amplifier

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a constant transconductance input stage circuit for an operational amplifier, which comprises a segmented tail current compensation circuit, an NMOS (N-channel Metal Oxide Semiconductor) differential input pair and a PMOS (P-channel Metal Oxide Semiconductor) differential input pair, wherein the segmented tail current compensation circuit comprises an NMOS (N-channel Metal Oxide Semiconductor) tail current compensation circuit and a PMOS (P-channel Metal Oxide Semiconductor) tail current compensation circuit; wherein the NMOS tail current compensation circuit is used for providing different compensation currents when the PMOS differential input pair is located in a sub-threshold region and a cut-off region, and the PMOS tail current compensation circuit is used for providing different compensation currents when the NMOS differential input pair is located in the sub-threshold region and the cut-off region. According to the invention, a segmented tail current compensation mode is adopted, different compensation currents are provided when a sub-threshold region and a cut-off region of work of the geminate transistor are input, so that transconductance of the sub-threshold region and the cut-off region can be effectively and properly compensated, the problem of poor transconductance stability of a triple current mirror method in the sub-threshold region is solved, and the stability of the transconductance of the geminate transistor is improved. And better transconductance stability can be realized in a full input range.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a constant transconductance input stage circuit for an operational amplifier. Background Art

[0002] In single-ended to differential applications, the fully differential operational amplifier needs to have a constant transconductance over a wide input range to meet the linearity requirements in wide input scenario applications.

[0003] At present, the existing traditional rail-to-rail input stage structure without constant transconductance is as follows Figure 1 As shown, it is mainly composed of two complementary NMOS (N-channel metal oxide semiconductor FET, N-channel metal oxide semiconductor field effect transistor) and PMOS (P-channel metal oxide semiconductor FET, P-channel metal oxide semiconductor field effect transistor) differential pairs; specifically, when the input common mode voltage V CM At the power supply voltage V DD / 2, the two differential pairs work simultaneously, and the input transconductance is the sum of the transconductances of the NMOS and PMOS input tubes; when the input common-mode voltage V CM When close to the power supply or ground, only one type of differential pair works, and only one type of input tube provides transconductance. The change curve of input transconductance is as follows: Figure 2 As shown, the total input transconductance presents an intermediate V DD The transconductance near / 2 is twice the transconductance near the power supply or ground on both sides, and the input transconductance changes greatly within the full input range.

[0004] In order to keep the input transconductance constant over the entire input range, the traditional triple current mirror method constant transconductance input stage structure is as follows: Figure 3 As shown; among them, M 7 and M 8 To compensate the current control tube, V s1 and V s2 is the control voltage, M 9 ~M 12 is a compensation current mirror; when the input common-mode voltage V CM When close to the power supply or ground, the input transconductance is increased to twice the original value through the action of the triple compensation current mirror, so that the input transconductance is constant within the full input common mode range; Figure 4 The input transconductance variation curve obtained by using the triple current mirror method is shown. Figure 4 It can be seen from the figure that in the subthreshold region, the transconductance varies greatly; in the subthreshold region, the tail current source M 5 and M 6 Both are in the linear region, with M6 For example, the current I p for:

[0005]

[0006] In the formula, K p =μ p C ox W p / L p , μ p is the hole mobility, C ox is the gate oxide capacitance, W p , L p is the width and length of the PMOS conductive channel; V GS6 and V DS6 They are PMOS tube M 6 The gate-source voltage and drain-source voltage, V THP is the threshold voltage of the PMOS tube;

[0007] From the above formula, we can see that I p It is a M 6 The drain-source voltage V DS6 is a quadratic function of the variable;

[0008] Current control tube M 8 The current I s1 for:

[0009]

[0010] Where V GS8 and V s1 They are PMOS tube M 8 The gate-source voltage and control voltage;

[0011] From the above formula, we can see that I s1 The same is a V DS6 is a quadratic function of the variable, but the polarity of the coefficients of the function is the same as I p on the contrary;

[0012] When the PMOS input pair works in the subthreshold region, the total transconductance of the input stage is:

[0013]

[0014] In the formula, I n For the input pipe M 1 and M 2 The total current flowing, V dsatn is its saturated drain-source voltage; ζ>1, which is a non-ideal factor; thermal voltage V T =kT / q, k is the Boltzmann constant, q is the electron charge, and T represents the absolute temperature.

[0015] In summary, the total transconductance in the subthreshold region is composed of the NMOS saturation region transconductance, the compensation transconductance and the PMOS subthreshold region transconductance, where the saturation region transconductance remains constant, and the compensation transconductance and subthreshold region transconductance are respectively composed of I s1 and I p However, in order to compensate for the total transconductance in the cut-off region, the triple current mirror method makes the current I s1 The change is too large, resulting in excessive change in the compensation transconductance, causing overcompensation of the total transconductance in the subthreshold region. Summary of the invention

[0016] The purpose of the present invention is to provide a constant transconductance input stage circuit for an operational amplifier to solve one or more of the above-mentioned technical problems. In the technical solution provided by the present invention, a segmented tail current compensation method is adopted to provide different compensation currents in the subthreshold region and the cut-off region of the input pair tube, so that the transconductance in the subthreshold region and the cut-off region can be effectively and appropriately compensated; the technical solution of the present invention overcomes the technical problem of poor transconductance stability in the subthreshold region of the existing triple current mirror method, and can achieve better transconductance stability in the full input range.

[0017] In order to achieve the above object, the present invention adopts the following technical solutions:

[0018] The present invention provides a constant transconductance input stage circuit for an operational amplifier, comprising: a segmented tail current compensation circuit and a complementary NMOS differential input pair and a PMOS differential input pair; wherein:

[0019] The segmented tail current compensation circuit includes two parts: an NMOS tail current compensation circuit and a PMOS tail current compensation circuit; wherein the NMOS tail current compensation circuit is used to provide different compensation currents when the PMOS differential input pair is in the subthreshold region and the cut-off region, and the PMOS tail current compensation circuit is used to provide different compensation currents when the NMOS differential input pair is in the subthreshold region and the cut-off region.

[0020] A further improvement of the present invention is that

[0021] The NMOS differential input pair includes: NMOS tube M 1 and NMOS tube M 2 ;

[0022] The PMOS differential input pair includes: a PMOS tube M 3 And PMOS tube M 4 ;

[0023] The NMOS tail current compensation circuit comprises: an NMOS tube M 5 、NMOS tube M11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、PMOS tube M 8 And PMOS tube M 10 ;

[0024] The PMOS tail current compensation circuit comprises: a PMOS tube M 6 、PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 、NMOS tube M 7 and NMOS tube M 9 ;

[0025] in,

[0026] PMOS tube M 6 、PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 The source of NMOS tube M is connected to the power supply. 5 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 The source is grounded;

[0027] PMOS tube M 18 The gate, drain and PMOS tube M 17 The gates of the PMOS tube M are connected to form a current mirror. 16 The gate, drain and PMOS tube M 15 The gates of the PMOS tube M are connected to form a current mirror; 18 The drain of NMOS tube M 9 The drain of PMOS tube M 16 The drain of NMOS tube M 7 The drain of NMOS tube M 7 The gate is connected to the bias voltage V s2 , NMOS tube M 9 The gate is connected to the bias voltage V s4 , PMOS tube M 6 The gate is connected to the bias voltage V b2 ;

[0028] PMOS tube M 6 、PMOS tube M 15 、PMOS tube M 17The drain of the PMOS tube M 3 、PMOS tube M 4 、PMOS tube M 8 、PMOS tube M 10 The source of NMOS tube M 1 The gate and PMOS tube M 3 The gate is connected to the positive input V in , NMOS tube M 2 The gate and PMOS tube M 4 The gate is connected to the negative input V ip ; NMOS tube M 1 、NMOS tube M 2 、PMOS tube M 3 、PMOS tube M 4 The drain of is the output node;

[0029] NMOS tube M 1 、NMOS tube M 2 、NMOS tube M 7 、NMOS tube M 9 The source of NMOS tube M 5 、NMOS tube M 11 、NMOS tube M 13 The drain of NMOS tube M 5 The gate is connected to the bias voltage V b1 , PMOS tube M 8 The gate is connected to the bias voltage V s1 , PMOS tube M 10 The gate is connected to the bias voltage V s3 , PMOS tube M 8 The drain of NMOS tube M 12 The drain of PMOS tube M 10 The drain of NMOS tube M 14 The drain of NMOS tube M 12 The gate, drain and NMOS tube M 11 The gates of the NMOS tube M are connected to form a current mirror. 14 The gate, drain and NMOS tube M 13 The gates of the two terminals are connected to form a current mirror.

[0030] A further improvement of the present invention is that

[0031] NMOS tube M 11 The current of NMOS tube M 12 K 1 times, NMOS tube M 13 The current of NMOS tube M 14 K 3 times;

[0032] Among them, through the NMOS tube M 11 Copy k 1 NMOS tube M 12 The current provides PMOS tube M 3 And PMOS tube M 4 Compensation current working in the subthreshold region; through NMOS tube M 13 Copy k 3 NMOS tube M 14 The current provides PMOS tube M 3 And PMOS tube M 4 Compensation current working in the cut-off region.

[0033] A further improvement of the present invention is that

[0034] PMOS tube M 15 The current of PMOS tube M 16 K 2 times, PMOS tube M 17 The current of PMOS tube M 18 K 4 times;

[0035] Among them, through the PMOS tube M 15 Copy k 2 PMOS tube M 16 The current provides NMOS tube M 1 and NMOS tube M 2 Compensation current working in the subthreshold region; through the PMOS tube M 17 Copy k 4 PMOS tube M 18 The current provides NMOS tube M 1 and NMOS tube M 2 Compensation current working in the cut-off region.

[0036] A further improvement of the present invention is that

[0037] NMOS tube M 11 The width of NMOS tube M 12 K 1 times, NMOS tube M 13 The width of NMOS tube M 14 K 3 times, NMOS tube, M 5 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 The same length.

[0038] A further improvement of the present invention is that

[0039] PMOS tube M 15 The width of the PMOS tube M 16 K 2 times, PMOS tube M 17 The width of the PMOS tube M 18 K 4 times, PMOS tube M 6 、PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 The same length.

[0040] A further improvement of the present invention is that

[0041] PMOS tube M 8 The size and bias voltage V s1 It can make the PMOS tube M when the PMOS differential input pair is in the subthreshold region 8 Conductivity.

[0042] A further improvement of the present invention is that

[0043] PMOS tube M 10 The size and bias voltage V s3 It can make the PMOS tube M when the PMOS differential input pair is in the cut-off region 10 Conductivity.

[0044] A further improvement of the present invention is that

[0045] NMOS tube M 7 The size and bias voltage V s2 It can make the NMOS transistor M when the NMOS differential input pair is in the subthreshold region 7 Conductivity.

[0046] A further improvement of the present invention is that

[0047] NMOS tube M 9 The size and bias voltage V s4 It can make the NMOS tube M when the NMOS differential input pair is in the cut-off region 9 Conductivity.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] In view of the problem that the existing triple current mirror method has poor transconductance stability in the subthreshold region, the present invention discloses a constant transconductance input stage circuit for an operational amplifier, which adopts a segmented tail current compensation method to provide different compensation currents when the input pair tube works in the subthreshold region and the cutoff region; when the input pair tube works in the subthreshold region, the transconductance generated by the compensation current changes with the drain-source voltage of the tail current source tube, and is opposite to the input transconductance change trend in the subthreshold region, thereby achieving effective compensation; in the cutoff region, since the tail current source current is constant, the compensation transconductance remains unchanged, and its value is equal to the input transconductance that decreases from the saturation region to the cutoff region, thereby achieving effective compensation. In summary, the improved technical means of the technical solution of the present invention can provide adaptive compensation transconductance when the input pair tube works in different regions, so that the transconductance in the subthreshold region and the cutoff region can be effectively and appropriately compensated, thereby achieving better transconductance stability in the full input range. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below; obviously, the drawings described below are some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 It is a schematic diagram of a structure without a constant transconductance input stage in the prior art;

[0052] Figure 2 It is a schematic diagram of the input transconductance variation curve without a constant transconductance structure in the prior art;

[0053] Figure 3 It is a schematic diagram of the structure of a constant transconductance input stage using a triple current mirror method in the prior art;

[0054] Figure 4 It is a schematic diagram of the input transconductance variation curve of the triple current mirror method in the prior art;

[0055] Figure 5 is a schematic diagram of a constant transconductance input stage circuit for an operational amplifier in an embodiment of the present invention;

[0056] Figure 6 1 is a schematic diagram of a curve of input transconductance variation of segmented tail current compensation in an embodiment of the present invention;

[0057] Figure 7 It is a schematic diagram comparing the simulation verification results of the total input transconductance of the circuit disclosed in the embodiment of the present invention and the circuit without a constant transconductance structure and a triple current mirror in the prior art. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments and technical solutions are only part of the embodiments of the present invention, not all of the embodiments.

[0059] All other embodiments obtained by those of ordinary skill in the art without creative work based on the technical solutions disclosed in the embodiments of the present invention belong to the scope of protection of the present invention. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] See also Figure 5 The embodiment of the present invention discloses a constant transconductance input stage circuit for an operational amplifier, specifically a constant transconductance input stage structure with segmented tail current compensation, which comprises: a complementary NMOS differential input pair (NMOS tube M 1 、NMOS tube M 2 ) and PMOS differential input pair (PMOS tube M 3 、PMOS tube M 4 ) and a segmented tail current compensation circuit; wherein,

[0061] The segmented tail current compensation circuit includes two parts: an NMOS tail current compensation circuit and a PMOS tail current compensation circuit; the NMOS tail current compensation circuit is used to provide different compensation currents when the PMOS differential input pair is in the subthreshold region and the cut-off region, and the PMOS tail current compensation circuit is used to provide different compensation currents when the NMOS differential input pair is in the subthreshold region and the cut-off region.

[0062] Explanatory, in the technical solution of the embodiment of the present invention, the NMOS differential input pair (M 1 、M 2 ) and PMOS differential input pair (M 3 、M 4 ) is used as a basic complementary differential input pair circuit to receive input signals; based on the segmented tail current compensation circuit, through the segmented compensation mechanism, the input transconductance can be kept constant within the full input common mode range.

[0063] In the specific technical solution of the embodiment of the present invention, the NMOS tail current compensation circuit is used to compensate the tail current of the NMOS differential input pair, including a PMOS current control tube (PMOS tube M 8 、M 10) and NMOS compensation current mirror (NMOS tube M 11 ~M 14 ); a PMOS tail current compensation circuit for compensating the tail current of the PMOS differential input pair, including an NMOS current control tube (NMOS tube M 7 、M 9 ) and PMOS compensation current mirror (PMOS tube M 15 ~M 18 );in,

[0064] PMOS tube M 6 、M 15 ~M 18 The source of NMOS tube M is connected to the power supply. 5 、M 11 ~M 14 The source of the PMOS tube M is grounded; 18 The gate and drain of the PMOS tube M 17 The gates of the PMOS tube M are connected to form a current mirror. 16 The gate and drain of the PMOS tube M 15 The gates of the PMOS tube M are connected to form a current mirror; 18 The drain of NMOS tube M 9 The drain of PMOS tube M 16 The drain of NMOS tube M 7 The drain of NMOS tube M 7 The gate is connected to the bias voltage V s2 , NMOS tube M 9 The gate is connected to the bias voltage V s4 , PMOS tube M 6 The gate is connected to the bias voltage V b2 ; PMOS tube M 6 、M 15 、M 17 The drain of the PMOS tube M 3 、M 4 、M 8 、M 10 The source of NMOS tube M 1 The gate and PMOS tube M 3 The gate is connected to the positive input V in , NMOS tube M 2 The gate and PMOS tube M 4 The gate is connected to the negative input V ip , NMOS tube M 1 、M 2 And PMOS tube M 3 、M 4 The drain of NMOS tube M is the output node; 1 、M 2、M 7 、M 9 The source of NMOS tube M 5 、M 11 、M 13 The drain of NMOS tube M 5 The gate is connected to the bias voltage V b1 , PMOS tube M 8 The gate is connected to the bias voltage V s1 , PMOS tube M 10 The gate is connected to the bias voltage V s3 , PMOS tube M 8 The drain of NMOS tube M 12 The drain of PMOS tube M 10 The drain of NMOS tube M 14 The drain of NMOS tube M 12 The gate and drain of NMOS tube M 11 The gates of the NMOS tube M are connected to form a current mirror. 14 The gate and drain of NMOS tube M 13 The gates of the two terminals are connected to form a current mirror.

[0065] In the preferred technical solution of the embodiment of the present invention, the NMOS tube M 11 The current of NMOS tube M 12 K 1 times, NMOS tube M 13 The current of NMOS tube M 14 K 3 times. PMOS tube M 15 The current of PMOS tube M 16 K 2 times, PMOS tube M 17 The current of PMOS tube M 18 K 4 times. NMOS tube M 11 The width W is the width of the NMOS tube M 12 K 1 times, NMOS tube M 13 The width W is the width of the NMOS tube M 14 K 3 times, NMOS tube M 5 、M 11 ~M 14 The length L is the same as that of the PMOS tube M 15 The width W is the width of the PMOS tube M 16 K 2 times, PMOS tube M 17 The width W is the width of the PMOS tube M 18 K 4 times, PMOS tube M6 、M 15 ~M 18 The length L is the same.

[0066] In the embodiment of the present invention, by adjusting the PMOS tube M 8 The size and bias voltage V s1 When the PMOS differential input pair is in the subthreshold region, the PMOS tube M 8 By adjusting the PMOS tube M 10 The size and bias voltage V s3 When the PMOS differential input pair is in the cut-off region, the PMOS tube M 10 By adjusting the NMOS tube M 7 The size and bias voltage V s2 When the NMOS differential input pair is in the subthreshold region, the NMOS tube M 7 By adjusting the NMOS tube M 9 The size and bias voltage V s4 When the NMOS differential input pair is in the cut-off region, the NMOS tube M 9 Conductivity.

[0067] See also Figures 5 to 7 , a principle explanation of the technical solution of an embodiment of the present invention, the constant transconductance input stage circuit disclosed in the embodiment of the present invention includes a basic complementary differential input pair circuit, an NMOS tail current compensation circuit, and a PMOS current source compensation circuit.

[0068] In the basic complementary differential input pair, the input NMOS tube M 1 And PMOS tube M 3 The gate is connected to the positive input V in , input NMOS tube M 2 And PMOS tube M 4 The gate is connected to the negative input V ip ; Input NMOS tube M 1 、M 2 And PMOS tube M 3 、M 4 The drain of the PMOS tail current source tube M is the output node; 6 The drain of the input PMOS tube M 3 、M 4 The source of the b2 , NMOS tail current source tube M 5 The drain of the input NMOS tube M 1 、M 2 The source of the b1 .

[0069] In the NMOS tail current compensation circuit, the PMOS current control tube M 8 The gate is connected to the bias voltage V s1 , its drain is connected to NMOS tube M 12 The drain of the PMOS current control tube M 10 The gate is connected to the bias voltage V s3 , its drain is connected to NMOS tube M 14 The drain of both is connected to the source of the PMOS tail current source tube M 6 The drain and input PMOS tube M 3 、M 4 The source of the PMOS tail current source tube M is used to control the extraction 6 Current; NMOS tube M 12 The gate and drain of NMOS tube M 11 The gates of the two electrodes are connected to form a current mirror with a current replication ratio of 1:k 1 , used in the input PMOS tube M 3 、M 4 Provides compensation current when in the subthreshold region; NMOS tube M 14 The gate and drain of NMOS tube M 13 The gates are connected to form a current mirror with a current replication ratio of 1:k 3 , used in the input PMOS tube M 3 、M 4 Provides compensation current when in the cut-off region.

[0070] In the PMOS tail current compensation circuit, the NMOS current control tube M 7 The gate is connected to the bias voltage V s2 , its drain is connected to PMOS tube M 16 The drain of NMOS current control tube M 9 The gate is connected to the bias voltage V s4 , its drain is connected to PMOS tube M 18 The drain of both is connected to the source of NMOS tail current source tube M 5 The drain and input NMOS tube M 1 、M 2 The source of the NMOS tail current source tube M is used to control the extraction 5 The current of PMOS tube M 16 The gate and drain of the PMOS tube M 15 The gates of the two electrodes are connected to form a current mirror with a current replication ratio of 1:k 2 , used in the input NMOS tube M 1 、M 2 Provides compensation current when in the subthreshold region; PMOS tube M 18 The gate and drain of the PMOS tube M 17The gates of the two electrodes are connected to form a current mirror with a current replication ratio of 1:k 4 , used in the input NMOS tube M 1 、M 2 Provides compensation current when in the cut-off region.

[0071] The specific analysis is as follows: If the input common-mode voltage is V DD / 2~V DD area:

[0072] When the input pipe M 1 ~M 4 When both are working in the saturation region, the current control tube does not work, and the total transconductance of the input stage is:

[0073]

[0074] In the formula, I n For the input pipe M 1 and M 2 The total current flowing, V dsatn is its saturation drain-source voltage; I p For the input pipe M 3 and M 4 The total current flowing, V dsatp is its saturation drain-source voltage.

[0075] When the input pipe M 1 、M 2 When working in the saturation region, M 3 、M 4 When working in the subthreshold region, M 8 Turn on and start extracting M working in the linear region 6 The total transconductance of the input stage is:

[0076]

[0077] In the formula, k 1 M 11 and M 12 Current replication ratio; I s1 M is the current control tube 8 The current flowing; ζ>1, is a non-ideal factor; the thermal voltage V T =kT / q, k is the Boltzmann constant, q is the electron charge, and T represents the absolute temperature.

[0078] Will I s1 and I p Substitute and set 2(V s1 –V THP )=V GS6 –V THP , to determine the current mirror replication ratio k 1and the sizes of the current control tube and the current mirror so that the sum of the compensation transconductance and the subthreshold region transconductance remains constant;

[0079] When the input pipe M 1 、M 2 When working in the saturation region, M 3 、M 4 When working in the cut-off region, M 6 The current remains unchanged, M 10 The two sets of compensation current mirrors work simultaneously. At this time, the total transconductance of the input stage is:

[0080]

[0081] In the formula, k 3 M 13 and M 14 Current replication ratio; I s3 M is the current control tube 10 The current flowing through.

[0082] Figure 6 is the input transconductance variation curve of the segmented tail current compensation structure, g mtot1 is a total transconductance variation curve of a set of compensation current mirrors, which mainly compensates for the subthreshold transconductance, and its cut-off region transconductance is lower than the total transconductance; g mtot2 The total transconductance variation curve of the two sets of compensation current mirrors is shown in Figure 2. It can be seen that the transconductance in the subthreshold region and the cut-off region are effectively compensated, solving the problem of poor transconductance stability in the subthreshold region of the triple current mirror method.

[0083] Specifically, based on the 0.18 μm CMOS process, the total input transconductance is simulated at a power supply voltage of 1.8 V. The total input transconductance change curve of the circuit disclosed in the embodiment of the present invention is compared with that of the circuit without a constant transconductance structure and the triple current mirror. Figure 7 As shown, from Figure 7 It can be seen that the circuit disclosed in the embodiment of the present invention has no constant transconductance structure compared with the triple current mirror, and achieves a constant transconductance effect in the input common-mode voltage range of 0V to 1.8V; but when the input common-mode voltage is in the range of 0.2V to 0.7V and 1.1V to 1.6V, the circuit disclosed in the embodiment of the present invention achieves better transconductance stability than the triple current mirror.

[0084] In summary, an embodiment of the present invention provides a constant transconductance input stage circuit for an operational amplifier, including complementary NMOS and PMOS differential input pairs and a segmented tail current compensation circuit; wherein, when the NMOS differential input pair is in the subthreshold region and the cut-off region, the NMOS current control tube extracts the NMOS tail current source working in the linear region, and injects the compensation current into the PMOS differential input pair through the PMOS compensation current mirror; when the PMOS differential input pair is in the subthreshold region and the cut-off region, the PMOS current control tube extracts the PMOS tail current source working in the linear region, and injects the compensation current into the NMOS differential input pair through the NMOS compensation current mirror; when the NMOS differential input pair and the NMOS differential input pair are both in the saturation region, the segmented tail current compensation circuit does not work. Compared with the traditional constant transconductance input stage circuit, the constant transconductance input stage circuit of the present invention effectively improves the transconductance stability within the full input common mode range, thereby improving the linearity of the operational amplifier.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A constant transconductance input stage circuit for an operational amplifier, characterized in that: include: A segmented tail current compensation circuit and a complementary NMOS differential input pair and a PMOS differential input pair; wherein, The segmented tail current compensation circuit includes two parts: an NMOS tail current compensation circuit and a PMOS tail current compensation circuit; wherein the NMOS tail current compensation circuit is used to provide different compensation currents when the PMOS differential input pair is in the subthreshold region and the cut-off region, and the PMOS tail current compensation circuit is used to provide different compensation currents when the NMOS differential input pair is in the subthreshold region and the cut-off region.

2. A constant transconductance input stage circuit for an operational amplifier according to claim 1, characterized in that: The NMOS differential input pair includes: an NMOS tube M1 and an NMOS tube M2; The PMOS differential input pair includes: a PMOS tube M3 and a PMOS tube M4; The NMOS tail current compensation circuit includes: an NMOS tube M5, an NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 , PMOS tube M8 and PMOS tube M 10 ; The PMOS tail current compensation circuit includes: a PMOS tube M6, a PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 , NMOS tube M7 and NMOS tube M9; in, PMOS tube M6, PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 The source of the NMOS tube M5 and the NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 The source is grounded; PMOS tube M 18 The gate, drain and PMOS tube M 17 The gates of the PMOS tube M are connected to form a current mirror. 16 The gate, drain and PMOS tube M 15 The gates of the PMOS tube M are connected to form a current mirror; 18 The drain of the NMOS tube M9 is connected to the drain of the PMOS tube M 16 The drain of the NMOS tube M7 is connected to the drain of the NMOS tube M7, and the gate of the NMOS tube M7 is connected to the bias voltage V s2 , the gate of NMOS tube M9 is connected to the bias voltage V s4 , the gate of PMOS tube M6 is connected to the bias voltage V b2 ; PMOS tube M6, PMOS tube M 15 、PMOS tube M 17 The drain of PMOS tube M3, PMOS tube M4, PMOS tube M8, PMOS tube M 10 The source of the NMOS tube M1 and the gate of the PMOS tube M3 are connected to the positive input V in , the gate of NMOS tube M2 and the gate of PMOS tube M4 are connected to the negative input V ip The drains of the NMOS tube M1, the NMOS tube M2, the PMOS tube M3, and the PMOS tube M4 are output nodes; The sources of the NMOS tubes M1, M2, M7, and M9 are connected to the NMOS tubes M5 and M9. 11 、NMOS tube M 13 The drain of NMOS tube M5 is connected to the bias voltage V b1 , the gate of PMOS tube M8 is connected to the bias voltage V s1 , PMOS tube M 10 The gate is connected to the bias voltage V s3 , the drain of PMOS tube M8 is connected to NMOS tube M 12 The drain of PMOS tube M 10 The drain of NMOS tube M 14 The drain of NMOS tube M 12 The gate, drain and NMOS tube M 11 The gates of the NMOS tube M are connected to form a current mirror. 14 The gate, drain and NMOS tube M 13 The gates of the two terminals are connected to form a current mirror.

3. A constant transconductance input stage circuit for an operational amplifier according to claim 2, characterized in that: NMOS tube M 11 The current of NMOS tube M 12 k1 times, NMOS tube M 13 The current of NMOS tube M 14 k3 times; Among them, through the NMOS tube M 11 Copy k1 times NMOS tube M 12 The current provides the compensation current for the PMOS tube M3 and the PMOS tube M4 to work in the subthreshold region; 13 Copy k3 times NMOS tube M 14 The current provides a compensation current for the PMOS tube M3 and the PMOS tube M4 to work in the cut-off region.

4. A constant transconductance input stage circuit for an operational amplifier according to claim 3, characterized in that: PMOS tube M 15 The current of PMOS tube M 16 k2 times, PMOS tube M 17 The current of PMOS tube M 18 k4 times; Among them, through the PMOS tube M 15 Copy k2 times PMOS tube M 16 The current provides the compensation current for NMOS tube M1 and NMOS tube M2 to work in the subthreshold region; 17 Copy k4 times PMOS tube M 18 The current provides a compensation current for the NMOS tube M1 and the NMOS tube M2 to operate in the cut-off region.

5. A constant transconductance input stage circuit for an operational amplifier according to claim 4, characterized in that: NMOS tube M 11 The width of NMOS tube M 12 k1 times, NMOS tube M 13 The width of NMOS tube M 14 k3 times, NMOS tube, M5, NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 The same length.

6. A constant transconductance input stage circuit for an operational amplifier according to claim 5, characterized in that: PMOS tube M 15 The width of the PMOS tube M 16 k2 times, PMOS tube M 17 The width of the PMOS tube M 18 k4 times, PMOS tube M6, PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 The same length.

7. A constant transconductance input stage circuit for an operational amplifier according to claim 2, characterized in that: The size and bias voltage V of PMOS tube M8 s1 It can make the PMOS tube M8 conduct when the PMOS differential input pair is in the subthreshold region.

8. The constant transconductance input stage circuit for an operational amplifier according to claim 2, characterized in that: PMOS tube M 10 The size and bias voltage V s3 It can make the PMOS tube M when the PMOS differential input pair is in the cut-off region 10 Conductivity.

9. The constant transconductance input stage circuit for an operational amplifier according to claim 2, characterized in that: The size and bias voltage V of NMOS tube M7 s2 It can make the NMOS tube M7 conduct when the NMOS differential input pair is in the subthreshold region.

10. The constant transconductance input stage circuit for an operational amplifier according to claim 2, characterized in that: The size and bias voltage V of NMOS tube M9 s4 It can make the NMOS tube M9 turned on when the NMOS differential input pair is in the cut-off region.

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