A clock phase error calibration apparatus and method

Abstract

The application provides a clock phase error calibration device and method, which comprises a delay chain, a clock data recovery circuit, a phase error detection circuit and a calibration logic circuit; the delay chain is used for outputting a plurality of delay clock signals with different phases under the control of a control code value; the clock data recovery circuit selects two delay clock signals with a desired phase error of a set error value from the plurality of delay clock signals in sequence; the phase error detection circuit is used for detecting a detection phase error between the two delay clock signals selected by the clock data recovery circuit; and the calibration logic circuit is used for outputting a control code value for adjusting the delay of the delay clock signal by the delay chain according to a direct current voltage point corresponding to the detection phase error, so that the delay clock signal and the real phase error of two delay clock signals thereof are close to the set error value.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a clock phase error calibration method device and method. BACKGROUND

[0002] With the continuous upgrading of integrated circuit technology, the running speed and throughput rate of chips are continuously improved, and the requirement for clock quality is also improved. The phase error is an important indicator of high-speed clock; for a high-speed serdes interface, the clock quality of a clock data recovery device directly determines the performance of the serdes. And for the clock data recovery circuit, the phase error of the multi-phase input clock directly affects the linearity performance of the clock data recovery circuit.

[0003] However, the high-speed clock sent out from the PLL will cause the deterioration of the clock phase error due to process mismatch, long-distance transmission, design mismatch of the circuit itself, and the like. Therefore, it is an unavoidable choice to design a multi-phase clock phase error calibration circuit. SUMMARY

[0004] The application aims to provide a clock phase error calibration method device and method, and aims to solve the problem in the related art that digital clock calibration cannot achieve high-speed and high-precision clock calibration, and that analog-digital clock calibration is easily affected by the mismatch of the detection circuit itself.

[0005] According to a first aspect of the application, a clock phase error calibration device is provided, comprising: a delay chain, a clock data recovery circuit, a phase error detection circuit, and a calibration logic circuit.

[0006] The delay chain is configured to output a plurality of delay clock signals with different phases under the control of a control code value, and the expected phase error between any one of the plurality of delay clock signals and two of the plurality of delay clock signals is a set error value.

[0007] The clock data recovery circuit is configured to sequentially select two delay clock signals with the set error value from the plurality of delay clock signals.

[0008] The phase error detection circuit is configured to detect a detection phase error between the two delay clock signals selected by the clock data recovery circuit.

[0009] The calibration logic circuit is configured to output a control code value for adjusting the delay of the delay clock signal by the delay chain according to a direct current voltage point corresponding to the detection phase error, so that the real phase error between the delay clock signal and the two delay clock signals approaches the set error value.

[0010] In an optional embodiment, the clock data recovery circuit comprises a first signal selector and a second signal selector.

[0011] The first signal selector receives a half number of the delay clock signals from the delay chain and selects one delay clock signal therefrom; the expected phase error between any two of the delay clock signals received by the first signal selector is an even multiple of the set error value.

[0012] The second signal selector receives another half number of the delay clock signals from the delay chain and selects one delay clock signal therefrom; the expected phase error between any two of the delay clock signals received by the second signal selector is also an even multiple of the set error value.

[0013] The delay clock signals selected by the first signal selector and the second signal selector at each time form a clock signal combination to be detected, and the first signal selector and the second signal selector sequentially and cyclically select a plurality of different clock signal combinations to be detected.

[0014] In an optional embodiment, the phase error detection circuit comprises an exclusive-OR logic circuit.

[0015] The exclusive-OR logic circuit receives two delay clock signals selected by the clock data recovery circuit and detects the detection phase error between the two delay clock signals selected by the clock data recovery circuit through exclusive-OR logic operation.

[0016] In an optional embodiment, the calibration logic circuit comprises a comparator, a digital-to-analog converter, and a calibration algorithm circuit.

[0017] The comparator receives a first voltage signal corresponding to the detection phase error output by the phase error detection circuit and a second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal by comparing the first voltage signal and the second voltage signal;

[0018] The calibration algorithm circuit outputs the adjustment signal to the digital-to-analog converter and updates a direct current voltage point corresponding to the second voltage signal according to the adjustment signal;

[0019] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before adjustment;

[0020] After the adjusted second voltage signal meets a set condition, the calibration algorithm circuit determines the updated direct current voltage point as the direct current voltage point of the detection phase error, and outputs a control code value corresponding to the detection phase error according to the direct current voltage point corresponding to the detection phase error.

[0021] In an optional embodiment, the calibration algorithm circuit pre-determines the direct current voltage point corresponding to the detection phase error of each of the clock signal combinations to be detected, and determines a direct current total voltage point corresponding to a total phase error of all the clock signal combinations to be detected according to the direct current voltage point corresponding to each of the clock signal combinations to be detected.

[0022] During the clock calibration process, the calibration algorithm circuit determines the current direct current voltage point for the clock signal combination to be detected currently output by the clock data recovery circuit, and compares the current direct current voltage point with the direct current total voltage point, and adjusts the control code value of the delay clock signal with a larger phase in the two delay clock signals selected by the current clock data recovery circuit according to the comparison result.

[0023] In an optional embodiment, the control code value is determined based on a difference between a direct current average voltage point and the current direct current voltage point, and the direct current average voltage point is determined based on the direct current total voltage point and a total number of types of the clock signal combinations to be detected.

[0024] The delay chain adjusts the delay of the delay clock signal with a larger phase in the two delay clock signals selected by the current clock data recovery circuit under the control of the control code value, and the adjusted delay length is related to the difference.

[0025] According to a second aspect of the present application, a clock phase error calibration method is provided, comprising:

[0026] A delay chain outputs a plurality of delay clock signals with different phases under the control of a control code value, and any one of the plurality of delay clock signals has a set error value as an expected phase error with any two of the plurality of delay clock signals.

[0027] A clock data recovery circuit receives the plurality of delay clock signals, and selects two delay clock signals with a set error value as an expected phase error from the plurality of delay clock signals in sequence.

[0028] A phase error detection circuit receives and detects a detection phase error between the two delay clock signals selected by the clock data recovery circuit.

[0029] The calibration logic circuit outputs a control code value to control the delay chain to adjust the delay of the delay clock signals according to a direct current voltage point corresponding to the detected phase error, so that the real phase error between the two delay clock signals approaches the set error value.

[0030] In an optional embodiment, the clock data recovery circuit receives the plurality of delay clock signals, and sequentially selects two delay clock signals with a desired phase error being the set error value from the plurality of delay clock signals, including:

[0031] The clock data recovery circuit receives half of the plurality of delay clock signals from the delay chain using a first signal selector, and selects one delay clock signal from the half of the plurality of delay clock signals and outputs the selected delay clock signal to the phase error detection circuit; the desired phase error between any two delay clock signals received by the first signal selector is an even multiple of the set error value.

[0032] The clock data recovery circuit further receives the other half of the plurality of delay clock signals from the delay chain using a second signal selector, and selects one delay clock signal from the other half of the plurality of delay clock signals and outputs the selected delay clock signal to the phase error detection circuit; the desired phase error between any two delay clock signals received by the second signal selector is also an even multiple of the set error value; wherein the delay clock signals selected by the first signal selector and the second signal selector each time form a to-be-detected clock signal combination, and the first signal selector and the second signal selector sequentially and cyclically select a plurality of different to-be-detected clock signal combinations.

[0033] In an optional embodiment, the phase error detection circuit receives and detects a detected phase error between the two delay clock signals selected by the clock data recovery circuit, including:

[0034] The phase error detection circuit receives the two delay clock signals selected by the clock data recovery circuit using an exclusive OR logic circuit, and detects the detected phase error between the two delay clock signals selected by the clock data recovery circuit through an exclusive OR logic operation.

[0035] In an optional embodiment, the calibration logic circuit outputs a control code value to control the delay chain to adjust the delay of the delay clock signals according to a direct current voltage point corresponding to the detected phase error, including:

[0036] The calibration logic circuit receives a first voltage signal corresponding to the detected phase error output by the phase error detection circuit using a comparator, and compares the first voltage signal with a second voltage signal output by a digital-to-analog converter, and outputs an adjustment signal to adjust the second voltage signal according to a comparison result.

[0037] The calibration logic circuit outputs the adjustment signal to the digital-to-analog converter by using a calibration algorithm circuit, and updates a direct current voltage point corresponding to the second voltage signal according to the adjustment signal;

[0038] The digital-to-analog converter outputs the second voltage signal adjusted according to the adjustment signal to the comparator, so that the second voltage signal adjusted is closer to the first voltage signal than before adjustment;

[0039] After the second voltage signal adjusted satisfies a set condition, the calibration algorithm circuit determines the direct current voltage point updated as a direct current voltage point for detecting a phase error, and outputs the control code value of the delay clock signal with a larger phase selected by the clock data recovery circuit corresponding to the phase error according to the direct current voltage point corresponding to the phase error.

[0040] In an optional embodiment, the method further comprises:

[0041] The calibration algorithm circuit determines the direct current voltage point corresponding to the phase error for each combination of the clock signals to be detected in advance, and determines a direct current total voltage point corresponding to a total phase error of all combinations of the clock signals to be detected according to the direct current voltage point corresponding to each combination of the clock signals to be detected.

[0042] Outputting the control code value of the delay clock signal with a larger phase selected by the clock data recovery circuit corresponding to the phase error according to the direct current voltage point of the phase error comprises:

[0043] Comparing the direct current voltage point with the direct current total voltage point, and adjusting the control code value of the delay clock signal with a larger phase selected by the clock data recovery circuit according to a comparison result.

[0044] In an optional embodiment, the control code value is determined based on a difference between a direct current average voltage point and the direct current voltage point; and the direct current average voltage point is determined based on the direct current total voltage point and a total number of types of the combinations of the clock signals to be detected.

[0045] The delay chain outputs a plurality of delay clock signals with different phases under the control of the control code value, comprising:

[0046] The delay chain adjusts a delay of the delay clock signal with a larger phase selected by the clock data recovery circuit under the control of the control code value, and the length of the delay adjusted is related to the difference.

[0047] Compared with the related art, the technical solution of the present application has the following advantages:

[0048] The clock phase error calibration device has high calibration speed and high calibration accuracy, and is not affected by the errors of the calibration logic circuit and the phase error detection circuit. The error between the multiple-phase clock signals obtained through final adjustment is small, so that a high-quality data sampling clock clk_pmix can be generated.

[0049] Other features and advantages of the present application will be described in the following description, and some will become apparent from the description, or will be understood through implementation of the present application. The purposes and other advantages of the present application can be achieved and obtained through the structures and processes indicated in the description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiment or related art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0051] Figure 1 is a structural schematic diagram of a clock phase error calibration device according to an exemplary embodiment of the present application.

[0052] Figure 2 is a timing logic schematic diagram of clock phase error detection according to an exemplary embodiment of the present application.

[0053] Figure 3 is a calibration logic and corresponding relationship with a direct current voltage point according to an exemplary embodiment of the present application.

[0054] Figure 4 is a flowchart of a clock phase error calibration method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0056] In the related art, clock phase error calibration methods mainly include digital clock calibration and analog clock calibration. Digital clock calibration cannot achieve high-speed and high-precision clock calibration due to the constraint of delay units. The main difference between the many analog clock phase error calibration methods is the difference in multi-phase clock phase error detection methods, which can often achieve high-speed and high-precision calibration, but the calibration results are easily affected by the mismatch of the detection circuit itself.

[0057] Based on the above analysis, the present application uses a high-speed serdes (SERializer and DESerializer) interface IP to design a high-speed multi-phase clock phase error calibration device based on a clock data recovery circuit, a delay line, a phase error detection circuit, and a calibration logic circuit. The device has the characteristics of high speed, high precision, and is not affected by the error of the error detection circuit.

[0058] In the related art, the clock phase error calibration idea is to detect the direct current voltage of the clock phase error, adjust the rising or falling edge strength of the clock drive by judging the size of the direct current operating point, and thus realize the delay control of the clock. Such clock phase error calibration is easily affected by the deviation of the direct current operating point. The present application detects and judges the direct current operating point of the clock multiple times, and compares it with the single detection result, so as to eliminate the error caused by the detection circuit and the calibration logic itself.

[0059] As shown in Figure 1 The present application exemplarily provides a clock phase error calibration device, which comprises a delay line, a clock data recovery circuit, a phase error detection circuit, and a calibration logic circuit.

[0060] The delay line is used to output a plurality of delay clock signals with different phases under the control of a control code value, and the expected phase error between any one of the plurality of delay clock signals and two of the plurality of delay clock signals is a set error value.

[0061] The clock data recovery circuit selects two delay clock signals with the expected phase error of the set error value from the plurality of delay clock signals in sequence.

[0062] The phase error detection circuit is used to detect the detection phase error between the two delay clock signals selected by the clock data recovery circuit.

[0063] The calibration logic circuit is used to output a control code value for adjusting the delay of the delay clock signal by the delay line according to the direct current voltage point corresponding to the detection phase error, so that the real phase error between the delay clock signal and the two delay clock signals approaches the set error value.

[0064] Exemplarily, the delay chain is a clock driving circuit based on single-ended clock delay adjustment, used to realize fine adjustment of a high-speed clock; the clock data recovery circuit can be a key circuit in a high-speed serdes application, used to output a high-speed clock adjusted by the delay chain and provide a data sampling clock of a next stage; the phase error detection circuit is used to sequentially detect detection phase errors between a plurality of phase-different delay clock signalsxor <n>wherein n represents the number of the plurality of delayed clock signals, and is also the number of combinations of the two delayed clock signals whose expected phase error is the set error value, for the convenience of description, the combination of the two delayed clock signals whose expected phase error is the set error value is referred to as the combination of the clock signals to be detected in the following; the calibration logic circuit converts the corresponding direct current voltage point code according to the detection phase error detected by the phase error detection circuit <n>; calibration logic circuit according to the direct current voltage point code <n>Delay instructions are given to delay circuits that provide delays for clock signals with different phases. The delay chain includes multiple delay circuits, each corresponding to a delay clock signal.

[0065] For example, such as Figure 1 As shown, there are eight delayed clock signals: clk0°, clk45° (with a desired phase error of 45 degrees from clk0°), clk90° (with a desired phase error of 45 degrees from clk45°), clk135° (with a desired phase error of 45 degrees from clk90°), clk180° (with a desired phase error of 45 degrees from clk135°), clk225° (with a desired phase error of 45 degrees from clk180°), clk270° (with a desired phase error of 45 degrees from clk225°), and clk315° (with a desired phase error of 45 degrees from clk270° and also with a desired phase error of 45 degrees from clk0°). The phases of these eight delayed clock signals are all different, and the desired phase error between any one of them and the other two is 45 degrees. Figure 1 In the illustrated embodiment, the error value is set to 45 degrees. It is understood that the error value is not limited to 45 degrees and can be set according to actual needs. Figure 1 In the illustrated embodiment, clk0° can be combined with clk45° to form a clock signal combination with a desired phase error of a set error value; clk45° can be combined with clk90° to form a clock signal combination with a desired phase error of a set error value; and so on. clk315° can be combined with clk0° to form a clock signal combination with a desired phase error of a set error value. There are a total of 8 clock signal combinations with a desired phase error of a set error value, which is the same as the number of delayed clock signals.

[0066] It is understandable that, considering the process deviation of the phase error detection circuit itself, the detected phase error of the combination of clock signals to be detected may not be the true phase error of the two delayed clock signals. The true phase error is denoted as Δphase<7:0>, and the error caused by the process deviation of the phase error detection circuit itself is denoted as Δoffset1. Then the detected phase error xor<7:0> = Δphase<7:0> + Δoffset1.

[0067] For example, when the calibration logic circuit adjusts the control code value of the delay of the delayed clock signal according to the detected phase error output, the above-mentioned Δoffset1 is considered, and finally adjusted so that the real phase error of the two delayed clock signals in each to-be-detected clock signal combination is as close as possible to the set error value, until the difference between the real phase error and the set error value is within a set threshold range, which can be a small range centered on 0 degrees. The clock data recovery circuit can output the two delayed clock signals with the calibrated real phase error close to the set error value to the phase interpolator PI, so as to output a data sampling clock signal clk_pmix with a controllable phase.

[0068] In some optional embodiments, the clock data recovery circuit comprises a first signal selector and a second signal selector.

[0069] The first signal selector receives half of the number of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between the two delayed clock signals received by the first signal selector is an even multiple of the set error value.

[0070] The second signal selector receives the other half of the number of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between the two delayed clock signals received by the second signal selector is also an even multiple of the set error value.

[0071] The delayed clock signals selected by the first signal selector and the second signal selector at each time form a to-be-detected clock signal combination, and the first signal selector and the second signal selector cyclically select a plurality of different to-be-detected clock signal combinations in turn.

[0072] For example, as Figure 1 As shown, the selection signals sel<7:0> can be set so that the first signal selector and the second signal selector synchronously output two delay clock signals at a time, and the two delay clock signals synchronously output at each time form a clock signal combination to be detected. The first signal selector and the second signal selector can sequentially select two delay clock signals in various clock signal combinations to be detected, for example, the first signal selector receives clk0°, clk90°, clk180° and clk270° from the delay link and selects and outputs them in a set order, and the second signal selector receives clk45°, clk135°, clk225° and clk315° from the delay link and selects and outputs them in a set order. Thus, the delay clock signals selected and output by the first signal selector and the second signal selector at each time form a clock signal combination to be detected. After 8 times of selection and output, 8 clock signal combinations to be detected can be obtained. Of course, it can be understood that the selection and output process is cyclically executed, i.e., one cycle is performed every 8 times, and one clock signal combination to be detected is selected and output every time.

[0073] In some optional embodiments, the phase error detection circuit comprises an exclusive-OR logic circuit.

[0074] The exclusive-OR logic circuit receives the two delay clock signals selected by the clock data recovery circuit and detects the detection phase error between the two delay clock signals selected by the clock data recovery circuit through an exclusive-OR logic operation.

[0075] For example, after the phase error detection circuit receives the two delay clock signals capable of forming a clock signal combination to be detected from the first signal selector and the second signal selector, the phase error detection circuit detects the phase error of the two delay clock signals by using the exclusive-OR logic circuit. For convenience of description, the detected phase error can be referred to as a detection phase error. For example, in the embodiment shown, after 8 times, the detection phase errors xor<7:0> of the two delay clock signals in the 8 clock signal combinations to be detected can be detected in sequence. As described above, because of the process deviation of the detection circuit itself, there is a certain detection error Δoffset1, and the same error Δoffset1 is introduced in each error detection. Figure 1

[0076] In some optional embodiments, the calibration logic circuit comprises a comparator, a digital-to-analog converter and a calibration algorithm circuit.

[0077] The comparator receives the first voltage signal corresponding to the detection phase error output by the phase error detection circuit and the second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal by comparing the first voltage signal and the second voltage signal.

[0078] ​The calibration algorithm circuit outputs the adjustment signal to the digital-to-analog converter, and updates the direct current voltage point corresponding to the second voltage signal according to the adjustment signal;

[0079] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than the unadjusted second voltage signal;

[0080] After the adjusted second voltage signal meets the set condition, the calibration algorithm circuit determines the updated direct current voltage point as the direct current voltage point of the detected phase error, and outputs the control code value of the delay clock signal with a larger phase selected by the clock data recovery circuit corresponding to the detected phase error according to the direct current voltage point corresponding to the detected phase error.

[0081] Exemplarily, the positive terminal of the comparator is connected to the output of the phase error detection circuit, and the phase error detection circuit outputs the first voltage signal after converting the detected phase error of the combined clock signal, thus the positive terminal of the comparator receives the first voltage signal corresponding to the detected phase error, and the negative terminal of the comparator receives the second voltage signal output by the digital-to-analog converter, and the comparator outputs the adjustment signal by comparing the first voltage signal and the second voltage signal, the adjustment signal is a digital signal, which can be 0 or 1, and is used to represent that the first voltage signal is greater than the second voltage signal or the first voltage signal is less than the second voltage signal, respectively.

[0082] The calibration algorithm circuit can output the adjustment signal to the digital-to-analog converter, and the digital-to-analog converter can adjust the second voltage signal output to the comparator according to the adjustment signal, for example, if the adjustment signal indicates that the first voltage signal is greater than the second voltage signal, the second voltage signal is adjusted to be higher, and if the adjustment signal indicates that the first voltage signal is less than the second voltage signal, the second voltage is adjusted to be lower, and the comparator re-compare the first voltage signal and the adjusted second voltage signal, thereby outputting a new adjustment signal. After the adjustment of the above process for many times, the adjustment signal will be flipped (i.e. the adjustment signal changes from 0 to 1, or from 1 to 0), which means that the first voltage signal and the second voltage signal are almost equal. At this time, it can be considered that the second voltage signal meets the set condition, and the adjustment of the second voltage signal is completed.

[0083] Exemplarily, the direct current voltage point can be understood as a digital signal representing the voltage size, thus the direct current voltage point of the detected phase error can be understood as a digital signal representing the size of the first voltage signal corresponding to the detected phase error. The calibration algorithm circuit will set an initial direct current voltage point corresponding to an initial second voltage signal at the beginning, for example, Figure 1 The code<7:0> is shown, and the calibration algorithm circuit adjusts the DC voltage point each time it receives an adjustment signal, and the digital-to-analog conversion circuit also increases the second voltage signal each time it receives an adjustment signal. The adjustment size of the DC voltage point can correspond to the adjustment size of the second voltage signal, for example, if the DC voltage point increases by one number, the second voltage signal is increased by a set value, and if the DC voltage point decreases by one number, the second voltage signal is decreased by a set value. After the second voltage signal meets the set condition, the final DC voltage point can be used as the DC voltage point corresponding to the detection phase error of the to-be-detected clock signal combination, so that the control code value of the control delay chain can be output according to the final DC voltage point. That is, after the second voltage signal meets the set condition, the final DC voltage point is the DC voltage point corresponding to the second voltage signal, and at this time, the second voltage signal is adjusted to be equal to or almost equal to the first voltage signal, so the DC voltage point is also the DC voltage point of the first voltage signal corresponding to the detection phase error. Further, the delay chain can adjust the delay of the delay clock signal with a larger phase in the to-be-detected clock signal combination corresponding to the detection phase error xor<7:0> according to the DC voltage point of the first voltage signal corresponding to the detection phase error, so that the real phase error Δphase<7:0> of the to-be-detected clock signal combination output to the clock data recovery circuit next time is a set error value, such as 45 degrees.

[0084] In some optional embodiments, the calibration algorithm circuit determines the DC voltage point corresponding to the detection phase error of each to-be-detected clock signal combination in advance, and determines the DC total voltage point corresponding to the total phase error of all to-be-detected clock signal combinations according to the DC voltage point corresponding to each to-be-detected clock signal combination.

[0085] In the clock calibration process, the calibration algorithm circuit determines the current DC voltage point corresponding to the to-be-detected clock signal combination currently output by the clock data recovery circuit, compares the current DC voltage point with the DC total voltage point, and adjusts the control code value of the delay clock signal with a larger phase in the two delay clock signals selected by the current clock data recovery circuit according to the comparison result.

[0086] For example, the calibration algorithm circuit can determine the DC voltage point corresponding to the detection phase error of all different to-be-detected clock signal combinations through multiple calculations, and can obtain the DC total voltage point corresponding to the total phase error of the detection phase error of all to-be-detected clock signal combinations by adding the DC voltage points corresponding to the detection phase errors of all different to-be-detected clock signal combinations. The DC average voltage point of the DC total voltage point (that is, the DC total voltage point is averaged for multiple to-be-detected clock signal combinations, such as Figure 1 The DC average voltage point of the 8 clock signal combinations to be detected in the embodiment is actually the adjustment target of the DC voltage point corresponding to the detection phase error of each clock signal combination to be detected in the subsequent clock calibration process. Therefore, in the clock calibration process, after the calibration algorithm circuit receives the detection phase error of each clock signal combination to be detected, the DC voltage point is determined, and the DC voltage point is compared with the DC average voltage point of the DC total voltage point, so as to determine the control code value of the delay of the delay clock signal in the clock signal combination to be detected, so that the DC voltage point corresponding to the detection phase error of the clock signal combination to be detected after adjustment is equal to the DC average voltage point of the DC total voltage point. It can be seen that, after the multiple DC voltage points of the detection phase errors of the multiple different clock signal combinations to be detected are obtained by multiple detections, the multiple DC voltage points are compared with the DC voltage point of the detection phase error of the clock signal combination to be detected once in the subsequent single detection, so as to output the control code value of the phase larger delay clock signal in the clock signal combination to be detected once, thereby eliminating the error caused by the phase error detection circuit and the calibration logic circuit itself. The comparison of the multiple DC voltage points with the DC voltage point of the detection phase error of the clock signal combination to be detected once in the subsequent single detection can be understood as the comparison of the DC average voltage point of the multiple DC voltage points with the single obtained DC voltage point.

[0087] In some optional embodiments, the control code value is determined based on the difference between the DC average voltage point and the current DC voltage point; and the DC average voltage point is determined based on the DC total voltage point and the total number of types of the clock signal combinations to be detected.

[0088] The delay chain adjusts the delay of the delay clock signal with the larger phase in the two delay clock signals selected by the current clock data recovery circuit under the control of the control code value, and the adjustment length of the delay is related to the difference.

[0089] Exemplarily, the control code value is actually the control code value corresponding to the difference between the DC average voltage point and the DC voltage point, which can be a digital signal, and the delay chain can determine the adjustment amplitude and the adjustment direction (i.e., increase or decrease) of the delay clock signal based on the control code value.

[0090] Exemplarily, as Figure 2 shown, the calibration logic circuit sequentially compares and judges the corresponding DC voltage point code<7:0> according to the detected detection phase error xor<7:0>, and the mapping relationship is as Figure 3 It can be seen that a calibration error Δoffset2 caused by the process deviation of the comparator in the calibration logic circuit will occur again in the mapping process, and the calibration error caused by the mapping process is constant. That is, the manufacturing errors of two points will cause the loss of the accuracy of the phase calibration, which are Δoffset1 and Δoffset2.

[0091] The calibration algorithm circuit linearly adds the corresponding DC voltage points of each combination of the to-be-detected clock signals to obtain a DC total voltage point code_tot corresponding to the total phase error. Figure 1 Taking the embodiment shown in the figure as an example, code_tot is expressed as follows:

[0092] code_tot = code<0> + code<1> + code<2> + code<3> + code<4> + code<5> + code<6> + code<7> = Δphase0 + Δphase1 + Δphase2 + Δphase3 + Δphase4 + Δphase5 + Δphase6 + Δphase7 + 8*Δoffset.

[0093] Wherein, Δoffset = Δoffset1 + Δoffset2; code<0> is a DC voltage point corresponding to the first combination of the to-be-detected clock signals, such as the clk0° and clk45° combination, and so on. There are 8 DC voltage points code<7:0> of 8 combinations of the to-be-detected clock signals in total. Δphase0, …, Δphase7 are the real phase errors corresponding to the 8 combinations of the to-be-detected clock signals.

[0094] It can be found from the above formula that Δphase0 + Δphase1 + Δphase2 + Δphase3 + Δphase4 + Δphase5 + Δphase6 + Δphase7 is exactly equal to one clock period, so if code_tot - 8*code<0> is used as the phase error, the phase error will be equal to one clock period. <n>As a basis for the determination of the phase error, the calibration will not be affected by the Δoffset. As shown in Figure 3 by comparing code_tot and 8*code <n>A control code value delay ctr1 code<n+1> that controls how the delay chain delays can be output, code <n>code<0> represents a direct current voltage point corresponding to a detected phase error of a current clock signal combination n to be detected, and code<0+1> represents a direct current voltage point corresponding to a detected phase error of a next clock signal combination n to be detected.

[0095] For example, for the first clock signal combination to be detected,

[0096] code_tot-8*code<0>=Δphase0+Δphase1+Δphase2+Δphase3+Δphase4+Δphase5+Δphase6+Δphase7+8*Δoffset-8*Δphase0-8*Δoffset

[0097] code_tot-8*code<0>=Δphase0+Δphase1+Δphase2+Δphase3+Δphase4+Δphase5+Δphase6+Δphase7-8*Δphase0。

[0098] The clock phase error calibration device has high calibration speed and high calibration accuracy, is not affected by errors of the calibration logic circuit and the phase error detection circuit, and has small error between the multiple-phase clock signals finally adjusted, so that a high-quality data sampling clock clk_pmix can be generated.

[0099] Correspondingly, as Figure 4 shown, the application exemplarily provides a clock phase error calibration method, comprising:

[0100] In step S401, the delay chain outputs multiple delay clock signals with different phases under the control of a control code value, and an expected phase error between any one of the multiple delay clock signals and two of the multiple delay clock signals is a set error value;

[0101] In step S402, the clock data recovery circuit receives the multiple delay clock signals, and selects two delay clock signals with the expected phase error being the set error value from the multiple delay clock signals in sequence;

[0102] In step S403, the phase error detection circuit receives and detects a detected phase error between the two delay clock signals selected by the clock data recovery circuit;

[0103] In step S404, the calibration logic circuit outputs a control code value for controlling the delay chain to adjust a delay of the delay clock signal according to a direct current voltage point corresponding to the detected phase error, so that a real phase error between the delay clock signal and the two delay clock signals approaches the set error value.

[0104] In some alternative embodiments, the clock data recovery circuit receives the plurality of delay clock signals, and sequentially selects two delay clock signals with a desired phase error being a set error value from the plurality of delay clock signals, comprising:

[0105] The clock data recovery circuit receives half of the plurality of delay clock signals from the delay chain using a first signal selector, and selects one delay clock signal from the half of the plurality of delay clock signals and outputs the selected delay clock signal to the phase error detection circuit; the desired phase error between any two delay clock signals received by the first signal selector is an even multiple of the set error value;

[0106] The clock data recovery circuit also receives the other half of the plurality of delay clock signals from the delay chain using a second signal selector, and selects one delay clock signal from the other half of the plurality of delay clock signals and outputs the selected delay clock signal to the phase error detection circuit; the desired phase error between any two delay clock signals received by the second signal selector is also an even multiple of the set error value; wherein the selected delay clock signals by the first signal selector and the second signal selector each time form a kind of to-be-detected clock signal combination, and the first signal selector and the second signal selector sequentially and cyclically select a plurality of different to-be-detected clock signal combinations.

[0107] In some alternative embodiments, the phase error detection circuit receives and detects a detection phase error between the two delay clock signals selected by the clock data recovery circuit, comprising:

[0108] The phase error detection circuit receives the two delay clock signals selected by the clock data recovery circuit using an exclusive-OR logic circuit, and detects the detection phase error between the two delay clock signals selected by the clock data recovery circuit through exclusive-OR logic operation.

[0109] In some alternative embodiments, the calibration logic circuit outputs a control code value for adjusting the delay of the delay clock signal according to a direct current voltage point corresponding to the detection phase error, comprising:

[0110] The calibration logic circuit receives a first voltage signal corresponding to the detection phase error output by the phase error detection circuit using a comparator, and compares the first voltage signal with a second voltage signal output by a digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal according to the comparison result;

[0111] The calibration logic circuit outputs the adjustment signal to the digital-to-analog converter using a calibration algorithm circuit, and updates a direct current voltage point corresponding to the second voltage signal according to the adjustment signal;

[0112] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before adjustment;

[0113] After the adjusted second voltage signal meets a set condition, the calibration algorithm circuit determines the updated direct current voltage point as the direct current voltage point for detecting phase error, and outputs the control code value of the delay clock signal with a larger phase among two delay clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the direct current voltage point for detecting phase error.

[0114] In some optional embodiments, the method further comprises:

[0115] The calibration algorithm circuit determines the direct current voltage point corresponding to the detected phase error for each combination of the to-be-detected clock signals in advance, and determines a direct current total voltage point corresponding to a total phase error of all combinations of the to-be-detected clock signals according to the direct current voltage point corresponding to each combination of the to-be-detected clock signals;

[0116] The outputting of the control code value of the delay clock signal with a larger phase among two delay clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the direct current voltage point for detecting phase error comprises:

[0117] Comparing the direct current voltage point with the direct current total voltage point, and adjusting the control code value of the delay clock signal with a larger phase among two delay clock signals selected by the clock data recovery circuit according to a comparison result.

[0118] In some optional embodiments, the control code value is determined based on a difference between a direct current average voltage point and the current direct current voltage point; and the direct current average voltage point is determined based on the direct current total voltage point and a total number of types of the combinations of the to-be-detected clock signals.

[0119] The delay chain outputs a plurality of delay clock signals with different phases under the control of the control code value, and the plurality of delay clock signals comprise:

[0120] The delay chain adjusts a delay of the delay clock signal with a larger phase among two delay clock signals selected by the clock data recovery circuit under the control of the control code value, and the length of the adjusted delay is related to the difference.

[0121] The above method can be implemented by the clock phase error calibration device provided in the above embodiments, and the specific implementation manner can be referred to the description of the clock phase error calibration device in the above embodiments, which will not be described here again.

[0122] It can be understood that the circuit structure, name and parameter described in the above embodiments are only examples. Those skilled in the art can also easily think of combinations and adjustments of the structural features of the above multiple embodiments according to the use needs, and the concept of the present application should not be limited to the specific details of the above examples.

[0123] Although the present application is described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A clock phase error calibration device, characterized in that, include: Delay chain, clock data recovery circuit, phase error detection circuit and calibration logic circuit; The delay chain is used to output multiple delayed clock signals with different phases under the control of the control code value. The desired phase error between any one of the multiple delayed clock signals and two of the multiple delayed clock signals is a set error value. The clock data recovery circuit sequentially selects two delayed clock signals from multiple delayed clock signals, with the desired phase error being a set error value; The phase error detection circuit is used to detect the phase error between the two delayed clock signals selected by the clock data recovery circuit. The calibration logic circuit is used to output a control code value for adjusting the delay of the delay clock signal based on the DC voltage point corresponding to the detected phase error, so that the actual phase error between the delay clock signal and two of the delay clock signals approaches the set error value; The calibration logic circuit includes: a comparator, a digital-to-analog converter, and a calibration algorithm circuit; The comparator receives a first voltage signal corresponding to the detected phase error output by the phase error detection circuit and a second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal to adjust the second voltage signal by comparing the first voltage signal and the second voltage signal. The calibration algorithm circuit outputs the adjustment signal to the digital-to-analog converter and updates the DC voltage point corresponding to the second voltage signal according to the adjustment signal; The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment; After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with the larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error. The calibration algorithm circuit predetermines the DC voltage point corresponding to the detection phase error of each combination of clock signals to be detected, and determines the total DC voltage point corresponding to the total phase error of all combinations of clock signals to be detected based on the DC voltage point corresponding to each combination of clock signals to be detected. During clock calibration, the calibration algorithm circuit determines the current DC voltage point based on the combination of clock signals to be detected currently output by the clock data recovery circuit, compares the current DC voltage point with the total DC voltage point, and adjusts the control code value of the delayed clock signal with the larger phase among the two delayed clock signals selected by the current clock data recovery circuit according to the comparison result. The control code value is determined based on the difference between the average DC voltage point and the current DC voltage point; the average DC voltage point is determined based on the total number of types of combinations of the total DC voltage point and the clock signal to be detected. Under the control of the control code value, the delay chain adjusts the delay of the delay clock signal with the larger phase among the two delay clock signals selected by the current clock data recovery circuit, and the adjusted delay length is related to the difference.

2. The clock phase error calibration device according to claim 1, characterized in that, The clock data recovery circuit includes: a first signal selector and a second signal selector; The first signal selector receives half of the delayed clock signals from the delayed link and selects one delayed clock signal from them; the expected phase error between any two pairs of the delayed clock signals received by the first signal selector is an even multiple of the set error value; The second signal selector receives the other half of the delayed clock signals from the delayed link and selects one delayed clock signal from them; the expected phase error between each pair of the delayed clock signals received by the second signal selector is also an even multiple of the set error value; The delayed clock signals selected by the first signal selector and the second signal selector each time form a combination of clock signals to be detected, and the first signal selector and the second signal selector sequentially select multiple different combinations of clock signals to be detected.

3. The clock phase error calibration device according to claim 1, characterized in that, The phase error detection circuit includes: an XOR logic circuit; The XOR logic circuit receives two delayed clock signals selected by the clock data recovery circuit and detects the phase error between the two delayed clock signals selected by the clock data recovery circuit through XOR logic operation.

4. A clock phase error calibration method, characterized in that, include: Under the control of the control code value, the delay chain outputs multiple delayed clock signals with different phases. The desired phase error between any one of the multiple delayed clock signals and two of the multiple delayed clock signals is a set error value. The clock data recovery circuit receives the plurality of delayed clock signals and sequentially selects two delayed clock signals from the plurality of delayed clock signals for which the desired phase error is a set error value; The phase error detection circuit receives and detects the phase error between two delayed clock signals selected by the clock data recovery circuit. The calibration logic circuit outputs a control code value to control the delay chain to adjust the delay of the delayed clock signal based on the DC voltage point corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value; The calibration logic circuit outputs a control code value to control the delay chain to adjust the delay of the delay clock signal based on the DC voltage point corresponding to the detected phase error, including: The calibration logic circuit uses a comparator to receive the first voltage signal corresponding to the detected phase error output by the phase error detection circuit, compares the first voltage signal with the second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal to adjust the second voltage signal according to the comparison result. The calibration logic circuit uses a calibration algorithm circuit to output the adjustment signal to the digital-to-analog converter, and updates the DC voltage point corresponding to the second voltage signal according to the adjustment signal; The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment; After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with the larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error. The calibration algorithm circuit predetermines the DC voltage point corresponding to the detection phase error of each combination of clock signals to be detected, and determines the total DC voltage point corresponding to the total phase error of all combinations of clock signals to be detected based on the DC voltage point corresponding to each combination of clock signals to be detected. Based on the DC voltage point where the phase error is detected, the control code value of the delayed clock signal with the larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error is output, including: The DC voltage point is compared with the total DC voltage point, and the control code value of the delayed clock signal with the larger phase among the two delayed clock signals selected by the current clock data recovery circuit is adjusted according to the comparison result. The control code value is determined based on the difference between the average DC voltage point and the current DC voltage point; the average DC voltage point is determined based on the total number of types of combinations of the total DC voltage point and the clock signal to be detected. Under the control of the control code value, the delay chain outputs multiple delayed clock signals with different phases, including: Under the control of the control code value, the delay chain adjusts the delay of the delay clock signal with the larger phase among the two delay clock signals selected by the current clock data recovery circuit, and the adjusted delay length is related to the difference.

5. The clock phase error calibration method according to claim 4, characterized in that, The clock data recovery circuit receives the plurality of delayed clock signals and sequentially selects two delayed clock signals from the plurality of delayed clock signals with a desired phase error of a set error value, including: The clock data recovery circuit uses a first signal selector to receive half of the delayed clock signals from the delayed link, selects one delayed clock signal from it, and outputs it to the phase error detection circuit; the expected phase error between any two pairs of the delayed clock signals received by the first signal selector is an even multiple of the set error value; The clock data recovery circuit also uses a second signal selector to receive the other half of the delayed clock signals from the delayed link, and selects one delayed clock signal from them and outputs it to the phase error detection circuit; the expected phase error between each pair of the delayed clock signals received by the second signal selector is also an even multiple of the set error value; wherein, the delayed clock signals selected by the first signal selector and the second signal selector each time form a combination of clock signals to be detected, and the first signal selector and the second signal selector sequentially and cyclically select multiple different combinations of clock signals to be detected.

6. The clock phase error calibration method according to claim 4, characterized in that, The phase error detection circuit receives and detects two delayed clock signals selected by the clock data recovery circuit, including: The phase error detection circuit uses an XOR logic circuit to receive two delayed clock signals selected by the clock data recovery circuit, and detects the phase error between the two delayed clock signals selected by the clock data recovery circuit through an XOR logic operation.

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