Resistance-capacitance hybrid analog-to-digital converter and working method thereof

Abstract

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and provides a resistance-capacitance hybrid analog-to-digital converter and a quantization method thereof. According to the resistance-capacitance hybrid analog-to-digital converter, a CDAC capacitor array is connected with the positive input end and the negative input end of a comparator, and the output end of the comparator is connected with an SAR control logic circuit; the reference voltage sampling capacitor unit is selectively connected between the output end of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or is connected between the input end of the CDAC capacitor array and the output end of the RDAC resistor array to provide reference voltage for the CDAC capacitor array; in the sampling stage, the input voltage is stored on the CDAC, and meanwhile, the reference voltage sampling capacitor unit samples the output voltage of the RDAC; and in the conversion stage, the comparator obtains a comparison result according to the voltage at the output end of the CDAC, and controls the switching of the RDAC and the CDAC through the SAR control logic circuit according to the comparison result, thereby completing the successive approximation analog-to-digital conversion process.

Description

Technical Field

[0001] The invention relates to the technical field of digital-analog hybrid integrated circuit design, and in particular to a resistor-capacitor hybrid analog-to-digital converter and a working method thereof. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] SAR ADC has attracted wide attention in the academic community and has been widely used in actual production due to its low power consumption, easy to achieve medium to high precision, and good compatibility with advanced processes. High-precision SAR ADC is generally implemented using a charge redistribution structure. The number of unit capacitors required for this structure increases exponentially with the improvement of resolution. Therefore, the number of unit capacitors required to achieve high-precision SAR ADC is considerable, which will occupy a very large layout area. Moreover, large capacitors will make the design of input buffers and power buffers more difficult. In addition, the mismatch problem caused by too many unit capacitors will also seriously affect the linearity of the ADC.

[0004] In order to reduce the number of unit capacitors in CDAC, a segmented capacitor structure or a C-2C structure can be used. However, these structures are very sensitive to parasitic capacitance, which limits the accuracy of the overall ADC. In the traditional binary weighted capacitor array structure, when the accuracy of the ADC is too high (greater than 12 bits), the capacitor mismatch will have a very serious impact. In order to make the ADC reach a sufficiently high effective number of bits (ENOB), the capacitor mismatch must be calibrated. There are many effective calibration methods, such as mismatch error shaping (MES), analog foreground calibration, digital background calibration, etc. However, although adding additional calibration circuits can meet the requirements, it will generate additional area and power consumption overhead, and increase the complexity of the design. Summary of the invention

[0005] In order to solve the technical problems existing in the above-mentioned background technology, the present invention provides a RC hybrid analog-to-digital converter and a working method thereof. The first stage uses RDAC to generate most significant bits (MSBs), and the second stage uses CDAC to generate least significant bits (LSBs). This segmented RC hybrid structure can effectively reduce the number of unit capacitors and alleviate the impact of capacitor mismatch.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] A first aspect of the present invention provides a RC hybrid analog-to-digital converter.

[0008] A hybrid RC analog-to-digital converter, comprising: a SAR control logic circuit, and an RDAC resistor array, a CDAC capacitor array, a reference voltage sampling capacitor unit and a comparator all connected thereto, wherein the CDAC capacitor array is connected to a positive input terminal and a negative input terminal of the comparator, and an output terminal of the comparator is connected to the SAR control logic circuit;

[0009] The reference voltage sampling capacitor unit is selectively connected between the output terminal of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or connected between the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array;

[0010] In the sampling stage, the input voltage is stored on the CDAC capacitor array, and the reference voltage sampling capacitor unit samples the output voltage of the RDAC resistor array. In the conversion stage, the comparator obtains the comparison result based on the output voltage of the CDAC capacitor array, and controls the switching of the RDAC resistor array and the CDAC capacitor array through the SAR control logic circuit according to the comparison result to complete the successive approximation analog-to-digital conversion process.

[0011] Furthermore, the RDAC resistor array includes ladder resistor networks RDACP and RDACN.

[0012] Furthermore, the RDACP / RDACN ladder resistor network includes N+1 first series units, each of which includes two first unit resistors Ru connected in series, and one end of the second to the N+1th first series units is recorded as the first to the Nth nodes, and the other end is recorded as the N input ends of the RDAC resistor array as DP M / DN M to DP M+N-1 / DN M+N-1 , connected to a ground voltage or a reference voltage through a first switch array.

[0013] Furthermore, adjacent nodes from the first to the Nth nodes are connected via a second unit resistor, one end of the first series unit is directly connected to the first node, and the other end is fixedly connected to the common mode reference voltage, and the Nth node serves as the output end of the RDACP / RDACN ladder resistor network ROUTP / ROUTN.

[0014] Furthermore, the CDAC capacitor array includes binary weighted capacitor arrays CDACP and CDACN, the binary weighted capacitor array CDACP is connected to the positive input terminal of the comparator, and the binary weighted capacitor array CDACN is connected to the negative input terminal of the comparator.

[0015] Furthermore, the binary weighted capacitor array CDACP / CDACN includes M capacitors, which are Cu, Cu, 2 1 Cu, 2 2 Cu, …, 2 M-2 Cu; one end of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, connected to the positive / negative input of the comparator, and the other end is the M input of CDACP / CDACN, which is DP0 / DN0 to DP M-1 / DN M-1 , through the switch array, the connection to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit is selected.

[0016] Furthermore, the reference voltage sampling capacitor array includes four capacitors Cpu, Cnu, Cpd and Cnd, Cpu and Cpd are selectively connected between ROUTP and ground, or between the input switch array of the binary weight capacitor array CDACP and ROUTP through switches controlled by sampling signals; Cnu and Cnd are selectively connected between ROUTN and ground, or between the input switch array of the binary weight capacitor array CDACN and ROUTN through switches controlled by sampling signals.

[0017] A second aspect of the present invention provides a method for operating a RC hybrid analog-to-digital converter.

[0018] A working method of a RC hybrid analog-to-digital converter, applied to the RC hybrid analog-to-digital converter described in the first aspect, comprising:

[0019] In the sampling phase, the differential input signal Vip / Vin is connected to all input ends of the CDAC capacitor array through the switch array to complete the sampling, while all input ends of the RDAC resistor array are connected to GND, and the reference voltage sampling capacitor unit is connected between the output end of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array;

[0020] During the conversion phase, the output ROUT of the RDAC resistor array is connected to the input of the CDAC capacitor array, and the reference voltage sampling capacitor unit is connected between the switch array at the input of the CDAC capacitor array and the output of the RDAC resistor array, providing the CDAC capacitor array with the reference voltage required for conversion during the conversion period.

[0021] Furthermore, during the sampling phase, the voltage at the ROUTP / ROUTN point is V REF / 2 N+1, is sampled to Cpu / Cpd and Cnu / Cnd; in the conversion stage, the upper plate of Cpu / Cnu is connected to the input switch array of CDACP / CDACN, and the lower plate is connected to ROUTP / ROUTN; the upper plate of Cpd / Cnd is connected to ROUTP / ROUTN, and the lower plate is connected to the input switch array of CDACP / CDACN, and the reference voltage sampling capacitor unit is used to provide the CDAC capacitor array with the reference voltage required for conversion; the upper plate voltage of Cpu is V REFPU =V ROUTP +V REF / 2 N+1 , the lower plate voltage of Cpd is V REFPD =V ROUTP -V REF / 2 N+1 ; The upper plate voltage of Cnu is V REFNU =V ROUTN +V REF / 2 N+1 , the lower plate voltage of Cnd is V REFND =V ROUTN -V REF / 2 N+1 After the conversion starts, the switching of the voltage at the input terminals of the RDAC resistor array and the CDAC capacitor array is controlled by the logic control circuit according to the comparison result of the comparator, and the successive approximation process begins.

[0022] Furthermore, the successive approximation process is performed from the highest bit to the lowest bit in sequence:

[0023] (1) Switching of RDAC resistor array:

[0024] When the first comparator output is 1, the SAR control logic circuit controls the input terminal corresponding to RDACP / RDACN to switch to V REF / GND, the voltage difference between the positive and negative input terminals of the comparator is

[0025] When the comparator output is 0 for the first time, the input terminal corresponding to RDACP / RDACN switches to GND / V REF , the voltage difference between the positive and negative input terminals of the comparator is

[0026] By analogy, when the resistor array comparison is completed, the voltage difference at the comparator input is: When the comparator result is 1, B i =1, when the comparator result is 0, B i = -1;

[0027] (2) Then the switching of the CDAC capacitor array begins:

[0028] When the comparator output is 1 for the first time, the switch SP M-1 and SN M-1 Switch the highest bit input of binary weight capacitor array CDACP from ROUTP to V REFPU =V ROUTP +V REF / 2 N+1 , causing the voltage at COUTP to change Switch the highest bit input of binary weight capacitor array CDACN from ROUTN to V REFND =V ROUTN -V REF / 2 N+1 , causing the voltage at COUTN to change The change in the voltage difference at the comparator input is:

[0029] When the comparator output is 0 for the first time, the highest input terminal of CDACP switches from ROUTP to V REFPD =V ROUTP -V REF / 2 N+1 , causing the voltage at COUTP to change Switch the highest input terminal of CDACN from ROUTN to V REFNU =V ROUTN +V REF / 2 N+1 , causing the voltage at COUTN to change The change in the voltage difference at the comparator input is:

[0030] By analogy, when all bit comparisons are completed, the voltage difference between the two ends of the comparator is: Since the final V COUTP -V COUTN ≈0, so: That is, the accuracy of the SAR control logic circuit reaches N+M bits.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention provides a hybrid RC analog-to-digital converter, wherein a resistor array is implemented by an R-2R ladder resistor network, which can effectively reduce the number of unit resistors in the resistor array and reduce the circuit area, thereby having more area margin to allow the use of unit devices with larger areas, reducing the mismatch between devices and improving the linearity of the overall circuit.

[0033] The present invention discloses a RC hybrid (RC) successive approximation register (SAR) analog to digital converter (ADC), which uses a resistive digital to analog converter (RDAC) to quantize the upper N bits and a capacitive digital to analog converter (CDAC) to quantize the lower M bits, and finally obtains an (N+M)-bit output code. Due to the use of an RC segmented structure, the present invention can reduce the number of unit capacitors in a DAC and alleviate the influence of capacitor mismatch on the linearity of an ADC; the RDAC of a conventional RC hybrid ADC generally uses a resistor string structure, while the RDAC in the present invention is implemented using an R-2R ladder resistor network, which can effectively reduce the number of unit resistors. By controlling the accuracy ratio of RDAC and CDAC, the present invention can achieve a compromise between linearity, area, and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0035] Figure 1 It is a circuit principle diagram of a conventional resistor-capacitor hybrid ADC using a resistor string structure shown in the present invention;

[0036] Figure 2 It is a principle diagram of a capacitive-resistive hybrid ADC of an R-2R structure shown in the present invention;

[0037] Figure 3 It is a circuit principle diagram of a resistor-capacitor hybrid analog-to-digital converter based on an R-2R structure shown in the present invention;

[0038] Figure 4 is a sampling schematic diagram of a reference voltage sampling unit shown in the present invention;

[0039] Figure 5 It is a schematic diagram showing that a reference voltage sampling unit generates a reference voltage according to the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0041] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0042] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0043] Embodiment 1

[0044] The RDAC in a traditional RC hybrid ADC usually adopts a resistor string structure. The schematic diagram of a traditional RC hybrid ADC is shown in the figure below. Figure 1 As shown in the figure, when the RDAC accuracy is N bits, the traditional structure requires 2 N The number of unit resistors increases exponentially with the increase of RDAC precision. The RDAC of the RC hybrid ADC in the present invention is implemented by an R-2R ladder resistor network. Under the differential structure, the N-bit RDAC only needs (6N+2) unit resistors, and the number of resistors increases linearly with the increase of RDAC precision. Therefore, the present invention can effectively reduce the number of unit resistors, thereby reducing the area of ​​the RDAC, and more area margin allows the use of larger unit capacitance values ​​to reduce the mismatch between capacitors, thereby avoiding the use of a calibration circuit.

[0045] For the capacitive-resistive hybrid ADC using an R-2R structure, the schematic diagram of the capacitive-resistive hybrid ADC is as follows: Figure 2 As shown. The capacitive-resistance hybrid ADC uses a capacitor DAC to quantize the MSBs and a resistor DAC to quantize the LSBs. Since the matching between capacitors is better than the matching between resistors in the current advanced technology, the capacitive DAC can achieve higher accuracy than the resistor DAC. In the SAR ADC, the accuracy of the LSBs determines the accuracy of the ADC as a whole. Therefore, compared with the capacitive-resistance ADC, the present invention uses a capacitive DAC to quantize the LSBs to achieve higher accuracy and reduce the requirements for comparator performance. In addition, the voltage variation range of the capacitor array of the capacitive-resistance ADC is V REF In the present invention, since the reference voltage of the capacitor array is generated by the resistor array and scaled by the resistor array, its variation range is Where N is the precision of the resistor array, V REFU and V REFD The voltage provided by the reference voltage sampling capacitor unit. Since the power consumption generated when the capacitor array is switched is proportional to the square of the voltage change across the capacitor, the dynamic power consumption of the capacitor array in the present invention is lower.

[0046] To specifically illustrate the working principle and working process of the present invention, a RC hybrid analog-to-digital converter proposed by the present invention is implemented using a Vcm-based switch timing, as shown in the schematic diagram. Figure 3 The overall circuit includes a resistor array RDAC, a capacitor array CDAC, a reference voltage sampling capacitor unit, a comparator, a control logic and a number of switches.

[0047] The resistor array RDAC includes resistor arrays RDACP and RDACN. The resistor array adopts an R-2R ladder network. Each resistor array contains N+1 series units. Each series unit includes two series-connected unit resistors Ru, which are equivalent to a resistor arm with a resistance value of 2Ru. One end of the second to Nth series units is connected through the unit resistor Ru, and the connection forms N nodes. The other end is used as the N input ends of RDACP / RDACN, which are DP M / DN M to DP M+N-1 / DN M+N-1 , respectively, through the switch SP M / SN M To SP M+N-1 / SN M+N-1 Select the ground voltage GND, the reference voltage V REF Or common mode reference voltage V CM (V CM =V REF / 2); one end of the first series unit is directly connected to the first node, and the other end is fixed to V CM , the Nth node serves as the output end of RDACP / RDACN, which is ROUTP / ROUTN.

[0048] The CDAC capacitor array includes two groups of binary weighted capacitor arrays CDACP and CDACN. Each group of capacitor arrays includes M capacitors, Cu, Cu, 2 1 Cu, 2 2 Cu, …, 2 M-2 Cu; one end of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, and is connected to the positive / negative input of the comparator; the other end is the M input of CDACP / CDACN, which is DP0 / DN0 to DP M-1 / DN M-1 , through the switch array SP0 / SN0 to SP M-1 / SN M-1 Select the corresponding position connected to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit.

[0049] The reference voltage sampling capacitor array includes four capacitors Cpu, Cnu, Cpd and Cnd. Cpu and Cpd are connected between ROUTP and ground, or between the input switch array of CDACP and ROUTP through the switch selection controlled by the sampling signal; Cnu and Cnd are connected between ROUTN and ground, or between the input switch array of CDACN and ROUTN through the switch selection controlled by the sampling signal.

[0050] The reference voltage sampling capacitor unit is not a bridge capacitor between MSB and LSB. Its connection mode and working principle are fundamentally different from the bridge capacitor in the traditional segmented capacitor array. The reference voltage sampling capacitor unit works like a battery. During the input signal sampling period, the reference voltage sampling capacitor unit is charged by RDAC. During the conversion period of CDAC, the reference voltage sampling capacitor unit provides a reference voltage to the lower plate of CDAC by switching the connection mode, so that the overall analog-to-digital converter can achieve a successive approximation process of N+M.

[0051] The specific working process of the RC hybrid analog-to-digital converter described in the present invention can be divided into two stages:

[0052] The first stage is the sampling stage: through the switch group SP0 / SN0 to SP M-1 / SN M-1 , connect all input terminals of CDACP and CDACN to Vip and Vin respectively, and sample the input signal. At this time, both COUTP and COUTN nodes are connected to V CM , so the voltage difference between the upper and lower plates of CDACP and CDACN during sampling is V CM -Vip、V CM -Vin; through switch group SP M / SN M To SP M+N-1 / SN M+N-1 Connect the input terminals of RDACP and RDACN to GND, and connect Cpu / Cpd and Cnu / Cnd between ROUTP / ROUTN and GND to sample and hold the output voltage of RDAC. Figure 4 As shown, it is a simple statement. Figure 4 Only one resistor array is shown, but the actual circuit has two resistor arrays. ROUTP0 / V ROUTN0 =V CM / 2 N =V REF / 2 N+1 . V ROUTP0 and V ROUTN0 They are sampled on Cpu / Cpd and Cnu / Cnd respectively.

[0053] The second stage is the conversion stage: before the conversion starts, the switch group SP M / SN M To SP M+N-1 / SN M+N-1 Connect the input terminals of RDACP and RDACN to V CM . Through switch group SP0 / SN0 to SP M-1 / SN M-1 , connect all input terminals of CDACP / CDACN to ROUTP / ROUTN. Since the voltage at the ROUTP and ROUTN points is V ROUTP1 =V ROUTN1 =V CM (1 / 2+1 / 2 2 +…+1 / 2 N +1 / 2 N )=V CM Therefore, the voltages at COUTP and COUTN are 2V respectively. CM -Vip and 2V CM -Vin. At the same time, connect the upper plate of Cpu / Cnu to the input switch array of CDACP / CDACN, and the lower plate to ROUTP / ROUTN; connect the upper plate of Cpd / Cnd to ROUTP / ROUTN, and the lower plate to the input switch array of CDACP / CDACN, such as Figure 5 As shown, it is a simple statement. Figure 5 Only one set of resistor arrays is shown, but the actual circuit has two sets. During the conversion process, the reference voltage sampling capacitor unit provides the CDAC with the reference voltage required for conversion. The upper plate voltage of the CPU is V REFPU =V ROUTP +V REF / 2 N+1 , the lower plate voltage of Cpd is V REFPD =V ROUTP -V REF / 2 N+1 ; The upper plate voltage of Cnu is V REFNU =V ROUTN +V REF / 2 N+1 , the lower plate voltage of Cnd is V REFND =V ROUTN -V REF / 2 N+1 After the conversion starts, the switching of the RDAC and CDAC input voltages is controlled by the logic control circuit according to the comparison result of the comparator, and the successive approximation process begins.

[0054] By switch SP M+N-1 / SN M+N-1The input terminals controlled by SP0 / SN0 correspond to the (N + M)-th to the first bit of the ADC in sequence. The successive approximation process is carried out in sequence from the highest bit to the lowest bit.

[0055] When the result of the first comparison is 1, it indicates that V COUTP >V COUTN , that is, 2V CM -Vip > 2V CM -Vin, that is, Vip < Vin. At this time, the logic control circuit switches the input terminals corresponding to RDACP / RDACN to V M+N-1 / SN M+N-1 control to switch to V REF / GND. This causes the change in the voltage of the highest bit input terminal of RDACP to be V REF -V CM =V CM , and the voltage at the ROUTP point rises by V CM / 2; the change in the voltage of the highest bit input terminal of RDACN is GND - V CM =-V CM . The voltage at the ROUTN point drops by V CM / 2; since the input terminals of CDACP and CDACN are respectively connected to ROUTP and RDACN during the RDAC conversion and the charges at the COUTP and COUTN points are conserved, the voltages at the COUTP and COUTN points respectively become 2V CM -Vip + V CM / 2 and 2V CM -Vin - V CM / 2, and the voltage difference between the positive and negative terminals of the comparator is:

[0056]

[0057]

[0058] Similarly, when the result of the first comparison is 0, the input terminals corresponding to RDACP / RDACN are switched to GND / V REF . This causes the voltage changes at the COUTP and COUTN points to be 2V CM- Vip - V CM / 2 and 2V CM -Vin + V CM / 2. The voltage difference between the input terminals of the comparator is:

[0059] And so on, when the comparison of the resistor array is completed, the voltage difference between the input terminals of the comparator is:

[0060]

[0061] When the comparator result is 1, B i =1, when the comparator result is 0, B i =-1.

[0062] Then the capacitor array switching starts. Similarly, when the comparator output is 1, the switch SP M-1 and SN M-1 Switch the highest input of CDACP from ROUTP to V REFPU =V ROUTP +V REF / 2 N+1 , causing the voltage at COUTP to change Switch the highest input terminal of CDACN from ROUTN to V REFND =V ROUTN -V REF / 2 N+1 , causing the voltage at COUTN to change Therefore, the change in the voltage difference at the comparator input is:

[0063]

[0064] When the comparator output is 0, the highest input of CDACP switches from ROUTP to V REFPD =V ROUTP -V REF / 2 N +1 , causing the voltage at COUTP to change Switch the highest input terminal of CDACN from ROUTN to V REFNU =V ROUTN +V REF / 2 N+1 , causing the voltage at COUTN to change Therefore, the change in the voltage difference at the comparator input is:

[0065]

[0066] In summary, when the highest bit of CDAC completes the comparison, the voltage difference across the comparator is:

[0067]

[0068] Right now:

[0069]

[0070] By analogy, when all bit comparisons are completed, the voltage difference between the two ends of the comparator is:

[0071]

[0072] Since the final V COUTP -V COUTN ≈0, so:

[0073]

[0074] That is, the accuracy of SAR ADC reaches N+M bits.

[0075] In summary, the present invention proposes a hybrid RC analog-to-digital converter. Compared with the traditional RC hybrid SAR ADC, the present invention can effectively reduce the area of ​​the resistor array. By adjusting the accuracy ratio of the resistor array and the capacitor array, the present invention can better achieve a compromise between linearity, area and power consumption. It is worth noting that the analog-to-digital converter proposed by the present invention is not limited to the implementation of Vcm-based switch timing. By adjusting the number and connection method of the reference voltage sampling units, the present invention can be applied to any switch timing, which will not be described in detail here.

[0076] Embodiment 2

[0077] This embodiment provides a working method of a RC hybrid analog-to-digital converter.

[0078] A working method of a resistor-capacitor hybrid analog-to-digital converter, applied to the resistor-capacitor hybrid analog-to-digital converter, comprising:

[0079] In the sampling stage, the input voltage is stored on the capacitor array by sampling the lower plate, and the reference voltage sampling capacitor unit samples the voltage output by the RDAC; in the conversion stage, the comparator obtains the comparison result based on the CDAC output voltage, and then controls the switching of RDAC and CDAC through the logic control circuit according to the comparison result to complete the successive approximation analog-to-digital conversion process.

[0080] In the sampling phase, the differential input signal Vip / Vin is connected to all input terminals of the capacitor array CDACP / CDACN through the switch array to complete the sampling. At the same time, the input terminals of the resistor arrays RDACP and RDACN are all connected to GND, and the reference voltage sampling capacitor unit is connected between the output terminal of the resistor array and the ground to sample the output voltage of the RDAC.

[0081] During the conversion phase, the output terminals ROUTP / ROUTN of the resistor array are connected to the input terminals of the capacitor array CDACP / CDACN respectively, and the reference voltage sampling capacitor is connected between the switch array at the CDAC input terminal and the RDAC output terminal to provide the CDAC with the reference voltage required for conversion during the conversion period.

[0082] In some embodiments, the RC hybrid analog-to-digital converter includes: an RDAC resistor array, a CDAC capacitor array, a reference voltage sampling capacitor unit, a comparator, and a SAR control logic circuit;

[0083] The RDAC resistor array includes two groups of R-2R ladder resistor networks RDACP and RDACN, each of which includes N+1 series units, and each series unit includes two series-connected unit resistors Ru. One end of the second to the N+1th series units is recorded as the first to the Nth nodes, and the other end is the N input ends of the RDAC, which are DP M / DN M to DP M+N-1 / DN M+N-1 , connected to the ground voltage or the reference voltage through the switch array. Adjacent nodes from the first to the Nth nodes are connected through a unit resistor, one end of the first series unit is directly connected to the first node, and the other end is fixedly connected to the common mode reference voltage. The Nth node is the output end of RDACP / RDACN as ROUTP / ROUTN;

[0084] The reference voltage sampling capacitor unit is selectively connected between the RDAC resistor array output terminal and ground to sample the RDAC resistor array output voltage, or connected between the CDAC capacitor array input terminal and the RDAC resistor array output terminal to provide a reference voltage for the CDAC capacitor array.

[0085] The CDAC capacitor array includes two groups of binary weighted capacitor arrays CDACP and CDACN, each group of capacitor arrays includes M capacitors, Cu, Cu, 2 1 Cu, 2 2 Cu, …, 2 M-2 Cu; one end of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, connected to the positive / negative input of the comparator, and the other end is the M input of CDACP / CDACN, which is DP0 / DN0 to DP M-1 / DN M-1 , through the switch array, the connection to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit is selected.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A hybrid RC analog-to-digital converter, characterized in that: include: A SAR control logic circuit, and an RDAC resistor array, a CDAC capacitor array, a reference voltage sampling capacitor unit and a comparator all connected thereto, wherein the CDAC capacitor array is connected to the positive input terminal and the negative input terminal of the comparator, and the output terminal of the comparator is connected to the SAR control logic circuit; The reference voltage sampling capacitor unit is selectively connected between the output terminal of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or connected between the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array; In the sampling phase, the input voltage is stored on the CDAC capacitor array, while the reference voltage sampling capacitor unit samples the output voltage of the RDAC resistor array; In the conversion stage, the comparator obtains the comparison result according to the output voltage of the CDAC capacitor array, and controls the switching of the RDAC resistor array and the CDAC capacitor array through the SAR control logic circuit according to the comparison result to complete the successive approximation analog-to-digital conversion process.

2. The RC hybrid analog-to-digital converter according to claim 1, characterized in that: The RDAC resistor array includes ladder resistor networks RDACP and RDACN.

3. The RC hybrid analog-to-digital converter according to claim 2, characterized in that: The RDACP / RDACN ladder resistor network includes N+1 first series units, each of which includes two first unit resistors Ru in series, and one end of the second to the N+1th first series units is recorded as the first to the Nth nodes, and the other end is used as the N input ends of the RDAC resistor array, which are DP M / DN M to DP M+N-1 / DN M+N-1 , connected to a ground voltage or a reference voltage through a first switch array.

4. The RC hybrid analog-to-digital converter according to claim 3, characterized in that: Adjacent nodes from the first to the Nth nodes are connected via a second unit resistor, one end of the first series unit is directly connected to the first node, and the other end is fixedly connected to the common-mode reference voltage, and the Nth node serves as the output end of the RDACP / RDACN ladder resistor network, which is ROUTP / ROUTN.

5. The RC hybrid analog-to-digital converter according to claim 2, characterized in that: The CDAC capacitor array includes a binary weight capacitor array CDACP and CDACN, the binary weight capacitor array CDACP is connected to the positive input end of the comparator, and the binary weight capacitor array CDACN is connected to the negative input end of the comparator.

6. The RC hybrid analog-to-digital converter according to claim 5, characterized in that: The binary weighted capacitor array CDACP / CDACN includes M capacitors, Cu, Cu, 2 1 Cu, 2 2 Cu, …, 2 M-2 Cu; one end of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, connected to the positive / negative input of the comparator, and the other end is the M input of CDACP / CDACN, which is DP0 / DN0 to DP M-1 / DN M-1 , through the switch array, the connection to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit is selected.

7. The RC hybrid analog-to-digital converter according to claim 6, characterized in that: The reference voltage sampling capacitor array includes four capacitors Cpu, Cnu, Cpd and Cnd. Cpu and Cpd are selectively connected between ROUTP and ground, or between the input end switch array of the binary weight capacitor array CDACP and ROUTP through switches controlled by sampling signals; Cnu and Cnd are selectively connected between ROUTN and ground, or between the input end switch array of the binary weight capacitor array CDACN and ROUTN through switches controlled by sampling signals.

8. A method for operating a hybrid RC analog-to-digital converter, characterized in that: The RC hybrid analog-to-digital converter according to any one of claims 1 to 7 comprises: In the sampling phase, the differential input signal Vip / Vin is connected to all input ends of the CDAC capacitor array through the switch array to complete the sampling, while all input ends of the RDAC resistor array are connected to GND, and the reference voltage sampling capacitor unit is connected between the output end of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array; During the conversion phase, the output ROUT of the RDAC resistor array is connected to the input of the CDAC capacitor array, and the reference voltage sampling capacitor unit is connected between the switch array at the input of the CDAC capacitor array and the output of the RDAC resistor array, providing the CDAC capacitor array with the reference voltage required for conversion during the conversion period.

9. The working method of the RC hybrid analog-to-digital converter according to claim 8, characterized in that: During the sampling phase, the voltage at the ROUTP / ROUTN point is V REF / 2 N+1 , is sampled to Cpu / Cpd and Cnu / Cnd; In the conversion stage, the upper plate of Cpu / Cnu is connected to the input switch array of CDACP / CDACN, and the lower plate is connected to ROUTP / ROUTN; the upper plate of Cpd / Cnd is connected to ROUTP / ROUTN, and the lower plate is connected to the input switch array of CDACP / CDACN, and the reference voltage sampling capacitor unit is used to provide the CDAC capacitor array with the reference voltage required for conversion; the upper plate voltage of Cpu is V REFPU =V ROUTP +V REF / 2 N+1 , the lower plate voltage of Cpd is V REFPD =V ROUTP -V REF / 2 N+1 ; The upper plate voltage of Cnu is V REFNU =V ROUTN +V REF / 2 N+1 , the lower plate voltage of Cnd is V REFND =V ROUTN -V REF / 2 N+1 After the conversion starts, the switching of the voltage at the input terminals of the RDAC resistor array and the CDAC capacitor array is controlled by the logic control circuit according to the comparison result of the comparator, and the successive approximation process begins.

10. The working method of the RC hybrid analog-to-digital converter according to claim 9, characterized in that: The successive approximation process is performed from the highest bit to the lowest bit: (1) Switching of RDAC resistor array: When the first comparator output is 1, the SAR control logic circuit controls the input terminal corresponding to RDACP / RDACN to switch to V REF / GND, the voltage difference between the positive and negative input terminals of the comparator is When the comparator output is 0 for the first time, the input terminal corresponding to RDACP / RDACN switches to GND / V REF , the voltage difference between the positive and negative input terminals of the comparator is By analogy, when the resistor array comparison is completed, the voltage difference at the comparator input is: When the comparator result is 1, B i =1, when the comparator result is 0, B i = -1; (2) Then the switching of the CDAC capacitor array begins: When the comparator output is 1 for the first time, the SP M-1 and SN M-1 Switch the highest bit input of the binary weight capacitor array CDACP from ROUTP to V REFPU =V ROUTP +V REF / 2 N+1 , causing the voltage at COUTP to change Switch the highest bit input of binary weight capacitor array CDACN from ROUTN to V REFND =V ROUTN -V REF / 2 N+1 , causing the voltage at COUTN to change The change in the voltage difference at the comparator input is: When the comparator output is 0 for the first time, the highest input terminal of CDACP switches from ROUTP to V REFPD =V ROUTP -V REF / 2 N +1 , causing the voltage at COUTP to change Switch the highest input terminal of CDACN from ROUTN to V REFNU =V ROUTN +V REF / 2 N+1 , causing the voltage at COUTN to change The change in the voltage difference at the comparator input is: By analogy, when all bit comparisons are completed, the voltage difference between the two ends of the comparator is: Since the final V COUTP -V COUTN ≈0, so: That is, the accuracy of the SAR control logic circuit reaches N+M bits.

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