Semiconductor device, method for controlling semiconductor device and control program

Abstract

The invention relates to a semiconductor device, a method for controlling the semiconductor device, and a control program. A semiconductor device according to the present disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit including: a multi-phase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop, a second-stage flip-flop, and a subsequent flip-flop, the first-stage flip-flop receiving an inverted signal of an output signal of the flip-flop in the last stage; and each of the second stage flip-flop and the subsequent flip-flop receives an output signal of the flip-flop in the preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of a count value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-183664 filed on October 26, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, a method for controlling a semiconductor device, and a control program, and to, for example, a semiconductor device, a method for controlling a semiconductor device, and a control program suitable for achieving high-quality operation. Background Art

[0004] In general, an image sensor includes at least a plurality of pixels; a comparison circuit that compares a pixel signal (measurement signal) indicating a potential corresponding to the amount of light received by the pixel with a ramp signal; and a counter circuit that counts a period from when the comparison circuit starts comparing the pixel signal and the ramp signal to when the pixel signal and the ramp signal match. The count value of the counter circuit is used as a digital signal obtained by AD conversion of the pixel signal.

[0005] The disclosed techniques are listed below.

[0006] [Non-Patent Literature 1] F. Morishita et al., “30.2-μVrms Horizontal Fringe Noise 8.3-Megapixel 60 Frames / Second CMOS Image Sensor with Built-in Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Cameras,” IEEE Journal of Solid-State Circuits, Vol. 57, No. 10, October 2022

[0007] For example, Non-Patent Document 1 discloses a technology related to an image sensor. Summary of the invention

[0008] Image sensors are required to obtain high-quality images by suppressing noise. Here, noise is suppressed by repeating the counting operation of the period from the start of the comparison between the pixel signal and the ramp signal by the comparison circuit to the matching between the pixel signal and the ramp signal at high speed multiple times, and averaging the obtained count values.

[0009] However, when the counting operation of the counter circuit is accelerated, the waveform of the plurality of bits representing the count value collapses, so there is a problem that the accuracy of the counting operation of the counter circuit decreases. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] A semiconductor device according to the present disclosure includes a semiconductor chip, wherein the semiconductor chip includes on its surface: a comparator circuit, one terminal of which is input with a measurement signal, and another terminal of which is input with a reference voltage signal whose potential periodically and linearly changes; a counter circuit, a count value of which changes according to a time change of the reference voltage signal; and a latch circuit, which is connected to the comparator circuit and stores the count value of the counter circuit at a timing when an output signal from the comparator circuit changes, wherein the counter circuit includes: a multi-phase signal generator, which shifts the phase of a reference clock signal and generates a plurality of clock signals having phases different from each other; and a plurality of trigger circuits, which are connected to the multi-phase signal generator and are connected to each other in succession, and wherein the plurality of trigger circuits include a first-stage trigger and a second-stage trigger and subsequent triggers, the first-stage trigger receives an inverted signal of an output signal of a trigger in a final stage, and each of the second-stage trigger and subsequent triggers receives an output signal of a trigger in a preceding stage in synchronization with each of the plurality of clock signals, and the output signal of each of the plurality of trigger circuits is output as a count signal of a count value.

[0011] A method for controlling a semiconductor device according to the present disclosure is a method for controlling a semiconductor device including a semiconductor chip, wherein the semiconductor chip includes on its surface: a comparator circuit, one terminal of which is input with a measurement signal, and another terminal of which is input with a reference voltage signal whose potential changes linearly and periodically; a counter circuit, a count value of which changes according to a time change of the reference voltage signal; and a latch circuit, which is connected to the comparator circuit and stores the count value of the counter circuit at a timing when an output signal from the comparator circuit changes, wherein the counter circuit includes: a multi-phase signal generator, which shifts the phase of a reference clock signal and generates a plurality of clock signals having different phases from each other; and a plurality of trigger circuits, which are connected to the multi-phase signal generator and are connected in series to each other, and wherein the plurality of trigger circuits include a first-stage trigger, a second-stage trigger, and subsequent triggers, the first-stage trigger receiving an output signal of the trigger in the final stage an inverted signal, and each of the second-stage trigger and the subsequent trigger receives the output signal of the trigger in the previous stage synchronously with each of the multiple clock signals, and the output signal of each of the multiple trigger circuits is output as a counting signal of a counting value, the method comprising: causing the comparator circuit to compare the black signal as a black pixel signal with the reference voltage signal; causing the latch circuit to latch a first counting value, which is the counting value of the counter circuit within a period from the start of the comparison between the black signal and the reference voltage signal at the comparator circuit to the matching between the black signal and the reference voltage signal; causing the comparator circuit to compare the pixel signal as a measurement signal with the reference voltage signal; causing the latch circuit to latch a second counting value, which is the counting value of the counter circuit within a period from the start of the comparison between the pixel signal and the reference voltage signal at the comparator circuit to the matching between the pixel signal and the reference voltage signal; and processing the difference between the second counting value and the first counting value as a digital signal corresponding to the pixel signal.

[0012] The control program according to the present disclosure is a control program that causes a computer to perform control processing in a semiconductor device, the semiconductor device including a semiconductor chip, wherein the semiconductor chip includes on its surface: a comparator circuit, one terminal of which is input with a measurement signal, and another terminal of which is input with a reference voltage signal whose potential changes linearly and periodically; a counter circuit, the count value of which changes according to the time change of the reference voltage signal; and a latch circuit, which is connected to the comparator circuit and stores the count value of the counter circuit at the timing when the output signal from the comparator circuit changes, wherein the counter circuit includes: a multi-phase signal generator, which shifts the phase of a reference clock signal and generates a plurality of clock signals having different phases from each other; and a plurality of trigger circuits, which are connected to the multi-phase signal generator and are connected in series to each other, and wherein the plurality of trigger circuits include a first-stage trigger and a second-stage trigger and subsequent triggers, the first-stage trigger receiving the inverse of the output signal of the trigger in the final stage signal, and each of the second-stage trigger and the subsequent trigger receives the output signal of the trigger in the previous stage in synchronization with each of the multiple clock signals, and the output signal of each of the multiple trigger circuits is output as a count signal of a count value, and the control program causes the computer to perform the following processing: causes the comparator circuit to compare the black signal as a black pixel signal with the reference voltage signal; causes the latch circuit to latch a first count value, which is the count value of the counter circuit within a time period from the start of the comparison between the black signal and the reference voltage signal at the comparator circuit to the match between the black signal and the reference voltage signal; causes the comparator circuit to compare the pixel signal as a measurement signal with the reference voltage signal; causes the latch circuit to latch a second count value, which is the count value of the counter circuit within a time period from the start of the comparison between the pixel signal and the reference voltage signal at the comparator circuit to the match between the pixel signal and the reference voltage signal; and processes the difference between the second count value and the first count value as a digital signal corresponding to the pixel signal.

[0013] The present disclosure can provide a semiconductor device capable of achieving high-quality operation, a method for controlling the semiconductor device, and a control program. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing a configuration example of an image sensor according to the first embodiment.

[0015] Figure 2 is a block diagram showing the configuration of components of the image sensor according to the first embodiment more specifically.

[0016] Figure 3is a block diagram showing a configuration example of a counter circuit provided in the image sensor according to the first embodiment.

[0017] Figure 4 : is a schematic diagram showing a first configuration example of a four-phase clock signal generating circuit provided in the counter circuit according to the first embodiment.

[0018] Figure 5 It is shown Figure 4 The timing diagram of the operation of the four-phase clock signal generating circuit is shown.

[0019] Figure 6 : is a schematic diagram showing a second configuration example of the four-phase clock signal generating circuit provided in the counter circuit according to the first embodiment.

[0020] Figure 7 It is shown in Figure 6 Schematic diagram of a configuration example of a clock signal output circuit provided in a four-phase clock signal generating circuit shown.

[0021] Figure 8 It is shown Figure 6 and Figure 7 The timing diagram of the operation of the four-phase clock signal generating circuit is shown.

[0022] Fig. 9 : is a block diagram showing a first configuration example of a phase shift counter provided in the counter circuit according to the first embodiment.

[0023] Fig.10 : is a block diagram showing a second configuration example of the phase shift counter provided in the counter circuit according to the first embodiment.

[0024] Fig.11 is a timing chart showing the overall operation of the counter circuit according to the first embodiment.

[0025] Fig.12 is a timing chart showing the operation of the image sensor according to the second embodiment.

[0026] Fig.13 is a block diagram showing a configuration example of an image sensor that was preliminarily studied.

[0027] Fig.14 More specifically, Fig.13 A block schematic diagram showing the configuration of components of an image sensor.

[0028] Fig.15 It is shown in Fig.13 A schematic diagram of a configuration example of a ramp signal generating circuit provided in an image sensor shown in FIG.

[0029] Fig.16 It is shown in Fig.13 A block diagram of a configuration example of a counter circuit provided in an image sensor shown.

[0030] Fig.17 It is shown by Fig.13 FIG. 2 is a timing chart of a first example of an AD conversion process performed by an image sensor shown in FIG.

[0031] Fig.18 Is used to describe Fig.13 FIG. 1 is a schematic diagram of a problem of a first example of AD conversion processing of an image sensor.

[0032] Fig.19 It is shown by Fig.13 FIG. 2 is a timing chart of a second example of the AD conversion process performed by the image sensor shown.

[0033] Fig. 20 Is used to describe Fig.13 FIG. 1 is a schematic diagram of a problem of a second example of AD conversion processing of an image sensor.

[0034] Fig.21 It is shown by Fig.13 FIG. 2 is a timing chart of a third example of the AD conversion process performed by the image sensor shown.

[0035] Fig. 22 Is used to describe Fig.13 A schematic diagram of a third operating problem of the image sensor is shown. DETAILED DESCRIPTION

[0036] Hereinafter, the embodiment will be described with reference to the accompanying drawings. Since the accompanying drawings are simplified, the technical scope of the embodiment should not be narrowly interpreted based on the description of the accompanying drawings. In addition, the same elements are represented by the same reference numerals, and redundant descriptions will be omitted.

[0037] In the following embodiments, for convenience, the description is divided into multiple sections or embodiments when necessary. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed description, supplementary description, etc. of another. In addition, in the following embodiments, when the number of elements, etc. (including the number of pieces, numerical values, numbers, ranges, etc.) is mentioned, the number is not limited to a specific number unless otherwise specified or is obviously limited to the specific number in principle, and the number may be equal to or greater than the specific number, or may be equal to or less than the specific number.

[0038] In addition, in the following embodiments, components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of components, etc., unless otherwise specified or considered to be obviously different in principle, those that are substantially similar or similar to the shapes, etc. are included. The same applies to the above-mentioned numbers, etc. (including the number of pieces, values, amounts, ranges, etc.).

[0039] <Preliminary Study by the Inventor>

[0040] First, an image sensor preliminarily studied by the present inventors will be described. Fig.13 is a block diagram showing a configuration example of the image sensor 50 that is preliminarily studied. Fig.14 2 is a block diagram showing the configuration of components of the image sensor 50 in more detail.

[0041] like Fig.13 and Fig.14 As shown, the image sensor 50 includes at least a plurality of pixels 51 arranged in a matrix form, a plurality of comparison circuits 52 corresponding to the number of columns of the plurality of pixels 51, a plurality of latch circuits 53 corresponding to the number of columns of the plurality of pixels 51, a counter circuit 54, a ramp signal generating circuit 55, a control circuit 56, and a PLL circuit 57. These circuits are formed on the surface of the semiconductor chip. Note that Fig.13 In the example of , a group of a plurality of comparison circuits 52, a group of a plurality of latch circuits 53, and a counter circuit 54 are arranged in corresponding areas on the upper and lower sides of an area on the surface of a semiconductor chip where a plurality of pixels 51 are formed. A plurality of AD conversion circuits including comparison circuits 52 and latch circuits 53 are arranged along one side of a quadrilateral semiconductor chip. Since the image sensor 50 is provided with several thousand AD converters including comparison circuits 52 and latch circuits 53, each AD converter adopts a simple configuration of a single slope integrated AD converter.

[0042] The ramp signal generating circuit 55 generates a ramp signal (reference voltage signal) RS whose potential changes linearly in a horizontal scanning period (an access period to a plurality of pixels in each row). Here, a case where the ramp signal generating circuit 55 generates a ramp signal RS whose potential decreases linearly in a horizontal scanning period will be described as an example.

[0043] Fig.15 is a schematic diagram showing a configuration example of the ramp signal generating circuit 55. Fig.15As shown, the ramp signal generating circuit 55 includes a DA converter (DAC) 551, an operational amplifier 552 and a resistor element 553. The resistor element 553 is arranged between the non-inverting input terminal of the operational amplifier 552 and the ground voltage terminal, and the ground voltage GND is supplied to the ground voltage terminal. The DA converter 551 converts the digital code input from the outside into an analog voltage. The output voltage of the DA converter 551 is supplied to the non-inverting input terminal of the operational amplifier 552. The output signal of the operational amplifier 552 is fed back to the inverting input terminal of the operational amplifier 552. The operational amplifier 552 amplifies and outputs the potential difference between the voltages supplied to each of the two input terminals. The output voltage of the operational amplifier 522 is not only used as a feedback signal of the inverting input terminal of the operational amplifier 552, but also used as a ramp signal RS. Here, the ramp signal generating circuit 55 generates a ramp signal RS, the potential of which changes linearly with the slope (conversion rate) corresponding to the digital code.

[0044] The PLL circuit 57 generates a reference clock signal CLK. Here, a case where the PLL circuit 57 generates a reference clock signal CLK having a frequency of 1.34 GHz will be described as an example.

[0045] Each comparison circuit 52 compares the pixel signal (measurement signal) VPIX indicating the potential corresponding to the amount of light received by the pixel with the ramp signal RS whose potential decreases linearly within the horizontal scanning period, and outputs a comparison result COUT. For example, when the potential of the ramp signal RS changes from a potential equal to or higher than the pixel signal VPIX to a potential lower than the pixel signal VPIX, each comparison circuit 52 changes (rises) the comparison result COUT from the L level to the H level.

[0046] The counter circuit 54 performs a count-up operation in synchronization with the reference clock signal CLK.

[0047] Each latch circuit 53 latches the count value of the counter circuit 54 at the timing when the comparison result COUT of the corresponding comparison circuit 52 changes from the L level to the H level. That is, each latch circuit 53 latches the count value of the counter circuit 54, which is counted in the period from the start of the comparison between the pixel signal VPIX and the ramp signal RS to the matching between the pixel signal VPIX and the ramp signal RS by the corresponding comparison circuit 52. The latched count value is input to a processing circuit (not shown) as a digital signal obtained by AD conversion of the pixel signal.

[0048] Fig.16is a block diagram showing a configuration example of the counter circuit 54. Here, a case where the counter circuit 54 outputs the count signal CNT_code of a count value substantially corresponding to 12 binary digits represented by a 13-bit value will be described as an example.

[0049] like Fig.16 As shown, the counter circuit 54 includes an LSB counter 541, a binary counter 542, and a binary Gray converter 543. The LSB counter 541 performs an incremental counting operation of a count value LSB[3:0], which substantially corresponds to three binary digits represented by the value of the lower 4 bits of the count value represented by the 13-bit value. The binary counter 542 performs an incremental counting operation on the count value of the binary code represented by the upper 9-bit value of the count value represented by the 13-bit value. The binary Gray converter 543 converts the count value of the binary code output from the binary counter 542 into a count value GC[12:4] of the Gray code. As a result, the change of the bit value associated with the incremental counting operation is reduced, thereby reducing erroneous operations.

[0050] Then, the counter circuit 54 outputs the count signal CNT_code of a 13-bit count value including the count value GC[12:4] and the count value LSB[3:0].

[0051] The control circuit 56 performs overall control of the image sensor 50. Furthermore, the control circuit 56 performs offset removal control in an AD conversion process described later and noise suppression control in an AD conversion process described later.

[0052] Fig.17 is a timing chart showing a first example of AD conversion processing of the image sensor 50. Fig.17 As shown, in the image sensor 50, when the potential of the ramp signal RS changes from a potential equal to or higher than the potential of the pixel signal VPIX to a potential lower than the potential of the pixel signal VPIX, each comparison circuit 52 changes the comparison result COUT from the L level to the H level (time t11). Each latch circuit 53 latches the count value of the counter circuit 54 at the timing when the comparison result COUT of the corresponding comparison circuit 52 changes from the L level to the H level. The latched count value is input to a processing circuit (not shown) as a digital signal obtained by AD conversion of the pixel signal.

[0053] Fig.18 1 is a schematic diagram for describing a problem of a first example of AD conversion processing of the image sensor 50. Fig.18As shown, in the image sensor 50, several thousand AD converters including a comparison circuit 52 and a latch circuit 53 are arranged in columns. Here, in most cases, the power supply to the several thousand AD converters arranged in columns is performed from both ends. For this reason, among the several thousand AD converters arranged in columns, the power supply voltage of the AD converter arranged at the center drops due to the IR drop. For example, assuming that 4096 AD converters are arranged in columns, the power supply voltage VDD supplied to the comparison circuit 52 and the latch circuit 53 constituting the AD converter arranged at the end are 3.0V and 1.2V respectively, and the current consumption of each AD converter is about 10uA, and the power supply voltage VDD supplied to the comparison circuit 52 and the latch circuit 53 constituting the AD converter arranged at the center drops to about 2.9V and 1.1V respectively. In addition, the ground voltage GND of the AD converter arranged at the center rises to about 0.1V.

[0054] Therefore, the inventors studied how Fig.19 The AD conversion process shown. Fig.19 is a timing chart showing a second example of the AD conversion process of the image sensor 50. Fig.19 In the example of FIG. 1 , the offset generated in each AD converter is removed by AD conversion processing of digital correlated double sampling (CDS).

[0055] First, the control circuit 56 causes each comparison circuit 52 and each latch circuit 53 to perform the following processing as the first AD conversion processing. Specifically, each comparison circuit 52 compares the pixel signal VPIX (hereinafter referred to as the black signal VPIX) indicating the potential of the black color that the pixel does not receive light with the ramp signal RS, and outputs the comparison result COUT. For example, when the potential of the ramp signal RS changes from a potential equal to or higher than the black signal VPIX to a potential lower than the black signal VPIX, each comparison circuit 52 changes the comparison result COUT from the L level to the H level (time t21). Each latch circuit 53 latches the count value of the counter circuit 54 at the timing (time t21) when the comparison result COUT of the corresponding comparison circuit 52 changes from the L level to the H level. The latched count value is used as a digital value obtained by AD converting the black signal VPIX. Note that the pixel signal indicating the black potential that the pixel does not receive light is a pixel signal in a state where no external light is incident when the shutter is closed.

[0056] Then, the control circuit 56 causes each comparison circuit 52 and each latch circuit 53 to perform the following processing as a second AD conversion process. Specifically, each comparison circuit 52 compares the pixel signal VPIX indicating the potential corresponding to the amount of light received by the pixel with the ramp signal RS, and outputs the comparison result COUT. For example, when the potential of the ramp signal RS changes from a potential equal to or higher than the pixel signal VPIX to a potential lower than the pixel signal VPIX, each comparison circuit 52 changes the comparison result COUT from the L level to the H level (time t22). Each latch circuit 53 latches the count value of the counter circuit 54 at the timing (time t22) when the comparison result COUT of the corresponding comparison circuit 52 changes from the L level to the H level. The latched count value is used as a digital value obtained by AD converting the pixel signal VPIX.

[0057] Then, the control circuit 56 can obtain the digital value of the pixel signal from which the offset has been removed by subtracting the digital value obtained by AD-converting the black signal VPIX from the digital value obtained by AD-converting the pixel signal VPIX, for each AD converter.

[0058] Fig. 20 1 is a schematic diagram for describing a problem of a second example of AD conversion processing of the image sensor 50. Fig. 20 As shown, when two-stage AD conversion processing is performed to remove the offset, the noise received by the element increases. Note that the noise received by the element mainly includes three types: noise received by the element of the ramp signal generating circuit 55, noise received by the pixel 51, and noise received by the AD converter (comparison circuit 52 and latch circuit 53).

[0059] Here, when the noise (mainly thermal noise) received by the element is Vsd, the noise generated in the first AD conversion process is Vs(t1), and the noise generated in the second AD conversion process is Vs(t2), the effective value Vsd of the noise received by the element is rms It is expressed by the following formula (1).

[0060] Vsd rms = {Vs(t2)-Vs(t1)} rms ...(1)

[0061] Since the corresponding effective values ​​of Vs(t2) and Vs(t1) can be expressed as the same Vs rms , so the following formula (2) is established.

[0062] Vsd rms =√(2×Vs 2 ) rms =√2×Vs rms...(2)

[0063] That is, the noise in the case where two-stage AD conversion processing is performed is √2 times the noise in the case where only one-stage AD conversion processing is performed.

[0064] Therefore, the inventors studied how Fig.21 The AD conversion process shown. Fig.21 is a timing chart showing a third example of the AD conversion process of the image sensor 50. Note that Fig.21 A comparative example is shown on the upper side of FIG.

[0065] exist Fig.21 In the example of FIG. 1 , each AD converter repeats the first AD conversion process n times using the black signal (n is an integer greater than or equal to 2; in Fig.21 4 times in the example of the comparison), and the second AD conversion process is repeated n times using the pixel signal. At this time, the ramp signal generating circuit 55 is adjusted so that the potential change speed (the slope of the potential change) of the ramp signal RS is n times the speed (reference speed) of the comparison example. In addition, the counter circuit 54 is adjusted so that the counting operation is n times the counting operation of the comparison example (reference speed). For each AD converter, by subtracting the average value of the n digital values ​​obtained by AD converting the black signal VPIX n times from the average value of the n digital values ​​obtained by AD converting the pixel signal VPIX n times, the control circuit 56 can obtain the digital value of the pixel signal, in which the noise is suppressed to 1 / (√n) times.

[0066] However, if Fig. 22 As shown, in order to realize the AD conversion processing of the third example at the same processing speed as the second example, the image sensor 50 needs to increase the operating frequency of the reference clock signal CLK by n times (4 times in this example). For example, when the operating frequency of the reference clock signal CLK increases from 1.34 GHz to 5.36 GHz, since the signal line through which the count signal of the counter circuit 54 used in common by a plurality of AD converters propagates is arranged along one side of the quadrilateral semiconductor chip together with the plurality of AD converters, the waveform of the count signal of the counter circuit 54 may collapse due to long-distance transmission. As a result, there is a problem that the image sensor 50 cannot achieve high-quality operation. If a dedicated transmission block using a small-amplitude high-speed I / F or the like is provided, or a repeater circuit is provided at regular intervals in the image sensor 50, in order to solve this problem, current consumption and rotation ratio increase.

[0067] Thus, an image sensor 1 capable of achieving high-quality operation has been found.

[0068] <First Embodiment>

[0069] Figure 12 is a block diagram showing a configuration example of the image sensor 1 . Figure 2 1 is a block diagram showing the configuration of components of the image sensor 1 in more detail.

[0070] like Figure 1 and Figure 2 As shown, the image sensor 1 includes at least a plurality of pixels 11 arranged in a matrix form, a plurality of comparison circuits (comparator circuits) 12 corresponding to the number of columns of the plurality of pixels 11, a plurality of latch circuits 13 corresponding to the number of columns of the plurality of pixels 11, a counter circuit 14, a ramp signal generating circuit 15, a control circuit 16, and a PLL circuit 17. These circuits are formed on the surface of a semiconductor chip. Note that Figure 1 In the example of , a group of a plurality of comparison circuits 12, a group of a plurality of latch circuits 13, and a counter circuit 14 are arranged in respective areas on the upper and lower sides of an area on the surface of a semiconductor chip where a plurality of pixels 11 are formed. A plurality of AD conversion circuits including the comparison circuits 12 and the latch circuits 13 are arranged along one side of a quadrilateral semiconductor chip.

[0071] The ramp signal generating circuit 15 generates a ramp signal RS whose potential changes linearly in a horizontal scanning period (an access period to a plurality of pixels in each row). In the present embodiment, a case where the ramp signal generating circuit 15 generates a ramp signal RS whose potential decreases linearly in a horizontal scanning period will be described as an example. The specific configuration example of the ramp signal generating circuit 15 is the same as that of the ramp signal generating circuit 55, so its description will be omitted.

[0072] The PLL circuit 17 generates a reference clock signal CLK. In the present embodiment, a case where the PLL circuit 17 generates a reference clock signal CLK having a frequency of 1.34 GHz will be described as an example.

[0073] Each comparison circuit 12 compares a pixel signal (measurement signal) VPIX indicating a potential corresponding to the amount of light received by a pixel with a ramp signal RS whose potential decreases linearly within a horizontal scanning period, and outputs a comparison result COUT. For example, when the potential of the ramp signal RS changes from a potential equal to or higher than the pixel signal VPIX to a potential lower than the pixel signal VPIX, each comparison circuit 12 changes (rises) the comparison result COUT from an L level to an H level.

[0074] The counter circuit 14 performs a count-up operation in synchronization with the reference clock signal CLK.

[0075] Each latch circuit 13 latches the count value of the counter circuit 14 at the timing when the comparison result COUT of the corresponding comparison circuit 12 changes from the L level to the H level. That is, each latch circuit 13 latches the count value of the counter circuit 14, which is counted in the period from the start of the comparison between the pixel signal VPIX and the ramp signal RS to the matching between the pixel signal VPIX and the ramp signal RS by the corresponding comparison circuit 12. The latched count value is input to a processing circuit (not shown) as a digital signal obtained by AD conversion of the pixel signal.

[0076] The control circuit 16 performs overall control of the image sensor 1. Furthermore, the control circuit 16 performs control for offset removal in AD conversion processing and control for noise suppression in AD conversion processing.

[0077] (Configuration Example of Counter Circuit 14)

[0078] Figure 3 : is a block diagram showing a configuration example of the counter circuit 14. In the present embodiment, a case where the counter circuit 14 outputs the count signal CNT_code of a count value of approximately 12 binary digits represented by a 13-bit value will be described as an example.

[0079] like Figure 3 As shown, the counter circuit 14 includes a multi-phase clock signal generating circuit (multi-phase signal generator) 141, a phase shift counter (low-bit counter) 142, a CML / CMOS converter (level conversion circuit) 143, a binary counter (high-bit counter) 144 and a binary Gray converter (code conversion circuit) 145.

[0080] The multi-phase clock signal generating circuit 141 and the phase shift counter 142 are each configured using a current mode logic (CML) circuit. As a result, in the multi-phase clock signal generating circuit 141 and the phase shift counter 142, the collapse (wraparound) of the signal waveform is suppressed. The other circuits of the image sensor 1 are not particularly limited, but are basically configured using a complementary metal oxide semiconductor (CMOS) circuit.

[0081] The multi-phase clock signal generating circuit 141 generates four clock signals CLK1 to CLK4 having different phases from the reference clock signal CLK. The frequency of each of the clock signals CLK1 to CLK4 is 1.34 GHz, which is the same as the frequency of the reference clock signal CLK.

[0082] (First Configuration Example of Multi-Phase Clock Signal Generating Circuit 141)

[0083] Figure 41 is a schematic diagram showing a first configuration example of the multi-phase clock signal generating circuit 141 as the multi-phase clock signal generating circuit 141a. Figure 4 As shown, the multi-phase clock signal generating circuit 141 a includes a buffer BF11 , delay circuits DL1 to DL4 , a phase comparator (PFD: Phase Frequency Detector) 1411 , a charge pump (CP: Charge Pump) 1412 , and a low pass filter (LPF: Low Pass Filter) 1413 .

[0084] The buffer BF11 outputs a reference clock signal CLK supplied from the outside. The delay circuits DL1 to DL4 are cascade-connected, and output clock signals CLK1 to CLK4 obtained by delaying the reference clock signal CLK by different delay amounts. The phase comparator 1411 compares the phase of the reference clock signal CLK with the phase of the output signal of the final-stage delay circuit DL4, and outputs a comparison result UP or DN. The charge pump 1412 outputs a current Icp corresponding to the comparison result UP or DN of the phase comparator 1411. The low-pass filter 1413 filters the voltage generated based on the output current Icp of the charge pump 1412, and outputs a driving voltage Vcnt of the delay circuits DL1 to DL4.

[0085] Figure 5 1 is a timing chart showing the operation of the multi-phase clock signal generating circuit 141a. Figure 4 and Figure 5 As shown, the delay amount of each of the delay circuits DL1 to DL4 is, for example, 186.6 ps. Therefore, the multi-phase clock signal generating circuit 141a generates clock signals CLK1 to CLK4 that are offset from each other by a 1 / 4 period of the reference clock signal CLK.

[0086] (Second Configuration Example of Multi-Phase Clock Signal Generating Circuit 141)

[0087] Figure 6 1 is a schematic diagram showing a second configuration example of the multi-phase clock signal generating circuit 141 as the multi-phase clock signal generating circuit 141b. Figure 6 As shown, the multi-phase clock signal generating circuit 141 b includes an inverter INV21 , a buffer BF21 , frequency dividing circuits DIV21 and DIV22 , integrators INT21 to INT24 , and a clock signal output circuit 1415 .

[0088] Inverter INV21 outputs an inverted signal of the reference clock signal CLK. Buffer BF21 outputs a normal signal of the reference clock signal CLK. Frequency division circuit DIV21 divides the output signal of inverter INV21 (the inverted signal of the reference clock signal CLK) by 2, and outputs a frequency division signal Q1 and its inverted signal QB1. Frequency division circuit DIV22 divides the output signal of buffer BF21 (the normal signal of the reference clock signal CLK) by 2, and outputs a frequency division signal Q2 and its inverted signal QB2. Integrator INT21 performs integration processing on the frequency division signal Q1, and outputs an integration result M1 (=φ180). Integrator INT22 performs integration processing on the frequency division signal Q2, and outputs an integration result M2 (=φ540). Integrator INT23 performs integration processing on the frequency division signal Q3, and outputs an integration result M3 (=φ0). Integrator INT24 performs integration processing on the frequency division signal Q4, and outputs an integration result M4 (=φ360). The clock signal output circuit 1415 generates and outputs clock signals CLK1 to CLK4 based on the integration results M1 to M4 of the integrators INT21 to INT24 .

[0089] Figure 7 14 is a schematic diagram showing a configuration example of a clock signal output circuit 1415 provided in a multi-phase clock signal generating circuit 141b. Figure 8 is a timing chart showing the operation of the multi-phase clock signal generating circuit 141b.

[0090] like Figure 7 As shown, the clock signal output circuit 1415 includes inverters INV31 to INV33, INV41 to INV43, INV51 to INV53, and INV61 to INV63, and capacitive elements C31, C41, C51, and C61.

[0091] Inverter INV31 outputs the inverted signal of the integration result M3. Inverter INV32 outputs the inverted signal of the integration result M3. Capacitive element C31 is arranged between the input terminal and the ground voltage terminal of inverter INV33, and the ground voltage GND is supplied to the ground voltage terminal. The charge of the corresponding output signal of inverter INV31 and INV32 is accumulated in the capacitive element C31. When the voltage corresponding to the charge accumulated in the capacitive element C31 is equal to or higher than the threshold voltage Vt, the inverter (logic circuit) INV33 outputs the clock signal CLK1 of the L level, and when the voltage is lower than the threshold voltage Vt, the clock signal CLK1 of the H level is output.

[0092] Inverter INV41 outputs the inverted signal of the integration result M3. Inverter INV42 outputs the inverted signal of the integration result M1. Capacitive element C41 is arranged between the input terminal and the ground voltage terminal of inverter INV43, and the ground voltage GND is supplied to the ground voltage terminal. The charge of the corresponding output signal of inverter INV41 and INV42 is accumulated in the capacitive element C41. When the voltage corresponding to the charge accumulated in the capacitive element C41 is equal to or higher than the threshold voltage Vt, the inverter (logic circuit) INV43 outputs the clock signal CLK2 of the L level, and when the voltage is lower than the threshold voltage Vt, the clock signal CLK2 of the H level is output.

[0093] Inverter INV51 outputs the inverted signal of the integration result M1. Inverter INV52 outputs the inverted signal of the integration result M1. Capacitive element C51 is arranged between the input terminal of inverter INV53 and the ground voltage terminal, and the ground voltage GND is supplied to the ground voltage terminal. The charge of the corresponding output signal of inverter INV51 and INV52 is accumulated in the capacitive element C51. When the voltage corresponding to the charge accumulated in the capacitive element C51 is equal to or higher than the threshold voltage Vt, the inverter (logic circuit) INV53 outputs the clock signal CLK3 of the L level, and when the voltage is lower than the threshold voltage Vt, the clock signal CLK3 of the H level is output.

[0094] Inverter INV61 outputs the inverted signal of the integration result M1. Inverter INV62 outputs the inverted signal of the integration result M4. Capacitive element C61 is arranged between the input terminal of inverter INV63 and the ground voltage terminal, and the ground voltage GND is supplied to the ground voltage terminal. The charge of the corresponding output signal of inverters INV61 and INV62 is accumulated in the capacitive element C61. When the voltage corresponding to the charge accumulated in the capacitive element C61 is equal to or higher than the threshold voltage Vt, the inverter (logic circuit) INV63 outputs the clock signal CLK4 of the L level, and when the voltage is lower than the threshold voltage Vt, the clock signal CLK4 of the H level is output.

[0095] The phase shift counter 142 performs an increment count operation on a 3-bit count value JC[3:0] which is basically binary and is represented by the value of the lower 4 bits of the count value represented by the 13-bit value. Here, the phase shift counter 142 performs an increment count operation of the count value JC[3:0] represented by the value of the lower 4 bits by selectively changing any one of the values ​​of the lower 4 bits that change synchronously with each of the clock signals CLK1 to CLK3. Therefore, when the operating frequency of the reference clock signal CLK is 1.34 GHz, the operating frequency of the lower 4-bit count signal representing the count value JC[3:0] is suppressed to 670 MHz (=5.36 GHz / 8). Therefore, the collapse of the waveform of the lower 4-bit count signal representing the count value JC[3:0] due to long-distance transmission can be suppressed.

[0096] (First Configuration Example of Phase Shift Counter 142)

[0097] Fig. 9 2 is a schematic diagram showing a first configuration example of the phase shift counter 142 as the phase shift counter 142 a.

[0098] like Fig. 9 As shown, the phase shift counter 142a includes four D flip-flops FF11 to FF14. The D flip-flops FF12 to FF14 receive the output signals of the D flip-flops FF11 to FF13 in the front stage synchronized with the clock signals CLK2 to CLK4, respectively, and output the results. The D flip-flop FF11 receives the inverted signal of the output signal of the D flip-flop FF14 in the final stage in synchronization with the clock signal CLK1, and outputs the result. Note that, except for the D flip-flop FF14 in the final stage of the D flip-flops FF11 to FF13, the inverted output terminal QB of the D flip-flops FF11 to FF14 is not connected to any other D flip-flops. Then, the phase shift counter 142a outputs the output signal of the D flip-flop FF11 to FF14 as the count signals of the count values ​​JC[0], JC[1], JC[2] and JC[3], respectively.

[0099] (Second Configuration Example of Phase Shift Counter 142)

[0100] Fig.10 2 is a schematic diagram showing a second configuration example of the phase shift counter 142 as the phase shift counter 142 b.

[0101] like Fig.10As shown, the phase shift counter 142b includes four JK flip-flops FF21 to FF24. The JK flip-flops FF22 to FF24 receive the output signals of the JK flip-flops FF21 to FF23 in the previous stage and their inverted signals at input terminals J and K, respectively, in synchronization with the clock signals CLK2 to CLK4. The JK flip-flop FF21 receives the output signal of the JK flip-flop FF24 in the final stage and their inverted signals at input terminals J and K, in synchronization with the clock signal CLK1. Then, the phase shift counter 142b outputs the output signals (Q) of the JK flip-flops FF21 to FF24 as count signals of the count values ​​JC[0], JC[1], JC[2], and JC[3], respectively.

[0102] It should be noted that in the present embodiment, as an example, the case where the phase shift counter 142 performs an increment count operation on the count value JC[3:0] represented by the value of the lower 4 bits of the count value represented by the 13-bit value has been described, but the present invention is not limited thereto. The phase shift counter 142 may be configured to perform an increment count operation on the count value represented by the value of the lower 2 bits or more bits of the count value represented by the 13-bit value or the count value represented by all 13-bit values. In this case, the number of flip-flops provided in the phase shift counter 142 is a number corresponding to the number of bits used to represent the count value.

[0103] The CML / CMOS converter 143 converts the output signal of the phase shift counter 142 (the count signal of the count value JC[3:0]) from the level of the CML circuit to the level of the CMOS circuit. That is, the counter circuit 14 converts the count signal of the count value JC[3:0] output from the phase shift counter 142 into the CMOS level using the CML / CMOS converter 143, and then outputs the CMOS level. As a result, the collapse of the waveform of the lower 4-bit count signal is further suppressed.

[0104] The binary counter 144 performs an up-counting operation on the count value of the binary code represented by the upper 9-bit value of the count value represented by the 13-bit value. In other words, the binary counter 144 counts up the count value of the binary code represented by the upper 9-bit value of the count value represented by the 13-bit value based on the count value of the lower bit (the carry of the count value of the lower bit).

[0105] The binary Gray code converter 145 converts the count value of the binary code output from the binary counter 144 into the count value GR[12:4] of the Gray code. When the operating frequency of the reference clock signal CLK is 1.34 GHz, the operating frequency of the upper 9-bit count signal representing the count value GR[12:4] is 167 MHz (=5.36 GHz / 32). Here, in the Gray code, only the value of any one bit of the 9-bit count value GR[12:4] changes due to a code change, thereby reducing erroneous operations.

[0106] Then, the counter circuit 14 outputs a count signal CNT_code of a 13-bit count value including the count value GR[12:4] and the count value JC[3:0].

[0107] Fig.11 1 is a timing chart showing the overall operation of the counter circuit 14. Fig.11 As shown, the operating frequency of the clock signals CLK1 to CLK4 generated inside the counter circuit 14 is 1.34 GHz, which is the same as the operating frequency of the reference clock signal CLK. In addition, the operating frequency of the 13-bit count signal representing the count value of the counter circuit 14 is less than the operating frequency of the reference clock signal CLK. However, the counter circuit 14 can implement the counting operation at an operating frequency of 5.36 GHz, which is 4 times the operating frequency of the reference clock signal CLK. That is, the counter circuit 14 can implement a high-speed counting operation without accelerating the reference clock signal CLK or accelerating the internal operation. In addition, the counter circuit 14 can thereby implement the counting operation without collapsing the waveform of the count signal. In other words, the counter circuit 14 can implement a high-speed and high-quality counting operation. In addition, in the counter circuit 14, the shapes of the signal waveforms of each of the 13 bits are not very different from each other, so differential nonlinearity (DNL) degradation is suppressed.

[0108] For example, the image sensor 1 performs the following Fig.21 Specifically, in the image sensor 1, each AD converter repeats the first AD conversion process n (n is an integer greater than or equal to 2; in Fig.21 4 times in the example of FIG. 4 ), while repeating the second AD conversion process n times using the pixel signal. For each AD converter, by subtracting the average value of the n digital values ​​obtained by AD converting the black signal VPIX n times from the average value of the n digital values ​​obtained by AD converting the pixel signal VPIX n times, the control circuit 16 can obtain the digital value of the pixel signal, in which the noise is suppressed to 1 / (√n) times. Here, the image sensor 1 can achieve a counter operation equivalent to that at 5.36 GHz without increasing the operating frequency of the reference clock signal CLK of 1.34 GHz by 4 times to 5.36 GHz, thereby making it possible to achieve high-quality operation with suppressed noise without collapsing the waveform of the count signal. In addition, compared with the case where the operating frequency of the reference clock signal CLK is increased by 4 times, the image sensor 1 can significantly reduce power consumption.

[0109] <Second Embodiment>

[0110] Fig.12 is a timing chart showing the operation of the image sensor 1 according to the second embodiment. Fig.12 A comparative example is shown on the upper side of FIG. Fig.12 As shown, in the image sensor 1 according to the second embodiment, each AD converter performs a first AD conversion process once using a black signal, and performs a second AD conversion process once using a pixel signal. For each AD converter, the control circuit 16 can obtain a digital value of the pixel signal from which an offset has been removed by subtracting a digital value obtained by AD-converting the black signal VPIX from a digital value obtained by AD-converting the pixel signal VPIX. Here, the image sensor 1 according to the second embodiment can implement a counter operation equivalent to an operation at 5.36 GHz without increasing the operating frequency of the reference clock signal CLK of 1.34 GHz by 4 times to 5.36 GHz, thereby making it possible to implement high-speed operation without collapsing the waveform of the count signal. Fig.12 In the example of FIG. 5 , the AD conversion process including the first AD conversion and the second AD conversion is shortened from 13.6 us to 9.8 us.

[0111] As described above, the image sensor 1 according to the above-described embodiment and the counter circuit 14 provided in the image sensor 1 can achieve high-quality operation without collapsing the waveform of the count signal even in high-speed operation.

[0112] Although the invention made by the inventors of the present application has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

[0113] In the present embodiment, the case where the multi-phase clock signal generating circuit 141 generates four clock signals CLK1 to CLK4 having a phase different from that of the reference clock signal CLK has been described as an example, but the present invention is not limited thereto. The multi-phase clock signal generating circuit 141 may be configured to generate p (p is an integer greater than or equal to 2) clock signals CLK1 to CLKp having a phase different from that of the reference clock signal CLK according to the bit width representing the count value.

[0114] In addition, in the present embodiment, the case where the counter circuit 14 is applied to the image sensor 1 has been described as an example, but the present invention is not limited thereto. The counter circuit 14 can be applied to various semiconductor devices including an internal circuit that operates based on a count value.

[0115] Furthermore, the present disclosure can be realized by causing a CPU to execute a computer program for part or all of the processing of the image sensor 1 or a semiconductor device to which the counter circuit 14 is applied.

[0116] The above-mentioned program includes a command group (or software code) for causing the computer to execute one or more functions described in the embodiment when read by the computer. The program can be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other storage technology, a CD-ROM, a digital versatile disk (DVD), The program may be transmitted on a transient computer readable medium or communication medium. By way of example and not limitation, a transient computer readable medium or communication medium includes a propagated signal in electrical, optical, acoustic or other form.

Claims

1. A semiconductor device comprising a semiconductor chip, The semiconductor chip includes on a surface of the semiconductor chip: a comparator circuit having one terminal to which a measurement signal is input and another terminal to which a reference voltage signal having a periodic and linearly changing potential is input; a counter circuit, wherein a count value of the counter circuit changes according to a time change of the reference voltage signal; as well as a latch circuit connected to the comparator circuit and storing the count value of the counter circuit at a timing at which an output signal from the comparator circuit changes, The counter circuit comprises: a multi-phase signal generator that shifts the phase of a reference clock signal and generates a plurality of clock signals having phases different from each other; as well as a plurality of trigger circuits connected to the multi-phase signal generator and connected in series with each other, and The multiple trigger circuits include first-stage triggers and second-stage triggers and subsequent triggers, the first-stage trigger receives an inverted signal of an output signal of a trigger in a final stage, and each of the second-stage trigger and subsequent triggers receives an output signal of a trigger in a previous stage in synchronization with each of the multiple clock signals, and the output signal of each of the multiple trigger circuits is output as a count signal of the count value.

2. The semiconductor device according to claim 1, Among the plurality of flip-flop circuits, an inverting output terminal of each flip-flop except the flip-flop in the final stage is not connected to another flip-flop.

3. The semiconductor device according to claim 1, The semiconductor chip includes on a surface of the semiconductor chip: a plurality of comparator circuits; and a plurality of latch circuits corresponding to the plurality of comparator circuits, and A count signal indicating a count value of the common counter circuit is input to the plurality of latch circuits.

4. The semiconductor device according to claim 3, wherein the counter circuit outputs the count signal having a longer period than periods of the plurality of clock signals.

5. The semiconductor device according to claim 4, wherein the semiconductor chip has a quadrilateral shape, and A plurality of signal lines through which the count signal propagates are wired along one side of the quadrilateral semiconductor chip.

6. The semiconductor device according to claim 1, further comprising a reference voltage signal generating circuit that generates the reference voltage signal, wherein the reference voltage signal generating circuit is configured to start a voltage change of the reference voltage signal in synchronization with a start timing of a counting operation by the counter circuit.

7. The semiconductor device according to claim 6, wherein the reference voltage signal generating circuit generates the reference voltage signal, and the voltage change speed of the reference voltage signal is n times (n is an integer greater than or equal to 2) the reference speed, wherein the counter circuit performs a counting operation at a speed n times the reference speed, and The comparator circuit and the latch circuit repeat the AD conversion process of the measurement signal n times.

8. The semiconductor device according to claim 1, wherein the multi-phase signal generator and the counter circuit are both configured using a current mode logic CML circuit, and The semiconductor device further includes a level conversion circuit that converts an output signal of the counter circuit from a level of the CML circuit to a level of a complementary metal oxide semiconductor (CMOS) circuit.

9. The semiconductor device according to claim 1, The multiphase signal generator comprises: a plurality of delay circuits, the plurality of delay circuits delaying the reference clock signal by different delay amounts and outputting the reference clock signal as the plurality of clock signals; a phase comparator that compares the phase of the output signal of the final stage of the plurality of delay circuits with the phase of the reference clock signal; a charge pump, the charge pump outputting a current corresponding to a comparison result of the phase comparator; as well as A filter filters a voltage generated based on an output current of the charge pump and outputs a driving voltage of the plurality of delay circuits.

10. The semiconductor device according to claim 1, The multiphase signal generator comprises: a frequency division circuit, wherein the frequency division circuit divides the reference clock signal to generate a plurality of frequency division signals with different phases; a plurality of integrators, the plurality of integrators performing integration processing on each of the plurality of divided frequency signals; as well as A plurality of logic circuits output the plurality of clock signals of logic values ​​corresponding to each of a plurality of potentials obtained by combining some of the integration results of the plurality of integrators.

11. The semiconductor device according to claim 1, wherein the counter circuit further includes a high-bit counter that performs an up-counting operation based on a count value of a low-bit counter configured by the plurality of flip-flop circuits, and The counter circuit outputs the count signal using the count value of the lower bit counter and the count value of the upper bit counter as the count value of the counter circuit.

12. The semiconductor device according to claim 11, The upper bit counter is a binary counter that performs an up-counting operation based on a count value of the lower bit counter.

13. The semiconductor device according to claim 12, The high-order counter comprises: a binary counter that performs an up-counting operation based on a count value of the lower bit counter; as well as A code conversion circuit converts the count value of the binary counter into a Gray code.

14. The semiconductor device according to claim 1, further comprising a control circuit, The control circuit described herein: causing the comparator circuit to compare a black signal as a black pixel signal with the reference voltage signal, causing the latch circuit to latch a first count value, the first count value being a count value of the counter circuit within a period from the start of comparison between the black signal and the reference voltage signal at the comparator circuit to a match between the black signal and the reference voltage signal, causing the comparator circuit to compare the pixel signal as the measurement signal with the reference voltage signal, causing the latch circuit to latch a second count value, the second count value being a count value of the counter circuit within a period from when comparison between the pixel signal and the reference voltage signal is started at the comparator circuit to when the pixel signal and the reference voltage signal are matched, and A difference between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

15. The semiconductor device according to claim 14, The control circuit described herein: The comparator circuit compares the black signal with the reference voltage signal n times (n is an integer greater than or equal to 2), causing the latch circuit to latch a first count value n times, the first count value being a count value of the counter circuit within a period from the start of comparison between the black signal and the reference voltage signal at the comparator circuit to a match between the black signal and the reference voltage signal, causing the comparator circuit to compare the pixel signal as the measurement signal with the reference voltage signal n times, causing the latch circuit to latch a second count value n times, the second count value being a count value of the counter circuit within a period from the start of comparison between the pixel signal and the reference voltage signal at the comparator circuit to a match between the pixel signal and the reference voltage signal, and An average value of n-times differences between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

16. A method for controlling a semiconductor device, the semiconductor device comprising a semiconductor chip, The semiconductor chip comprises on the surface: a comparator circuit, a measurement signal being input to one terminal of the comparator circuit and a reference voltage signal whose potential changes linearly and periodically being input to the other terminal of the comparator circuit; a counter circuit, wherein a count value of the counter circuit changes according to a time change of the reference voltage signal; as well as a latch circuit connected to a comparator circuit and storing the count value of the counter circuit at a timing at which an output signal from the comparator circuit changes, The counter circuit comprises: a multi-phase signal generator that shifts the phase of a reference clock signal and generates a plurality of clock signals having different phases from each other; and a plurality of trigger circuits connected to the multi-phase signal generator and connected in series with each other, and wherein the plurality of flip-flop circuits include first-stage flip-flops and second-stage and subsequent flip-flops, the first-stage flip-flops receive an inverted signal of an output signal of a flip-flop in a final stage, and each of the second-stage and subsequent flip-flops receives an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value, The method comprises: causing the comparator circuit to compare a black signal as a black pixel signal with the reference voltage signal; causing the latch circuit to latch a first count value, the first count value being a count value of the counter circuit within a period from when comparison between the black signal and the reference voltage signal is started at the comparator circuit to when the black signal and the reference voltage signal are matched; causing the comparator circuit to compare the pixel signal as the measurement signal with the reference voltage signal; causing the latch circuit to latch a second count value, the second count value being a count value of the counter circuit within a period from the start of comparison between the pixel signal and the reference voltage signal at the comparator circuit to a match between the pixel signal and the reference voltage signal; and A difference between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

17. The method for controlling a semiconductor device according to claim 16, further comprising: The comparator circuit compares the black signal with the reference voltage signal n times (n is an integer greater than or equal to 2); causing the latch circuit to latch a first count value n times, the first count value being a count value of the counter circuit within a period from the start of comparison between the black signal and the reference voltage signal at the comparator circuit to a match between the black signal and the reference voltage signal; causing the comparator circuit to compare the pixel signal as the measurement signal with the reference voltage signal n times; causing the latch circuit to latch a second count value n times, the second count value being a count value of the counter circuit within a period from the start of comparison between the pixel signal and the reference voltage signal at the comparator circuit to a match between the pixel signal and the reference voltage signal; as well as An average value of n-times differences between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

18. A control program for causing a computer to execute a control process in a semiconductor device, the semiconductor device comprising a semiconductor chip, The semiconductor chip includes on a surface of the semiconductor chip: a comparator circuit having one terminal to which a measurement signal is input and another terminal to which a reference voltage signal having a periodic and linearly changing potential is input; a counter circuit, wherein a count value of the counter circuit changes according to a time change of the reference voltage signal; as well as a latch circuit connected to a comparator circuit and storing the count value of the counter circuit at a timing at which an output signal from the comparator circuit changes, The counter circuit comprises: a multi-phase signal generator that shifts the phase of a reference clock signal and generates a plurality of clock signals having different phases from each other; and a plurality of trigger circuits connected to the multi-phase signal generator and connected in series with each other, and wherein the plurality of flip-flop circuits include first-stage flip-flops and second-stage flip-flops and subsequent flip-flops, the first-stage flip-flops receiving an inverted signal of an output signal of a flip-flop in a final stage, and each of the second-stage flip-flops and subsequent flip-flops receiving an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits being output as a count signal of the count value, The control program causes the computer to execute the following processing: causing the comparator circuit to compare a black signal as a black pixel signal with the reference voltage signal; causing the latch circuit to latch a first count value, the first count value being a count value of the counter circuit within a period from when comparison between the black signal and the reference voltage signal is started at the comparator circuit to when the black signal and the reference voltage signal are matched; causing the comparator circuit to compare the pixel signal as the measurement signal with the reference voltage signal; causing the latch circuit to latch a second count value, the second count value being a count value of the counter circuit within a period from the start of comparison between the pixel signal and the reference voltage signal at the comparator circuit to a match between the pixel signal and the reference voltage signal; and A difference between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

19. The control program according to claim 18 causes a computer to execute the following processing: The comparator circuit compares the black signal with the reference voltage signal n times (n is an integer greater than or equal to 2); causing the latch circuit to latch a first count value n times, the first count value being a count value of the counter circuit within a period from the start of comparison between the black signal and the reference voltage signal at the comparator circuit to a match between the black signal and the reference voltage signal; causing the comparator circuit to compare the pixel signal as the measurement signal with the reference voltage signal n times; causing the latch circuit to latch a second count value n times, the second count value being a count value of the counter circuit within a period from the start of comparison between the pixel signal and the reference voltage signal at the comparator circuit to a match between the pixel signal and the reference voltage signal; as well as An average value of n-times differences between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

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