Field effect transistor including electrode trench structure

Abstract

The FET includes a semiconductor substrate having mesas arranged between electrode trench structures along a first lateral direction. The FET also includes a recess contact extending from a top surface of the mesa into the mesa. The recess contact bottom is located at a first vertical reference level. The mesa includes a source region of a first conductivity type, a body structure of a second conductivity type, and a drift region of the first conductivity type. The drift region and the body structure form a pn junction. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, a doping concentration of the body structure increases along the first lateral direction from the electrode trench structure to a center of the mesa by 5 to 100 times. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level, a first vertical distance from the first reference level.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a field effect transistor (FET) including an electrode trench structure and a method for manufacturing the same. Background Art

[0002] The technological development of new generations of semiconductor devices, such as field effect transistors (FETs), aims to improve the characteristics of electronic devices and reduce costs by reducing the device geometry. Although cost can be reduced by reducing the device geometry, various trade-offs and challenges must be met when increasing the device functionality per unit area. For example, the area-specific on-resistance R is affected by, for example, avalanche breakdown behavior. on The trade-off between xA and reliability requirements requires design optimization.

[0003] Therefore, there is a need for an improved field effect transistor. Summary of the invention

[0004] An example of the present disclosure relates to a field effect transistor FET. The FET includes a semiconductor substrate having a table arranged between electrode groove structures along a first lateral direction. The FET also includes a groove contact extending from the top surface of the table to the table. The bottom of the groove contact is located at a first vertical reference level. The table includes a source region of a first conductivity type, a main structure of a second conductivity type, and a drift region of the first conductivity type. The drift region forms a pn junction with the main structure. The pn junction has a minimum vertical distance to the top surface of the table at a second vertical reference level, and has a maximum vertical distance to the top surface of the table at a third vertical reference level. At a fourth vertical reference level, the doping concentration of the main structure increases from the electrode groove structure to the center of the table along the first lateral direction to 5 to 100 times. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level, and is a first vertical distance from the first reference level. The first vertical distance is 1.5 to 10 times the second vertical distance from the fourth vertical reference level to the second vertical reference level.

[0005] Another example of the present disclosure relates to a method for manufacturing a field effect transistor (FET). The method includes forming a mesa in a semiconductor substrate arranged between electrode trench structures along a first lateral direction. The method also includes forming a groove contact extending from the top surface of the mesa into the mesa. The bottom of the groove contact is located at a first vertical reference level. The method also includes forming a source region of a first conductivity type in the mesa. The method also includes forming a main structure of a second conductivity type in the mesa. The method also includes forming a drift region of the first conductivity type in the mesa. The drift region forms a pn junction with the main structure. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, the doping concentration of the main structure increases from the electrode trench structure to the center of the mesa along the first lateral direction to 5 to 100 times. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level, and is a first vertical distance from the first reference level. The first vertical distance is 1.5 to 10 times the second vertical distance from the fourth vertical reference level to the second vertical reference level.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate examples of FETs and together with the description serve to explain the principles of these examples. Further examples are described in the detailed description and claims below.

[0008] Figure 1A is a schematic cross-sectional view for illustrating a configuration example of a FET including a recess contact and a body structure.

[0009] Figure 1B is a schematic graph illustrating an exemplary doping concentration profile of the body structure along a lateral direction at a fourth vertical reference level.

[0010] Figure 2 is a schematic graph illustrating an exemplary doping concentration profile of a host structure along a vertical direction at a center of a mesa.

[0011] Figure 3 is a schematic cross-sectional view for illustrating a configuration example of a FET including an electrode trench structure having a gate electrode and a field electrode.

[0012] Figures 4A to 4D is a schematic cross-sectional view for illustrating process features for manufacturing a FET including a recessed contact and a body structure. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form part of the description and in which specific examples of FETs are illustrated by way of illustration. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used in conjunction with other examples to produce yet another example. The present disclosure is intended to include such modifications and variations. Specific language is used to describe these examples, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustration purposes only. If not otherwise specified, corresponding elements are designated by the same reference numerals in different drawings.

[0014] The terms "having", "containing", "including", "comprising", etc. are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0015] The term "electrically connected" may describe a permanent low resistance connection between electrically connected elements, such as direct contact between the associated elements or a low resistance connection via metal and / or heavily doped semiconductor material. The term "electrically coupled" may include that one or more intermediate elements suitable for signal and / or power transmission may be connected between electrically coupled elements, such as an element controllable to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.

[0016] Ranges given for physical dimensions may include boundary values. For example, a range of parameter y from a to b is understood as a≤y≤b. The same applies to ranges with a boundary value, such as "at most" and "at least".

[0017] The terms “on” and “over” should not be interpreted as meaning only “directly on” and “directly over.” Rather, if an element is positioned “on” or “over” another element (e.g., a layer is “on” or “over” another layer, or is “on” or “over” a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., if a layer is “on” or “over” a substrate, another layer may be positioned between the layer and the substrate).

[0018] An example of the present disclosure relates to a field effect transistor FET. The FET includes a semiconductor substrate having a table arranged between electrode groove structures along a first lateral direction. The FET also includes a groove contact extending from the top surface of the table into the table. The bottom of the groove contact is located at a first vertical reference level. The table includes a source region of a first conductivity type, a main structure of a second conductivity type, and a drift region of the first conductivity type. The drift region forms a pn junction with the main structure. The pn junction has a minimum vertical distance to the top surface of the table at a second vertical reference level, and has a maximum vertical distance to the top surface of the table at a third vertical reference level. At a fourth vertical reference level, the doping concentration of the main structure can increase from the electrode groove structure toward the center of the table along the first lateral direction to 5 to 100 times. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level, and is a first vertical distance from the first reference level. The first vertical distance can be 1.5 to 10 times the second vertical distance from the fourth vertical reference level to the second vertical reference level.

[0019] The first conductivity type may be n-type, and the second conductivity type may be p-type. For example, in this case, the FET is an n-channel FET. The first conductivity type may also be p-type, and the second conductivity type may be n-type. For example, in this case, the FET is a p-channel FET.

[0020] For example, the FET may be a lateral FET. In a lateral FET, the direction of flow of the load current is a lateral direction, and the source region and the drain region are separated from each other along the lateral direction. For example, the lateral FET may be a lateral trench FET, such as a lateral trench metal oxide semiconductor field effect transistor, a lateral trench MOSFET. The FET may also be a vertical FET. In a vertical FET, the direction of flow of the load current is a vertical direction, and the source region and the drain region are separated from each other along the vertical direction. For example, the source region may be electrically connected to a source electrode on a first surface of a semiconductor substrate, and the drain region may be electrically coupled to a drain electrode on a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface.

[0021] For example, a FET may be part of an integrated circuit, or may be a discrete semiconductor device or semiconductor module. For example, a FET may be implemented monolithically using a hybrid technology. This hybrid technology may be used, for example, to form analog circuit blocks in a chip by bipolar devices included in the technology to provide an interface to a digital system, and to form digital circuit blocks by complementary metal oxide semiconductor (CMOS) devices included in the technology to provide signal processing, and to form low, medium or high voltage or power blocks by field effect transistors included in the technology. This hybrid technology is known as, for example, bipolar CMOS-DMOS, BCD technology or smart power technology, SPT, and is used in various application areas in the fields of, for example, lighting, motor control, automotive electronics, power management of mobile devices, audio amplifiers, power supplies, hard disks, printers. For example, a FET may be part of a BCD or smart power chip in one of the above application areas.

[0022] The semiconductor substrate may be based on various semiconductor materials, such as silicon (Si), silicon on insulator (SOI), silicon-sapphire (SOS), silicon-germanium, germanium, gallium arsenide, silicon carbide, gallium nitride or other compound semiconductor materials. The semiconductor substrate may be based on a semiconductor base substrate, such as a semiconductor wafer, and may include one or more epitaxial layers deposited thereon and / or may be backside thinned.

[0023] In order to achieve the desired current carrying capacity, the FET can be designed by a plurality of transistor cells connected in parallel. The transistor cells connected in parallel can be, for example, transistor cells formed in the shape of strips or strip segments. Of course, the transistor cells can also have any other shape, such as a circle, an ellipse, a polygon such as a hexagon or an octagon. The transistor cells can be arranged in a transistor cell region of a semiconductor substrate. The transistor cell region can be an active region, in which the source region of the FET is electrically connected to the source electrode. In the active region, the load current can enter or leave the semiconductor substrate of the FET, for example, via a contact plug on the first surface of the semiconductor substrate.

[0024] The semiconductor substrate may have a first surface, which may be a front surface or a top surface of the semiconductor substrate. For example, the first surface may be a surface where a table with a source region is located. For example, the second surface may be a back surface or a rear surface of the semiconductor substrate. For a vertical FET, the second surface may be a surface where a drain is located. For example, the semiconductor substrate may be attached to a lead frame via the second surface. For example, a bonding pad may be arranged above the first surface of the semiconductor substrate, and a bonding wire may be bonded to the bonding pad.

[0025] The source region and the main structure can be electrically connected to the source electrode via a groove contact. For example, the source electrode and the groove contact can be part of a wiring area on the first surface of the semiconductor substrate. The wiring area can include one or more than one, such as two, three, four or even more wiring layers. Each wiring layer can be formed by a single conductive layer or a stack of conductive layers, such as one or more metal layers. For example, the wiring layer can be patterned by photolithography. Between the stacked wiring layers, an interlayer dielectric structure can be arranged. One or more contact plugs or one or more contact lines can be formed in the opening in the interlayer dielectric structure to electrically connect parts of different wiring layers (such as metal lines or contact areas) to each other. The groove contact can provide electrical contact between the active area in the semiconductor substrate and the first wiring layer, and the first wiring layer is the wiring layer closest to the first surface of the semiconductor substrate. The groove contact can include one or more conductive materials and bonding and / or diffusion barrier materials / pads. The source electrode can be formed by one or more elements of the wiring area. Similarly, the FET can further include a drain electrode. The drain electrode can also be formed by one or more elements of the wiring area on the first surface for the lateral FET. For example, the source electrode and the drain electrode may include separate portions of a patterned first wiring layer, such as a first metal layer. In some examples related to lateral FETs, the drain electrode may also be formed above the second surface of the semiconductor substrate. In this case, the drain region of the FET may be electrically connected to the drain electrode via a through contact or trench contact extending at least partially through the semiconductor substrate. In some examples related to vertical FETs, the drain electrode may be formed above the second surface of the semiconductor substrate.

[0026] For example, the drift region may extend from the mesa into a portion of the semiconductor substrate below the electrode trench structure. Among other things, by adjusting the parameters of the drift region, such as the vertical range and / or the doping distribution, the blocking voltage of the FET may be adjusted along a vertical direction perpendicular to the first surface. For example, along the vertical direction, the drift region may become a highly doped drain region or a buried layer region. At least in the portion extending vertically thereof, the doping concentration in the drift region may gradually or stepwise increase or decrease as the distance to the first surface increases. According to other examples, the impurity concentration in the drift region may be approximately uniform in the vertical direction.

[0027] The second vertical reference level may be at or near the electrode trench structure. The third vertical reference level may be at a central region or center of the mesa relative to the first lateral direction. The difference between the second vertical reference level and the third vertical reference level corresponds to the vertical extent of the pn junction in the mesa.

[0028] The main structure of the configuration example described herein is associated with a pn junction between the main structure and the drift region, which has a vertical extension between the second vertical reference level and the third vertical reference level. The bottom or lowest point of the pn junction is in the central region of the mesa. This allows keeping avalanche currents (e.g., holes in the case of n-channel FETs) away from sensitive channel regions at the sidewalls of the electrode trench structure. Avalanche robustness and safe operating area can thereby be improved.

[0029] For example, the main structure may include a superposition of doping concentration distributions of at least a main region, a main contact region, and a main strengthening region. The pn junction at the third vertical reference level may coincide with the intersection between the doping concentration distribution of the main strengthening region and the doping concentration distribution of the drift region along the vertical direction. Therefore, the main strengthening region of the main structure may be a part of the main structure that determines the avalanche breakdown behavior of the position of the hole avalanche current path of the n-channel device. The main region of the main structure may be a part of the main structure that determines the channel behavior (e.g., threshold voltage) in the main structure. For example, the main contact region of the main structure may be a part of the main structure that determines the ohmic contact behavior of the groove contact. By forming the main structure by the superposition of doping concentration distributions of at least the main region, the main contact region, and the main strengthening region, the functional behavior of the FET can be adjusted separately with respect to the threshold voltage, avalanche breakdown robustness, and ohmic contact behavior. In addition, the main strengthening region (and the main contact region) is formed by ion implantation of dopants through the bottom of the groove contacted by the groove, and no separate mask process is required to optimize the avalanche breakdown robustness.

[0030] For example, the maximum concentration of the doping concentration profile of the body contact region may be 5 to 200 times, or 8 to 150 times, the maximum concentration of the doping concentration profile of the body enhancement region. For example, the dopant of the body contact region may be implanted at a higher dose but at a lower energy than the dopant of the body enhancement region.

[0031] For example, the maximum concentration of the doping concentration distribution of the body enhancement region may be 5 to 200 times, or 8 to 150 times, the maximum concentration of the doping concentration distribution of the body region. For example, the dopant of the body enhancement region may be implanted at a higher dose than the dopant of the body region.

[0032] For example, the doping concentration of the main structure at the first vertical reference level at or near the electrode trench structure can be mainly determined by the doping concentration of the main region. This allows the channel behavior of the FET, such as the threshold voltage, to be adjusted by the doping concentration profile of the main region, which dominates the doping concentration of the main structure in the channel region.

[0033] For example, the doping concentration of the body structure at a first vertical reference level at or near the bottom of the recess contact may be determined primarily (eg, more than 50%) by the doping concentration of the body contact region.

[0034] For example, the doping concentration of the body structure at or near the third vertical reference level may be primarily determined by the doping concentration of the body reinforcement region.

[0035] For example, the absolute difference between the second vertical reference level and the third vertical reference level may have a value in the range from 30% to 150% or from 50% to 130% of the absolute difference between the first vertical reference level and the second vertical reference level. This may allow, for example, a beneficial breakdown behavior of the FET.

[0036] For example, the electrode trench structure may include an electrode structure and a dielectric structure. The electrode structure may include a gate electrode and a field electrode. In addition to a single field electrode in the trench, multiple field electrodes may also be arranged in the trench, for example stacked on top of each other in a vertical direction, such that a portion of the dielectric structure is arranged between each pair of field electrodes.

[0037] For example, the dielectric structure may include a gate dielectric portion that electrically isolates the gate electrode from surrounding portions of the semiconductor substrate. For example, the gate dielectric may be an insulating material such as an oxide, e.g., SiO 2 , nitrides such as Si 3 N 4 , a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the dielectric structure may further include a field dielectric that electrically isolates the one or more field electrodes from surrounding portions of the semiconductor substrate. For example, the field dielectric may be an insulating material such as an oxide, e.g., SiO 2 , nitrides such as Si 3 N 4 , a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the field dielectric can be formed as or include a thermal oxide and / or a deposited and annealed oxide. For example, the field dielectric can have a greater thickness than the gate dielectric. The gate electrode and one or more field electrodes can be formed of one or more conductive materials, such as metals, metal silicides, metal compounds, highly doped semiconductor materials, such as highly doped polysilicon. For example, the gate electrode can be a single layer, such as a highly doped polycrystalline layer, or a stack of layers.

[0038] For example, a portion of the dielectric structure may be arranged between the gate electrode and the field electrode. For example, in the case of an n-channel FET, this may allow improved electric field characteristics to keep holes generated during an avalanche breakdown event away from the channel region at the gate electrode.

[0039] For example, the maximum vertical distance can be greater than the vertical distance from the bottom of the gate electrode to the top surface of the mesa. For example, in the case of an n-channel FET, holes generated during an avalanche breakdown event can be kept away from the channel region / gate electrode / gate dielectric.

[0040] For example, the maximum vertical distance may be smaller than the vertical distance from the top of the field electrode to the top surface of the mesa.

[0041] For example, the FET may be a vertical FET having a source electrode on a first surface of the semiconductor substrate. The vertical FET may also have a drain electrode on a second surface of the semiconductor substrate, the second surface being opposite to the first surface.

[0042] Details regarding the structural, functional, or technical benefits of features described above with respect to FETs are equally applicable to the exemplary methods described herein.

[0043] The description and drawings merely illustrate the principles of the present disclosure. In addition, all examples recorded herein are primarily intended to be used for illustrative purposes only, to help readers understand the principles of the present disclosure and the concepts contributed by one or more inventors to promote the art. All statements recording the principles, aspects and examples of the present disclosure and their specific examples herein are intended to include their equivalents.

[0044] It should be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims cannot be interpreted as being in a specific order unless explicitly or implicitly stated otherwise, such as by an expression like "afterwards", for example for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order unless these actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or may be divided into multiple sub-actions, functions, processes, operations or steps respectively. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action. Processing semiconductor substrate wafers for manufacturing FETs may include one or more optional additional features that correspond to one or more aspects mentioned in conjunction with the proposed concepts or one or more examples described above or below.

[0045] An example of the present disclosure relates to a method for manufacturing a field effect transistor (FET). The method includes forming a mesa in a semiconductor substrate arranged between electrode trench structures along a first lateral direction. The method also includes forming a groove contact extending from the top surface of the mesa into the mesa. The bottom of the groove contact is located at a first vertical reference level. The method also includes forming a source region of a first conductivity type in the mesa. The method also includes forming a main structure of a second conductivity type in the mesa. The method also includes forming a drift region of the first conductivity type in the mesa. The drift region forms a pn junction with the main structure. The pn junction has a minimum vertical distance to the top surface of the mesa at a second vertical reference level and a maximum vertical distance to the top surface of the mesa at a third vertical reference level. At a fourth vertical reference level, the doping concentration of the main structure may increase from the electrode trench structure toward the center of the mesa along the first lateral direction to 5 to 100 times. The fourth vertical reference level is located between the second vertical reference level and the first vertical reference level, and is a first vertical distance from the first reference level. The first vertical distance may be 1.5 to 10 times the second vertical distance from the fourth vertical reference level to the second vertical reference level.

[0046] For example, forming the body structure may include forming a superposition of doping concentration profiles of at least the body region, the body contact region, and the body reinforcement region. The pn junction at the third vertical reference level may coincide with an intersection between the doping concentration profile of the body reinforcement region and the doping concentration profile of the drift region along the vertical direction. For example, the doping concentration profile of the body reinforcement region may extend deeper into the mesa region from the top surface than the doping concentration profile of the body region. The doping concentration profile of the body region may extend deeper into the mesa region from the top surface than the doping concentration profile of the body contact region.

[0047] For example, the body region may be formed, for example, by ion implantation of dopants, before forming the recess contacts.

[0048] For example, forming a recessed contact may include forming a recess, for example, by an etching process using an etching mask. Thereafter, forming a body contact region may include introducing a dopant into the semiconductor substrate through a first ion implantation process through the bottom of the recess. Forming a body reinforcement region may include introducing a dopant into the semiconductor substrate through the bottom of the recess by a second ion implantation process. The second ion implantation process may be performed after or before the first ion implantation process. Electrical activation of the dopant in the body contact region and the dopant in the body reinforcement region may be performed by a common thermal annealing process. In other words, the implanted dopants may be activated with the same thermal budget.

[0049] For example, the ion implantation energy of the first ion implantation process may be less than the ion implantation energy of the second ion implantation process. 2When the ion implantation energy of the first ion implantation process is in the range of 3% to 25% of the ion implantation energy of the second ion implantation process.

[0050] The method according to any one of the preceding three claims, wherein an ion implantation dose of the first ion implantation process may be greater than an ion implantation dose of the second ion implantation process.

[0051] The examples and features described above and below may be combined.

[0052] In the following, further examples of field effect transistors FET will be explained in conjunction with the accompanying drawings. The functional and structural details described with respect to the above examples will also apply to the exemplary embodiments illustrated in the accompanying drawings and further described below. In the illustrated examples, for n-channel FETs, the first conductivity type is n-type, and the second conductivity type is p-type. However, for p-channel FETs, the first conductivity type may also be p-type, and the second conductivity type may be n-type.

[0053] Figure 1A A cross-sectional view of a portion of a transistor cell of a FET 100 is shown schematically and exemplarily.

[0054] The FET 100 includes a semiconductor substrate 102. For example, the semiconductor substrate 102 may include a base substrate and an n-doped semiconductor layer on the base substrate, such as an epitaxial layer formed by a layer deposition process.

[0055] The semiconductor substrate 102 has mesas 104 arranged along a first lateral direction x between the electrode trench structures 106. For example, the mesas 104 may be defined when trenches of the electrode trench structures 106 are formed by a mask etching process.

[0056] Electrical contact to the semiconductor substrate 102 is provided by a recess contact 108 extending from a top surface 1041 of the mesa 104 into the mesa 104. At a first vertical reference level yref1, the bottom of the recess contact 108 is located.

[0057] An n+ doped source region 110 is formed in the mesa 104. The n+ doped source region 110 laterally adjoins the electrode trench structure 106 on one side and further adjoins the recess contact 108 on the other side.

[0058] A p-doped body structure 112 is formed below the source region 110. The p-doped body structure 112 is based on a superposition of p-type doping concentration profiles, such as a superposition of a doping concentration profile defining a body region 1121, a doping concentration profile defining a body contact region 1122, and a doping concentration profile defining a body reinforcement region 1123.

[0059] The n-doped drift region 114 forms a pn junction 116 with the main structure 112 in the mesa 104. The pn junction 116 has a minimum vertical distance dmin to the top surface 1041 of the mesa 104 at the second vertical reference level yref2. The minimum vertical distance dmin of the pn junction 116 is located at or near the sidewall of the electrode trench structure 106. The pn junction 116 also has a maximum vertical distance dmax to the top surface 1041 of the mesa 104 at the third vertical reference level yref3. The maximum vertical distance dmax of the pn junction 116 is located at or near the center of the mesa 104 along the first lateral direction x.

[0060] refer to Figure 1A and Figure 1B , illustrates an exemplary doping concentration c of the body structure 112 along the first lateral direction x relative to a fourth vertical reference level yref4. The first vertical distance d1 is 1.5 to 10 times the second vertical distance d2 from the fourth vertical reference level yref4 to the second vertical reference level yref2. At the fourth vertical reference level yref4, the doping concentration c of the body structure 112 increases by 5 to 100 times along the first lateral direction x from the electrode trench structure 106 toward the center of the mesa 104. Figure 1B As shown in a simplified manner in FIG. 1 , the doping concentration c of the body structure 112 at the second vertical reference level yref2 at or near the electrode trench structure 106 is mainly determined by the doping concentration c1 of the body region 1121, and the doping concentration c of the body structure 112 at or near the third vertical reference level yref3 is mainly determined by the doping concentration c3 of the body reinforcement region 1123. Figure 1A , the absolute difference between the second vertical reference level yref2 and the third vertical reference level yref3 may have a value within a range from 30% to 150% of the absolute difference between the first vertical reference level yref1 and the second vertical reference level yref2.

[0061] refer to Figure 1A and Figure 2 , illustrating an exemplary doping concentration c of the body structure 112 relative to the center of the mesa 102 along the vertical direction y. The pn junction 116 at the third vertical reference level yref3 is located at or near the intersection between the doping concentration profile c3 of the body reinforcement region 1123 and the doping concentration profile c4 of the drift region 114 along the vertical direction y. The doping concentration c of the body structure 112 at the first vertical reference level yref1 at or near the bottom of the recess contact 108 is mainly determined by the doping concentration c2 of the body contact region 1122.

[0062] The maximum concentration cmax2 of the doping concentration profile c2 of the body contact region 1122 may be 5 to 200 times the maximum concentration cmax3 of the doping concentration profile c3 of the body reinforcement region 1123 .

[0063] In those parts of the body structure 112, the sub-regions of the body structure 112 are named similarly to the doping concentration profiles, for example, "body region" for "body concentration profile", in which the value of the corresponding doping concentration profile is greater than the value of each of the other doping concentration profiles of the body structure 112. The doping concentration profile is determined by the manufacturing process, such as ion implantation energy, dose, and dopant type. For example, a sub-region of the body structure 112 can be named a body contact region 1122, although the dopant of the doping concentration profile c3 of the body reinforcement region 1123 or the dopant of the doping concentration profile c1 of the body region 1121 is also present in the body contact region 1122. However, in the body contact region 1122, the dopant concentration of the doping concentration profile c2 (body contact region) is greater than the concentration of the dopant of the doping concentration profile c1 (body region) or c3 (body reinforcement region).

[0064] refer to Figure 2 , the maximum concentration cmax2 of the doping concentration distribution c2 of the body contact region 1122 may be 5 to 200 times the maximum concentration cmax3 of the doping concentration distribution c3 of the body reinforcement region 1123 .

[0065] Figure 3 A cross-sectional view schematically and exemplarily showing a portion of a transistor cell of another configuration example of the FET 100 .

[0066] The electrode trench structure 106 of the FET 100 includes an electrode structure 118 and a dielectric structure 120. The electrode structure 118 includes a gate electrode 1181 and a field electrode 1182. A portion of the dielectric structure 120 is arranged between the gate electrode 1181 and the field electrode 1182.

[0067] FET 100 also includes a source electrode S on top surface 1041 of mesa 104 and on electrode trench structure 106. Source electrode S is electrically isolated from gate electrode 1181 by an intermediate dielectric 122 disposed between gate electrode 1181 and source electrode S.

[0068] exist Figure 3In the illustrated configuration example, the maximum vertical distance dmax is greater than the vertical distance dg from the bottom of the gate electrode 1181 to the top surface 1041 of the mesa 104. In addition, the maximum vertical distance dmax is less than the vertical distance df from the top of the field electrode 1182 to the top surface 1041 of the mesa 104. In some other configuration examples, the maximum vertical distance dmax may also be equal to or greater than the vertical distance df from the top of the field electrode 1182 to the top surface 1041 of the mesa 104.

[0069] Figures 4A to 4D The schematic cross-sectional view of illustrates features of a process for fabricating a FET 100 as described herein.

[0070] refer to Figure 4A Before forming the recessed contact, for example, by ion implantation of dopants, the body region 1121 of the body structure 112 and the source layer 1101 are formed.

[0071] refer to Figure 4B After forming the body region 1121 and after forming the source layer 1101 , a groove 1081 of the groove contact is formed by an etching process using the mask 124 . The etching process patterns the source layer 1101 into the source region 110 .

[0072] refer to Figure 4C After the groove 1081 is formed, a dopant is introduced into the semiconductor substrate 102 through the bottom of the groove 1081 through a first ion implantation process I1 to form a body contact region 1122 .

[0073] refer to Figure 4D Through a second ion implantation process I2, additional dopants are introduced into the semiconductor substrate 102 through the bottom of the groove 1081 to form a body reinforcement region 1123. Figure 4C The process shown can also be Figure 4D The illustrated process is then performed. The ion implantation energy of the first ion implantation process I1 may be less than the ion implantation energy of the second ion implantation process I2, for example, for common dopant types, such as, for example, boron. The ion implantation dose of the first ion implantation process may be greater than the ion implantation dose of the second ion implantation process, for example, for common dopant types, such as, for example, boron.

[0074] Aspects and features mentioned and described in conjunction with one or more of the previously described examples and figures may also be combined with one or more of the other examples in order to replace similar features of the other examples or in order to additionally introduce the features into the other examples.

[0075] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the illustrated and described specific embodiments without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A field effect transistor FET (100), comprising: A semiconductor substrate (102) having a mesa (104) arranged between electrode trench structures (106) along a first lateral direction (x); A groove contact (108) extending from a top surface (1041) of the mesa (104) into the mesa (104), wherein a bottom of the groove contact (108) is located at a first vertical reference level (yref1), and the mesa (104) comprises: A source region (110) of a first conductivity type; A main structure (112) of a second conductivity type; a drift region (114) of a first conductivity type, the drift region (114) forming a pn junction (116) with the main structure (112), the pn junction (116) having a minimum vertical distance (dmin) to a top surface (1041) of the mesa (104) at a second vertical reference level (yref2) and a maximum vertical distance (dmax) to a top surface (1041) of the mesa (104) at a third vertical reference level (yref3); and wherein At a fourth vertical reference level (yref4), the doping concentration (c) of the main structure (112) increases to 5 to 100 times along the first lateral direction (x) from the electrode trench structure (106) toward the center of the mesa (104), and the fourth vertical reference level (yref4) is located between the second vertical reference level (yref2) and the first vertical reference level (yref1), and is separated from the first reference level (yref1) by a first vertical distance (d1), wherein the first vertical distance (d1) is 1.5 to 10 times the second vertical distance (d2) from the fourth vertical reference level (yref4) to the second vertical reference level (yref2).

2. The FET (100) according to the preceding claim, wherein The main structure (112) includes at least a superposition of doping concentration distributions (c1, c2, c3) of a main region (1121), a main contact region (1122) and a main strengthening region (1123), and the pn junction (116) at the third vertical reference level (yref3) coincides with an intersection between a doping concentration distribution (c3) of the main strengthening region (1123) and a doping concentration distribution (c4) of the drift region (114) along a vertical direction (y).

3. The FET (100) according to the preceding claim, wherein The maximum concentration (cmax2) of the doping concentration distribution (c2) of the body contact region (1122) is 5 to 200 times the maximum concentration (cmax3) of the doping concentration distribution (c3) of the body reinforcement region (1123).

4. The FET (100) according to any one of the two preceding claims, wherein The maximum concentration (cmax3) of the doping concentration distribution (c3) of the body reinforcement region (1123) is 5 to 200 times the maximum concentration of the doping concentration distribution of the body region.

5. The FET (100) according to any one of the three preceding claims, wherein: The doping concentration (c) of the body structure (112) at a second vertical reference level (yref2) at or near the electrode trench structure (106) is primarily determined by the doping concentration (c1) of the body region (1121).

6. The FET (100) according to any one of the preceding claims, wherein: The doping concentration of the body structure (112) at a first vertical reference level (yref1) at or near the bottom of the recessed contact (108) is primarily determined by the doping concentration (c2) of the body contact region (1122).

7. A FET (100) according to any one of the five preceding claims, wherein the doping concentration (c) of the main structure (112) at or near the third vertical reference level (yref3) is mainly determined by the doping concentration (c3) of the main reinforcement region (1123).

8. The FET (100) according to any one of the preceding claims, wherein The absolute difference between the second vertical reference level (yref2) and the third vertical reference level (yref3) has a value ranging from 30% to 150% of the absolute difference between the first vertical reference level (yref1) and the second vertical reference level (yref2).

9. The FET (100) according to any one of the preceding claims, wherein The electrode trench structure (106) includes an electrode structure (118) and a dielectric structure (120), wherein the electrode structure (118) includes a gate electrode (1181) and a field electrode (1182).

10. The FET (100) according to the preceding claim, wherein A portion of the dielectric structure (120) is arranged between the gate electrode (1181) and the field electrode (1182).

11. The FET (100) according to the preceding claim, wherein The maximum vertical distance (dmax) is greater than the vertical distance from the bottom of the gate electrode (1181) to the top surface (1041) of the mesa (104).

12. The FET (100) according to the preceding claim, wherein The maximum vertical distance (dmax) is less than the vertical distance from the top of the field electrode (1182) to the top surface (1041) of the mesa (104).

13. The FET (100) according to any one of the preceding claims, wherein The FET (100) is a vertical FET having a source electrode on a first surface of a semiconductor substrate (102) and a drain electrode on a second surface of the semiconductor substrate (102), the second surface being opposite to the first surface.

14. A method for manufacturing a field effect transistor (FET) (100), the method comprising: forming a mesa (104) in the semiconductor substrate (102) arranged between the electrode trench structures (106) along a first lateral direction (x); forming a recessed contact (108) extending from a top surface (1041) of the mesa (104) into the mesa (104), wherein a bottom of the recessed contact (108) is located at a first vertical reference level (yref1); and wherein the method further comprises: forming a source region (110) of a first conductivity type in the mesa; forming a second conductivity type body structure (112) in the mesa; A drift region (114) of a first conductivity type is formed in the mesa, the drift region (114) forms a pn junction (116) with the main structure (112), the pn junction (116) having a minimum vertical distance (dmin) to a top surface (1041) of the mesa (104) at a second vertical reference level (yref2), and having a maximum vertical distance (dmax) to the top surface (1041) of the mesa (104) at a third vertical reference level (yref3); and wherein At a fourth vertical reference level (yref4), the doping concentration (c) of the main structure (112) increases to 5 to 100 times along the first lateral direction (x) from the electrode trench structure (106) toward the center of the mesa (104), and the fourth vertical reference level (yref4) is located between the second vertical reference level (yref2) and the first vertical reference level (yref1), and is separated from the first reference level (yref1) by a first vertical distance (d1), wherein the first vertical distance (d1) is 1.5 to 10 times the second vertical distance (d2) from the fourth vertical reference level (yref4) to the second vertical reference level (yref2).

15. A method according to the preceding claim, wherein forming the main structure (112) comprises forming a superposition of doping concentration profiles (c1, c2, c3) of at least a main region (1121), a main contact region (1122) and a main reinforcement region (1123), and a pn junction (116) at a third vertical reference level (yref3) coincides with an intersection between the doping concentration profile (c3) of the main reinforcement region (1223) and the doping concentration profile (c4) of the drift region (114) along a vertical direction (y).

16. A method according to the preceding claim, wherein: The body region (1121) is formed before forming the recess contact (108).

17. A method according to any one of the two preceding claims, wherein Forming a recessed contact (108) includes forming a trench; and thereafter Forming the body contact region (1122) includes introducing a dopant into the semiconductor substrate (102) through the bottom of the groove by a first ion implantation process; and Forming the body reinforcement region (1123) includes introducing dopants into the semiconductor substrate (102) through the bottom of the recess by a second ion implantation process.

18. A method according to the preceding claim, wherein: The ion implantation energy of the first ion implantation process is less than the ion implantation energy of the second ion implantation process.

19. The method according to any one of the three preceding claims, wherein: The ion implantation dose of the first ion implantation process is greater than the ion implantation dose of the second ion implantation process.

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