Ferroelectric field effect transistor based on strained silicon technology and preparation method thereof

Abstract

The invention discloses a ferroelectric field effect transistor based on a strained silicon technology and a preparation method of the ferroelectric field effect transistor. The ferroelectric field effect transistor comprises a Si substrate of a first doping type; the drain region and the source region of the second doping type are located in the two ends of the Si substrate, and the upper surfaces of the drain region and the source region are flush with the upper surface of the Si substrate; the SiO2 insulating layer is positioned on the Si substrate and is in contact with the drain region and the source region; the HZO ferroelectric dielectric layer is positioned on the SiO2 insulating layer; a gate electrode on the HZO ferrodielectric layer; the source electrode and the drain electrode are respectively positioned on a part of the drain region and a part of the source region; and the SiN layer is positioned on the residual drain region, the residual source region, the gate electrode, the source electrode and the drain electrode, and on the side walls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode and the drain electrode. According to the invention, the ferroelectric characteristic and the storage capability of the FeFET can be further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a ferroelectric field effect transistor based on strained silicon technology and a preparation method thereof. Background Art

[0002] At present, the development of microelectronics is in an important period of theoretical and technological change. It no longer simply pursues the reduction of feature size, but focuses on overcoming power consumption and improving computing power, developing new materials, devices, processes, architectures and packaging technologies, etc., to promote the continuous innovation and development of information technology.

[0003] Semiconductor memory is currently the most mainstream data storage and data exchange carrier, and is the core component to ensure the normal operation of the system. Among the new generation of memory, non-volatile ferroelectric memory made by integrated circuit processing technology using the dielectric and ferroelectric switching effects of ferroelectric thin films has very important application prospects. Hafnium dioxide (HfO 2 )-based ferroelectric materials can still maintain their ferroelectric properties at a very thin thickness (about 10nm), overcoming the size miniaturization problem faced by traditional ferroelectric materials. They have many advantages in the field of ferroelectric storage, but they still have the same wake-up effect, poor durability, fatigue effect, imprinting effect and other problems as traditional ferroelectric materials. In order to solve these problems, high-performance HfO 2 Ferroelectric memory urgently needs important changes in materials and processes. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a ferroelectric field effect transistor based on strained silicon technology and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides a ferroelectric field effect transistor based on strained silicon technology, the ferroelectric field effect transistor comprising:

[0006] A Si substrate of a first doping type;

[0007] A drain region and a source region of a second doping type are located within two ends of the Si substrate, and their upper surfaces are flush with the upper surface of the Si substrate;

[0008] SiO 2 An insulating layer, located on the Si substrate and in contact with the drain region and the source region;

[0009] The HZO ferroelectric layer is located on the SiO 2 On the insulation layer;

[0010] A gate electrode, located on the HZO ferroelectric dielectric layer;

[0011] A source electrode and a drain electrode, respectively located on part of the drain region and part of the source region;

[0012] The SiN layer is located on the remaining part of the drain region, the remaining part of the source region, the gate electrode, the drain electrode and the source electrode, and the SiO 2 The SiN layer has an intrinsic tensile stress and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer and the source region and the drain region, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region and the drain region to shrink, so that the channel and the ferroelectric dielectric layer are stretched to generate tensile stress.

[0013] In one embodiment of the present invention, when the first doping type is P type, the second doping type is N type.

[0014] In one embodiment of the present invention, the SiO 2 The thickness of the insulating layer is 1 nm to 3 nm.

[0015] In one embodiment of the present invention, the HZO ferroelectric dielectric layer is composed of alternately distributed HfO 2 Thin films and ZrO 2 Film composition: the thickness of the HZO ferroelectric dielectric layer is 10nm to 12nm.

[0016] In one embodiment of the present invention, the thickness of the SiN layer is 100 nm to 200 nm.

[0017] In a second aspect, an embodiment of the present invention provides a method for preparing a ferroelectric field effect transistor based on strained silicon technology, the method comprising:

[0018] Selecting a Si substrate of a first doping type;

[0019] Performing ion implantation of a first doping type on both ends of the Si substrate to form a source region and a drain region of a second doping type;

[0020] Growing SiO on the Si substrate except for the source region and the drain region 2 Insulating layer; wherein the SiO 2 An insulating layer is in contact with the drain region and the source region;

[0021] In the SiO 2 Depositing a HZO ferroelectric dielectric layer on the insulating layer;

[0022] depositing a gate electrode on the HZO ferroelectric dielectric layer;

[0023] Depositing a source electrode and a drain electrode on part of the source region and part of the drain region respectively;

[0024] On the remaining part of the drain region, the remaining part of the source region, the gate electrode, above the source electrode and the drain electrode, and the SiO 2 A SiN layer is grown on the side walls of the insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode; wherein the SiN layer has intrinsic tensile stress and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer and the source region and the drain region, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region and the drain region to shrink, so that the channel and the HZO ferroelectric dielectric layer are stretched to generate tensile stress.

[0025] In one embodiment of the present invention, when the first doping type is P type, the second doping type is N type.

[0026] In one embodiment of the present invention, SiO is grown on the Si substrate except for the source region and the drain region. 2 Insulation layer, including:

[0027] Using a dry oxygen process, a SiO layer with a thickness of 1 nm to 3 nm is grown on the Si substrate except for the source region and the drain region. 2 Insulation layer.

[0028] In one embodiment of the present invention, the SiO 2 A HZO ferroelectric dielectric layer is deposited on the insulating layer, comprising:

[0029] Using atomic layer deposition method, the SiO 2 A HZO ferroelectric dielectric layer with a thickness of 10nm to 12nm is deposited on the insulating layer; the specific process includes: the temperature range of the ALD equipment is 280℃ to 300℃, TDMAHf and TDMAZr are used as precursors of Hf and Zr respectively, and water vapor is introduced as an oxygen source; HfO is alternately deposited 2 Thin films and ZrO 2 The HZO thin film is obtained by controlling the HfO 2 Thin films and ZrO 2 The number of cycles of alternate film deposition controls the thickness of the HZO film to reach 10 nm to 12 nm to form a HZO ferroelectric dielectric layer.

[0030] In one embodiment of the present invention, on the remaining part of the drain region, the remaining part of the source region, the gate electrode, the source electrode and the drain electrode, and the SiO 2A SiN layer is grown on the side walls of the insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode, comprising:

[0031] Plasma enhanced chemical vapor deposition is used to deposit the remaining drain region, the remaining source region, the gate electrode, the source electrode and the drain electrode, and the SiO 2 A SiN layer with a thickness of 100 nm to 200 nm is grown on the sidewalls of the insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode; the specific process includes: the temperature range in the PECVD equipment is 200° C. to 500° C., the pressure range is 400 mTorr to 1700 mTorr, the frequency of the high-frequency power source is 13.5 MHz, the power range of the high-frequency power source is 20 W to 300 W, and the SiH 4 and NH 3 The gas flow ratio ranges from 0.2 to 2.0.

[0032] Beneficial effects of the present invention:

[0033] The ferroelectric field effect transistor based on strained silicon technology proposed in the present invention is a new structure of a ferroelectric field effect transistor. It innovatively introduces uniaxial tensile stress by covering the source region, the drain region and the gate electrode with a SiN layer, ultimately achieving better FeFET ferroelectric properties and better storage capacity than ordinary ferroelectric field effect transistors, opening up a new technical approach to further improve the performance of ferroelectric field effect transistors.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic structural diagram of a ferroelectric field effect transistor based on strained silicon technology provided by an embodiment of the present invention;

[0036] Figure 2 It is a schematic flow chart of a method for preparing a ferroelectric field effect transistor based on strained silicon technology provided by an embodiment of the present invention;

[0037] Figure 3a to Figure 3g The embodiment of the present invention provides Figure 2 Schematic diagram of the corresponding structure during the preparation process.

[0038] Description of reference numerals:

[0039] 1-Si substrate of the first doping type; 2-drain region of the second doping type; 3-source region of the second doping type; 4-SiO 2 Insulating layer; 5-HZO ferroelectric dielectric layer; 6-gate electrode; 7-SiN layer; 8-source electrode; 9-drain electrode. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0041] Compared with traditional MOSFET, FeFET only uses ferroelectric thin film materials instead of SiO 2 As a gate dielectric. In essence, FeFET uses the polarization state of the ferroelectric transistor to adjust the channel conduction state, thereby switching between the logic 0 state and the logic 1 state. The difference in the threshold voltage VTH of the ferroelectric transistor corresponding to logic 1 or 0 is called the FeFET hysteresis loop storage window. The larger the hysteresis loop storage window means that it is easier to distinguish the difference between logic 1 or 0, and the stored data is not easy to be lost, which improves the storage capacity of the device.

[0042] Strained silicon technology is an advanced process that introduces strain into silicon-based materials. Strained silicon technology stretches or compresses silicon-based materials to slightly distort their lattices, thereby changing the electronic motion characteristics of silicon materials to achieve the advantage of improving device performance. 2 FeFET has many advantages in the field of storage, but there are still problems such as wake-up effect, poor durability, fatigue effect, and imprinting effect. In order to solve these problems, high-performance HfO 2 Based on FeFET, HfO can be controlled by stress regulation technology 2 The ferroelectric properties of FeFET can be regulated by the research. The study shows that the magnitude of tensile stress is positively correlated with the residual polarization of the ferroelectric film. The introduction of tensile stress into the ferroelectric film increases the storage window of the hysteresis loop, improves the storage capacity of FeFET, and can effectively improve the performance of FeFET. The existing stress regulation technology can be achieved by replacing the electrode and substrate materials, and the stress regulation technology of FeFET using strained silicon process is still in its infancy.

[0043] Based on the above research, the present invention proposes to introduce strained silicon technology into HfO 2 Based on the FeFET manufacturing process, the ferroelectric properties and storage capacity of FeFET can be further improved. Specifically:

[0044] First, see Figure 1 , an embodiment of the present invention provides a ferroelectric field effect transistor based on strained silicon technology, the ferroelectric field effect transistor comprising:

[0045] A Si substrate 1 of a first doping type;

[0046] The drain region 2 and the source region 3 of the second doping type are located at two ends of the Si substrate 1, and their upper surfaces are flush with the upper surface of the Si substrate 1;

[0047] SiO 2 An insulating layer 4 is located on the Si substrate 1 and is in contact with the drain region 2 and the source region 3;

[0048] HZO ferroelectric layer 5, located on SiO 2 On the insulating layer 4;

[0049] A gate electrode 6, located on the HZO ferroelectric dielectric layer 5;

[0050] The source electrode 8 and the drain electrode 9 are respectively located on part of the drain region and part of the source region;

[0051] The SiN layer 7 is located on the remaining drain region 2, the remaining source region 3, the gate electrode 6, the source electrode 8, the drain electrode 9, and the SiO 2 On the side walls of the insulating layer 4, the HZO ferroelectric layer 5, the gate electrode 6, the source electrode 8 and the drain electrode 9; wherein, the SiN layer 7 has intrinsic tensile stress, and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer 7 and the source region 3 and the drain region 2, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region 3 and the drain region 2 to shrink, so that the channel and the ferroelectric layer are stretched to generate tensile stress.

[0052] In the embodiment of the present invention, when the first doping type is P type, the second doping type is N type. At this time, the substrate is a P type Si substrate 1 , the drain region 2 is an N type doped drain region 2 , and the source region 3 is an N type doped source region 3 .

[0053] In the embodiment of the present invention, SiO 2 The thickness of the insulating layer 4 is 1 nm to 3 nm. The material of the insulating layer is SiO 2 , because SiO 2 It has good interface properties with Si.

[0054] In the embodiment of the present invention, the HZO ferroelectric dielectric layer 5 is composed of HfO 2 Thin films and ZrO 2 Film composition: Alternating distribution of HfO 2 Thin films and ZrO 2 The number of periods of the thin film is determined by the thickness of the HZO ferroelectric dielectric layer 5 . Preferably, the thickness of the HZO ferroelectric dielectric layer 5 is 10 nm to 12 nm.

[0055] The gate electrode 6 of the embodiment of the present invention is made of TaN and has a thickness of 90 nm to 100 nm. 2 The insulating layer 4 , the HZO ferroelectric dielectric layer 5 , and the gate electrode 6 constitute a stacked gate structure.

[0056] In the embodiment of the present invention, the thickness of the SiN layer 7 is 100 nm to 200 nm.

[0057] In the HZO ferroelectric dielectric layer 5 of the embodiment of the present invention, HfO 2 The remnant polarization of the film increases with the increase of uniaxial tensile stress, and increases towards HfO 2 The introduction of uniaxial tensile stress in the film makes the storage window of the FeFET hysteresis loop increase with the increase of uniaxial tensile stress, which is beneficial to the HfO 2 The presence of thin film ferroelectricity improves the storage capacity of FeFET. 2 The stress in the film is caused by many factors, such as: lattice mismatch between Si substrate 1 and epitaxial film, difference in thermal expansion coefficient between epitaxial film and Si substrate 1, and phase change. In strained silicon process technology, uniaxial tensile stress can be introduced by covering the device surface with SiN layer 7. The basic principle is: based on the lattice mismatch between materials, when the device covered with SiN layer 7 is cooled from the deposition temperature to the measurement temperature, both SiN layer 7 and Si substrate 1 will shrink as the temperature drops, but the shrinkage degree of the two is different.

[0058] The source region 3, drain region 2 and gate electrode 6 of the FeFET are covered with a SiN layer 7 having uniaxial tensile stress. By contacting the source region 3 and drain region 2 in the Si substrate 1, the source region 3 and drain region 2 shrink under the action of the lattice mismatch principle, and the channel is stretched, so that uniaxial tensile stress is generated inside the channel. At the same time, the Si substrate 1 material in the FeFET is in direct contact with the stacked gate material, and the HfO 2 The film is constrained by the Si substrate 1 material to produce internal stress, which in turn affects the HfO 2 Thin film ferroelectricity.

[0059] In addition, the presence of channel tensile stress will also affect the polarization switching characteristics of ferroelectric materials. The polarization switching characteristics of ferroelectric materials affect the write / erase speed of the corresponding memory device. When a positive write voltage is applied to the gate electrode 6, an inversion layer is formed on the channel surface, and a current channel is formed between the source region 3 and the drain region 2, corresponding to the write process of the device; when a negative erase voltage is applied to the gate electrode 6, an accumulation layer is formed on the channel surface, and the current channel between the source region 3 and the drain region 2 is cut off, corresponding to the erase process of the device.

[0060] In FeFET, the polarized surface charge of ferroelectric affects the surface potential of the semiconductor through Coulomb coupling, thereby adjusting the carrier concentration in the FeFET channel. For example, when the FeFET in the embodiment of the present invention is an N-type FeFET, the electrons provide carriers for the conductive channel in the FeFET inversion mechanism. Mobility is a physical quantity in solid-state physics used to describe the speed at which electrons / holes inside a semiconductor move under the action of an electric field. The introduction of channel tensile stress increases electron mobility, thereby increasing the write / erase speed of the FeFET.

[0061] In summary, the ferroelectric field effect transistor based on strained silicon technology proposed in the embodiment of the present invention is a new structure of a ferroelectric field effect transistor, which innovatively introduces uniaxial tensile stress by covering the source region 3, the drain region 2 and the gate electrode 6 with a SiN layer 7, ultimately achieving better FeFET ferroelectric properties and better storage capacity than ordinary ferroelectric field effect transistors, opening up a new technical approach to further improve the performance of ferroelectric field effect transistors.

[0062] Second, see Figure 2 The embodiment of the present invention provides a method for preparing a ferroelectric field effect transistor based on strained silicon technology, the preparation method comprising:

[0063] S10, selecting a Si substrate 1 of a first doping type.

[0064] In the embodiment of the present invention, a Si substrate 1 of the first doping type is selected. Figure 3a As shown, the Si substrate 1 is subjected to organic ultrasonic cleaning in the order of acetone, anhydrous ethanol and water, in order to remove organic pollutants on the surface of the Si substrate 1, and then diluted hydrofluoric acid (HF:H 2 After being immersed in a molten-salt (0:0.040) solution for one minute, the organic layer is inorganically cleaned at room temperature to remove the intrinsic oxide layer to avoid affecting the subsequent process and device performance. The first doping type may be P type.

[0065] S20 , performing ion implantation of the first doping type on both ends of the Si substrate 1 to form a source region 3 and a drain region 2 of the second doping type.

[0066] In the embodiment of the present invention, after the Si substrate 1 is cleaned by S10, a patterning process is performed on the Si substrate 1, and a series of operations such as resin spinning, resin baking, contact exposure, development, and fixing are performed to define the source and drain regions, and a reactive ion etching method is used to etch the source region 3 and the drain region 2. The specific reactive ion etching process is: using a reaction gas of Cl 2 and BCl 3 The chlorine-based atomic groups are used as an etchant, and then the source and drain regions are photolithographically processed, and the source and drain regions are self-aligned with the first doping type ion implantation to form the second doping type source region 3 and drain region 2. Figure 3b As shown in the figure, the ion implantation energy and dose are 30keV and 2×10 15 cm -2 , and finally at 900℃, N 2 A rapid thermal annealing is performed for 1 minute in the atmosphere to activate the dopant injected into the source region 3 and the drain region 2. When the first doping type in S10 is P type and the second doping type is N type, the source and drain regions 2 are self-aligned with P+ ion implantation to form an N type doped source region 3 and an N type doped drain region 2.

[0067] S30, growing SiO on the Si substrate 1 except the source region 3 and the drain region 2 2 Insulating layer 4; wherein SiO 2 The insulating layer 4 is in contact with the drain region 2 and the source region 3 .

[0068] In the embodiment of the present invention, the Si substrate 1 after S20 activation is placed in SPM (H 2 SO 4 :H 2 O=1:3) and DHF(HF:H 2 O=1:50) solution to remove the photoresist and the surface oxide layer. Using dry oxygen process, SiO with a thickness of 1nm to 3nm is grown on the Si substrate 1 except the source region 3 and the drain region 2. 2 Insulation layer 4 such as Figure 3c shown.

[0069] S40, in SiO 2 A HZO ferroelectric layer 5 is deposited on the insulating layer 4 .

[0070] The embodiment of the present invention utilizes atomic layer deposition method to deposit SiO 2 A HZO ferroelectric dielectric layer 5 with a thickness of 10 nm to 12 nm is deposited on the insulating layer 4; the specific process includes: the temperature range in the ALD equipment is 280°C to 300°C, TDMAHf (tetrakis(dimethylamino)hafnium) and TDMAZr (tetrakis(dimethylamino)zirconium) are used as precursors of Hf (hafnium) and Zr (zirconium), respectively, and water vapor (H 2 O) as an oxygen source; by alternately depositing HfO 2 Thin films and ZrO 2 The HZO thin film is obtained by controlling the HfO 2 Thin films and ZrO 2 The number of cycles of film alternating deposition controls the thickness of the HZO film to reach 10nm to 12nm to form the HZO ferroelectric dielectric layer 5. Figure 3d As shown in the figure, the number of cycles varies with the thickness requirement of the HZO ferroelectric dielectric layer 5. In each cycle, HfO is deposited alternately. 2 The film thickness can be 1nm and ZrO2 The thickness of the film can be 1 nm.

[0071] S50 , depositing a gate electrode 6 on the HZO ferroelectric dielectric layer 5 .

[0072] In the embodiment of the present invention, the gate electrode 6 is deposited by a magnetron sputtering deposition process. Specifically, the sample is transferred to a chamber of a magnetron sputtering deposition system, and a gate electrode 6 having a thickness of 90 nm to 100 nm is deposited on the HZO ferroelectric dielectric layer 5. Figure 3e As shown, for example, the material of the gate electrode 6 may be TaN metal.

[0073] S60 , depositing a source electrode 8 and a drain electrode 9 on a portion of the source region 3 and a portion of the drain region 2 , respectively.

[0074] The embodiment of the present invention uses photolithography to define the gate pattern region, and uses reactive ion etching to etch the gate pattern region to expose the source region 3 and the drain region 2. Subsequently, by electron beam evaporation deposition and lift-off process, 30 nm of Ni metal is deposited on part of the source region 3 and part of the drain region 2 to form the source electrode 8 and the drain electrode 9. Figure 3f Finally, the fabricated device was heated at 550°C and N 2 Rapid annealing is performed in the atmosphere for 30s-60s to form an ohmic contact between the source region 3 and the drain region 2 and to crystallize the HZO film.

[0075] S70, on the remaining drain region 2, the remaining source region 3, the gate electrode 6, the source electrode 8 and the drain electrode 9, and the SiO 2 A SiN layer 7 is grown on the side walls of the insulating layer 4, the HZO ferroelectric dielectric layer 5, the gate electrode 6, the source electrode 8 and the drain electrode 9; wherein the SiN layer 7 has intrinsic tensile stress, and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer 7 and the source region 3 and the drain region 2, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region 3 and the drain region 2 to shrink, so that the channel and the HZO ferroelectric dielectric layer 5 are stretched to generate tensile stress.

[0076] In the embodiment of the present invention, on the remaining drain region 2, the remaining source region 3, the gate electrode 6, the source electrode 8 and the drain electrode 9, and the SiO 2 The SiN layer 7 is grown on the sidewalls of the insulating layer 4, the HZO ferroelectric dielectric layer 5, the gate electrode 6, the source electrode 8 and the drain electrode 9, including: using a plasma enhanced chemical vapor deposition method on the drain region 2, the source region 3, the gate electrode 6, the source electrode 8 and the drain electrode 9, and the SiO 2 A SiN layer 7 with a thickness of 100 nm to 200 nm is grown on the side walls of the insulating layer 4, the HZO ferroelectric dielectric layer 5, the gate electrode 6, the source electrode 8 and the drain electrode 9. Figure 3gThe specific process includes: the temperature range of the PECVD equipment is 200℃~500℃, the pressure range is 400mTorr~1700mTorr, the frequency of the high-frequency power source is 13.5MHz, the power range of the high-frequency power source is 20W~300W, and the SiH 4 and NH 3 The gas flow ratio ranges from 0.2 to 2.0. At this time, the deposited SiN layer 7 has intrinsic tensile stress, and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer 7 and the source region 3 and the drain region 2, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region 3 and the drain region 2 to shrink, so that the channel and the HZO ferroelectric dielectric layer 5 are stretched to generate tensile stress.

[0077] As for the preparation method embodiment of the second aspect, since it is basically similar to the structural embodiment of the first aspect, the description is relatively simple, and the relevant parts may refer to the partial description of the structural embodiment of the first aspect.

[0078] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0079] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0080] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A ferroelectric field effect transistor based on strained silicon technology, characterized in that: The ferroelectric field effect transistor comprises: A Si substrate of a first doping type; A drain region and a source region of a second doping type are located at two ends of the Si substrate, and their upper surfaces are flush with the upper surface of the Si substrate; A SiO2 insulating layer, located on the Si substrate and in contact with the drain region and the source region; A HZO ferroelectric dielectric layer, located on the SiO2 insulating layer; A gate electrode, located on the HZO ferroelectric dielectric layer; A source electrode and a drain electrode, respectively located on part of the drain region and part of the source region; The SiN layer is located on the remaining drain region, the remaining source region, the gate electrode, the source electrode and the drain electrode, and on the side walls of the SiO2 insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode; wherein the SiN layer has intrinsic tensile stress and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer and the source region and the drain region, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region and the drain region to shrink, so that the channel and the ferroelectric dielectric layer are stretched to generate tensile stress.

2. The ferroelectric field effect transistor based on strained silicon technology according to claim 1, characterized in that: When the first doping type is P type, the second doping type is N type.

3. The ferroelectric field effect transistor based on strained silicon technology according to claim 1, characterized in that: The thickness of the SiO2 insulating layer is 1nm to 3nm.

4. The ferroelectric field effect transistor based on strained silicon technology according to claim 1, characterized in that: The HZO ferroelectric dielectric layer is composed of HfO2 thin films and ZrO2 thin films distributed alternately; the thickness of the HZO ferroelectric dielectric layer is 10nm-12nm.

5. The ferroelectric field effect transistor based on strained silicon technology according to claim 1, characterized in that: The thickness of the SiN layer is 100nm-200nm.

6. A method for preparing a ferroelectric field effect transistor based on strained silicon technology, characterized in that: The preparation method comprises: Selecting a Si substrate of a first doping type; Performing ion implantation of a first doping type on both ends of the Si substrate to form a source region and a drain region of a second doping type; Growing a SiO2 insulating layer on the Si substrate except the source region and the drain region; wherein the SiO2 insulating layer is in contact with the drain region and the source region; Depositing a HZO ferroelectric dielectric layer on the SiO2 insulating layer; depositing a gate electrode on the HZO ferroelectric dielectric layer; Depositing a source electrode and a drain electrode on part of the source region and part of the drain region respectively; A SiN layer is grown on the remaining drain region, the remaining source region, the gate electrode, the source electrode and the drain electrode, and on the side walls of the SiO2 insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode; wherein the SiN layer has intrinsic tensile stress and will be compressed in the horizontal direction under the action of chemical bonds, and through the contact between the SiN layer and the source region and the drain region, under the action of the lattice adaptation principle, the compression force generated by the compression will drive the source region and the drain region to shrink, so that the channel and the HZO ferroelectric dielectric layer are stretched to generate tensile stress.

7. The method for preparing a ferroelectric field effect transistor based on strained silicon technology according to claim 6, characterized in that: When the first doping type is P type, the second doping type is N type.

8. The method for preparing a ferroelectric field effect transistor based on strained silicon technology according to claim 6, characterized in that: Growing a SiO2 insulating layer on the Si substrate except the source region and the drain region, comprising: A SiO2 insulating layer with a thickness of 1 nm to 3 nm is grown on the Si substrate except the source region and the drain region by using a dry oxygen process.

9. The method for preparing a ferroelectric field effect transistor based on strained silicon technology according to claim 6, characterized in that: Depositing a HZO ferroelectric dielectric layer on the SiO2 insulating layer, comprising: A HZO ferroelectric dielectric layer with a thickness of 10nm to 12nm is deposited on the SiO2 insulating layer by atomic layer deposition. The specific process includes: the temperature range in the ALD equipment is 280℃ to 300℃, TDMAHf and TDMAZr are used as precursors of Hf and Zr respectively, and water vapor is introduced as an oxygen source; the HZO film is obtained by alternately depositing HfO2 film and ZrO2 film, and the thickness of the HZO film is controlled to reach 10nm to 12nm by controlling the number of cycles of alternate deposition of the HfO2 film and the ZrO2 film, so as to form the HZO ferroelectric dielectric layer.

10. The method for preparing a ferroelectric field effect transistor based on strained silicon technology according to claim 6, characterized in that: Growing a SiN layer on the remaining part of the drain region, the remaining part of the source region, the gate electrode, the source electrode and the drain electrode, and the sidewalls of the SiO2 insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode, comprising: A SiN layer with a thickness of 100nm to 200nm is grown on the remaining drain region, the remaining source region, the gate electrode, the source electrode and the drain electrode, as well as on the side walls of the SiO2 insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode and the drain electrode by plasma enhanced chemical vapor deposition; the specific process includes: the temperature range in the PECVD equipment is 200℃ to 500℃, the pressure range is 400mTorr to 1700mTorr, the frequency of the high-frequency power source is 13.5MHz, the power variation range of the high-frequency power source is 20W to 300W, and the flow ratio range of the introduced SiH4 and NH3 gases is 0.2 to 2.0.

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