Semiconductor device

Abstract

A semiconductor device includes a back interlayer insulating film, a back wiring line disposed within the back interlayer insulating film, a fin-type pattern disposed on a first surface of the back wiring line, a source / drain pattern disposed on the fin-type pattern, and a back wiring contact connecting the back wiring line and the source / drain pattern. A bottom surface of the source / drain pattern is connected to the fin-type pattern and faces the back wiring line. The back wiring contact includes a back contact barrier film, a back contact plug film, and a back ferroelectric material film. The back wiring contact includes a third surface facing the back wiring line. A vertical length from a second surface of the back wiring line to a third surface of the back wiring contact is less than a vertical length from the second surface to a bottom surface of the source / drain pattern.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] One of scaling schemes for increasing the integration density of semiconductor devices proposes a multi-gate transistor in which a multi-channel active pattern (or silicon body) in the shape of a fin or a nanowire is formed on a substrate, and a gate is formed on a surface of the multi-channel active pattern.

[0003] Because such a multi-gate transistor uses a three-dimensional channel, it is easy to scale it. In addition, the current control capability of the multi-gate transistor can be improved without increasing the gate length of the multi-gate transistor. In addition, the multi-gate transistor can effectively suppress the SCE (short channel effect), in which the potential of the channel region is affected by the drain voltage.

[0004] As the pitch size of semiconductor devices decreases, research is required to reduce the capacitance between contacts in semiconductor devices to ensure the electrical stability of the devices. Summary of the invention

[0005] The present disclosure provides semiconductor devices with improved device performance and reliability.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, which includes: a back interlayer insulating film; a back wiring line arranged in the back interlayer insulating film and including a first surface and a second surface opposite to each other in a first direction; a fin-type pattern arranged on the first surface of the back wiring line and extending in a second direction; a source / drain pattern arranged on the fin-type pattern, wherein the bottom surface of the source / drain pattern is connected to the fin-type pattern and faces the back wiring line; and a back wiring contact connecting the back wiring line and the source / drain pattern to each other, wherein the back wiring contact includes a back contact barrier film, a back contact plug film and a back ferroelectric material film arranged between the back contact barrier film and the back contact plug film, wherein the back wiring contact includes a third surface facing the back wiring line, wherein a vertical length from the second surface of the back wiring line to the third surface of the back wiring contact is less than a vertical length from the second surface of the back wiring line to the bottom surface of the source / drain pattern.

[0007] According to another aspect of the present disclosure, a semiconductor device is provided, which includes: a back interlayer insulating film; a back wiring line arranged in the back interlayer insulating film and including a first surface and a second surface opposite to each other in a first direction; a first source / drain pattern arranged on the first surface of the back wiring line; and a back wiring contact arranged between the first source / drain pattern and the back wiring line, connected to the first source / drain pattern and overlapping the first source / drain pattern in the first direction, wherein the back wiring contact includes a back contact barrier film, a back contact plug film, and a back ferroelectric material film arranged between the back contact barrier film and the back contact plug film.

[0008] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a back interlayer insulating film; a back wiring line disposed in the back interlayer insulating film and including a first surface and a second surface opposite to each other in a first direction; a fin pattern disposed on the first surface of the back wiring line and extending in a second direction; a plurality of sheet patterns disposed on the fin pattern; a gate electrode disposed on the fin pattern, surrounding the plurality of sheet patterns and extending in a third direction; a source / drain pattern disposed on the fin pattern and connected to the plurality of sheet patterns, wherein the source / drain pattern is disposed on the gate electrode on the side surface, wherein the bottom surface of the source / drain pattern is connected to the fin pattern and faces the back wiring line; and a back wiring contact connecting the back wiring line and the source / drain pattern to each other, wherein the back wiring contact includes a back contact barrier film, a back contact plug film and a back ferroelectric material film, and the back ferroelectric material film is arranged between the back contact barrier film and the back contact plug film, wherein the back wiring contact includes a third surface facing the back wiring line, wherein the vertical length from the second surface of the back wiring line to the third surface of the back wiring contact is less than the vertical length from the second surface of the back wiring line to the bottom surface of the source / drain pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is an example layout diagram for illustrating a semiconductor device according to some embodiments.

[0011] Figure 2 is along Figure 1 Cross-sectional view taken at AA in .

[0012] Figure 3 is along Figure 1 Cross-sectional view taken through BB in FIG.

[0013] Figure 4 is along Figure 1 Cross-sectional view taken from CC in .

[0014] Figure 5 and Figure 6 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0015] Figure 7 and Figure 8 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0016] Fig. 9 and Fig.10 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0017] Figure 11 to Figure 13 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0018] Fig.14 and Fig.15 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0019] Fig.16 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0020] Fig.17 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0021] Fig.18 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0022] Fig.19 and Fig. 20 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0023] Figure 21 to Figure 25 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0024] Figures 26 to 30 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0025] Figures 31 to 38 is a schematic diagram of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0026] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part without departing from the spirit and scope of the present disclosure.

[0027] A semiconductor device according to some embodiments includes a fin transistor (FinFET) including a channel region in a fin pattern shape, a transistor including a nanowire or a nanosheet, and an MBCFET TM (Multi-bridge channel field effect transistor) However, the present disclosure is not limited thereto.

[0028] According to some embodiments, the semiconductor device may include a tunnel transistor (tunnel FET), a three-dimensional (3D) transistor, or a vertical transistor (vertical FET). In another example, the semiconductor device according to some embodiments may include a planar transistor. In addition, the technical concept of the present disclosure can be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures.

[0029] Furthermore, the semiconductor device according to some embodiments may include a bipolar junction transistor, an LDMOS (Lateral Double Diffused MOS) transistor, or the like.

[0030] refer to Figures 1 to 4 , describing semiconductor devices according to some embodiments.

[0031] Figure 1 is an example layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 is along Figure 1 Cross-sectional view taken at AA in . Figure 3 is along Figure 1 Cross-sectional view taken through BB in FIG. Figure 4 is along Figure 1 Cross-sectional view taken from CC in .

[0032] A cross-sectional view of the second active pattern AP2 taken in the first direction X may be similar to Figure 2 .

[0033] Reference Figures 1 to 4According to some embodiments, a semiconductor device includes a first active pattern AP1, a second active pattern AP2, a plurality of gate electrodes 120, a first source / drain pattern 150, a second source / drain pattern 250, a first back wiring contact 170, a second back wiring contact 270, a first front source / drain contact 175, a second front source / drain contact 275, a first back wiring line 50, a second back wiring line 60, and a front wiring structure 195.

[0034] The first back wiring line 50 and the second back wiring line 60 may be disposed within the back interlayer insulating film 290. Each of the first back wiring line 50 and the second back wiring line 60 may extend in the first direction X. The first back wiring line 50 may be spaced apart from the second back wiring line 60 in the second direction Y.

[0035] In one example, each of the first back wiring line 50 and the second back wiring line 60 may be a power line for supplying power to the semiconductor device. In another example, each of the first back wiring line 50 and the second back wiring line 60 may be a signal line for supplying an operation signal of the semiconductor device. In yet another example, one of the first back wiring line 50 and the second back wiring line 60 may be a power line, and the other one thereof may be a signal line.

[0036] The first back wiring line 50 includes a first surface 50_S1 and a second surface 50_S2 opposite to each other in the third direction Z. The second back wiring line 60 may include a first surface and a second surface opposite to each other in the third direction Z. The first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60 may face the first active pattern AP1 and the second active pattern AP2. In this regard, the first direction X may intersect the second direction Y and the third direction Z. In addition, the second direction Y may intersect the third direction Z.

[0037] Each of the first back wiring line 50 and the second back wiring line 60 is shown to have a trapezoidal cross section. However, the embodiments of the present disclosure are not limited thereto. Different from what is shown, each of the first back wiring line 50 and the second back wiring line 60 may have a rectangular cross section. The first back wiring line 50 is described as an example. The width of the first surface 50_S1 of the first back wiring line in the second direction Y may be less than the width of the second surface 50_S2 of the first back wiring line in the second direction Y.

[0038] For example, the first back wiring line 50 and the second back wiring line 60 may be formed using a damascene process. After forming a trench extending in the first direction X in the first back interlayer insulating film 290 , the trench may be filled with a conductive material to form the first back wiring line 50 .

[0039] Each of the first back wiring line 50 and the second back wiring line 60 is shown as having a single conductive film structure. However, the embodiments of the present disclosure are not limited thereto. Unlike what is shown, each of the first back wiring line 50 and the second back wiring line 60 may have a multi-conductive film structure including a wiring barrier film and a wiring filling film, such as Figures 2 to 4 Like the front wiring line 197 shown.

[0040] Each of the first back wiring line 50 and the second back wiring line 60 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material. The two-dimensional material (2D material) may include a two-dimensional allotrope or a two-dimensional compound. The two-dimensional material (2D material) may, for example, include at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. However, the present disclosure is not limited thereto. That is, the above-mentioned 2D materials are listed only as examples. The 2D materials that may be included in the semiconductor device according to some embodiments of the present disclosure are not limited to the above-mentioned materials.

[0041] Unlike what is shown, each of the first back wiring line 50 and the second back wiring line 60 may extend in the second direction Y. In this case, Figure 1 The shape of a cross-sectional view thereof taken at each of AA, BB, and CC in the figure may be changed.

[0042] For example, the back interlayer insulating film 290 may include at least one of silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, and a low dielectric constant (low-k) material. The dielectric constant of the low-k material may have a value lower than the dielectric constant of silicon oxide, and the dielectric constant of silicon oxide is 3.9. The back interlayer insulating film 290 is shown as a single film. However, this is only for convenience of explanation, and the embodiments of the present disclosure are not limited thereto.

[0043] Each of the first and second active patterns AP1 and AP2 may be disposed on the back interlayer insulating film 290. A portion of the back interlayer insulating film 290 may be disposed between the first active pattern AP1 and the first back wiring line 50 and between the second active pattern AP2 and the second back wiring line 60.

[0044] Each of the first active pattern AP1 and the second active pattern AP2 may extend in an elongated manner in the first direction X. For example, the first active pattern AP1 and the second active pattern AP2 may be disposed on the first back wiring line 50 and the second back wiring line 60, respectively. The first active pattern AP1 and the second active pattern AP2 may be disposed on the first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60, respectively.

[0045] The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in the second direction Y. The first active pattern AP1 and the second active pattern AP2 may be adjacent to each other in the second direction Y.

[0046] The first active pattern AP1 is shown to be closest to the second active pattern AP2 in the second direction Y. However, embodiments of the present disclosure are not limited thereto. In another example, an additional active pattern may be disposed between the first active pattern AP1 and the second active pattern AP2.

[0047] In one example, the first active pattern AP1 may be a region in which a p-type transistor is formed, and the second active pattern AP2 may be a region in which an n-type transistor is formed. In another example, each of the first active pattern AP1 and the second active pattern AP2 may be a region in which a p-type transistor is formed. In yet another example, each of the first active pattern AP1 and the second active pattern AP2 may be a region in which an n-type transistor is formed.

[0048] Each of the first active pattern AP1 and the second active pattern AP2 may be a multi-channel active pattern. For example, the first active pattern AP1 includes a first lower pattern BP1 and a plurality of first sheet patterns NS1. The second active pattern AP2 includes a second lower pattern BP2 and a plurality of second sheet patterns NS2. In a semiconductor device according to some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may be an active pattern including nanosheets or nanowires.

[0049] The first and second lower patterns BP1 and BP2 may be disposed on the back interlayer insulating film 290. In the semiconductor device according to some embodiments, a portion of the back interlayer insulating film 290 may be disposed between the first lower pattern BP1 and the first back wiring line 50, and between the second lower pattern BP2 and the second back wiring line 60.

[0050] Each of the first lower pattern BP1 and the second lower pattern BP2 may protrude in the third direction Z. Each of the first lower pattern BP1 and the second lower pattern BP2 may be a fin type pattern.

[0051] Each of the first and second lower patterns BP1 and BP2 may extend in an elongated manner in the first direction X. The first lower pattern BP1 may be spaced apart from the second lower pattern BP2 in the second direction Y. The first and second lower patterns BP1 and BP2 may be isolated from each other by the fin trench extending in the first direction X.

[0052] The first lower pattern BP1 includes a first surface BP1_S1 and a second surface BP1_S2 opposite to each other in the third direction Z. The second surface BP1_S2 of the first lower pattern may face the back interlayer insulating film 290, the first back wiring line 50, and the second back wiring line 60. The first back wiring line 50 and the second back wiring line 60 may be disposed on the second surface BP1_S2 of the first lower pattern.

[0053] For example, the second surface BP1_S2 of the first lower pattern may be a bottom surface of the first lower pattern BP1. The first surface BP1_S1 of the first lower pattern may be an upper surface of the first lower pattern BP1.

[0054] As in the first lower pattern BP1 , the second lower pattern BP2 may include first and second surfaces opposite to each other in the third direction Z. The second surface of the second lower pattern BP2 may face the back interlayer insulating film 290 , the first back wiring line 50 , and the second back wiring line 60 .

[0055] In the semiconductor device according to some embodiments, the first lower pattern BP1 may contact the back interlayer insulating film 290. The second lower pattern BP2 may contact the back interlayer insulating film 290.

[0056] The first lower pattern BP1 includes a sidewall connecting the first surface BP1_S1 of the first lower pattern and the second surface BP1_S2 of the first lower pattern to each other. The sidewall of the first lower pattern BP1 may extend in the first direction X. The second lower pattern BP2 may include a sidewall extending in the first direction X. The sidewall of the second lower pattern BP2 faces the sidewall of the first lower pattern BP1.

[0057] A plurality of first sheet patterns NS1 may be disposed on the first lower pattern BP1. A plurality of first sheet patterns NS1 may be disposed on the first surface BP1_S1 of the first lower pattern. The plurality of first sheet patterns NS1 may be spaced apart from the first lower pattern BP1 in the third direction Z.

[0058] The plurality of second sheet patterns NS2 may be disposed on the second lower pattern BP2. The plurality of second sheet patterns NS2 may be disposed on a first surface of the second lower pattern BP2. The plurality of second sheet patterns NS2 may be spaced apart from the second lower pattern BP2 in the third direction Z.

[0059] The first sheet pattern NS1 and the second sheet pattern NS2 may be respectively disposed on the first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60. Three first sheet patterns NS1 and three second sheet patterns NS2 are shown to be arranged in the third direction Z. However, this is only for convenience of explanation, and embodiments of the present disclosure are not limited thereto.

[0060] The first sheet pattern NS1 may include an upper surface and a bottom surface opposite to each other in the third direction Z. The bottom surface of the first sheet pattern NS1 may face the first back wiring line 50 .

[0061] The first sheet pattern NS1 may include an uppermost sheet pattern farthest from the first back wiring line 50 and the second back wiring line 60. The upper surface AP1_US of the first active pattern may be an upper surface of the uppermost sheet pattern among the first sheet pattern NS1. The description of the second active pattern AP2 and the second sheet pattern NS2 may be substantially the same as the description of the first active pattern AP1 and the first sheet pattern NS1.

[0062] Each of the first and second lower patterns BP1 and BP2 may include silicon or germanium as an elemental semiconductor material. Alternatively, each of the first and second lower patterns BP1 and BP2 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0063] Group IV-IV compound semiconductors may include, for example, binary compounds containing two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), ternary compounds containing three of them, or compounds obtained by doping Group IV elements therein.

[0064] The III-V compound semiconductor may include, for example, a binary compound, a ternary compound, or a quaternary compound obtained by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0065] Each of the first sheet pattern NS1 and the second sheet pattern NS2 may include one of an elemental semiconductor material such as silicon or germanium, a group IV-IV compound semiconductor, and a group III-V compound semiconductor. The width of the first sheet pattern NS1 in the second direction Y may increase or decrease in proportion to the width of the first lower pattern BP1 in the second direction Y. The width of the second sheet pattern NS2 in the second direction Y may increase or decrease in proportion to the width of the second lower pattern BP2 in the second direction Y.

[0066] Taking the first sheet pattern NS1 as an example, although it is shown that the widths of the first sheet patterns NS1 disposed on the first lower pattern BP1 in the second direction Y are equal to each other, embodiments of the present disclosure are not limited thereto.

[0067] The field insulating film 105 may be disposed on the first back wiring line 50 and the second back wiring line 60. For example, the field insulating film 105 may be disposed on the first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60.

[0068] The field insulating film 105 may be disposed on the sidewalls of the first lower pattern BP1 and the sidewalls of the second lower pattern BP2. In one example, the field insulating film 105 may cover the entire sidewalls of the first lower pattern BP1 and the entire sidewalls of the second lower pattern BP2. Different from what is shown, in another example, the field insulating film 105 may cover a portion of the sidewalls of the first lower pattern BP1 and / or a portion of the sidewalls of the second lower pattern BP2.

[0069] The field insulating film 105 does not cover the first surface BP1_S1 of the first lower pattern BP1 and the first surface of the second lower pattern BP2. The first sheet pattern NS1 and the second sheet pattern NS2 are disposed above the upper surface of the field insulating film 105 based on the first back wiring line 50 and the second back wiring line 60. The field insulating film 105 may include an upper surface and a bottom surface opposite to each other in the third direction Z. The bottom surface of the field insulating film 105 faces the first back wiring line 50 and the second back wiring line 60.

[0070] The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. The field insulating film 105 is shown as a single film. However, this is only for convenience of description, and embodiments of the present disclosure are not limited thereto.

[0071] A plurality of gate structures GS may be disposed on the upper surface of the field insulating film 105. Each gate structure GS may extend in the second direction Y. The gate structures GS may be arranged to be spaced apart from each other in the first direction X. The gate structures GS may be adjacent to each other in the first direction X.

[0072] The gate structure GS may be disposed on the first active pattern AP1 and the second active pattern AP2. The gate structure GS may cross the first active pattern AP1 and the second active pattern AP2.

[0073] The gate structure GS may be disposed on the first lower pattern BP1 and the second lower pattern BP2. The gate structure GS may surround each of the first sheet patterns NS1. The gate structure GS may surround each of the second sheet patterns NS2.

[0074] The gate structure GS is shown to extend across the first active pattern AP1 and the second active pattern AP2. However, this is only for convenience of explanation, and the embodiments of the present disclosure are not limited thereto. That is, the gate structure GS can be divided into two parts via a gate isolation structure disposed on the field insulating film 105, so that the two parts are respectively disposed on the first active pattern AP1 and the second active pattern AP2.

[0075] The gate structure GS may include, for example, a gate electrode 120 , a gate insulating film 130 , a gate spacer 140 , and a gate capping pattern 145 .

[0076] The gate structure GS includes a plurality of inner gate structures I_GS, which are respectively disposed between first sheet patterns NS1 adjacent to each other in the third direction Z and between the first lower pattern BP1 and the lowermost first sheet pattern NS1. Each inner gate structure I_GS may be disposed between the first surface BP1_S1 of the first lower pattern and the bottom surface of the first sheet pattern NS1, or between the upper surface of the first sheet pattern NS1 facing each other and the bottom surface of the first sheet pattern NS1 adjacent thereto in the third direction Z. Each inner gate structure I_GS includes a gate electrode 120 and a gate insulating film 130.

[0077] The number of inner gate structures I_GS may be equal to the number of first sheet patterns NS1. Each inner gate structure I_GS contacts the first surface BP1_S1 of the first lower pattern and the bottom surface of the first sheet pattern NS1, or the upper surface of the first sheet pattern NS1 and the bottom surface of the first sheet pattern NS1. In a semiconductor device according to some embodiments, the inner gate structure I_GS may contact a first source / drain pattern 150 to be described later.

[0078] Each inner gate structure I_GS includes a gate electrode 120 and a gate insulating film 130 disposed between adjacent first sheet patterns NS1 or between the first lower pattern BP1 and the first sheet pattern NS1.

[0079] The inner gate structure I_GS may be respectively disposed between the second sheet patterns NS2 adjacent to each other in the third direction Z, and between the second lower pattern BP2 and the lowermost second sheet pattern NS2.

[0080] The gate electrode 120 may be disposed on the first and second lower patterns BP1 and BP2. The gate electrode 120 may cross the first and second lower patterns BP1 and BP2. The gate electrode 120 may surround each of the first and second sheet patterns NS1 and NS2.

[0081] In such Figure 2In the cross-sectional view shown, the upper surface of the gate electrode 120 is shown as a concave curved surface. However, the present disclosure is not limited thereto. In another example, the upper surface of the gate electrode 120 may be flat.

[0082] The gate electrode 120 may include at least one of a metal, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal silicon nitride, and a conductive metal oxynitride. The gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (Ta The conductive metal oxide and the conductive metal oxynitride may include at least one of the above materials. The conductive metal oxide and the conductive metal oxynitride may include at least one of the above materials. The conductive metal oxide and the conductive metal oxynitride may include at least one of the above materials.

[0083] The gate insulating film 130 may extend along the upper surface of the field insulating film 105, the first surface BP1_S1 of the first lower pattern, and the first surface of the second lower pattern BP2. The gate insulating film 130 may surround each of the plurality of first sheet patterns NS1. The gate insulating film 130 may surround each of the plurality of second sheet patterns NS2. The gate insulating film 130 may be disposed around each of the first sheet pattern NS1 and the second sheet pattern NS2. The gate electrode 120 is disposed on the gate insulating film 130.

[0084] The gate insulating film 130 is disposed between the gate electrode 120 and each first sheet pattern NS1 and between the gate electrode 120 and each second sheet pattern NS2. In the semiconductor device according to some embodiments, the gate insulating film 130 included in the inner gate structure I_GS may contact the first source / drain pattern 150 described later.

[0085] The gate insulating film 130 may include silicon oxide, silicon oxynitride, silicon nitride or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant (high-k) material may, for example, include at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

[0086] Although the gate insulating film 130 is shown as being implemented as a single film, this is only for convenience of explanation, and the present disclosure is not limited thereto. The gate insulating film 130 may include a plurality of films. The gate insulating film 130 may include an interface film and a high dielectric constant insulating film disposed between the first active pattern AP1 and the gate electrode 120 and between the second active pattern AP2 and the gate electrode 120. For example, the interface film may not be formed along the contour of the upper surface of the field insulating film 105.

[0087] The semiconductor device according to some embodiments may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the gate insulating film 130 may include a gate ferroelectric material film having ferroelectric properties and a gate paraelectric material film having paraelectric properties.

[0088] The gate ferroelectric material film may have a negative capacitance, and the gate paraelectric material film may have a positive capacitance. For example, when two or more capacitors may be connected in series to each other and the capacitance of each of the capacitors has a positive value, the total capacitance is less than the capacitance of each individual capacitor. On the contrary, when at least one of the capacitances of two or more capacitors connected in series to each other has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitor.

[0089] When a gate ferroelectric material film having a negative capacitance and a gate paraelectric material film having a positive capacitance are connected in series with each other, the total capacitance value of the gate ferroelectric material film and the gate paraelectric material film connected in series with each other can be increased. With the increase in the total capacitance value, a transistor including the gate ferroelectric material film can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0090] The gate ferroelectric material film may have ferroelectric properties. The gate ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In this regard, in one example, hafnium zirconium oxide may refer to a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may refer to a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0091] The gate ferroelectric material film may further include dopants incorporated therein. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the gate ferroelectric material film may vary depending on the type of ferroelectric material included in the gate ferroelectric material film.

[0092] When the gate ferroelectric material film includes hafnium oxide, the dopant contained in the gate ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0093] When the dopant is aluminum (Al), the gate ferroelectric material film may contain about 3 at% (atomic %) to about 8 at% (atomic %) of aluminum. In this regard, the content of the dopant may be the content of aluminum based on the sum of hafnium and aluminum.

[0094] When the dopant is silicon (Si), the gate ferroelectric material film may contain about 2at% to about 10at% silicon. When the dopant is yttrium (Y), the gate ferroelectric material film may contain about 2at% to about 10at% yttrium. When the dopant is gadolinium (Gd), the gate ferroelectric material film may contain about 1at% to about 7at% gadolinium. When the dopant is zirconium (Zr), the gate ferroelectric material film may contain about 50at% to about 80at% zirconium.

[0095] The gate paraelectric material film may have paraelectric properties. The gate paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide with a high dielectric constant. The metal oxide contained in the gate paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide and aluminum oxide. However, the present disclosure is not limited thereto.

[0096] The gate ferroelectric material film and the gate paraelectric material film may include the same material. The gate ferroelectric material film may have ferroelectric properties, but the gate paraelectric material film may not have ferroelectric properties. For example, when each of the gate ferroelectric material film and the gate paraelectric material film includes hafnium oxide or hafnium zirconium oxide, the crystal structure of the hafnium oxide contained in the gate ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the gate paraelectric material film. For example, the gate ferroelectric material film may include grains having an orthorhombic crystal system.

[0097] The gate ferroelectric material film may have a thickness that is sized to exhibit ferroelectric properties. Although the thickness of the gate ferroelectric material film may be, for example, in the range of about 0.5 to about 10 nm, the present disclosure is not limited thereto. Because the critical thickness for exhibiting ferroelectric properties may vary based on the type of ferroelectric material, the thickness of the gate ferroelectric material film may vary depending on the type of ferroelectric material.

[0098] In one example, the gate insulating film 130 may include a gate ferroelectric material film. In another example, the gate insulating film 130 may include a plurality of gate ferroelectric material films spaced apart from each other. The gate insulating film 130 may have a multilayer structure in which a plurality of gate ferroelectric material films and a plurality of gate paraelectric material films are alternately stacked on top of each other.

[0099] The gate spacer 140 may be disposed on the sidewall of the gate electrode 120. The gate spacer 140 may not be disposed between the first lower pattern BP1 and the lowermost first sheet pattern NS1 and between the first sheet patterns NS1 adjacent to each other in the third direction Z.

[0100] The gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and at least one of a combination thereof. The present disclosure is not limited thereto. Although it is shown that the gate spacer 140 is implemented as a single film, this is only for convenience of explanation, and the present disclosure is not limited thereto.

[0101] The gate capping pattern 145 may be disposed on the gate electrode 120 . An upper surface 145US of the gate capping pattern may be coplanar with an upper surface of the first front interlayer insulating film 190 .

[0102] Unlike what is shown, in one example, the gate capping pattern 145 may be disposed between the gate spacers 140. In another example, the gate structure GS may not include the gate capping pattern 145. The gate capping pattern may not be disposed on the gate electrode 120.

[0103] For example, the gate capping pattern 145 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The gate capping pattern 145 may include a material having an etching selectivity relative to the material of the first front interlayer insulating film 190.

[0104] The first source / drain pattern 150 may be disposed on the first active pattern AP1. The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain patterns 150 disposed on the first active pattern AP1 may be spaced apart from each other in the first direction X.

[0105] The first source / drain pattern 150 may be disposed between the gate electrodes 120 adjacent to each other in the first direction X. The first source / drain pattern 150 may be disposed on a side surface of the gate electrode 120. The first source / drain pattern 150 may contact the first active pattern AP1. The first source / drain pattern 150 may contact the first sheet pattern NS1. The first source / drain pattern 150 may be disposed on the first surface 50_S1 of the first back wiring line.

[0106] The first source / drain pattern 150 includes a first back connection epitaxial pattern 150_1 and a first front connection epitaxial pattern 150_2. The first back connection epitaxial pattern 150_1 may be connected to the first back wiring line 50. The first front connection epitaxial pattern 150_2 may be connected to the front wiring line 197. Each of the first back connection epitaxial pattern 150_1 and the first front connection epitaxial pattern 150_2 is one of the first source / drain patterns 150.

[0107] The second source / drain pattern 250 may be disposed on the second active pattern AP2. The second source / drain pattern 250 may be disposed on the second lower pattern BP2. The second source / drain pattern 250 may be spaced apart from the first source / drain pattern 150 in the second direction Y.

[0108] The second source / drain pattern 250 may contact the second active pattern AP2 . The second source / drain pattern 250 may contact the second sheet pattern NS2 . The second source / drain pattern 250 may be disposed on a first surface of the second back wiring line 60 .

[0109] Like the first source / drain pattern 150 , the second source / drain pattern 250 may include a back connection epitaxial pattern connected to the second back wiring line 60 and a front connection epitaxial pattern connected to the front wiring line 197 .

[0110] The first source / drain pattern 150 may be included in a source / drain of a transistor using the first sheet pattern NS1 as a channel region. The second source / drain pattern 250 may be included in a source / drain of a transistor using the second sheet pattern NS2 as a channel region.

[0111] exist Figure 4, the shape of each of the first source / drain pattern 150 and the second source / drain pattern 250 is shown to be similar to a hexagon. However, the embodiments of the present disclosure are not limited thereto. Different from what is shown, the shape of each of the first source / drain pattern 150 and the second source / drain pattern 250 may be similar to a pentagon or a quadrilateral.

[0112] The first source / drain pattern 150 includes a bottom surface 150BS facing the first lower pattern BP1. The bottom surface 150BS of the first source / drain pattern may be connected to the first lower pattern BP1. The bottom surface 150BS of the first source / drain pattern may be disposed lower than the first surface BP1_S1 of the first lower pattern. For example, the bottom surface 150BS of the first source / drain pattern may contact the first lower pattern BP1. The second source / drain pattern 250 includes a bottom surface 250BS connected to the second lower pattern BP2.

[0113] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include an epitaxial pattern. Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include a semiconductor material.

[0114] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include, for example, silicon or germanium as an elemental semiconductor material. Alternatively, each of the first source / drain pattern 150 and the second source / drain pattern 250 may include, for example, a binary compound containing two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), a ternary compound containing three of them, or a compound obtained by doping a group IV element therein. Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include an epitaxial film made of a semiconductor material. Each of the first source / drain pattern 150 and the second source / drain pattern 250 is shown as a single film. However, this is only for convenience of explanation, and embodiments of the present disclosure are not limited thereto.

[0115] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include a dopant doped into the semiconductor material. In one example, each of the first source / drain pattern 150 and the second source / drain pattern 250 may include a p-type dopant. In another example, each of the first source / drain pattern 150 and the second source / drain pattern 250 may include an n-type dopant. In yet another example, the first source / drain pattern 150 may include a p-type dopant, and the second source / drain pattern 250 may include an n-type dopant.

[0116] For example, the p-type dopant may include at least one of boron (B) and gallium (Ga). However, the embodiments of the present disclosure are not limited thereto. For example, the n-type dopant may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). However, the embodiments of the present disclosure are not limited thereto.

[0117] The first front interlayer insulating film 190 is disposed on the first lower pattern BP1, the second lower pattern BP2, and the field insulating film 105. The first front interlayer insulating film 190 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 250. The first front interlayer insulating film 190 may not cover the upper surface 145US of the gate capping pattern. For example, the upper surface of the first front interlayer insulating film 190 may be coplanar with the upper surface 145US of the gate capping pattern.

[0118] The first front interlayer insulating film 190 is disposed on the first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60 .

[0119] For example, the first front interlayer insulating film 190 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluoride silicate glass), polyimide nanofoam such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof. However, the spirit of the present disclosure is not limited thereto.

[0120] The source / drain etch stop film 185 may extend along the outline of the first source / drain pattern 150 and the outline of the second source / drain pattern 250. The source / drain etch stop film 185 may be disposed between the first source / drain pattern 150 and the first front interlayer insulating film 190, and between the second source / drain pattern 250 and the first front interlayer insulating film 190.

[0121] The source / drain etch stop film 185 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0122] The first back wiring contact 170 may extend in an elongated manner in the third direction Z. The first back wiring contact 170 may be connected to the first source / drain pattern 150. For example, the first back wiring contact 170 may be connected to the first back connection epitaxial pattern 150_1. The first back wiring contact 170 is electrically connected to the first source / drain pattern 150.

[0123] The first back wiring contact 170 may connect the first source / drain pattern 150 and the first back wiring line 50 to each other. The first back wiring contact 170 may be connected to the first back wiring line 50. The first back wiring contact 170 may be connected to the first surface 50_S1 of the first back wiring line.

[0124] The first back wiring contact 170 may be disposed between the first source / drain pattern 150 and the first back wiring line 50. In the semiconductor device according to some embodiments, the first back wiring contact 170 may overlap the first back wiring line 50 and the first source / drain pattern 150 in the third direction Z. The first back wiring contact 170 may overlap a bottom surface 150BS of the first source / drain pattern in the third direction Z.

[0125] For example, at least a portion of the first back wiring contact 170 may be disposed within the back interlayer insulating film 290 and the first lower pattern BP1. A portion of the first back wiring contact 170 may be disposed within the back interlayer insulating film 290. The first back wiring contact 170 may extend from the first surface 50_S1 of the first back wiring line to the first source / drain pattern 150. Unlike shown, the back interlayer insulating film 290 may not be disposed between the second surface BP1_S2 of the first lower pattern and the first surface 50_S1 of the first back wiring line.

[0126] The first back wiring contact 170 includes a first surface 170_S1 facing the first back wiring line 50. The first surface 170_S1 of the first back wiring contact may be connected to the first back wiring line 50. The first back wiring contact 170 includes a sidewall 170SW extending in the third direction Z from the first surface 170_S1 of the first back wiring contact.

[0127] The first back wiring contact 170 includes a first back contact barrier film 170A, a first back contact plug film 170B, and a first back ferroelectric material film 170C. The first back ferroelectric material film 170C may be disposed between the first back contact barrier film 170A and the first back contact plug film 170B.

[0128] The first back ferroelectric material film 170C may extend along the outline of the first back contact barrier film 170A. The first back ferroelectric material film 170C may define a first contact plug recess 170C_R. The first back contact plug film 170B may fill the first contact plug recess 170C_R. The first back ferroelectric material film 170C may extend along a sidewall of the first back contact plug film 170B extending in the third direction Z.

[0129] The first back ferroelectric material film 170C may extend along a bottom surface of the first back contact plug film 170B.

[0130] A bottom surface of the first back contact plug film 170B faces the first source / drain pattern 150 .

[0131] A vertical length H11 from the second surface 50_S2 of the first back wiring line to the first surface 170_S1 of the first back wiring contact may be smaller than a vertical length H12 from the second surface 50_S2 of the first back wiring line to the bottom surface 150BS of the first source / drain pattern. The vertical length H12 from the second surface 50_S2 of the first back wiring line to the bottom surface 150BS of the first source / drain pattern may be greater than a vertical length H12 from the second surface 50_S2 of the first back wiring line to the bottom surface 150BS of the first source / drain pattern. Figure 2 A cross-sectional view rather than a Figure 4 Measured in cross-section.

[0132] As the size of semiconductor devices decreases, the size of back wiring contacts connected to back wiring lines decreases. As the size of the back wiring contacts decreases, the resistance of the back wiring contacts may increase.

[0133] The first back ferroelectric material film 170C may be disposed between the first back contact barrier film 170A and the first back contact plug film 170B, so that the resistance of the first back wiring contact 170 may be reduced. Therefore, the current flow in the third direction Z in the first back wiring contact 170 may be improved. Thus, the performance and reliability of the semiconductor device may be improved.

[0134] The first back contact barrier film 170A may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal oxynitride, a conductive metal silicon nitride, a conductive metal carbon nitride, and a two-dimensional material. The first back contact plug film 170B may include a metal. The first back ferroelectric material film 170C may include a ferroelectric material. The description of the first back ferroelectric material film 170C may be substantially the same as the description of the gate ferroelectric material film as described above.

[0135] The first back contact silicide film 155 may be disposed between the first back wiring contact 170 and the first source / drain pattern 150. The first back contact silicide film 155 contacts the first back wiring contact 170. The first back contact silicide film 155 may include a metal silicide material.

[0136] The contact insulating pad 171 may extend along the sidewall 170SW of the first back wiring contact. The contact insulating pad 171 may be disposed between the first back wiring contact 170 and the first lower pattern BP1. Unlike shown, the contact insulating pad 171 may not be disposed between the first back wiring contact 170 and the first lower pattern BP1. The contact insulating pad 171 may include an insulating material.

[0137] The connection structure in which the second back wiring contact 270 is electrically connected to the second source / drain pattern 250 on the second lower pattern BP2 may be similar to Figure 2 and Figure 4 The second back wiring contact 270 may be connected to the second back wiring line 60 .

[0138] The first front source / drain contact 175 may extend in the third direction Z. The first front source / drain contact 175 may be connected to the first source / drain pattern 150. For example, the first front source / drain contact 175 may be connected to the first front connection epitaxial pattern 150_2. The first front source / drain contact 175 is electrically connected to the first source / drain pattern 150.

[0139] The first front source / drain contact 175 is disposed on the first surface BP1_S1 of the first lower pattern. The first source / drain pattern 150 may be disposed between the first front source / drain contact 175 and the first back wiring line 50. The first front source / drain contact 175 may be disposed within the first front interlayer insulating film 190 and the first source / drain pattern 150. A portion of the first front source / drain contact 175 may be disposed within the first source / drain pattern 150. The first front source / drain contact 175 does not extend through the first lower pattern BP1.

[0140] A vertical length from the upper surface AP1_US of the first active pattern to the upper surface 175US of the first front source / drain contact may be equal to a vertical length from the upper surface AP1_US of the first active pattern to the upper surface 145US of the first gate capping pattern.

[0141] The second front source / drain contact 275 may be disposed on the second source / drain pattern 250. The second source / drain pattern 250 may be disposed between the second front source / drain contact 275 and the second back wiring line 60. The second front source / drain contact 275 is disposed on a first surface of the second back wiring line 60. The second front source / drain contact 275 may be connected to the second source / drain pattern 250. The second front source / drain contact 275 is electrically connected to the second source / drain pattern 250.

[0142] The first front source / drain contact 175 includes a first front contact barrier film 175A and a first front contact plug film 175B. The second front source / drain contact 275 includes a second front contact barrier film 275A and a second front contact plug film 275B.

[0143] Each of the first front contact barrier film 175A and the second front contact barrier film 275A may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal oxynitride, a conductive metal silicon nitride, a conductive metal carbon nitride, and a two-dimensional material. Each of the first front contact plug film 175B and the second front contact plug film 275B may include a metal.

[0144] The first front contact silicide film 156 may be disposed between the first front source / drain contact 175 and the first source / drain pattern 150. The second front contact silicide film 256 may be disposed between the second front source / drain contact 275 and the second source / drain pattern 250. Each of the first front contact silicide film 156 and the second front contact silicide film 256 may include a metal silicide material.

[0145] The second front interlayer insulating film 191 may be disposed on the first front interlayer insulating film 190, the gate structure GS, and the front source / drain contacts 175 and 275. The second front interlayer insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, and a low dielectric constant material.

[0146] The front wiring structure 195 may be disposed within the second front interlayer insulating film 191. The front wiring structure 195 is disposed on the first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60. The front wiring structure 195 includes a front via plug 196 and a front wiring line 197.

[0147] The front wiring structure 195 may be connected to the first front source / drain contact 175. The front wiring structure 195 may be connected to the upper surface 175US of the first front source / drain contact.

[0148] The first front source / drain contact 175 may be disposed between the front wiring structure 195 and the first source / drain pattern 150. The first front source / drain contact 175 may connect the front wiring structure 195 and the first source / drain pattern 150 to each other. The first front source / drain contact 175 may be connected to the front wiring line 197. For example, the front wiring structure 195 may not be connected to the first source / drain pattern 150 connected to the first back wiring contact 170.

[0149] Unlike what is shown, the front wiring structure 195 may be connected to the first back connection epitaxial pattern 150_1 via another front source / drain contact. That is, the front wiring structure 195 may be connected to the first back wiring contact 170 via the first back connection epitaxial pattern 150_1.

[0150] The front wiring structure 195 may be connected to the second front source / drain contact 275. The description regarding the first front source / drain contact 175 may be applied to the second front source / drain contact 275.

[0151] The front wiring structure 195 may include a front via plug 196 and a front wiring line 197. The front wiring line 197 includes a front wiring barrier film 197A and a front wiring plug film 197B.

[0152] The front via plug 196 may have a single conductive film structure, and the front wiring line 197 may have a multi-conductive film structure.

[0153] Unlike what is shown, in one example, the front via plug 196 may have a multi-conductive film structure like the front wiring line 197. In another example, the front wiring line 197 may have a single conductive film structure like the front via plug 196. In yet another example, the front via plug 196 and the front wiring line 197 may have a structure integral with each other without a boundary existing therebetween.

[0154] The front wiring barrier film 197A may include at least one of metal, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal oxynitride, conductive metal silicon nitride, conductive metal carbon nitride, and a two-dimensional material. Each of the front via plug 196 and the front wiring plug film 197B may include a metal.

[0155] Figure 5 and Figure 6 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figures 1 to 4 The descriptions are different.

[0156] refer to Figure 5 and Figure 6 , the semiconductor device according to some embodiments may further include a sacrificial epitaxial pattern 170SC disposed within the first lower pattern BP1 .

[0157] The sacrificial epitaxial pattern 170SC may be disposed between the first source / drain pattern 150 and the first back wiring line 50. The first source / drain pattern 150 may be disposed on the sacrificial epitaxial pattern 170SC.

[0158] The sacrificial epitaxial pattern 170SC may overlap the first source / drain pattern 150 in the third direction Z. The sacrificial epitaxial pattern 170SC may overlap the first back wiring contact 170 in the first direction X.

[0159] For example, the sacrificial epitaxial pattern 170SC may be disposed between the first front connection epitaxial pattern 150_2 and the first back wiring line 50. The first front connection epitaxial pattern 150_2 may be disposed on the sacrificial epitaxial pattern 170SC. The first front connection epitaxial pattern 150_2 may overlap the sacrificial epitaxial pattern 170SC in the third direction Z.

[0160] The sacrificial epitaxial pattern 170SC may be disposed within the second lower pattern BP2. The sacrificial epitaxial pattern 170SC may be disposed under the second source / drain pattern 250 connected to the front wiring line 197. The sacrificial epitaxial pattern 170SC may be disposed between the second source / drain pattern 250 and the second back wiring line 60.

[0161] The sacrificial epitaxial pattern 170SC may include a material having an etch selectivity with respect to a material of each of the first and second lower patterns BP1 and BP2 . The sacrificial epitaxial pattern 170SC may include a semiconductor material.

[0162] The first back wiring contact 170 includes a first portion 170BP and a second portion 170UP. The first portion 170BP of the first back wiring contact is directly connected to the second portion 170UP of the first back wiring contact. The first portion 170BP of the first back wiring contact may be disposed between the second portion 170UP of the first back wiring contact and the first back wiring line 50. For example, the second portion 170UP of the first back wiring contact may be formed by filling a space obtained by removing the sacrificial epitaxial pattern 170SC with a conductive material and a ferroelectric material.

[0163] The width of the first portion 170BP of the first back wiring contact 170 in the second direction Y decreases as the first portion extends away from the first surface 50_S1 of the first back wiring line. The width of the second portion 170UP of the first back wiring contact 170 in the second direction Y is shown to be constant. However, this is only for convenience of explanation, and embodiments of the present disclosure are not limited thereto.

[0164] In one example, the second portion 170UP of the first back wiring contact may be distinguished from the first portion 170BP of the first back wiring contact at a point where the width of the first back wiring contact 170 in the first direction X or the second direction Y changes. For example, the width of the first back wiring contact 170 may suddenly decrease near a boundary between the second portion 170UP of the first back wiring contact and the first portion 170BP of the first back wiring contact.

[0165] In another example, the second portion 170UP of the first back wiring contact may be distinguished from the first portion 170BP of the first back wiring contact at a point where the slope of the sidewall 170SW of the first back wiring contact changes. Near a boundary between the second portion 170UP of the first back wiring contact and the first portion 170BP of the first back wiring contact, the slope of the sidewall 170SW of the first portion 170BP of the first back wiring contact may be different from the slope of the sidewall 170SW of the second portion 170UP of the first back wiring contact.

[0166] The second portion 170UP of the first back wiring contact may be distinguished from the first portion 170BP thereof based on a variation trend of the width of the first back wiring contact 170 or a variation of the slope of the sidewall 170SW of the first back wiring contact.

[0167] Unlike what is shown, as the first back wiring contact 170 extends away from the first surface 50_S1 of the first back wiring line, the width of the first back wiring contact 170 in the first direction X or the second direction Y continuously decreases. Alternatively, the first back wiring contact 170 may not include a point where the slope of the sidewall 170SW of the first back wiring contact changes. That is, the first back wiring contact 170 may not be divided into a first portion 170BP of the first back wiring contact and a second portion 170UP of the first back wiring contact.

[0168] The contact insulating pad 171 is shown to extend along the sidewall 170SW of the second portion 170UP of the first back wiring contact and the sidewall 170SW of the first portion 170BP of the first back wiring contact. However, embodiments of the present disclosure are not limited thereto.

[0169] Unlike what is shown, in one example, the contact insulating pad 171 may be formed on the sidewall 170SW of the second portion 170UP of the first back wiring contact, but may not be formed on the sidewall 170SW of the first portion 170BP of the first back wiring contact. In another example, the contact insulating pad 171 may not be formed on the sidewall 170SW of the second portion 170UP of the first back wiring contact, but may be formed on the sidewall 170SW of the first portion 170BP of the first back wiring contact. In yet another example, the portion of the contact insulating pad 171 on the sidewall 170SW of the second portion 170UP of the first back wiring contact may not be directly connected to the portion of the contact insulating pad 171 on the sidewall 170SW of the first portion 170BP of the first back wiring contact.

[0170] Figure 7 and Figure 8 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figure 5 and Figure 6 The descriptions are different.

[0171] refer to Figure 7 and Figure 8 In a semiconductor device according to some embodiments, the sacrificial epitaxial pattern ( Figure 5 170SC) in may not be disposed under the first source / drain pattern 150 connected to the first front source / drain contact 175.

[0172] Sacrificial epitaxial pattern ( Figure 5 170SC) may not be disposed under the second source / drain pattern 250 connected to the second front source / drain contact 275.

[0173] Sacrificial epitaxial pattern ( Figure 5 170SC) in the first back wiring contact 170 and the Figure 1 The sacrificial epitaxial pattern 170SC formed during the manufacturing process may be removed in the process of forming the first and second back source / drain contacts 170 and 270.

[0174] Fig. 9 and Fig.10 is a schematic diagram for explaining a semiconductor device according to some embodiments. Figure 11 to Figure 13 is a schematic diagram for explaining a semiconductor device according to some embodiments.

[0175] refer to Fig. 9 and Fig.10The semiconductor device according to some embodiments may further include a back contact connection pattern 180 disposed between the first back wiring contact 170 and the first back wiring line 50 .

[0176] The back contact connection pattern 180 may connect the first back wiring contact 170 and the first back wiring line 50 to each other.

[0177] The back contact connection pattern 180 includes a back connection barrier film 180A and a back connection plug film 180B. The back connection barrier film 180A may include at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal oxynitride, a conductive metal silicon nitride, a conductive metal carbon nitride, and a two-dimensional material. The back connection plug film 180B may include a metal.

[0178] Unlike what is shown, in one example, the back contact connection pattern 180 may have a single conductive film structure. In another example, the back contact connection pattern 180 may further include a ferroelectric material film disposed between the back connection barrier film 180A and the back connection plug film 180B.

[0179] The back connection pattern insulating liner may extend along a sidewall of the back contact connection pattern 180. The sidewall of the back contact connection pattern 180 may extend in the third direction Z.

[0180] Figure 11 to Figure 13 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figures 1 to 4 The descriptions are different.

[0181] Reference Figures 11 to 13 , in the semiconductor device according to some embodiments, the first active pattern AP1 may include only the first sheet pattern NS1 .

[0182] The second active pattern AP2 may include only the second sheet pattern NS2. In other words, the first active pattern AP1 may not include the first lower pattern ( Figure 3 The second active pattern AP2 may not include the second lower pattern ( Figure 3 BP2 in ).

[0183] A back insertion insulating film 291 may be disposed between the first source / drain pattern 150 and the first back wiring line 50. A back insertion insulating film 291 may be disposed between the second source / drain pattern 250 and the second back wiring line 60.

[0184] The first back wiring contact 170 may be disposed within the back insertion insulating film 291. The back insertion insulating film 291 may cover the first back wiring contact 170. The back insertion insulating film 291 may cover the sidewall 170SW of the first back wiring contact.

[0185] Since the first back wiring contact 170 is disposed within the back insertion insulating film 291, the contact insulating pad 171 may not be disposed on the sidewall 170SW of the first back wiring contact. The back insertion insulating film 291 may contact the sidewall 170SW of the first back wiring contact.

[0186] The back insertion insulating film 291 may be formed by filling a space obtained by removing the first and second lower patterns BP1 and BP2 with an insulating material. The back insertion insulating film 291 may include an insulating material.

[0187] When the back insertion insulating film 291 includes the same material as the field insulating film 105, the boundary between the back insertion insulating film 291 and the field insulating film 105 may not be defined. In this case, an insulating pattern surrounding the first back wiring contact 170 may be provided between the first source / drain pattern 150 and the first back wiring line 50.

[0188] Fig.14 and Fig.15 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figures 11 to 13 The descriptions are different.

[0189] refer to Fig.14 and Fig.15 , the semiconductor device according to some embodiments may further include a sacrificial epitaxial pattern 170SC disposed within the back insertion insulating film 291 .

[0190] The back insertion insulating film 291 may cover the sacrificial epitaxial pattern 170SC. For example, the back insertion insulating film 291 may contact the sacrificial epitaxial pattern 170SC.

[0191] The sacrificial epitaxial pattern 170SC in the back insertion insulating film 291 may be disposed between the first source / drain pattern 150 and the first back wiring line 50. The sacrificial epitaxial pattern 170SC in the back insertion insulating film 291 may be disposed between the second source / drain pattern 250 and the second back wiring line 60. The sacrificial epitaxial pattern 170SC may include a semiconductor material.

[0192] Fig.16 is a schematic diagram for explaining a semiconductor device according to some embodiments. Fig.17 is a schematic diagram for explaining a semiconductor device according to some embodiments. Fig.18is a schematic diagram for explaining a semiconductor device according to some embodiments. Fig.19 and Fig. 20 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figures 1 to 4 The descriptions are different.

[0193] refer to Fig.16 , the semiconductor device according to some embodiments may further include inner spacers 140IN, each of the inner spacers 140IN being disposed between a corresponding inner gate structure I_GS and the first source / drain pattern 150 .

[0194] The inner spacers 140IN may be respectively disposed between the first sheet patterns NS1 adjacent to each other in the third direction Z and between the lowermost first sheet pattern NS1 and the first lower pattern BP1 . The inner spacers 140IN may contact the first source / drain patterns 150 .

[0195] Each of the inner spacers 140IN may include an insulating material.

[0196] In one example, in a cross-sectional view of the second active pattern AP2 taken in the first direction X, each inner spacer 140IN may be disposed between a corresponding inner gate structure I_GS and the second source / drain pattern 250 .

[0197] In another example, in a cross-sectional view of the second active pattern AP2 taken in the first direction X, each inner spacer 140IN may not be disposed between the corresponding inner gate structure I_GS and the second source / drain pattern 250. In other words, a cross-sectional view of the second active pattern AP2 taken in the first direction X may be similar to Figure 2 .

[0198] Reference Fig.17 In the semiconductor device according to some embodiments, the front wiring line 197 may further include a front wiring ferroelectric material film 197C disposed between the front wiring barrier film 197A and the front wiring plug film 197B.

[0199] The front wiring ferroelectric material film 197C may include a ferroelectric material. The description about the front wiring ferroelectric material film 197C may be substantially the same as the description about the gate ferroelectric material film as set forth above.

[0200] The front wiring line 197 includes the front wiring ferroelectric material film 197C, so that the resistance of the front wiring line 197 can be reduced.

[0201] Unlike what is shown, the second front source / drain contact 275 may further include a ferroelectric material film disposed between the second front contact barrier film 275A and the second front contact plug film 275B.

[0202] refer to Fig.18 , in the semiconductor device according to some embodiments, the first lower pattern BP1 and the second lower pattern BP2 may protrude from the substrate 100 in the third direction Z.

[0203] The substrate 100 may be disposed between the back interlayer insulating film 290 and the first lower pattern BP1 and between the back interlayer insulating film 290 and the second lower pattern BP2. The back interlayer insulating film 290 may be in contact with the substrate 100.

[0204] For example, the first back wiring contact 170 may extend through the substrate 100. Fig. 9 and Fig.10 When the back contact connection pattern 180 is provided as shown, the back contact connection pattern 180 may extend through the substrate 100 .

[0205] The substrate 100 may be made of bulk silicon or silicon on insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, embodiments of the present disclosure are not limited thereto.

[0206] refer to Fig.19 and Fig. 20 In the semiconductor device according to some embodiments, the first active pattern AP1 may not include the first sheet pattern ( Figure 2 NS1 in the .

[0207] The second active pattern AP2 may not include a second sheet pattern ( Figure 3 NS2 in the .

[0208] Inner gate structure ( Figure 2 The I_GS in the first direction X may not be disposed between the first source / drain patterns 150 adjacent to each other in the first direction X.

[0209] Figure 21 to Figure 25 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figures 1 to 4 The descriptions are different.

[0210] For reference, Fig.21 is an example layout diagram for illustrating a semiconductor device according to some embodiments. Fig. 22 is along Fig.21 Cross-sectional view taken at AA in . Fig.23 is along Fig.21 Cross-sectional view taken through BB in FIG. Fig.24 and Fig.25 Along Fig.21 A cross-sectional view taken along line CC.

[0211] refer to Figure 21 to Figure 25 , the semiconductor device according to some embodiments may further include a front contact connection via 160 .

[0212] The first lower pattern BP1 and the second lower pattern BP2 may protrude from the substrate 100 in the third direction Z. For example, the first lower pattern BP1 and the second lower pattern BP2 may protrude from the upper surface of the substrate 100 .

[0213] Unlike what is shown, the substrate 100 may not be provided. In this case, the first lower pattern BP1 and the second lower pattern BP2 may contact the back interlayer insulating film 290 .

[0214] When another active pattern adjacent to the first active pattern AP1 in the second direction Y is provided, the third back wiring contact 370 may be provided between the first active pattern AP1 and the other active pattern adjacent to each other in the second direction Y. Unlike shown, the third back wiring contact 370 may be provided between the first active pattern AP1 and the second active pattern AP2.

[0215] The semiconductor device according to some embodiments may include a third back wiring contact 370 connected to the first back wiring line 50 .

[0216] The third back wiring contact 370 may be disposed between the lower patterns adjacent to each other in the second direction Y. The third back wiring contact 370 may overlap a portion of the field insulating film 105 disposed between the lower patterns in the third direction Z.

[0217] The third back wiring contact 370 is shown to have a contact shape. However, embodiments of the present disclosure are not limited thereto. The third back wiring contact 370 may have a line shape.

[0218] The third back wiring contact 370 may connect the first source / drain pattern 150 and the first back wiring line 50 to each other. The third back wiring contact 370 may be connected to the first surface 50_S1 of the first back wiring line.

[0219] The third back wiring contact 370 may be connected to the first front source / drain contact 175 via the front contact connection via 160. The third back wiring contact 370 may be electrically connected to the first source / drain pattern 150 via the first front source / drain contact 175.

[0220] The third back wiring contact 370 may extend through the substrate 100 . The third back wiring contact 370 may extend in the third direction Z. For example, a portion of the third back wiring contact 370 may protrude beyond the upper surface of the substrate 100 in the third direction Z. A portion of the third back wiring contact 370 may be disposed within the field insulating film 105 .

[0221] The third back wiring contact 370 may not overlap the first lower pattern BP1 in the third direction Z. The third back wiring contact 370 may not overlap the bottom surface 150BS of the first source / drain pattern in the third direction Z. The third back wiring contact 370 may not be disposed within the first lower pattern BP1. The third back wiring contact 370 may overlap the first lower pattern BP1 in the second direction Y.

[0222] Unlike what is shown, the third back wiring contact 370 may not protrude beyond the upper surface of the substrate 100 in the third direction Z.

[0223] The third back wiring contact 370 includes a first surface 370_S1 facing the first back wiring line 50 The first surface 370_S1 of the third back wiring contact may be connected to the first back wiring line 50.

[0224] The third back wiring contact 370 includes a third back contact barrier film 370A, a third back contact plug film 370B, and a third back ferroelectric material film 370C. The third back ferroelectric material film 370C may be disposed between the third back contact barrier film 370A and the third back contact plug film 370B. The third back contact plug film 370B may fill a third contact plug recess 370C_R defined by the third back ferroelectric material film 370C.

[0225] exist Fig.24 , a vertical length H11 from the second surface 50_S2 of the first back wiring line to the first surface 370_S1 of the third back wiring contact may be smaller than a vertical length H12 from the second surface 50_S2 of the first back wiring line to the bottom surface 150BS of the first source / drain pattern.

[0226] The descriptions about the materials respectively included in the third back contact barrier film 370A, the third back contact plug film 370B and the third back ferroelectric material film 370C may be substantially the same as the descriptions about the materials respectively included in the first back contact barrier film 170A, the first back contact plug film 170B and the first back ferroelectric material film 170C.

[0227] A contact insulation pad may be disposed along a sidewall of the third back wiring contact 370 .

[0228] The front contact connection via 160 may be disposed between the first front source / drain contact 175 and the third back wiring contact 370. The front contact connection via 160 may connect the first back connection epitaxial pattern 150_1 and the third back wiring contact 370 to each other.

[0229] For example, the front contact connection via 160 may be directly connected to the first front source / drain contact 175. The front contact connection via 160 may extend through the source / drain etch stop film 185 to be connected to the third back wiring contact 370. A portion of the front contact connection via 160 may be disposed within the field insulating film 105.

[0230] The front contact connection via 160 may be spaced apart from the first source / drain pattern 150 in the second direction Y. The front contact connection via 160 may overlap the first source / drain pattern 150 in the second direction Y. A width of the front contact connection via 160 in the second direction Y may increase as the front contact connection via 160 extends away from the first back wiring line 50.

[0231] The front contact connection via 160 includes a front connection via blocking film 160A and a front connection via plug film 160B. The front connection via plug film 160B may be disposed on the front connection via blocking film 160A. The front connection via blocking film 160A may extend along the sidewall and bottom surface of the front connection via plug film 160B.

[0232] For example, the front connection via blocking film 160A may include at least one of, for example, metal, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal oxynitride, conductive metal silicon nitride, conductive metal carbon nitride, and a two-dimensional material. The front connection via plug film 160B may include metal.

[0233] Unlike shown, the front connection via plug film 160B may contact the third back wiring contact 370. The front connection via plug film 160B may contact the third back contact barrier film 370A. The front connection via barrier film 160A may extend along the sidewalls of the front connection via plug film 160B, but may not extend along the bottom surface of the front connection via plug film 160B.

[0234] exist Fig.24 In the embodiment, the front contact connection via 160 may not include a ferroelectric material film disposed between the front connection via barrier film 160A and the front connection via plug film 160B.

[0235] exist Fig.25In the embodiment of the present invention, the front contact connection path 160 further includes a front connection ferroelectric material film 160C disposed between the front connection path barrier film 160A and the front connection path plug film 160B. The front connection ferroelectric material film 160C may include a ferroelectric material. The description of the front connection ferroelectric material film 160C may be substantially the same as the description of the gate ferroelectric material film as described above.

[0236] Figures 26 to 30 is a schematic diagram for illustrating a semiconductor device according to some embodiments. For the convenience of description, the following description focuses on its Figures 1 to 4 The descriptions are different.

[0237] For reference, Fig.26 is an example layout diagram for illustrating a semiconductor device according to some embodiments. Fig. 27 is along Fig.26 Cross-sectional view taken at AA in . Fig.28 is along Fig.26 Cross-sectional view taken from CC in . Fig.29 and Fig.30 Along Fig.26 A cross-sectional view taken along line DD.

[0238] Reference Figures 26 to 30 , the semiconductor device according to some embodiments may further include a third active pattern AP3 , a fourth active pattern AP4 , a fourth back wiring contact 470 , a third front source / drain contact 375 , a fourth front source / drain contact 475 , and an element isolation structure 165 .

[0239] The third and fourth active patterns AP3 and AP4 may be disposed on the back interlayer insulating film 290. The third and fourth active patterns AP3 and AP4 may extend in the first direction X. The third active pattern AP3 may be spaced apart from the fourth active pattern AP4 in the second direction Y.

[0240] The third and fourth active patterns AP3 and AP4 may be disposed on the first and second back wiring lines 50 and 60. The third and fourth active patterns AP3 and AP4 may be disposed on the first surface 50_S1 of the first and second back wiring lines 60, respectively.

[0241] The third active pattern AP3 may be spaced apart from the first active pattern AP1 in the first direction X. The first active pattern AP1 and the third active pattern AP3 may be aligned with each other on a line along the first direction X.

[0242] The fourth active pattern AP4 may be spaced apart from the second active pattern AP2 in the first direction X. The second active pattern AP2 and the fourth active pattern AP4 may be aligned with each other on a line along the first direction X.

[0243] Like each of the first and second active patterns AP1 and AP2 , each of the third and fourth active patterns AP3 and AP4 may include a lower pattern and a plurality of sheet patterns.

[0244] Gate electrodes may be disposed on the third and fourth active patterns AP3 and AP4.

[0245] A source / drain pattern similar to each of the first source / drain pattern 150 and the second source / drain pattern 250 may be disposed on each of the third active pattern AP3 and the fourth active pattern AP4 .

[0246] A pair of element isolation structures 165 may be disposed on the back interlayer insulating film 290, the first back wiring line 50 and the second back wiring line 60. The element isolation structure 165 may be disposed on the first surface 50_S1 of the first back wiring line and the first surface of the second back wiring line 60.

[0247] The pair of element isolation structures 165 may include a first sub-element isolation structure and a second sub-element isolation structure. The first sub-element isolation structure and the second sub-element isolation structure may extend in the second direction Y. The first sub-element isolation structure may be spaced apart from the second sub-element isolation structure in the first direction X.

[0248] The element isolation structure 165 may isolate the first lower pattern BP1 and the lower pattern included in the third active pattern AP3 from each other. The element isolation structure 165 may isolate the second lower pattern BP2 and the lower pattern included in the fourth active pattern AP4 from each other. The first active pattern AP1 and the third active pattern AP3 are not disposed between the first sub-element isolation structure and the second sub-element isolation structure. The second active pattern AP2 and the fourth active pattern AP4 are not disposed between the first sub-element isolation structure and the second sub-element isolation structure. A portion of the field insulating film 105 may be disposed between the first sub-element isolation structure and the second sub-element isolation structure that are adjacent to each other in the first direction X.

[0249] Unlike what is shown, a dummy active pattern including a semiconductor material may be disposed between the pair of element isolation structures 165 .

[0250] The first lower pattern BP1 may protrude from the first sub-element isolation structure in the first direction X. The lower pattern included in the third active pattern AP3 may protrude from the second sub-element isolation structure in the first direction X.

[0251] The vertical length between the first surface BP1_S1 of the first lower pattern and the upper surface of the element isolation structure 165 may be equal to the vertical length between the first surface BP1_S1 of the first lower pattern and the upper surface 145US of the gate capping pattern. Different from what is shown, based on the first surface BP1_S1 of the first lower pattern, the vertical height of the upper surface of the element isolation structure 165 may be higher than the vertical height of the upper surface 145US of the gate capping pattern.

[0252] The element isolation structure 165 may include an insulating material. The element isolation structure 165 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon carbide oxide (SiOC), and combinations thereof. Each of the first sub-element isolation structure and the second sub-element isolation structure is shown as being formed as a single film. However, embodiments of the present disclosure are not limited thereto.

[0253] An insulating residual pattern may be disposed between the first sub-element isolation structure and the first source / drain pattern 150. The insulating residual pattern may include the same material as that of the gate insulating film 130.

[0254] A first front interlayer insulating film 190 and a source / drain etch stop film 185 may be disposed between the pair of element isolation structures 165. For example, an insulating spacer pattern in contact with the source / drain etch stop film 185 may be disposed between the first sub-element isolation structure and the source / drain etch stop film 185. The insulating spacer pattern may include the same material as that of the gate spacer 140.

[0255] The first source / drain pattern 150 and the second source / drain pattern 250 may be disposed between the gate electrode 120 and the element isolation structure 165 .

[0256] The first front source / drain contact 175 and the second front source / drain contact 275 may be disposed between the gate electrode 120 and the element isolation structure 165 .

[0257] The third front source / drain contact 375 and the fourth front source / drain contact 475 may be disposed on the source / drain patterns disposed on the third active pattern AP3 and the fourth active pattern AP4, respectively. The shape of each of the third front source / drain contact 375 and the fourth front source / drain contact 475 as taken in the second direction Y may be similar to Fig.28 The shape of the.

[0258] The semiconductor device according to some embodiments includes a fourth back wiring contact 470 connected to the first back wiring line 50 .

[0259] The fourth back wiring contact 470 may be disposed between the pair of element isolation structures 165. The fourth back wiring contact 470 may be disposed between the first sub-element isolation structure and the second sub-element isolation structure adjacent to each other in the first direction X.

[0260] The fourth back wiring contact 470 may connect the first source / drain pattern 150 and the first back wiring line 50 to each other. The fourth back wiring contact 470 may be connected to the first surface 50_S1 of the first back wiring line.

[0261] The fourth back wiring contact 470 may be connected to the first front source / drain contact 175 via the front wiring structure 195. The front wiring line 197 may connect the fourth back wiring contact 470 and the first front source / drain contact 175 to each other. The fourth back wiring contact 470 may be electrically connected to the first source / drain pattern 150 via the first front source / drain contact 175.

[0262] The fourth back wiring contact 470 may extend through the substrate 100 . The fourth back wiring contact 470 may extend in the third direction Z. For example, the fourth back wiring contact 470 may extend from the first back wiring line 50 to the front wiring line 197 .

[0263] The fourth back wiring contact 470 may not overlap the first lower pattern BP1 in the third direction Z. The fourth back wiring contact 470 may not overlap the bottom surface 150BS of the first source / drain pattern in the third direction Z. The fourth back wiring contact 470 may not be disposed within the first lower pattern BP1. The fourth back wiring contact 470 may not overlap the first lower pattern BP1 in the second direction Y.

[0264] The fourth back wiring contact 470 includes a first surface 470_S1 facing the first back wiring line 50. The first surface 470_S1 of the fourth back wiring contact may be connected to the first back wiring line 50. A vertical length from the second surface 50_S2 of the first back wiring line to the first surface 470_S1 of the fourth back wiring contact may be less than a vertical length H12 from the second surface 50_S2 of the first back wiring line to the bottom surface 150BS of the first source / drain pattern.

[0265] The fourth back wiring contact 470 includes a fourth back contact barrier film 470A, a fourth back contact plug film 470B, and a fourth back ferroelectric material film 470C. The fourth back ferroelectric material film 470C may be disposed between the fourth back contact barrier film 470A and the fourth back contact plug film 470B.

[0266] The descriptions of materials respectively included in the fourth back contact barrier film 470A, the fourth back contact plug film 470B, and the fourth back ferroelectric material film 470C may be substantially the same as the descriptions of materials respectively included in the first back contact barrier film 170A, the first back contact plug film 170B, and the first back ferroelectric material film 170C.

[0267] exist Fig.29 In the embodiment of the present invention, as the fourth back wiring contact 470 extends away from the first back wiring line 50 , the width of the fourth back wiring contact 470 in the first direction X may decrease.

[0268] exist Fig.30 In the embodiment of the present invention, as the fourth back wiring contact 470 extends away from the first back wiring line 50 , the width of the fourth back wiring contact 470 in the first direction X may increase.

[0269] Figures 31 to 38 is a schematic diagram of an intermediate structure corresponding to an intermediate step of a method for fabricating a semiconductor device according to some embodiments.

[0270] refer to Fig.31 , the first lower pattern BP1 and the upper pattern structure U_AP may be formed on the substrate 100 .

[0271] The second lower pattern BP2 and the upper pattern structure U_AP may be formed on the substrate 100 .

[0272] Each of the first and second lower patterns BP1 and BP2 may extend in the first direction X. An upper pattern structure U_AP may be disposed on each of the first and second lower patterns BP1 and BP2.

[0273] The upper pattern structure U_AP may include sacrificial patterns SC_L and active patterns ACT_L alternately stacked on each other. The sacrificial patterns SC_L and the active patterns ACT_L may be alternately stacked on each other while being disposed on each of the first and second lower patterns BP1 and BP2.

[0274] For example, the sacrificial pattern SC_L may include a silicon germanium layer. The active pattern ACT_L may include a silicon film.

[0275] A field insulating film 105 may be formed on the substrate 100. The field insulating film 105 may cover at least a portion of a sidewall of the first lower pattern BP1 and at least a portion of a sidewall of the second lower pattern BP2.

[0276] Subsequently, a pre-spacer film 140P may be formed along the sidewalls and upper surfaces of the upper pattern structure U_AP and the upper surface of the field insulating film 105. The pre-spacer film 140P may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0277] refer to Fig.31 and Fig.32 , the upper pattern structure U_AP of the first lower pattern BP1 and the upper pattern structure U_AP of the second lower pattern BP2 may be removed by an etching process.

[0278] While the upper pattern structure U_AP is removed, a portion of the pre-spacer film 140P disposed on an upper surface of the upper pattern structure U_AP may be removed. In addition, at least a portion of the pre-spacer film 140P disposed on a sidewall of the upper pattern structure U_AP may be removed.

[0279] A portion of the first lower pattern BP1 and / or a portion of the second lower pattern BP2 may be removed to form a sacrificial epitaxial pattern ( Figure 6 Thus, a sacrificial epitaxial hole in which the sacrificial epitaxial pattern 170SC is to be formed may be formed in the first lower pattern BP1 and / or the second lower pattern BP2. Subsequently, a sacrificial epitaxial pattern 170SC may be formed within the sacrificial epitaxial hole.

[0280] Hereinafter, some embodiments are described in which a manufacturing process is performed in a state where the sacrificial epitaxial pattern 170SC is not formed.

[0281] refer to Fig.33 , a first source / drain pattern 150 may be formed on the first lower pattern BP1.

[0282] The second source / drain pattern 250 may be formed on the second lower pattern BP2. When the first source / drain pattern 150 and the second source / drain pattern 250 are respectively included in the source / drain of transistors of different conductivity types, the first source / drain pattern 150 and the second source / drain pattern 250 may be formed in different epitaxial processes.

[0283] The source / drain etch stop film 185 may be formed along an upper surface of the field insulating film 105 , an outline of the first source / drain pattern 150 , and an outline of the second source / drain pattern 250 .

[0284] refer to Fig.34 , a first front interlayer insulating film 190 may be formed on the source / drain etch stop film 185 .

[0285] Subsequently, a second front source / drain contact 275 may be formed on the second source / drain pattern 250. The second front source / drain contact 275 is connected to the second source / drain pattern 250.

[0286] The second front interlayer insulating film 191 may be formed on the first front interlayer insulating film 190 and the second front source / drain contacts 275. The front wiring structure 195 may be formed within the second front interlayer insulating film 191.

[0287] Reference Fig.34 and Fig.35 , the substrate 100 may be removed.

[0288] The substrate 100 may be removed to expose the first and second lower patterns BP1 and BP2. The field insulating film 105 may be exposed.

[0289] Subsequently, a first back interlayer insulating film 290_1 may be formed on the first and second lower patterns BP1 and BP2.

[0290] Contrary to what is shown, the first back interlayer insulating film 290_1 may not be formed.

[0291] Reference Fig.35 and Fig.36 , the first back source / drain contact holes 170H may be formed by removing a portion of the first lower pattern BP1.

[0292] The first back source / drain contact holes 170H may expose the first source / drain patterns 150 .

[0293] refer to Fig.36 and Fig.37 , a contact insulation liner 171 may be formed on a sidewall of the first back source / drain contact hole 170H.

[0294] On the exposed first source / drain patterns 150 , a first back contact silicide film 155 may be formed.

[0295] Subsequently, a first back contact barrier film 170A may be formed along sidewalls of the first back source / drain contact holes 170H and an upper surface of the first back interlayer insulating film 290_1 . The first back contact barrier film 170A may be formed on the contact insulating liner 171 and the first back contact silicide film 155 .

[0296] The first back ferroelectric material film 170C may be formed on the first back contact barrier film 170A. The first back ferroelectric material film 170C may be formed along the contour of the first back contact barrier film 170A. The first back ferroelectric material film 170C may define a first contact plug recess 170C_R.

[0297] Reference Fig.37 and Fig.38 , the first back contact plug film 170B may be formed within the first contact plug recess 170C_R.

[0298] The first back contact plug film 170B may fill the first contact plug recess 170C_R. Thus, the first back wiring contact 170 may be formed.

[0299] When the first back contact plug film 170B is formed, the first back contact barrier film 170A and the first back ferroelectric material film 170C formed along the upper surface of the first back interlayer insulating film 290_1 may be removed.

[0300] Then, refer to Figure 4 , a second back interlayer insulating film may be formed on the first back source / drain contact 170. The first back interlayer insulating film 290_1 and the second back interlayer insulating film may constitute the back interlayer insulating film 290. The first back wiring line 50 and the second back wiring line 60 may be formed in the second back interlayer insulating film.

[0301] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed. Certain technical features described in the present disclosure in the context of separate implementations can also be implemented in a single implementation in a combined manner. On the contrary, the various technical features described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. In addition, although the technical features can be described above as working in certain combinations, one or more technical features in the combination can be deleted from the combination in some cases, and the combination can be directed to a sub-combination or a variation of the sub-combination.

[0302] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive, but illustrative in all aspects.

[0303] This application claims the benefit of Korean Patent Application No. 10-2024-0044810 filed on April 2, 2024, and Korean Patent Application No. 10-2023-0145556 filed on October 27, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Back interlayer insulating film; a back wiring line disposed in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite to each other in a first direction; a fin-shaped pattern, disposed on the first surface of the back wiring line, the fin-shaped pattern extending in a second direction; a source / drain pattern disposed on the fin pattern, wherein a bottom surface of the source / drain pattern is connected to the fin pattern and faces the back wiring line; as well as a back wiring contact connecting the back wiring line and the source / drain pattern to each other, wherein the back wiring contact comprises a back contact barrier film, a back contact plug film and a back ferroelectric material film, wherein the back ferroelectric material film is disposed between the back contact barrier film and the back contact plug film, wherein the back wiring contact comprises a third surface facing the back wiring line, and wherein a vertical length from the second surface of the back wiring line to the third surface of the back wiring contact is smaller than a vertical length from the second surface of the back wiring line to the bottom surface of the source / drain pattern. 2 . The semiconductor device according to claim 1 , wherein the back wiring contact is provided between the source / drain pattern and the back wiring line, and wherein the back wiring contact overlaps the source / drain pattern in the first direction. 3 . The semiconductor device according to claim 2 , further comprising a contact insulation pad disposed between the back wiring contact and the fin pattern, the contact insulation pad extending along a sidewall of the back wiring contact. 4 . The semiconductor device according to claim 2 , further comprising a back contact connection pattern provided between the back wiring contact and the back wiring line, the back contact connection pattern connecting the back wiring contact and the back wiring line to each other. 5 . The semiconductor device according to claim 2 , wherein the fin type pattern is in contact with the back interlayer insulating film.

6. The semiconductor device according to claim 2, further comprising: A second source / drain pattern is disposed on the fin pattern; as well as A sacrificial epitaxial pattern is disposed within the fin pattern and between the second source / drain pattern and the back wiring line.

7. The semiconductor device according to claim 1, further comprising a front source / drain contact disposed on the source / drain pattern, wherein the source / drain pattern is disposed between the front source / drain contact and the back wiring line, and wherein the back wiring contact is electrically connected to the source / drain pattern via the front source / drain contact.

8. The semiconductor device according to claim 7, further comprising a front contact connection via disposed between the front source / drain contact and the back wiring contact, The front contact connection path overlaps the source / drain pattern in a third direction.

9. A semiconductor device according to claim 8, wherein the front contact connection path includes a front connection path barrier film, a front connection path plug film and a front connection ferroelectric material film, and wherein the front connection ferroelectric material film is arranged between the front connection path barrier film and the front connection path plug film.

10. The semiconductor device according to claim 7, further comprising a front wiring line disposed on and connected to the front source / drain contact, The front wiring line connects the front source / drain contact and the back wiring contact to each other.

11. The semiconductor device according to claim 1 further includes a front wiring line arranged on the source / drain pattern, wherein the front wiring line includes a front wiring plug film, a front wiring barrier film and a front wiring ferroelectric material film, and the front wiring ferroelectric material film is arranged between the front wiring plug film and the front wiring barrier film.

12. A semiconductor device comprising: Back interlayer insulating film; a back wiring line disposed in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite to each other in a first direction; a first source / drain pattern disposed on the first surface of the back wiring line; as well as a back wiring contact disposed between the first source / drain pattern and the back wiring line, the back wiring contact being connected to the first source / drain pattern and overlapping the first source / drain pattern in the first direction, The back wiring contact includes a back contact barrier film, a back contact plug film and a back ferroelectric material film, and the back ferroelectric material film is disposed between the back contact barrier film and the back contact plug film.

13. The semiconductor device according to claim 12, further comprising a fin pattern provided on the first surface of the back wiring line and extending in a second direction, wherein the fin pattern is disposed between the first source / drain pattern and the back wiring line, and At least a portion of the back wiring contact is disposed within the fin pattern. 14 . The semiconductor device of claim 13 , further comprising a contact insulation pad disposed between the back wiring contact and the fin pattern and extending along a sidewall of the back wiring contact. 15 . The semiconductor device according to claim 12 , further comprising a back contact connection pattern provided between the back wiring contact and the back wiring line, the back contact connection pattern connecting the back wiring contact and the back wiring line to each other. 16 . The semiconductor device according to claim 12 , further comprising a back insertion insulating film disposed between the back interlayer insulating film and the first source / drain pattern, wherein the back insertion insulating film is in contact with a side wall of the back wiring contact.

17. The semiconductor device according to claim 12, further comprising: a second source / drain pattern disposed on the first surface of the back wiring line and spaced apart from the first source / drain pattern in a second direction; as well as A sacrificial epitaxial pattern is disposed between the second source / drain pattern and the back wiring line. 18 . The semiconductor device according to claim 17 , wherein the sacrificial epitaxial pattern overlaps the back wiring contact in the second direction. 19 . The semiconductor device according to claim 17 , further comprising a front wiring line disposed on the first source / drain pattern and the second source / drain pattern and connected to the second source / drain pattern.

20. A semiconductor device comprising: Back interlayer insulating film; a back wiring line disposed in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite to each other in a first direction; a fin-shaped pattern, disposed on the first surface of the back wiring line, the fin-shaped pattern extending in a second direction; a plurality of sheet patterns, arranged on the fin pattern; a gate electrode disposed on the fin pattern, surrounding the plurality of sheet patterns, and extending in a third direction; a source / drain pattern disposed on the fin pattern and connected to the plurality of sheet patterns, wherein the source / drain pattern is disposed on a side surface of the gate electrode, wherein a bottom surface of the source / drain pattern is connected to the fin pattern and faces the back wiring line; as well as a back wiring contact connecting the back wiring line and the source / drain pattern to each other, wherein the back wiring contact comprises a back contact barrier film, a back contact plug film and a back ferroelectric material film, wherein the back ferroelectric material film is disposed between the back contact barrier film and the back contact plug film, wherein the back wiring contact comprises a third surface facing the back wiring line, and wherein a vertical length from the second surface of the back wiring line to the third surface of the back wiring contact is smaller than a vertical length from the second surface of the back wiring line to the bottom surface of the source / drain pattern.

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