Array substrate and display panel

Abstract

The embodiment of the invention provides an array substrate and a display panel, and aims to improve the processing performance of the display panel. The array substrate is used for the display panel. The array substrate comprises a substrate; the pixel circuit is arranged on the substrate, and the pixel circuit comprises a seventh transistor; the first reference signal line is located on the side, away from the substrate, of the seventh transistor; the array substrate further comprises first via holes, and the first reference signal lines are electrically connected with the seventh transistors of the two adjacent pixel circuits through the same first via hole. And the two seventh transistors share one first via hole, so that the number of via holes formed in the array substrate can be reduced, the preparation of the array substrate is simplified, the processing property of the array substrate is improved, and the processing property of the display panel is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel, aiming to improve the process performance of the display panel.

[0005] An embodiment of the first aspect of the present application provides an array substrate for a display panel, the array substrate comprising: a substrate; a pixel circuit, arranged on the substrate, the pixel circuit comprising a seventh transistor; a first reference signal line, located on a side of the seventh transistor away from the substrate; wherein the array substrate further comprises a first via hole, the first reference signal line being electrically connected to the seventh transistors of two adjacent pixel circuits through the same first via hole.

[0006] According to an implementation of the first aspect of the present application, the array substrate includes an active layer, a first insulating layer and a first conductive layer stacked in sequence in a direction away from the substrate, the pixel circuit includes a plurality of transistors, the seventh transistor is one of the plurality of transistors, and the transistor includes a semiconductor portion located in the active layer and a gate located in the first conductive layer.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the array substrate further includes: a light-emitting control signal line located in the first conductive layer; a plurality of transistors including a light-emitting control transistor, and a portion of the light-emitting control signal line forms a gate of the light-emitting control transistor.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, at least two pixel circuits adjacent to each other along the first direction are symmetrically arranged relative to a reference line extending along the second direction.

[0009] The first reference signal line extends along the first direction, and the first reference signal line is electrically connected to the seventh transistors of two adjacent and mutually symmetrical pixel circuits through the same first via hole.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the seventh transistor is an anode reset transistor.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the first via is arranged centered in the first direction with respect to its corresponding two seventh transistors.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes: an electrical connection portion, which is arranged on the side of the first reference signal line facing away from the substrate, and the array substrate also includes a second via hole, the electrical connection portion is electrically connected to the first reference signal line through the second via hole, and the electrical connection portion is electrically connected to the seventh transistors of two adjacent pixel circuits through the same first via hole, so that the first reference signal line is electrically connected to the seventh transistors of two adjacent pixel circuits through the electrical connection portion.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the first reference signal line is extended and formed along the first direction; the array substrate also includes a second reference signal line located on the side of the first reference signal line away from the substrate, the second reference signal line is extended and formed along the second direction, and the electrical connection portion and the second reference signal line are connected through a third via hole, wherein at least one third via hole and the second via hole are respectively arranged on both sides of the first via hole in the first direction.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, multiple pixel circuit arrays are distributed, the first direction is the row direction, the second direction is the column direction, multiple first reference signal lines are arranged side by side along the second direction, multiple second reference signal lines are arranged side by side along the first direction, and the multiple first reference signal lines are electrically connected to the multiple second reference signal lines in a grid shape.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, the same first reference signal line corresponds to multiple pixel circuits in the same row, and the same second reference signal line corresponds to multiple pixel circuits in four columns.

[0016] According to any of the aforementioned implementations of the first aspect of the present application, the second reference signal line and the first reference signal line are used to transmit the second reset voltage signal.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the array substrate also includes a third reference signal line and a fourth via, the pixel circuit also includes an eighth transistor, the third reference signal line is electrically connected to the eighth transistor through the fourth via, wherein in the same pixel circuit area, the fourth via is located on the side of the second via away from the first via.

[0018] According to any of the aforementioned implementations of the first aspect of the present application, the fourth via holes corresponding to the two pixel circuits are arranged on both sides of the first via hole in the first direction.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, at least one fourth via hole is located on a side of the third via hole away from the first via hole.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, the third reference signal line is extended and formed along the first direction; the array substrate also includes a fourth reference signal line, the fourth reference signal line is extended and formed along the second direction, and the third reference signal line and the fourth reference signal line are connected through a fifth via hole, wherein at least one fifth via hole and the fourth via hole are located on the same side of the first via hole in the first direction.

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, multiple pixel circuits are distributed in an array along a first direction and a second direction, the first direction is a row direction, and the second direction is a column direction; multiple third reference signal lines are arranged side by side along the second direction, and multiple fourth reference signal lines are arranged side by side along the first direction, and the multiple third reference signal lines are electrically connected to the multiple fourth reference signal lines in a grid shape.

[0022] According to any of the aforementioned embodiments of the first aspect of the present application, the same third reference signal line corresponds to multiple pixel circuits in the same row, and the same fourth reference signal line corresponds to multiple pixel circuits in four columns.

[0023] According to any of the aforementioned implementations of the first aspect of the present application, the third reference signal line and the fourth reference signal line are used to transmit a third reset voltage signal.

[0024] According to any of the aforementioned embodiments of the first aspect of the present application, the first reference signal line is extended along a first direction, and the array substrate also includes a second reference signal line located on a side of the first reference signal line away from the substrate, and the second reference signal line is extended along a second direction, wherein the second reference signal line and the fourth reference signal line are alternately arranged along the first direction.

[0025] According to any of the aforementioned embodiments of the first aspect of the present application, two pixel circuits arranged side by side along the first direction are arranged between the adjacent second reference signal line and the fourth reference signal line.

[0026] According to any of the aforementioned embodiments of the first aspect of the present application, the array substrate also includes an active layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer stacked in sequence in a direction away from the substrate, and the first reference signal line is located in the second conductive layer.

[0027] According to any of the aforementioned embodiments of the first aspect of the present application, the array substrate further includes a third insulating layer and a third conductive layer stacked in sequence in a direction away from the second conductive layer, and the electrical connection portion and the third reference signal line are located in the third conductive layer.

[0028] According to any of the aforementioned embodiments of the first aspect of the present application, the third reference signal line is extended and formed along the first direction; the array substrate also includes a fourth reference signal line located on the side of the third conductive layer away from the substrate, the fourth reference signal line is extended and formed along the second direction, the third reference signal line and the fourth reference signal line are connected through a fifth via hole, the array substrate also includes a fourth insulating layer and a fourth conductive layer stacked in sequence in a direction away from the third conductive layer, and the fourth reference signal line is located in the fourth conductive layer.

[0029] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a fifth reference signal line located in the second conductive layer, the multiple transistors include a fourth transistor, and the fifth reference signal line is electrically connected to the fourth transistor.

[0030] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a first driving power signal line, the first driving power signal line and the third reference signal line have the same extension direction, and the first driving power signal line is located in the third conductive layer.

[0031] According to any of the aforementioned implementations of the first aspect of the present application, it also includes a first fan-out signal line, the first fan-out signal line and the third reference signal line have the same extension direction, and the first fan-out signal line is located in the third conductive layer.

[0032] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a second driving power signal line, the second driving power signal line has the same extension direction as the fourth reference signal line, and the second driving power signal line is located in the fourth conductive layer, and the second driving power signal line is connected to the first power signal line via a via.

[0033] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a second fan-out signal line, the second fan-out signal line has the same extension direction as the fourth reference signal line, and the second fan-out signal line is located in the fourth conductive layer, and the second fan-out signal line is connected to the first fan-out signal line via a via.

[0034] According to any of the aforementioned implementations of the first aspect of the present application, it further includes a data signal line, the data signal line and the fourth reference signal line have the same extension direction, and the data signal line is located in the fourth conductive layer.

[0035] According to any of the aforementioned embodiments of the first aspect of the present application, the pixel circuit also includes a first transistor, the first transistor is a driving transistor, the eighth transistor is electrically connected to the source or drain of the first transistor, and the eighth transistor is a reset transistor.

[0036] According to any of the aforementioned embodiments of the first aspect of the present application, the pixel circuit further includes a third transistor, which is a threshold compensation transistor, and the third transistor is electrically connected to the gate of the first transistor.

[0037] According to any of the aforementioned embodiments of the first aspect of the present application, the pixel circuit further includes a second transistor, which is a data writing transistor and is used to apply a data signal to the gate of the first transistor.

[0038] According to any of the aforementioned embodiments of the first aspect of the present application, the pixel circuit further includes a fourth transistor, which is a driving reset transistor and is electrically connected to the gate of the first transistor.

[0039] According to any of the aforementioned embodiments of the first aspect of the present application, the pixel circuit also includes a fifth transistor and a sixth transistor, which are light-emitting control transistors, one of the fifth transistors is connected to the source of the first transistor, and the other is connected to the drain of the first transistor.

[0040] An embodiment of the second aspect of the present application further provides a display panel, comprising an array substrate of any of the above-mentioned embodiments of the first aspect.

[0041] In the array substrate provided in the embodiment of the present application, the array substrate includes a substrate and a pixel circuit and a first reference signal line arranged on the substrate. The pixel circuit can be used to drive the light-emitting unit of the display panel to emit light. The pixel circuit includes a plurality of transistors, one of which is a seventh transistor, and the first reference signal line is electrically connected to the seventh transistors of the two pixel circuits through the same first via hole, so that the first reference signal line is electrically connected to the two seventh transistors through the same first via hole, so that the first reference signal line can transmit signals to the two seventh transistors through one first via hole, and the two seventh transistors share one first via hole, which can reduce the number of via holes opened on the array substrate, simplify the preparation of the array substrate, improve the process performance of the array substrate, and thus improve the process performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0043] Figure 1 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0044] Figure 2 is a partial cross-sectional view of a display panel provided in an embodiment of the present application;

[0045] Figure 3 is a schematic diagram of a pixel circuit structure of a display panel provided in an embodiment of the present application;

[0046] Figure 4 is a schematic diagram of a partial layer structure of a display panel provided in an embodiment of the present application;

[0047] Figure 5 is a schematic structural diagram of a first conductive layer of a display panel provided in an embodiment of the present application;

[0048] Figure 6 is a schematic structural diagram of a second conductive layer of a display panel provided in an embodiment of the present application;

[0049] Figure 7 is a schematic structural diagram of a third conductive layer of a display panel provided in an embodiment of the present application;

[0050] Figure 8 is a schematic structural diagram of a fourth conductive layer of a display panel provided in an embodiment of the present application;

[0051] Fig. 9 is a schematic structural diagram of an active layer of a display panel provided in an embodiment of the present application;

[0052] Fig.10 It is a partial structural schematic diagram of a second conductive layer, a third conductive layer and a fourth conductive layer of a display panel provided in an embodiment of the present application.

[0053] Description of reference numerals:

[0054] 10. array substrate; 20. display panel;

[0055] 100, substrate;

[0056] 200, pixel circuit; T, transistor; g, gate; s, source; d, drain; b, semiconductor portion; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor;

[0057] 310, first reference signal line; 320, second reference signal line; 330, third reference signal line; 340, fourth reference signal line; 350, fifth reference signal line; 360, electrical connection portion;

[0058] 410, first via hole; 420, second via hole; 430, third via hole; 440, fourth via hole; 450, fifth via hole;

[0059] 510, a first insulating layer; 520, a second insulating layer; 530, a third insulating layer; 540, a fourth insulating layer;

[0060] M1, first conductive layer; M2, second conductive layer; M3, third conductive layer; M4, fourth conductive layer;

[0061] EM, light-emitting control signal line; VDD1, first power drive signal line; VDD2, second power drive signal line; FIAA1, first fan-out signal line; FIAA2, second fan-out signal line; Data, data signal line; Scan, scan signal line; Cst, capacitor; c1, first plate; c2, second plate;

[0062] L1, reference line; X, first direction; Y, second direction. DETAILED DESCRIPTION

[0063] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0064] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0065] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0066] like Figures 1 to 6As shown, an embodiment of the first aspect of the present application provides an array substrate 10 for a display panel 20, the array substrate 10 comprising: a substrate 100; a pixel circuit 200, arranged on the substrate 100, the pixel circuit 200 comprising a seventh transistor T7; a first reference signal line 310, located on a side of the seventh transistor T7 away from the substrate 100; wherein the array substrate 10 further comprises a first via hole 410, the first reference signal line 310 being electrically connected to the seventh transistors T7 of two adjacent pixel circuits 200 through the same first via hole 410.

[0067] In the array substrate 10 provided in the embodiment of the present application, the array substrate 10 includes a substrate 100 and a pixel circuit 200 and a first reference signal line 310 disposed on the substrate 100. The pixel circuit 200 can be used to drive the light-emitting unit of the display panel 20 to emit light. The pixel circuit 200 includes a plurality of transistors T, one of which is a seventh transistor T7. The first reference signal line 310 is electrically connected to the seventh transistors T7 of two pixel circuits 200 through the same first via hole 410, so that the first reference signal line 310 is electrically connected to the two seventh transistors T7 through the same first via hole 410, so that the first reference signal line 310 can transmit a signal to the two seventh transistors T7 through one first via hole 410, and the two seventh transistors T7 share one first via hole 410, which can reduce the number of via holes opened on the array substrate 10, simplify the preparation of the array substrate 10, improve the process performance of the array substrate 10, and further improve the process performance of the display panel 20.

[0068] Optionally, the circuit structure of the pixel circuit 200 can be any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, an 8T1C circuit, a 9T1C circuit, and a 14T1C circuit. Herein, a "2T1C circuit" refers to a pixel circuit 200 including two thin film transistors (T) and one capacitor (C), and other "7T1C circuits", "7T2C circuits", "9T1C circuits", and so on. Figure 3 As shown, the embodiment of the present application is described by taking the pixel circuit 200 as an 8T1C circuit as an example.

[0069] Optionally, the seventh transistor T7 may be any one of the plurality of transistors T of the pixel circuit 200. For example, the plurality of transistors T of the pixel circuit 200 include a driving transistor, a switching transistor, a light emission control transistor, a reset transistor, a threshold compensation transistor, etc., and the seventh transistor T7 may be at least one of the driving transistor, the switching transistor, the light emission control transistor, the reset transistor, the threshold compensation transistor, etc.

[0070] Optionally, the first reference signal line 310 may be at least one of a plurality of signal lines in the array substrate 10. For example, the array substrate 10 includes a driving power supply voltage signal line, a data signal line Data, a scanning signal line Scan, a reference voltage signal line, a light emission control signal line EM, etc., and the first reference signal line 310 may be at least one of the power supply voltage signal line, the data signal line Data, the scanning signal line Scan, the reference voltage signal line, the light emission control signal line EM, etc.

[0071] Optionally, the pixel circuit 200 includes a plurality of transistors T, one of which is a seventh transistor T7. The transistor T may be a triode, and the transistor T includes a semiconductor portion b and a gate g, and the semiconductor portion b includes a source region, a drain region, and a channel region.

[0072] Optionally, the first reference signal line 310 and the seventh transistor T7 are electrically connected to each other. The first reference signal line 310 may be electrically connected to a source region or a drain region of the semiconductor portion b of the seventh transistor T7.

[0073] In some optional embodiments, such as Figures 2 to 9 As shown, the array substrate 10 includes an active layer, a first insulating layer 510 and a first conductive layer M1 stacked in sequence in a direction away from the substrate 100, and the pixel circuit 200 includes a plurality of transistors T, and the transistor T includes a semiconductor portion b located in the active layer and a gate g located in the first conductive layer M1.

[0074] In these optional embodiments, the semiconductor portion b of the transistor T is located in the active layer, the gate g is located in the first conductive layer M1, and the distance between the first conductive layer M1 and the active layer is relatively short, so that the device performance can be guaranteed.

[0075] Optionally, the array substrate 10 further includes a scan signal line Scan, which may be located in the first conductive layer M1. The scan signal line Scan is usually electrically connected to the gate g of the switch transistor T in the pixel circuit 200, and the scan signal line Scan and the gate g are both located in the first conductive layer M1 in the same layer, so that the scan signal line Scan and the gate g are electrically connected to each other.

[0076] Optionally, the array substrate 10 further includes a light emitting control signal line EM, the light emitting control signal line EM is located in the first conductive layer M1, the plurality of transistors include a light emitting control transistor, and a portion of the light emitting control signal line EM forms a gate of the light emitting control transistor, so that the light emitting control signal line EM can control the switch of the light emitting control transistor.

[0077] Optionally, a plurality of pixel circuits 200 are arranged in an array, the first direction X is a row direction, and the second direction Y is a column direction. The array substrate 10 has pixel regions, the pixel regions are arranged in a one-to-one correspondence with the pixel circuits 200, and each pixel region is provided with a pixel circuit 200. When the array substrate 10 is used for a display panel 20, each pixel region is used to set a sub-pixel, the pixel region and the sub-pixel are arranged in a one-to-one correspondence, and each pixel region is provided with a sub-pixel.

[0078] In some optional embodiments, such as Figures 4 to 9 As shown, at least two pixel circuits 200 adjacent to each other along the first direction X are symmetrically arranged relative to a reference line L1 extending along the second direction Y, and a first reference signal line 310 extends along the first direction X. The first reference signal line 310 is electrically connected to the seventh transistors T7 of two adjacent and mutually symmetrical pixel circuits 200 through the same first via hole 410.

[0079] In these optional embodiments, two adjacent pixel circuits 200 are symmetrically arranged. When the seventh transistor T7 of one of the two symmetrically arranged pixel circuits 200 approaches the first via hole 410 in the first direction X, the seventh transistor T7 of the other pixel circuit 200 will also approach the first via hole 410, thereby reducing the distance between the first via hole 410 and the two corresponding seventh transistors T7, making it easier for the first reference signal line 310 to be electrically connected to the two seventh transistors T7 through the first via hole 410.

[0080] Optionally, among the multiple pixel circuits 200 spaced apart along the first direction X in the same row, two pixel circuits 200 form a group, and the two pixel circuits 200 in any group are symmetrically arranged about the reference line L1, and the seventh transistors T7 of the two pixel circuits 200 in the same group are electrically connected to the first reference signal line 310 through the same first via 410.

[0081] Optionally, in the two pixel circuits 200 located on both sides of the reference line L1, the distance between the seventh transistor T7 and the reference line L1 is smaller than the distance between other transistors T in the pixel circuit 200 and the reference line L1, which can further reduce the distance between two adjacent seventh transistors T7, making it easier for the two seventh transistors T7 to be electrically connected to the first reference signal line 310 through the same first via 410.

[0082] Optionally, the seventh transistor T7 is an anode reset transistor T. The seventh transistor T7 is used to connect the anode of the light emitting unit of the display panel 20 , and the seventh transistor T7 is used to reset the anode to improve the display effect of the display panel 20 .

[0083] Optionally, the first via 410 is arranged centered with respect to the two seventh transistors T7 corresponding thereto in the first direction X. That is, the orthographic projection of the first via 410 on the substrate 100 is arranged centered with respect to the orthographic projection of the semiconductor portions b of the two seventh transistors T7 on the substrate 100 in the first direction X, that is, the distances from the orthographic projection of the first via 410 on the substrate 100 to the orthographic projections of the semiconductor portions b of the two seventh transistors T7 corresponding thereto on the substrate 100 are equal, so that the transmission distance from the first reference signal line 310 to the two seventh transistors T7 connected thereto is close, thereby improving the display uniformity.

[0084] Optionally, the first reference signal line 310 may be directly electrically connected to the seventh transistor T7 through the first via 410 .

[0085] Alternatively, in another optional embodiment, the array substrate 10 further includes an electrical connection portion 360 , and the first reference signal line 310 may be electrically connected to the seventh transistor T7 through the electrical connection portion 360 .

[0086] For example, the semiconductor portion b is arranged on the side of the first reference signal line 310 away from the substrate 100, the array substrate 10 also includes a second via hole 420, the electrical connection portion 360 is electrically connected to the first reference signal line 310 through the second via hole 420, and the electrical connection portion 360 is electrically connected to the seventh transistor T7 of two adjacent pixel circuits 200 through the same first via hole 410, so that the first reference signal line 310 is electrically connected to the seventh transistor T7 of two adjacent pixel circuits 200 through the electrical connection portion 360.

[0087] In these optional embodiments, the first reference signal line 310 is electrically connected to an electrical connection portion 360 located on a side thereof facing away from the substrate 100, and the electrical connection portion 360 is electrically connected to the seventh transistor T7 through a first via 410. The second via 420 is located on a side of the first reference signal line 310 facing away from the substrate 100. The first via 410 and the first reference signal line 310 can be staggered with each other, thereby improving the change in the shape of the first reference signal line 310 caused by the opening of the via, thereby ensuring the stability of the signal transmission of the first reference signal line 310.

[0088] Optional, such as Figures 4 to 10 As shown, the first reference signal line 310 is extended and formed along the first direction X, and the array substrate 10 also includes a second reference signal line 320 located on the side of the first reference signal line 310 away from the substrate 100, and the second reference signal line 320 is extended and formed along the second direction Y. The electrical connection portion 360 and the second reference signal line 320 are connected through a third via hole 430, wherein at least one third via hole 430 and the second via hole 420 are respectively arranged on both sides of the first via hole 410 in the first direction X.

[0089] At least one third via 430 and a second via 420 are disposed on both sides of the first via 410 in the first direction X, which means that the orthographic projection of at least one third via 430 and the orthographic projection of the second via 420 on the substrate 100 are disposed on both sides of the orthographic projection of the first via 410 on the substrate 100 .

[0090] In these optional embodiments, by adding a second reference signal line 320, the second reference signal line 320 is electrically connected to the first reference signal line 310, so that the distribution area of ​​the first reference signal line 310 and the second reference signal line 320 can be increased and the voltage drop can be reduced. At least one third via 430 and a second via 420 are arranged on both sides of the first via 410, so that the positions of the third via 430 and the second via 420 do not interfere with each other, and the layout of the first via 410, the second via 420 and the third via 430 is more reasonable.

[0091] Optionally, please refer to the above, multiple pixel circuits 200 are distributed in an array along a first direction X and a second direction Y, the first direction X is a row direction, and the second direction Y is a column direction; multiple first reference signal lines 310 are arranged side by side along the second direction Y; multiple second reference signal lines 320 are arranged side by side along the first direction X, and the multiple first reference signal lines 310 and the multiple second reference signal lines 320 are electrically connected to form a grid.

[0092] In these optional embodiments, the plurality of first reference signal lines 310 and the plurality of second reference signal lines 320 are interconnected into a grid structure, which can further reduce the voltage drop and improve the display effect.

[0093] Optionally, the same first reference signal line 310 corresponds to a plurality of pixel circuits 200 in a same row, and the same second reference signal line 320 corresponds to a plurality of pixel circuits 200 in four columns.

[0094] In these optional embodiments, the first reference signal lines 310 correspond to the number of rows of the pixel circuits 200, so that the seventh transistors T7 of the plurality of pixel circuits 200 in each row can be electrically connected to the first reference signal line 310, ensuring normal signal transmission. The ratio of the number of second reference signal lines 320 to the number of columns of the pixel circuits 200 is 1:4, and the number of second reference signal lines 320 is small, which can make way for the arrangement of other signal lines.

[0095] Optionally, the number of the third via holes 430 and the number of the second via holes 420 is 1:2, and at least one of the two second via holes 420 and the third via hole 430 are disposed on both sides of the first via hole 410 .

[0096] In these optional embodiments, the ratio of the number of second vias 420 to the number of pixel circuits 200 is 1:2, and the ratio of the number of second reference signal lines 320 to the number of columns of the pixel circuit 200 is 1:4, so the number of third vias 430 and second vias 420 is 1:2, and at least one of the two second vias 420 and the third via 430 are arranged on both sides of the first via 410, that is, as long as the third via 430 exists, the second via 420 and the third via 430 are arranged on both sides of the first via 410 in the first direction X.

[0097] Optionally, the relative position relationship between each second via hole 420 and the corresponding pixel circuit 200 is the same, so as to simplify the distribution pattern of the second via holes 420 and simplify the preparation process of the array substrate 10 .

[0098] Optionally, the second reference signal line 320 and the first reference signal line 310 are used to transmit a second reset voltage signal. The first reference signal line 310 and the second reference line L1 are used to transmit a constant voltage signal. The first reference signal line 310 and the second reference signal line 320 have a larger distribution area, which can improve the voltage drop problem of the second reset voltage signal at different positions and improve the display effect.

[0099] In some optional embodiments, such as Figures 1 to 9 As shown, the array substrate 10 also includes a third reference signal line 330 and a fourth via 440, and the pixel circuit 200 also includes an eighth transistor T8, and the third reference signal line 330 is electrically connected to the eighth transistor T8 through the fourth via 440, wherein, in the same area where the pixel circuit 200 is located, the fourth via 440 is located on the side of the second via 420 away from the first via 410.

[0100] In these optional embodiments, the pixel circuit 200 further includes an eighth transistor T8, the eighth transistor T8 and the third reference signal line 330 are electrically connected through a fourth via hole 440, and the fourth via hole 440 is located on a side of the second via hole 420 away from the first via hole 410, so that the positions of the fourth via hole 440, the second via hole 420 and the first via hole 410 are unlikely to interfere with each other. When at least two pixel circuits 200 are arranged symmetrically, the space between the second via hole 420 and the first via hole 410 is small, and the space on the side of the second via hole 420 away from the first via hole 410 is large.

[0101] Optionally, the area where the pixel circuit 200 is located is the area of ​​a single sub-pixel, and the area where the pixel circuit 200 corresponding to the single sub-pixel is located.

[0102] Optionally, the fourth via holes 440 corresponding to the two pixel circuits 200 are disposed on both sides of the first via hole 410 in the first direction X. For example, in a group of two pixel circuits 200 that are symmetrical to each other, the fourth via holes 440 corresponding to the two pixel circuits 200 are disposed on both sides of the first via hole 410 in the first direction X. This makes the arrangement of the via holes corresponding to the group of pixel circuits 200 that are symmetrical to each other more regular, and facilitates preparation.

[0103] Optionally, at least one fourth via hole 440 is located on a side of the third via hole 430 away from the first via hole 410. For example, when the third via hole 430 is provided on one side of the first via hole 410, the fourth via hole 440 may be located on a side of the third via hole 430 away from the first via hole 410, so that the positions of the fourth via hole 440, the third via hole 430 and the first via hole 410 are unlikely to interfere with each other.

[0104] In some optional embodiments, such as Figures 1 to 10 As shown, the third reference signal line 330 is extended along the first direction X; the array substrate 10 also includes a fourth reference signal line 340, which is extended along the second direction Y. The third reference signal line 330 and the fourth reference signal line 340 are connected through a fifth via hole 450, wherein at least one fifth via hole 450 and the fourth via hole 440 are located on the same side of the first via hole 410 in the first direction X.

[0105] In these optional embodiments, the third reference signal line 330 and the fourth reference signal line 340 are electrically connected to each other through the fifth via 450. By adding the fourth reference signal line 340, the voltage drop can be reduced, thereby improving the display effect of the display panel 20. The fifth via 450 and the fourth via 440 are located on the same side of the first via 410, so that the arrangement of the fourth via 440 and the fifth via 450 is more scientific and reasonable.

[0106] Optionally, a lap portion is connected to the fourth reference signal line 340, the lap portion extends from the fourth reference signal line 340 along the first direction X, and the lap portion is electrically connected to the third reference signal line 330 through the fifth via 450, so that the fifth via 450 is misaligned with the intersection area of ​​the third reference signal line 330 and the fourth reference line L1. On the one hand, the fifth via 450 is not located at the intersection of the third reference signal line 330 and the fourth reference signal line 340. Usually, there are more wirings at the intersection of the third reference signal line 330 and the fourth reference signal line 340. The fifth via 450 is misaligned with the intersection area, so that there is enough space to arrange the fifth via 450.

[0107] Optionally, please refer to the above, the plurality of pixel circuits 200 are arrayed along the first direction X and the second direction Y, the first direction X is the row direction, and the second direction Y is the column direction. The plurality of third reference signal lines 330 are arranged side by side along the second direction Y; the plurality of fourth reference signal lines 340 are arranged side by side along the first direction X, and the plurality of third reference signal lines 330 and the plurality of fourth reference signal lines 340 are electrically connected to form a grid.

[0108] In these optional embodiments, the plurality of third reference signal lines 330 and the plurality of fourth reference signal lines 340 are interconnected into a grid structure, which can further reduce the voltage drop and improve the display effect.

[0109] Optionally, the same third reference signal line 330 corresponds to a plurality of pixel circuits 200 in the same row, and the same fourth reference signal line 340 corresponds to a plurality of pixel circuits 200 in four columns. In these optional embodiments, the third reference signal line 330 corresponds to the number of rows of the pixel circuits 200, so that the eighth transistors T8 of the plurality of pixel circuits 200 in each row can be electrically connected to the third reference signal line 330, ensuring normal transmission of the signal. The ratio of the number of fourth reference signal lines 340 to the number of columns of the pixel circuits 200 is 1:4, and the number of fourth reference signal lines 340 is small, which can make way for the arrangement of other signal lines.

[0110] Optionally, the number of the fifth via holes 450 and the number of the fourth via holes 440 is 1:4.

[0111] In these optional embodiments, the ratio of the number of fourth vias 440 to the number of pixel circuits 200 is 1:1, and the ratio of the number of fourth reference signal lines 340 to the number of columns of pixel circuits 200 is 1:4, so the number of fourth vias 440 and fifth vias 450 is 1:2.

[0112] Optionally, the third reference signal line 330 and the fourth reference signal line 340 are used to transmit a third reset voltage signal. The first reference signal line 310 and the second reference signal line L1 are used to transmit a constant voltage signal. The first reference signal line 310 and the second reference signal line 320 have a larger distribution area, which can improve the voltage drop problem of the second reset voltage signal at different positions and improve the display effect.

[0113] Optionally, as mentioned above, when the array substrate 10 includes the second reference signal lines 320 , the second reference signal lines 320 and the fourth reference signal lines 340 are alternately arranged along the first direction X.

[0114] In these optional embodiments, the second reference signal lines 320 and the fourth reference signal lines 340 are alternately arranged along the first direction X. On the one hand, the second reference signal lines 320 and the fourth reference signal lines 340 can be arranged in the same layer and their positions do not interfere with each other. On the other hand, the number of the second reference signal lines 320 and the fourth reference signal lines 340 are close, so that the voltage drop effects of the signal lines transmitted by the second reference signal lines 320 and the fourth reference signal lines 340 are close, which can improve the uniformity of the display effect.

[0115] Optionally, two pixel circuits 200 arranged side by side along the first direction X are arranged between the adjacent second reference signal line 320 and the fourth reference signal line 340. For example, when the two adjacent pixel circuits 200 are arranged symmetrically, two symmetrically distributed pixel circuits 200 may be arranged between the adjacent second reference signal line 320 and the fourth reference signal line 340.

[0116] In some optional embodiments, such as Figures 1 to 9 As shown, the array substrate 10 further includes an active layer, a first insulating layer 510, a first conductive layer M1, a second insulating layer 520, and a second conductive layer M2 which are sequentially stacked in a direction away from the substrate 100, and the first reference signal line 310 is located in the second conductive layer M2. The distance between the first reference signal line 310 and the pixel circuit 200 in the driving device layer can be reduced, so that the first reference signal line 310 and the seventh transistor T7 are electrically connected to each other.

[0117] Optionally, the array substrate 10 further includes a third insulating layer 530 and a third conductive layer M3 stacked in sequence in a direction away from the second conductive layer M2, and the electrical connection portion 360 and the third reference signal line 330 are located in the third conductive layer M3. In these optional embodiments, the electrical connection portion 360 is located in the third conductive layer M3, which can reduce the distance between the electrical connection portion 360 and the first reference signal line 310, and facilitate the electrical connection between the electrical connection portion 360 and the first reference signal line 310. The electrical connection portion 360 and the third reference signal line 330 are arranged in the same layer, which can simplify the preparation of the array substrate 10.

[0118] Optionally, please refer to the above, when the array substrate 10 includes the fourth reference signal line 340, the array substrate 10 also includes a fourth insulating layer 540 and a fourth conductive layer M4 stacked in sequence in a direction away from the third conductive layer M3, and the fourth reference signal line 340 is located in the fourth conductive layer M4.

[0119] In these optional embodiments, the fourth reference signal line 340 is located in the fourth conductive layer M4, which can reduce the distance between the fourth reference signal line 340 and the third reference signal line 330, thereby facilitating electrical connection between the two.

[0120] Optionally, please refer to the above, when the array substrate 10 includes the second reference signal line 320, the second reference signal line 320 is located in the fourth conductive layer M4.

[0121] In these optional embodiments, the second reference signal line 320 is located in the fourth conductive layer M4 , and the second reference signal line 320 and the fourth reference signal line 340 are arranged in the same layer, which can simplify the preparation of the array substrate 10 .

[0122] Optionally, when the signal lines are distributed in the above-mentioned conductive layers, the first via 410 can be arranged through the first insulating layer 510, the second insulating layer 520 and the third insulating layer 530, so that the electrical connection part 360 located in the third conductive layer M3 can be electrically connected to the semiconductor part b located in the active layer. The second via 420 can be arranged through the second insulating layer 520, so that the electrical connection part 360 located in the third conductive layer M3 and the first reference signal line 310 located in the second conductive layer M2 can be electrically connected to each other. The third via 430 is arranged through the third insulating layer 530 and the fourth insulating layer 540, so that the second reference signal line 320 located in the fourth conductive layer M4 and the first reference signal line 310 located in the second conductive layer M2 can be electrically connected to each other. The fourth via 440 is arranged through the first insulating layer 510, the second insulating layer 520 and the third insulating layer 530, so that the third reference signal line 330 located in the third conductive layer M3 and the semiconductor part b of the eighth transistor T8 located in the active layer can be electrically connected to each other. The fifth via 450 is disposed through the third insulating layer 530 and the fourth insulating layer 540 , so that the fourth reference signal line 340 located in the fourth conductive layer M4 and the third reference signal line 330 located in the second conductive layer M2 can be electrically connected to each other.

[0123] Optional, such as Figures 1 to 9 As shown, the array substrate 10 further includes a fifth reference signal line 350 located in the second conductive layer M2 , the plurality of transistors T include a fourth transistor T4 , and the fifth reference signal line 350 is electrically connected to the fourth transistor T4 .

[0124] In these optional embodiments, the fifth reference signal line 350 is located in the second conductive layer M2, which can reduce the distance between the fifth reference signal line 350 and the semiconductor portion b of the fourth transistor T4, thereby facilitating electrical connection between the two.

[0125] Optionally, the fifth reference signal line 350 may be used to transmit a first reset voltage signal.

[0126] Optionally, the array substrate 10 further includes a first driving power signal line, the first driving power signal line and the third reference signal line 330 extend in the same direction, and the first driving power signal line is located in the third conductive layer M3. This allows the first driving power signal line and the third reference signal line 330 to be arranged side by side and spaced apart along the second direction Y, and can also simplify the preparation process of the array substrate 10.

[0127] Optionally, the array substrate 10 further includes a first fan-out signal line FIAA1, the first fan-out signal line FIAA1 and the third reference signal line 330 extend in the same direction, and the first fan-out signal line FIAA1 is located in the third conductive layer M3. This allows the first fan-out signal line FIAA1 and the third reference signal line 330 to be arranged side by side and spaced apart along the second direction Y, and can also simplify the preparation process of the array substrate 10.

[0128] Optionally, the array substrate 10 further includes a second driving power signal line, the second driving power signal line and the fourth reference signal line 340 extend in the same direction, and the second driving power signal line is located in the fourth conductive layer M4, and the second driving power signal line is connected to the first power signal line via a via. On the one hand, the distance between the second driving power signal line and the first power signal line can be reduced, and on the other hand, the second driving power signal line and the fourth reference signal line 340 are arranged in the same layer, which can simplify the preparation process of the array substrate 10.

[0129] Optionally, the array substrate 10 further includes a second fan-out signal line FIAA2, the second fan-out signal line FIAA2 and the fourth reference signal line 340 extend in the same direction, and the second fan-out signal line FIAA2 is located in the fourth conductive layer M4, and the second fan-out signal line FIAA2 is connected to the first fan-out signal line FIAA1 via a via. On the one hand, the distance between the second fan-out signal line FIAA2 and the first fan-out signal line FIAA1 can be reduced, and on the other hand, the second fan-out signal line FIAA2 and the fourth reference signal line 340 are arranged in the same layer, which can simplify the preparation process of the array substrate 10.

[0130] Optionally, the array substrate 10 further includes a data signal line Data, the data signal line Data and the fourth reference signal line 340 extend in the same direction, and the data signal line Data is located in the fourth conductive layer M4, which can simplify the preparation process of the array substrate 10.

[0131] Furthermore, in the above embodiments, the signal lines arranged in the same layer have the same extension direction, so that the multiple signal lines arranged in the same layer can be arranged side by side and spaced apart, and are unlikely to affect each other.

[0132] Optionally, the array substrate 10 may further include a capacitor device Cst, the capacitor device Cst includes a first electrode plate c1 and a second electrode plate c2, one of the first electrode plate c1 and the second electrode plate c2 is located in the first conductive layer M1, and the other is located in the second conductive layer M2.

[0133] In an optional embodiment, the pixel circuit 200 further includes a first transistor T1 , which is a driving transistor, an eighth transistor T8 is electrically connected to a source s or a drain d of the first transistor T1 , and is a reset transistor.

[0134] In these optional embodiments, the first transistor T1 is a driving transistor, one of the source s and the drain d of the first transistor T1 is used to be electrically connected to a power supply voltage driving signal line (e.g., a first power supply voltage driving signal line), and the other is used to be electrically connected to the anode to drive the anode. The eighth transistor T8 is electrically connected to one of the source s and the drain d of the first transistor T1 to reset one of the source s and the drain d of the first transistor T1.

[0135] Optionally, the first transistor T1 is a P-type transistor, the source s of the first transistor T1 is electrically connected to a power supply voltage drive signal line (eg, a first power supply voltage drive signal line), the eighth transistor T8 is electrically connected to the source s, and the eighth transistor T8 is used to reset the source s of the drive transistor.

[0136] Optionally, the pixel circuit 200 further includes a third transistor T3, which is a threshold compensation transistor and is electrically connected to the gate g of the first transistor T1. The third transistor T3 is used to compensate for the threshold voltage of the first transistor T1.

[0137] Optionally, the pixel circuit 200 further includes a second transistor T2, which is a data writing transistor and is used to apply a data signal to the gate g of the first transistor T1. Optionally, the gate g of the second transistor T2 is connected to the scan signal line Scan, one of the source s and the drain d of the second transistor T2 is connected to the data signal line Data, and the other is connected to the gate g of the first transistor T1.

[0138] Optionally, the pixel circuit 200 further includes a fourth transistor T4, which is a driving reset transistor and is electrically connected to the gate g of the first transistor T1. The fourth transistor T4 is used to reset the gate g of the first transistor T1.

[0139] Optionally, the pixel circuit 200 further includes a fifth transistor T5 and a sixth transistor T6, the fifth transistor T5 and the sixth transistor T6 are light emitting control transistors, one of the fifth transistor T5 and the sixth transistor T6 is connected to the source s of the first transistor T1, and the other is connected to the drain d of the first transistor T1. Optionally, the first transistor T1 is connected between the fifth transistor T5 and the sixth transistor T6.

[0140] The embodiment of the second aspect of the present application further provides a display panel 20, comprising the array substrate 10 of any of the above-mentioned first aspect embodiments. Since the display panel 20 provided by the embodiment of the second aspect of the present application comprises the display array substrate 10 of any of the above-mentioned first aspect embodiments, the display panel 20 provided by the embodiment of the second aspect of the present application has the beneficial effects of the array substrate 10 of any of the above-mentioned first aspect embodiments, which will not be described in detail here.

[0141] The embodiment of the third aspect of the present application further provides a display device, comprising the display panel 20 of any of the above-mentioned second aspect embodiments. Since the display device provided by the embodiment of the third aspect of the present application comprises the display panel 20 of any of the above-mentioned second aspect embodiments, the display device provided by the embodiment of the third aspect of the present application has the beneficial effects of the display panel 20 of any of the above-mentioned second aspect embodiments, which will not be described in detail here.

[0142] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0143] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate for a display panel, characterized in that: The array substrate comprises: substrate; A pixel circuit is disposed on the substrate, wherein the pixel circuit includes a seventh transistor; A first reference signal line, located at a side of the seventh transistor away from the substrate; Wherein, the array substrate further includes a first via hole, and the first reference signal line is electrically connected to the seventh transistors of two adjacent pixel circuits through the same first via hole.

2. The array substrate according to claim 1, characterized in that: The array substrate comprises an active layer, a first insulating layer and a first conductive layer which are sequentially stacked in a direction away from the substrate, the pixel circuit comprises a plurality of transistors, the seventh transistor is one of the plurality of transistors, and the transistor comprises a semiconductor portion located in the active layer and a gate located in the first conductive layer; Preferably, the array substrate further comprises: a light emitting control signal line located in the first conductive layer; The plurality of transistors include a light emission control transistor, and a portion of the light emission control signal line forms a gate of the light emission control transistor.

3. The array substrate according to claim 1, characterized in that: At least two pixel circuits adjacent to each other along the first direction are symmetrically arranged relative to a reference line extending along the second direction, The first reference signal line extends along a first direction, and the first reference signal line is electrically connected to the seventh transistors of two adjacent and mutually symmetrical pixel circuits through the same first via hole; Preferably, the seventh transistor is an anode reset transistor; Preferably, the first via is arranged centrally in the first direction with respect to the two seventh transistors corresponding thereto.

4. The array substrate according to claim 1 or 3, characterized in that: Also includes: an electrical connection portion, arranged on a side of the first reference signal line away from the substrate, the array substrate further comprising a second via hole, the electrical connection portion being electrically connected to the first reference signal line through the second via hole, the electrical connection portion being electrically connected to the seventh transistors of two adjacent pixel circuits through the same first via hole, so that the first reference signal line is electrically connected to the seventh transistors of two adjacent pixel circuits through the electrical connection portion; Preferably, the first reference signal line is extended along a first direction; The array substrate further includes a second reference signal line located on a side of the first reference signal line away from the substrate, the second reference signal line is extended along a second direction, the electrical connection portion and the second reference signal line are connected through a third via hole, Wherein, at least one of the third via holes and the second via hole is disposed on both sides of the first via hole in the first direction; Preferably, the plurality of pixel circuits are arranged in an array, the first direction is a row direction, the second direction is a column direction, a plurality of the first reference signal lines are arranged side by side along the second direction, a plurality of the second reference signal lines are arranged side by side along the first direction, and a plurality of the first reference signal lines are electrically connected to a plurality of the second reference signal lines in a grid shape; Preferably, the same first reference signal line corresponds to a plurality of pixel circuits in a same row, and the same second reference signal line corresponds to a plurality of pixel circuits in four columns; Preferably, the second reference signal line and the first reference signal line are used to transmit a second reset voltage signal.

5. The array substrate according to claim 4, characterized in that: The array substrate further includes a third reference signal line and a fourth via hole. The pixel circuit further includes an eighth transistor, and the third reference signal line is electrically connected to the eighth transistor through the fourth via hole. Wherein, in the same area where the pixel circuit is located, the fourth via hole is located on a side of the second via hole away from the first via hole; Preferably, the fourth via holes corresponding to the two pixel circuits are respectively arranged on two sides of the first via hole in the first direction; Preferably, at least one of the fourth via holes is located on a side of the third via hole away from the first via hole.

6. The array substrate according to claim 5, characterized in that: The third reference signal line is extended along the first direction; The array substrate further includes a fourth reference signal line, the fourth reference signal line is extended along the second direction, the third reference signal line and the fourth reference signal line are connected through a fifth via hole, Wherein, at least one of the fifth via hole and the fourth via hole is located on the same side of the first via hole in the first direction; Preferably, the plurality of pixel circuits are distributed in an array along a first direction and a second direction, the first direction is a row direction, and the second direction is a column direction; The plurality of third reference signal lines are arranged side by side along the second direction, the plurality of fourth reference signal lines are arranged side by side along the first direction, and the plurality of third reference signal lines are electrically connected to the plurality of fourth reference signal lines in a grid shape; Preferably, the same third reference signal line corresponds to a plurality of pixel circuits in a same row, and the same fourth reference signal line corresponds to a plurality of pixel circuits in four columns; Preferably, the third reference signal line and the fourth reference signal line are used to transmit a third reset voltage signal.

7. The array substrate according to claim 6, characterized in that: The first reference signal line is formed by extending along a first direction, the array substrate further comprises a second reference signal line located on a side of the first reference signal line away from the substrate, and the second reference signal line is formed by extending along a second direction. Wherein, the second reference signal lines and the fourth reference signal lines are arranged alternately along the first direction; Preferably, two pixel circuits arranged side by side along the first direction are arranged between the adjacent second reference signal line and the fourth reference signal line.

8. The array substrate according to claim 5, characterized in that: The array substrate further comprises an active layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer which are sequentially stacked in a direction away from the substrate, and the first reference signal line is located in the second conductive layer; Preferably, the array substrate further comprises a third insulating layer and a third conductive layer which are sequentially stacked in a direction away from the second conductive layer, and the electrical connection portion and the third reference signal line are located in the third conductive layer; Preferably, the third reference signal line is extended and formed along the first direction; the array substrate further comprises a fourth reference signal line located on a side of the third conductive layer away from the substrate, the fourth reference signal line is extended and formed along the second direction, the third reference signal line and the fourth reference signal line are connected through a fifth via hole, the array substrate further comprises a fourth insulating layer and a fourth conductive layer sequentially stacked in a direction away from the third conductive layer, and the fourth reference signal line is located in the fourth conductive layer; Preferably, it further comprises a fifth reference signal line, which is located in the second conductive layer, the plurality of transistors comprises a fourth transistor, and the fifth reference signal line is electrically connected to the fourth transistor; Preferably, it further comprises a first driving power signal line, wherein the first driving power signal line and the third reference signal line extend in the same direction, and the first driving power signal line is located in the third conductive layer; Preferably, it further comprises a first fan-out signal line, wherein the first fan-out signal line and the third reference signal line have the same extension direction, and the first fan-out signal line is located in the third conductive layer; Preferably, it further includes a second driving power signal line, wherein the second driving power signal line and the fourth reference signal line extend in the same direction, and the second driving power signal line is located in the fourth conductive layer, and the second driving power signal line is connected to the first driving power signal line via a via hole; Preferably, it further includes a second fan-out signal line, wherein the second fan-out signal line and the fourth reference signal line have the same extension direction, and the second fan-out signal line is located in the fourth conductive layer, and the second fan-out signal line is connected to the first fan-out signal line via a via; Preferably, the device further comprises a data signal line, wherein the extension direction of the data signal line is the same as that of the fourth reference signal line, and the data signal line is located in the fourth conductive layer.

9. The array substrate according to claim 5, characterized in that: The pixel circuit further includes a first transistor, the first transistor is a driving transistor, the eighth transistor is electrically connected to a source or a drain of the first transistor, and the eighth transistor is a reset transistor; Preferably, the pixel circuit further includes a third transistor, the third transistor is a threshold compensation transistor, and the third transistor is electrically connected to the gate of the first transistor; Preferably, the pixel circuit further includes a second transistor, which is a data writing transistor and is used to apply a data signal to the gate of the first transistor; Preferably, the pixel circuit further includes a fourth transistor, which is a driving reset transistor and is electrically connected to the gate of the first transistor; Preferably, the pixel circuit further includes a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are light emitting control transistors, and one of the fifth transistors is connected to the source of the first transistor, and the other is connected to the drain of the first transistor.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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