Composite tube triggering SCR electrostatic protection device applied to power rail circuit

Abstract

The invention discloses a composite tube trigger SCR electrostatic protection device applied to a power supply rail circuit, which is characterized in that three devices, namely an NMOSFET, an NPN type transistor and an SCR, are integrated into a new device through structure change, device embedding and metal wire interconnection, a drain electrode of an NMOSFET T1 and a drain electrode of an NMOSFET T2 are the same electrode, and a substrate of the NMOSFET is a base electrode of the NPN transistor at the same time. The NMOSFET and the NPN are utilized to form the composite tube, so that the high switching speed, the low on-resistance and the good thermal stability are achieved. The SCR is rapidly conducted through a composite tube composed of an NMOSFET and an NPN, and the SCR is used as a main bleeder current path. The novel device structure is called CTTSCR for short, when an ESD signal comes, a composite tube composed of an NMOSFET and an NPN is rapidly started, early-stage current is injected into an SCR path, the trigger voltage of the SCR is reduced, the starting time of the SCR is shortened, and the SCR can serve as a main bleeder current path to be rapidly started. Compared with a traditional NMOSFET (N-channel metal oxide semiconductor field effect transistor), the CTTSCR has the advantages of higher starting speed and better robustness.

Description

Technical Field

[0001] The invention belongs to the technical field of electrostatic discharge protection of power rail circuits, and relates to a composite tube triggered SCR electrostatic protection device applied to power rail circuits. Background Art

[0002] In modern electronic devices, as circuit complexity and integration continue to increase, the stability and reliability of power rail circuits have become key considerations in electronic system design. Especially in high-frequency, high-integration circuits, any tiny disturbance may have a significant impact on circuit performance and even cause circuit damage. Among them, the electrostatic discharge (ESD) problem is one of the important factors affecting circuit performance and long-term reliability.

[0003] Electrostatic discharge may come from the external environment or from the accumulation of charge in the internal circuit. In the power rail circuit, if ESD is not effectively protected, the accumulation of electrostatic charge may cause high-voltage discharge inside the circuit, thereby damaging the circuit components and affecting the normal operation of the equipment.

[0004] At present, electrostatic protection between power rail circuits mainly relies on N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) as a protection device. This device is connected to the electrostatic signal detection circuit through its gate, the drain is connected to a high potential, and the source is connected to a low potential, so that it triggers conduction when an electrostatic signal is detected, and the electrostatic charge is discharged. However, there are some problems with NMOSFET as an electrostatic protection device. First, its current discharge capacity per unit area is relatively weak, and it is difficult to meet the high requirements for electrostatic protection in high-frequency and high-integration circuits. Secondly, since a large amount of current is concentrated in the inversion layer, the heat dissipation difficulty increases, which may further affect the reliability and service life of the device.

[0005] In order to overcome the shortcomings of NMOSFET in electrostatic protection, Silicon Controlled Rectifier (SCR) devices have gradually attracted attention due to their unique current positive feedback mechanism. Once the SCR device is turned on, its unit area discharge current is much higher than that of NMOSFET, thus having a stronger electrostatic protection capability. However, the SCR device itself also has the disadvantages of high trigger voltage and slow conduction speed. These disadvantages limit the application scope of SCR devices in the field of electrostatic protection, and also prompt researchers to further explore and optimize the performance of SCR devices.

[0006] Therefore, how to reduce the trigger voltage and increase the conduction speed while maintaining the high discharge current capability of the SCR device has become a hot issue in the current research of electrostatic protection devices. The present invention aims to provide an improved electrostatic protection device to solve the problems existing in the prior art and improve the electrostatic protection performance of the power rail circuit. Summary of the invention

[0007] The purpose of the present invention is to solve the problem that the discharge current of the traditional electrostatic protection device NMOSFET between power rail circuits in the prior art is mainly concentrated in the inversion layer of the NMOSFET, and a very large area is required to achieve the electrostatic protection level required by the circuit, and to provide a composite tube triggered SCR electrostatic protection device applied to the power rail circuit.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions: A composite tube triggered SCR electrostatic protection device applied to a power rail circuit comprises: a P substrate; a deep N well is arranged on the P substrate; N well 1, P well 1, N well 2, P well 2, and N well 3 are arranged in sequence on the upper surface of the deep N well; P+ injection area 1, groove 1, N+ injection area 1, groove 2, P+ injection area 2, groove 3, N+ injection area 2, groove 4, P+ injection area 3, groove 5, N+ injection area 3, oxide layer 1, N+ injection area 4, groove 6, N+ injection area 5, groove 7, N+ injection area 6, oxide layer 2, N+ injection area 7, groove 8, P+ injection area 4, groove 9, N+ injection area 8, groove 10, P+ injection area 5, groove 11, N+ injection area 9, groove 12, and P+ injection area 6 are arranged in sequence on the P substrate, the deep N well, the N well, and the upper surface of the P well; Among them, the lower surface of P+ injection area 1 is connected to P substrate; the lower surface of the groove is connected to N well 1 and P substrate at the same time; the lower surfaces of N+ injection area 1, groove 2, and P+ injection area 2 are connected to N well 1; the lower surface of groove 3 is connected to N well 1 and P well 1 at the same time; the lower surface of N+ injection area 2, groove 4, P+ injection area 3, groove 5, N+ injection area 3, oxide layer 1, and N+ injection area 4 are connected to P well 1; the upper surface of P well 1, the right side of N+ injection area 3, and the left side of N+ injection area 4 are provided with oxide layer 1; the lower surface of groove 6 is connected to P well 1 and N well 2 at the same time, and the lower surface of N+ injection area 5 is connected to N well 2; the lower surface of groove 7 is connected to N well 2 and P well 2 at the same time; the lower surface of N+ injection area 6, oxide layer 2, N+ injection area 7, groove 8, P+ injection area 4, groove 9, and N+ injection area 8 It is connected to P well two; oxide layer two is arranged on the upper surface of P well two, the right side of N+ injection area six and the left side of N+ injection area seven; the lower surface of groove ten is connected to P well two and N well three at the same time; the lower surface of P+ injection area five, groove eleven and N+ injection area nine is connected to N well three; the lower surface of groove twelve is connected to N well three and P substrate at the same time; the lower surface of P+ injection area six is ​​connected to P substrate; oxide layer one and oxide layer two are respectively connected to ESD signal detection circuit; P+ injection area three and N+ injection area three are short-circuited, and P+ injection area four and N+ injection area seven are short-circuited; P+ injection area one, N+ injection area two, N+ injection area eight and P+ injection area six are connected to cathode, and N+ injection area one, P+ injection area two, N+ injection area four, N+ injection area five, N+ injection area six, P+ injection area five and N+ injection area nine are connected to anode.

[0009] The ESD signal detection circuit is used to generate a bias voltage, which is applied to the upper surfaces of the first oxide layer and the second oxide layer respectively as the gate voltage of the NMOSFET.

[0010] The N+ implantation region 3 is used as a source, the oxide layer 1 is used as a gate, the N+ implantation region 4 is used as a drain and the P well 1 is used as a substrate to form NMOS1.

[0011] The N+ implantation region 6 is used as a drain, the oxide layer 2 is used as a gate, the N+ implantation region 7 is used as a source, and the P well 2 is used as a substrate to form NMOS2.

[0012] The N+ implantation region 2 is used as an emitter, the P well 1 is used as a base, and the N+ implantation region 4 is used as a collector to form a bipolar transistor NPN1.

[0013] The N+ implantation region eight serves as an emitter, the P well two serves as a base, and the N+ implantation region six serves as a collector to form a bipolar transistor NPN2.

[0014] The upper surfaces of the N-well 1, P-well 1, N-well 2, P-well 2 and N-well 3 are flush with the upper surface of the P substrate.

[0015] When a forward ESD event occurs, the P+ injection region 2 serves as the emitter, the N-well 1 as the base and the P-well 1 as the collector to form a bipolar transistor PNP1; the N+ injection region 2 serves as the emitter, the P-well 1 as the base and the N-well 1 as the collector to form a bipolar transistor NPN3; the bipolar transistor NPN3 and the bipolar transistor PNP1 together constitute the SCR1 structure; the P+ injection region 5 serves as the emitter, the N-well 3 as the base and the P-well 2 as the collector to form a bipolar transistor PNP2; the N+ injection region 8 serves as the emitter, the P-well 2 as the base and the N-well 3 as the collector to form a bipolar transistor NPN4; the bipolar transistor NPN4 and the bipolar transistor PNP2 together constitute the SCR2 structure.

[0016] When a negative ESD event occurs, the P+ injection area one, P+ injection area six, P substrate, deep N well, N well two and N+ injection area five constitute a diode PN1 structure; the P+ injection area one, P substrate, N well one and N+ injection area one constitute a diode PN2 structure; the P+ injection area six, P substrate, N well three and N+ injection area nine constitute a diode PN3 structure.

[0017] A chip, characterized in that it uses a composite tube triggered SCR electrostatic protection device applied to a power rail circuit as described in any of the preceding items.

[0018] Compared with the prior art, the present invention has the following beneficial effects: The composite tube trigger SCR electrostatic protection device applied to the power rail circuit of the present invention combines NMOSFET and NPN transistor to form a composite tube structure, and uses this as a trigger mechanism to quickly turn on the SCR, which can serve as the main discharge current path, significantly improving the current discharge capacity under ESD electrostatic discharge events. Not only does it ensure efficient current handling capacity, it also effectively reduces the required chip area and maximizes space utilization.

[0019] Reduced turn-on time: CTTSCR devices achieve a higher turn-on speed by optimizing their internal structure. When encountering an ESD shock, the device can respond quickly and open the discharge channel, effectively shortening the reaction time of the protection circuit, thereby better protecting the integrated circuit from damage.

[0020] Reduce on-resistance: The design of the composite tube structure effectively reduces the on-resistance of the overall device, which not only reduces energy loss, but also improves the efficiency of current discharge, ensuring the stability and reliability of the circuit under normal operation and ESD events.

[0021] Enhanced thermal stability: Through structural innovation, CTTSCR enhances the thermal stability of the device, enabling it to effectively manage heat when subjected to large current discharge, avoiding performance degradation or damage caused by overheating, and extending the service life of the device.

[0022] Saving chip area: Compared with traditional power rail circuits that require large-area support to achieve current discharge capability, CTTSCR achieves the goal of achieving high current discharge capability in a smaller area through process technologies such as structural changes, device embedding and metal wire interconnection, which is of great significance for improving the integration of integrated circuits and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 It is a schematic diagram of the structure of the composite tube triggered SCR electrostatic protection device applied to the power rail circuit of the present invention; Figure 2 It is a circuit structure diagram of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0028] The present invention is further described in detail below in conjunction with the accompanying drawings: See also Figure 1The present invention integrates NMOSFET, NPN transistor and SCR into a new device through structural change, device embedding and metal wire interconnection, wherein the drain N+ injection region 4 20 of NMOSFET1 and the drain N+ injection region 6 24 of NMOSFET2 are the same electrode, and P well 1 4 and P well 2 6 are both the substrate of NMOSFET1 (NMOSFET2) transistor and the base of NPN1 (NPN2) transistor. The P+ injection region three 16 and the N+ injection region three 18 are connected by metal wires, the P+ injection region four 28 and the N+ injection region seven 26 are connected by metal wires, the N+ injection region three 18 and the N+ injection region seven 26 are also the source of NMOSFET1 and NMOSFET2, the N+ injection region one 10, the P+ injection region two 12, the N+ injection region four 20, the N+ injection region five 22, the N+ injection region six 24, the P+ injection region five 32 and the N+ injection region nine 34 are all connected together to connect the anode, the P+ injection region one 8, the N+ injection region two 14, the N+ injection region eight 30 and the P+ injection region six 36 are all connected together to connect the cathode, the oxide layer one 19 and the oxide layer two 25 are the gates of NMOSFET1 and NMOSFET2 connected to the ESD signal detection circuit. Wherein, both NMOSFET1 and NMOSFET2 are enhancement type NMOSFETs.

[0029] The composite tube triggered SCR electrostatic protection device applied to the power rail circuit of the present invention comprises: a P substrate 1; a deep N well 2 is arranged on the P substrate 1; an N well 1 3, a P well 1 4, an N well 2 5, a P well 2 6, and an N well 3 7 are arranged in sequence on the upper surface of the deep N well 2; the upper surfaces of the N well 1 3, the P well 1 4, the N well 2 5, the P well 2 6, and the N well 3 7 are flush with the upper surface of the P substrate 1. A P+ implantation region 1 8, a trench 1 9, an N+ implantation region 1 10, a trench 2 11, a P+ implantation region 2 12, a trench 3 13, an N+ implantation region 2 14, a trench 4 15, a P+ implantation region 3 16, a trench 5 17, an N+ implantation region 3 18, an oxide layer 1 19, an N+ implantation region 4 20, a trench 6 21, an N+ implantation region 5 22, a trench 7 23, an N+ implantation region 6 24, an oxide layer 25, an N+ implantation region 7 26, a trench 8 27, a P+ implantation region 4 28, a trench 9 29, an N+ implantation region 8 30, a trench 10 31, a P+ implantation region 5 32, a trench 11 33, an N+ implantation region 9 34, a trench 12 35 and a P+ implantation region 6 36 are sequentially arranged on the P substrate 1, the deep N well 2, the N well and the P well upper surface; Among them, the lower surface of the P+ injection area 8 is connected to the P substrate 1; the lower surface of the groove 9 is connected to the N well 3 and the P substrate 1 at the same time; the lower surface of the N+ injection area 10, the groove 2 11, and the P+ injection area 2 12 are connected to the N well 3; the lower surface of the groove 3 13 is connected to the N well 3 and the P well 4 at the same time; the lower surface of the N+ injection area 2 14, the groove 4 15, the P+ injection area 3 16, the groove 5 17, the N+ injection area 3 18, the oxide layer 19, and the N+ injection area 4 20 are connected to the P well 4 The upper surface of the P well 1 4, the right side of the N + injection area 3 18, and the left side of the N + injection area 4 20 are provided with an oxide layer 19; the lower surface of the groove 6 21 is connected to the P well 1 4 and the N well 2 5 at the same time, and the lower surface of the N + injection area 5 22 is connected to the N well 2 5; the lower surface of the groove 7 23 is connected to the N well 2 5 and the P well 2 6 at the same time; the N + injection area 6 24, the oxide layer 25, the N + injection area 7 26, the groove 8 27, the P + injection area 4 28, the groove 9 29, and the lower surface of the N + injection area 8 30 The surface is connected to the P well 2 6; the upper surface of the P well 2 6, the right side of the N + injection area 6 24, and the left side of the N + injection area 7 26 are provided with an oxide layer 25; the lower surface of the groove 10 31 is connected to the P well 2 6 and the N well 3 7 at the same time; the lower surface of the P + injection area 5 32, the groove 11 33, and the N + injection area 9 34 are connected to the N well 3 7; the lower surface of the groove 12 35 is connected to the N well 3 7 and the P substrate 1 at the same time; the lower surface of the P + injection area 6 36 is connected to the P substrate 1; the oxide layer 19 and the oxide layer 25 are connected to the P well 2 6 and the N well 3 7 at the same time ... groove 12 35 is connected to the N well 3 7 and the P substrate 1 at the same time; the lower surface of the groove 12 35 is connected to the N well 3 7 and Layer two 25 are respectively connected to the ESD signal detection circuit; P+ injection area three 16 and N+ injection area three 18 are short-circuited, and P+ injection area four 28 and N+ injection area seven 26 are short-circuited; P+ injection area one 8, N+ injection area two 14, N+ injection area eight 30 and P+ injection area six 36 are connected to the cathode, and N+ injection area one 10, P+ injection area two 12, N+ injection area four 20, N+ injection area five 22, N+ injection area six 24, P+ injection area five 32 and N+ injection area nine 34 are connected to the anode.

[0030] The ESD signal detection circuit is used to generate a bias voltage, which is applied to the upper surfaces of the oxide layer 19 and the oxide layer 25 respectively. The upper surfaces of the oxide layer 19 and the oxide layer 25 also include polysilicon or metal as the gate voltage of the NMOSFET1 transistor and the NMOSFET2 transistor.

[0031] The N+ implantation region 3 18 is used as the source, the oxide layer 19 is used as the gate, the N+ implantation region 4 20 is used as the drain and the P well 1 4 is used as the substrate to form the NMOSFET1 transistor. The N+ implantation region 6 24 is used as the drain, the oxide layer 25 is used as the gate, the N+ implantation region 7 26 is used as the source and the P well 2 6 is used as the substrate to form the NMOSFET2 transistor.

[0032] The N+ implantation region 2 14 as the emitter, the P well 1 4 as the base and the N+ implantation region 4 20 as the collector form a bipolar transistor NPN1. The N+ implantation region 8 30 as the emitter, the P well 2 6 as the base and the N+ implantation region 6 24 as the collector form a bipolar transistor NPN2.

[0033] When a forward ESD event occurs, the P+ injection region 2 12 serves as an emitter, the N-well 1 3 serves as a base and the P-well 1 4 serves as a collector to form a bipolar transistor PNP1; the N+ injection region 2 14 serves as an emitter, the P-well 1 4 serves as a base and the N-well 1 3 serves as a collector to form a bipolar transistor NPN3; the bipolar transistor NPN3 and the bipolar transistor PNP1 together constitute the SCR1 structure; the P+ injection region 5 32 serves as an emitter, the N-well 3 7 serves as a base and the P-well 2 6 serves as a collector to form a bipolar transistor PNP2; the N+ injection region 8 30 serves as an emitter, the P-well 2 6 serves as a base and the N-well 3 7 serves as a collector to form a bipolar transistor NPN4; the bipolar transistor NPN4 and the bipolar transistor PNP2 together constitute the SCR2 structure.

[0034] When a negative ESD event occurs, the P+ injection region 18, P+ injection region 636, P substrate 1, deep N well 2, N well 25 and N+ injection region 522 constitute a diode PN1 structure; the P+ injection region 18, P substrate 1, N well 13 and N+ injection region 10 constitute a diode PN2 structure; the P+ injection region 636, P substrate 1, N well 37 and N+ injection region 934 constitute a diode PN3 structure.

[0035] The present invention provides an embodiment of a chip, which uses the composite tube trigger SCR electrostatic protection device applied to the power rail circuit as described in the previous item.

[0036] The ESD protection device CTTSCR (Composite Transistor Triggered SCR) in the present invention is divided into a triggering area and a discharge area after being fully turned on.

[0037] First, the trigger circuit is turned on. When an ESD event occurs, the gate 19 of NMOSFET1 and the gate 25 of NMOSFET2 form a high potential through the ESD signal detection circuit. The channels under the gates 19 and 25 of NMOSFET1 and NMOSFET2 generate a large number of electrons with a high concentration, which will form an inversion layer at the contact surface between P-well 14 and oxide layer 19. Similarly, a relatively thick inversion layer will be formed at the contact surface between P-well 26 and oxide layer 25. At the same time, the drain N+ injection region 20 of NMOSFET1 and the drain N+ injection region 24 of NMOSFET2 are connected to a high potential, and a current is formed between the N+ injection region 4 20 and the N+ injection region 3 18 (a current is formed between the N+ injection region 6 24 and the N+ injection region 7 26 of NMOSFET2). Current), the current of N+ injection area three 18 flows to P+ injection area three 16 through the metal wire (the current of N+ injection area seven 26 flows to P+ injection area four 28 through the metal wire), when the electrostatic current passes through P well one 4, and the voltage drop on the P well resistor is greater than 0.7V (the voltage drop of the P well resistor in P well two 6 is greater than 0.7V), the PN junction between P well one 4 and N+ injection area two 14 (the PN junction between P well two 6 and N+ injection area eight 30) is turned on, and then the N+ injection area two 14 (acting as the emitter), P well one 4 (acting as the base) and N+ injection area four 20 (acting as the collector) are turned on to form a bipolar transistor NPN1 (the N+ injection area eight 30 acts as the emitter, the P well two 6 acts as the base and the N+ injection area six 24 acts as the collector to form a bipolar transistor NPN2 that is turned on).

[0038] Secondly, the conduction of the main ESD current discharge area. When the bipolar transistors NPN1 and NPN2 are turned on, since the N+ injection area 10 and the P+ injection area 2 12 (N+ injection area 9 34 and P+ injection area 5 32) are connected to a high potential, the flowing current causes the well resistance voltage drop in the N-well 13 and the N-well 37 to be greater than 0.7V, making the PN junction (P+ injection area 2 12 / N-well 13, P+ injection area 5 32 / N-well 37) turned on, so that the P+ injection area 2 12 (acting as the emitter), the N-well 13 (acting as the base) and the P-well 14 (acting as the collector) together constitute the bipolar transistor PNP1 to be turned on; the N+ injection area 2 14 (acting as the emitter), the P-well 14 (acting as the base) and the N-well 1 3 (acting as the collector) together constitutes the bipolar transistor NPN3 to be turned on; the bipolar transistor NPN3 and the bipolar transistor PNP1 together constitute the SCR1 structure to be turned on (the P+ injection region five 32 acts as the emitter, the N well three 7 acts as the base and the P well two 6 acts as the collector to together constitute the bipolar transistor PNP2 to be turned on; the N+ injection region eight 30 acts as the emitter, the P well two 6 acts as the base and the N well three 7 acts as the collector to together constitute the bipolar transistor NPN4 to be turned on; the bipolar transistor NPN4 and the bipolar transistor PNP2 together constitute the SCR2 structure to be turned on), thereby forming the SCR1 (SCR2) positive feedback to discharge the ESD current, and then SCR1 (SCR2) plays the leading role in current discharge.

[0039] When negative ESD discharge occurs, the P+ injection area 18 (P+ injection area 636), P substrate 1, deep N well 2, N well 25 and N+ injection area 522 together constitute a diode PN1 that is turned on; the P+ injection area 18, P substrate 1, N well 13 and N+ injection area 10 together constitute a diode PN2 that is turned on; the P+ injection area 636, P substrate 1, N well 37 and N+ injection area 934 together constitute a diode PN3 that is turned on. When the resistance voltage drop in the P substrate 1 is greater than 0.7V, the PN junction diodes (PN1, PN2 and PN3) are turned on to play a leading role in discharging the ESD current.

[0040] The present invention utilizes the advantages of the composite tube and SCR, and integrates multiple originally discrete devices into a single new device through structural changes, device embedding and metal wire interconnection. The functional area in the new device structure can be divided into a trigger area and a discharge current area.

[0041] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A composite tube triggered SCR electrostatic protection device applied to a power rail circuit, characterized in that: include: P substrate (1); a deep N well (2) is arranged on the P substrate (1); N well 1 (3), P well 1 (4), N well 2 (5), P well 2 (6), and N well 3 (7) are sequentially arranged on the upper surface of the deep N well (2); A P+ implantation region 1 (8), a trench 1 (9), an N+ implantation region 1 (10), a trench 2 (11), a P+ implantation region 2 (12), a trench 3 (13), an N+ implantation region 2 (14), a trench 4 (15), a P+ implantation region 3 (16), a trench 5 (17), an N+ implantation region 3 (18), an oxide layer 1 (19), an N+ implantation region 4 (20), a trench 5 (21), a P+ implantation region 2 (12), a trench 6 (23), an N+ implantation region 2 (14), a trench 7 (25), a P+ implantation region 3 (16), a trench 8 (27), an N+ implantation region 3 (18), an oxide layer 1 (19), an N+ implantation region 4 (20), a trench 9 (21), a P+ implantation region 2 (12), a trench 10 (23), an N+ implantation region 2 (14), a trench 11 (25), a P+ implantation region 3 (16), a trench 12 (27), an N+ implantation region 3 (18), an oxide layer 1 (19), an N+ implantation region 4 (20), a trench 13 Groove six (21), N+ implantation region five (22), trench seven (23), N+ implantation region six (24), oxide layer two (25), N+ implantation region seven (26), trench eight (27), P+ implantation region four (28), trench nine (29), N+ implantation region eight (30), trench ten (31), P+ implantation region five (32), trench eleven (33), N+ implantation region nine (34), trench twelve (35) and P+ implantation region six (36); The lower surface of the P+ injection region 1 (8) is connected to the P substrate (1); the lower surface of the groove 1 (9) is connected to the N well 1 (3) and the P substrate (1); the lower surface of the N+ injection region 1 (10), the groove 2 (11), and the P+ injection region 2 (12) are connected to the N well 1 (3); the lower surface of the groove 3 (13) is connected to the N well 1 (3) and the P well 1 (4); the lower surface of the N+ injection region 2 (14), the groove 4 (15), the P+ injection region 3 (16), the groove 5 (17), the N+ injection region 3 (18), the oxide layer 1 (19), and the N+ injection region 4 (20) are connected to the P well 1 (4); the upper surface of the P well 1 (4), the right side of the N+ injection region 3 (18), and the left side of the N+ injection region 4 (20) are provided with the oxide layer 1 (19); the lower surface of the groove 6 (21) is connected to the P well 1 (4), N well two (5) are connected at the same time, the lower surface of N+ injection area five (22) is connected to N well two (5); the lower surface of groove seven (23) is connected to N well two (5) and P well two (6) at the same time; N+ injection area six (24), oxide layer two (25), N+ injection area seven (26), groove eight (27), P+ injection area four (28), groove nine (29), and the lower surface of N+ injection area eight (30) are connected to P well two (6); the upper surface of P well two (6), the right side of N+ injection area six (24), and the left side of N+ injection area seven (26) are provided with oxide layer two (25); the lower surface of groove ten (31) is connected to P well two (6) and N well three (7) at the same time; the lower surface of P+ injection area five (32), groove eleven (33), and N+ injection area nine (34) are connected to N well three (7); The lower surface of the groove twelve (35) is connected to the N well three (7) and the P substrate (1) at the same time; the lower surface of the P+ injection area six (36) is connected to the P substrate (1); the oxide layer one (19) and the oxide layer two (25) are respectively connected to the ESD signal detection circuit; the P+ injection area three (16) and the N+ injection area three (18) are short-circuited, and the P+ injection area four (28) and the N+ injection area seven (26) are short-circuited; the P+ injection area one (8), the N+ injection area two (14), the N+ injection area eight (30) and the P+ injection area six (36) are connected to the cathode, and the N+ injection area one (10), the P+ injection area two (12), the N+ injection area four (20), the N+ injection area five (22), the N+ injection area six (24), the P+ injection area five (32) and the N+ injection area nine (34) are connected to the anode.

2. A composite tube triggered SCR electrostatic protection device applied to a power rail circuit as claimed in claim 1, characterized in that: The ESD signal detection circuit is used to generate a bias voltage, which is applied to the upper surfaces of the first oxide layer (19) and the second oxide layer (25) respectively as the gate voltage of the NMOSFET.

3. The composite tube triggered SCR electrostatic protection device applied to the power rail circuit according to claim 1, characterized in that: The N+ implantation region three (18) is used as a source, the oxide layer one (19) is used as a gate, the N+ implantation region four (20) is used as a drain and the P well one (4) is used as a substrate to form NMOS1.

4. The composite tube triggered SCR electrostatic protection device applied to the power rail circuit as claimed in claim 1, characterized in that: The N+ implantation region six (24) is used as a drain, the oxide layer two (25) is used as a gate, the N+ implantation region seven (26) is used as a source, and the P well two (6) is used as a substrate, forming NMOS2.

5. The composite tube triggered SCR electrostatic protection device applied to the power rail circuit as claimed in claim 1, characterized in that: The N+ implantation region 2 (14) serves as an emitter, the P well 1 (4) serves as a base, and the N+ implantation region 4 (20) serves as a collector to form a bipolar transistor NPN1.

6. A composite tube triggered SCR electrostatic protection device applied to a power rail circuit as claimed in claim 1, characterized in that: The N+ implantation region eight (30) serves as an emitter, the P well two (6) serves as a base, and the N+ implantation region six (24) serves as a collector to form a bipolar transistor NPN2.

7. A composite tube triggered SCR electrostatic protection device applied to a power rail circuit as claimed in claim 1, characterized in that: The upper surfaces of the N well one (3), the P well one (4), the N well two (5), the P well two (6) and the N well three (7) are flush with the upper surface of the P substrate (1).

8. The composite tube triggered SCR electrostatic protection device applied to the power rail circuit as claimed in claim 1, characterized in that: When a forward ESD event occurs, the P+ injection region 2 (12) serves as an emitter, the N well 1 (3) serves as a base and the P well 1 (4) serves as a collector to form a bipolar transistor PNP1; the N+ injection region 2 (14) serves as an emitter, the P well 1 (4) serves as a base and the N well 1 (3) serves as a collector to form a bipolar transistor NPN3; the bipolar transistor NPN3 and the bipolar transistor PNP1 together constitute an SCR1 structure; the P+ injection region 5 (32) serves as an emitter, the N well 3 (7) serves as a base and the P well 2 (6) serves as a collector to form a bipolar transistor PNP2; the N+ injection region 8 (30) serves as an emitter, the P well 2 (6) serves as a base and the N well 3 (7) serves as a collector to form a bipolar transistor NPN4; the bipolar transistor NPN4 and the bipolar transistor PNP2 together constitute an SCR2 structure.

9. The composite tube triggered SCR electrostatic protection device applied to the power rail circuit as claimed in claim 1, characterized in that: When a negative ESD event occurs, the P+ injection region one (8), the P+ injection region six (36), the P substrate (1), the deep N well (2), the N well two (5) and the N+ injection region five (22) form a diode PN1 structure; the P+ injection region one (8), the P substrate (1), the N well one (3) and the N+ injection region one (10) form a diode PN2 structure; the P+ injection region six (36), the P substrate (1), the N well three (7) and the N+ injection region nine (34) form a diode PN3 structure.

10. A chip, characterized in that: A composite tube-triggered SCR electrostatic protection device applied to a power rail circuit as described in any one of claims 1 to 9 is used.

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