Method for improving limit frequency of logic area circuit of image sensor

Abstract

The invention discloses a method for improving the limit frequency of a logic region circuit of an image sensor, which comprises the following steps of: providing a substrate, forming a logic region and a pixel region on the substrate, and forming a groove in the logic region; depositing a dielectric layer on the substrate; and thinning the dielectric layer on the pixel region to enable the thickness of the dielectric layer on the pixel region to be smaller than that of the dielectric layer on the logic region so as to improve the limit frequency of the logic region circuit.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a method for increasing the limiting frequency of a logic area circuit of a CMOS image sensor. Background Art

[0002] CMOS (Complementary Metal-Oxide-Semiconductor) image sensors have the advantages of simple process, easy integration with other devices, small size, light weight, low power consumption and low cost. Therefore, with the development of technology, CMOS image sensors (CIS) are increasingly replacing CCD (Charge-coupled Device) image sensors in various electronic products. At present, CMOS image sensors have been widely used in static digital cameras, camera phones, digital video cameras, medical cameras (such as gastroscopes), automotive cameras, etc. CMOS image sensors can be divided into FSI (Front Side Illumination) and BSI (Back Side Illumination).

[0003] The image sensor operates in response to image light from an external scene being irradiated on the image sensor. The image sensor includes a pixel array having a portion that absorbs incident light and a photosensitive element (e.g., a photodiode) that generates image charge after absorbing the image light, and the pixel array is composed of a plurality of pixel units arranged in an array. The photosensitive element within the pixel unit changes according to changes in the incident image light, thereby generating different images according to the incident light.

[0004] In the manufacturing process of image sensors, generally, a logic area, a pixel area and a metal interconnection structure are formed on one side of a wafer, and then a carrier wafer is bonded to the front side of the semiconductor substrate, and then the back of the semiconductor substrate is thinned, and then the subsequent process of CIS is formed on the back side of the semiconductor substrate. The logic device may include a gate, a source area and a drain area, and an isolation structure may be formed in the logic area, and the isolation structure is used to isolate the logic device. However, in the existing CIS process, a complex circuit structure design is required, so complex metal routing is required on the BSI surface, but the currently designed metal routing structure has a thinner dielectric layer between the BSI surface and the substrate, so the capacitance is larger, which makes the time constant τ (τ=RC) larger, resulting in a lower limit frequency f (f=1 / (2πRC)). Summary of the invention

[0005] The object of the present invention is to provide a method for increasing the limiting frequency of a logic area circuit of a CMOS image sensor.

[0006] To achieve the above objectives, the method provided by the present invention specifically includes providing a substrate, forming a logic area and a pixel area on the substrate, and forming a groove in the logic area; depositing a dielectric layer on the substrate; thinning the dielectric layer on the pixel area so that the thickness of the dielectric layer on the pixel area is smaller than that of the dielectric layer on the logic area, so as to increase the limiting frequency of the logic area circuit.

[0007] Furthermore, the dielectric layer is a composite structure, including a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the second dielectric layer is an etch stop layer of the first dielectric layer, and the third dielectric layer is an etch stop layer of the second dielectric layer.

[0008] Furthermore, the thinning process is specifically to etch and remove the first dielectric layer and the second dielectric layer on the pixel area in sequence.

[0009] Furthermore, the thinning process is to etch the dielectric layer in the pixel area to a set thickness through a mask to maintain the optical performance of the pixel area.

[0010] Furthermore, after the thinning process, the method further includes preparing a metal wiring structure of the logic area.

[0011] Furthermore, the material of the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0012] Furthermore, the difference in thickness between the dielectric layer on the logic area and the dielectric layer on the pixel area is 10-600 nm.

[0013] Furthermore, the present application also provides an image sensor prepared according to the above method, comprising: a substrate, the substrate comprising a logic area and a pixel area; the thickness of the dielectric layer on the logic area is less than the thickness of the dielectric layer on the pixel area.

[0014] Furthermore, the material of the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the present invention forms a logic area and a pixel area on a substrate, forms a groove in the logic area; deposits a dielectric layer on the substrate; thins the dielectric layer on the pixel area so that the thickness of the dielectric layer on the pixel area is smaller than that of the dielectric layer on the logic area, thereby reducing the time constant τ to increase the limiting frequency of the logic area circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings of the present invention constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and together with the description are used to explain the principle of the present invention.

[0017] Figure 1 It is a schematic diagram of the structure of the logic area and the pixel area in the prior art.

[0018] Figure 2-5 This is a schematic diagram of the structure of the logic area and the pixel area according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following detailed descriptions are all illustrative and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0020] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention.

[0021] The invention provides a method for increasing the limiting frequency of a logic area circuit of a CMOS image sensor.

[0022] The following is an explanation based on some examples.

[0023] like Figure 1 As shown in the figure, it is a schematic diagram of the structure of the pixel area and the logic area of ​​the CMOS image sensor chip in the prior art. It can be seen from the figure that the image sensor is a BSI image sensor (back-illuminated image sensor), which includes a carrier wafer 101, a dielectric and metal interconnection layer 102, and a silicon substrate 103. The back of the silicon substrate 103 is divided into a logic area and a pixel area. A designed BSI metal wiring 104 is provided above the logic area. The BSI metal wiring 104 and the dielectric and metal interconnection layer 102 are connected through TSV105. A dielectric layer 106 is provided above the silicon substrate 103. If the thickness of the dielectric layer 106 is too thick, the light transmittance of the pixel area will be affected. If the thickness of the dielectric layer 106 is too thin, the distance between the BSI wiring in the logic area and the substrate will be too close, so that the RC value of the BSI metal wiring 104 is too large, which in turn leads to a decrease in the limit frequency, affecting the performance of the CMOS image sensor.

[0024] In view of the above problems in the prior art, the present application provides a method for improving the limit frequency of the logic area circuit of a CMOS image sensor, specifically: like Figure 2 As shown, the image sensor in this embodiment is a BSI image sensor (back-illuminated image sensor), which provides a substrate 203, wherein the front side of the substrate 203 is connected to a dielectric and metal interconnection layer 202 and a carrier wafer 201, wherein the back side (light incident side) of the substrate 203 is divided into a logic area and a pixel area, and a groove is formed above the logic area by etching so that the surface of the logic area is lower than the pixel area.

[0025] like Figure 3 As shown, a first dielectric layer 2061, a second dielectric layer 2062, and a third dielectric layer 2063 are sequentially deposited on the surface of the substrate 203, wherein the materials of the first, second, and third dielectric layers are silicon oxide, silicon nitride, and silicon oxide, respectively. In some other embodiments, it can also be a combination of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0026] like Figure 4 As shown, the surface of the substrate 203 is thinned by etching to remove the third dielectric layer 2063, the second dielectric layer 2062 and at least a portion of the first dielectric layer 2061, so that the dielectric layer thickness of the pixel area is smaller than the dielectric layer thickness of the logic area. Specifically, the dielectric layer thickness of the pixel area is 600nm smaller than the dielectric layer thickness of the logic area, and in some embodiments, it can also be 10-600nm, preferably 300nm.

[0027] Specifically, the second dielectric layer 2062 can serve as an etching stop layer for the third dielectric layer, the first dielectric layer 2061 can serve as an etching stop layer for the second dielectric layer 2062 , and the first dielectric layer 2061 can serve as a protective layer for the pixel region substrate to prevent etching from damaging the substrate 203 .

[0028] like Figure 5 As shown, TSV 205 and BSI metal trace 204 are formed on the logic region, so that the BSI metal trace is electrically connected to the dielectric and metal interconnect layer 202 through the TSV.

[0029] In some embodiments, a grid structure (not shown in the figure) is also formed above the dielectric layer 2061 in the pixel region.

[0030] The CMOS image sensor obtained by the above method has a dielectric layer thickness in the logic area that is greater than that in the pixel area, so that the dielectric layer thickness in the logic area is large enough while not affecting the transmittance of the pixel area, thereby increasing the limit frequency of the logic area circuit and improving the performance of the CMOS image sensor.

[0031] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0032] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for increasing the limit frequency of a logic area circuit of an image sensor, characterized in that: include providing a substrate, on which a logic region and a pixel region are formed, forming a trench in the logic region; depositing a dielectric layer on the substrate; The dielectric layer on the pixel area is thinned so that the dielectric layer on the pixel area is thinner than the dielectric layer on the logic area, so as to increase the limit frequency of the circuit in the logic area.

2. The method according to claim 1, characterized in that The dielectric layer is a composite structure, including a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the second dielectric layer is an etch stop layer of the first dielectric layer, and the third dielectric layer is an etch stop layer of the second dielectric layer.

3. The method according to claim 2, characterized in that The thinning process specifically includes etching and removing the first dielectric layer and the second dielectric layer on the pixel area in sequence.

4. The method according to claim 1, characterized in that The thinning process is to etch the dielectric layer in the pixel area to a set thickness through a mask to maintain the optical performance of the pixel area.

5. The method according to claim 1, characterized in that After the thinning process, the method further includes preparing a metal wiring structure of the logic area.

6. The method according to claim 1, characterized in that The material of the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride.

7. The method according to claim 1, characterized in that The difference in thickness between the dielectric layer on the logic area and the dielectric layer on the pixel area is 10-600 nm.

8. An image sensor prepared according to the method according to any one of claims 1 to 7, characterized in that: include: A substrate, the substrate comprising a logic area and a pixel area; The thickness of the dielectric layer on the logic area is smaller than the thickness of the dielectric layer on the pixel area.

9. The image sensor according to claim 8, wherein: The difference in thickness between the dielectric layer in the logic area and the dielectric layer in the pixel area is 10-600 nm.

10. The image sensor according to claim 8, wherein: The material of the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride.

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