Imaging apparatus, distance measuring apparatus, and control method of imaging apparatus

Abstract

An imaging device (100) is provided with: a first semiconductor layer (170); a unit cell including n pixels (201), where n is a natural number, and a charge storage section (FD) for storing charges generated by the n pixels; and a drive circuit (130), each of the n pixels includes a photoelectric conversion unit (211), a first transfer transistor (221) having a first control terminal (221g), and a second transfer transistor (231) having a second control terminal (231), and the drive circuit (130) supplies a voltage corresponding to one operation mode selected from among a plurality of operation modes to the first semiconductor layer (170) or the first control terminal (221g) or the second control terminal (231).

Description

Technical Field

[0001] The present disclosure relates to a camera device, a distance measuring device and a control method of the camera device. Background Art

[0002] Patent document 1 discloses an imaging device having a pixel array structure in which a plurality of pixels formed on a substrate are electrically insulated by an insulating groove. Each pixel includes a photodiode and two transfer transistors. In the imaging device disclosed in patent document 1, a positive voltage is applied to the substrate so that the transfer transistor is turned off at 0V.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0272291 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In the imaging device disclosed in Patent Document 1, when it is desired to take into account both imaging and distance measurement, in order to achieve high saturation during imaging and obtain a high-definition image, it is required to deepen the potential of the photodiode. On the other hand, when measuring distance, it is necessary to read the signal charge from the photodiode at a high speed. In order to read the signal charge at a high speed, it is necessary to set the control voltage of the transfer transistor to a higher level, so the power consumption increases. Thus, for the imaging device disclosed in Patent Document 1, there is a problem that it is not possible to take into account both the acquisition of a high-definition image and the distance measurement with low power consumption.

[0008] Therefore, an object of the present disclosure is to provide an imaging device or the like that can achieve both acquisition of a high-definition image and distance measurement with low power consumption.

[0009] Means used to solve problems

[0010] A camera device according to a technical solution of the present disclosure comprises: a first semiconductor layer; a unit cell arranged in the first semiconductor layer, including n (n is a natural number) pixels, and a charge accumulation section for accumulating charges generated by the n pixels; and a driving circuit, wherein the n pixels respectively include a photoelectric conversion section, a first transfer transistor, and a second transfer transistor, the first transfer transistor having a first control terminal, a first input / output terminal connected to the photoelectric conversion section, and a second input / output terminal connected to the charge accumulation section, the second transfer transistor having a second control terminal, a third input / output terminal connected to the photoelectric conversion section, and a fourth input / output terminal different from the third input / output terminal, and the driving circuit supplies a voltage corresponding to an action mode selected from a plurality of action modes to the first semiconductor layer, the first control terminal, or the second control terminal.

[0011] A distance measuring device according to one technical solution of the present disclosure includes: a light source; the imaging device according to the above-mentioned technical solution; and a calculation circuit for calculating the distance to an object based on a signal output from the imaging device.

[0012] A control method for a camera device according to a technical solution of the present disclosure includes, in an operation mode of exposing at least one of the n pixels to a flashing light of a second wavelength, during the exposure to the flashing light of the second wavelength, repeatedly switching between conduction and non-conduction in such a manner that the first transfer transistor and the second transfer transistor are each turned on at different times; and in an operation mode of exposing at least one of the n pixels to light of a first wavelength, during the exposure to the light of the first wavelength, maintaining the first transfer transistor and the second transfer transistor in a non-conduction state, and turning on only the first transfer transistor at a specified timing.

[0013] In addition, one aspect of the present disclosure can be implemented as a program that causes a computer to execute the above control method. Alternatively, one aspect of the present disclosure can be implemented as a computer-readable non-transitory recording medium storing the program.

[0014] Effects of the Invention

[0015] According to the present disclosure, it is possible to provide an imaging device or the like that can achieve both high-definition image acquisition and low-power distance measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a diagram showing the structure of an endoscope system according to an embodiment.

[0017] Figure 2 It is a diagram showing the structure of an imaging device according to an embodiment.

[0018] Figure 3 It is a diagram showing a circuit configuration of a unit cell according to an embodiment.

[0019] Figure 4 This is a diagram showing an example of control of the operation mode of the imaging device according to the embodiment.

[0020] Figure 5 This is a diagram used to explain the distance measurement method based on the CW-ToF method.

[0021] Figure 6 This is a diagram used to explain the distance measurement method based on the pulse ToF method.

[0022] Fig. 7A This is a timing chart showing a first driving example of the distance measurement mode of the CW-ToF method.

[0023] Figure 7B is Fig. 7A The diagram shows the relationship between the irradiated light and the reflected light and each frame period in the first driving example shown.

[0024] Figure 8 This is a timing chart showing a second driving example of the distance measurement mode of the CW-ToF method.

[0025] Fig.9A This is a timing chart showing a third driving example of the distance measurement mode of the CW-ToF method.

[0026] Fig. 9B This is a timing chart showing a modification of the third driving example of the distance measurement mode of the CW-ToF method.

[0027] Fig. 10A It is a timing chart showing a driving example of the distance measurement mode of the pulse ToF method.

[0028] Fig. 10B is Fig. 10A The illustrated example is a diagram showing the relationship between the irradiated light and the reflected light and each frame period.

[0029] Fig. 10C is Fig. 10A The example shown is a diagram showing an example of control signals supplied to two transfer transistors.

[0030] Fig.11 This is a timing chart showing the first driving example of the RGB mode.

[0031] Fig.12 This is a timing chart showing the second driving example of the RGB mode.

[0032] Fig.13AIt is a diagram showing the potential in the unit cell in the RGB mode.

[0033] Fig. 13B is a diagram showing the potential in the unit cell in the ToF mode.

[0034] Fig.14 It is a schematic plan view showing an example of a pixel according to the embodiment.

[0035] Fig.15A It is a schematic plan view showing another example of a pixel according to the embodiment.

[0036] Fig. 15B It is a schematic plan view showing another example of a pixel according to the embodiment.

[0037] Fig. 15C It is a schematic plan view showing another example of a pixel according to the embodiment.

[0038] Fig.15D It is a schematic plan view showing another example of a pixel according to the embodiment.

[0039] Fig.15E It is a schematic plan view showing another example of a pixel according to the embodiment.

[0040] Fig.15F It is a schematic plan view showing another example of a pixel according to the embodiment.

[0041] Fig.16 It is a diagram showing the structure of a driving circuit according to an embodiment.

[0042] Fig.17 It is a diagram showing the circuit configuration of a pixel control circuit and a substrate voltage supply circuit according to the embodiment.

[0043] Fig.18A 1 is a diagram showing an example of a potential supplied to a control terminal of a transfer transistor in an RGB mode.

[0044] Fig.18B : is a diagram showing an example of a potential supplied to a control terminal of a transfer transistor in the ToF mode.

[0045] Fig.18C FIG. 4 is a diagram showing another example of the potential supplied to the control terminal of the transfer transistor in the ToF mode.

[0046] Fig.19A 1 is a diagram showing an example of potentials supplied to the control terminals of the transfer transistor and the reset transistor in the RGB mode.

[0047] Fig.19B2 is a diagram showing an example of potentials supplied to the control terminals of the transfer transistor and the reset transistor in the ToF mode.

[0048] Fig. 20A 1 is a diagram showing an example of potentials supplied to the control terminals of the transfer transistor and the reset transistor and to the substrate in the RGB mode.

[0049] Fig. 20B 1 is a diagram showing an example of potentials supplied to the control terminals of the transfer transistor and the reset transistor and to the substrate in the ToF mode.

[0050] Fig. 20C 1 is a diagram showing a modification of the potentials supplied to the control terminals of the transfer transistor and the reset transistor and to the substrate in the ToF mode.

[0051] Fig.21 3 is a diagram showing the potential in the unit cell when the voltage of the capacitor is controlled in the ToF mode.

[0052] Fig. 22 It is a plan view of a photoelectric conversion unit according to an embodiment.

[0053] Fig.23A yes Fig. 22 Cross-sectional view of line XXIII-XXIII.

[0054] Fig. 23B is equivalent to Fig. 22 A cross-sectional view of a pixel of the comparative example taken along line XXIII-XXIII.

[0055] Fig.24 It is a cross-sectional view showing the cross-sectional structure of the photoelectric conversion unit when a negative voltage is supplied to the control terminal of the transfer transistor.

[0056] Fig.25 This is a diagram showing the dynamic range of the imaging device corresponding to the area ratio of the hole accumulation region. DETAILED DESCRIPTION

[0057] (Overview of the present disclosure)

[0058] The camera device of the first technical solution related to the present disclosure comprises: a first semiconductor layer; a unit unit, which is arranged in the above-mentioned first semiconductor layer, including n (n is a natural number) pixels and a charge accumulation part for accumulating charges generated by the n pixels; and a driving circuit, wherein the n pixels respectively include a photoelectric conversion part, a first transfer transistor, and a second transfer transistor, the above-mentioned first transfer transistor has a first control terminal, a first input-output terminal connected to the above-mentioned photoelectric conversion part, and a second input-output terminal connected to the above-mentioned charge accumulation part, the above-mentioned second transfer transistor has a second control terminal, a third input-output terminal connected to the above-mentioned photoelectric conversion part, and a fourth input-output terminal different from the above-mentioned third input-output terminal, and the above-mentioned driving circuit supplies a voltage corresponding to an action mode selected from a plurality of action modes to the above-mentioned first semiconductor layer, or the above-mentioned first control terminal or the above-mentioned second control terminal.

[0059] Thus, in the imaging device of the present technical solution, an appropriate voltage can be supplied to the first semiconductor layer, the first control terminal, or the second control terminal according to the operation mode. Therefore, even if the potential of the photoelectric conversion unit is deepened in order to obtain a high-definition image, it is possible to suppress power consumption and perform high-precision distance measurement. Thus, it is possible to achieve both high-definition image acquisition and low-power distance measurement.

[0060] Regarding the camera device of the second technical solution of the present disclosure, in the camera device related to the first technical solution, the above-mentioned multiple action modes include: a first action mode, exposing at least one pixel of the above-mentioned n pixels to light of a first wavelength; and a second action mode, exposing at least one pixel of the above-mentioned n pixels to flashing light of a second wavelength.

[0061] Thus, a high-quality image can be acquired in the first operation mode, and low-power-consumption distance measurement can be performed in the second operation mode.

[0062] Regarding the camera device of the third technical solution of the present disclosure, in the camera device of the first technical solution or the second technical solution, the above-mentioned driving circuit includes: a first voltage supply circuit, which supplies voltage to the above-mentioned first semiconductor layer; and a second voltage supply circuit, which supplies voltage to at least one of the above-mentioned first control terminal and the second control terminal.

[0063] This allows appropriate voltages to be supplied to the first semiconductor layer and at least one of the first control terminal and the second control terminal, respectively. This allows both high-definition image acquisition and low-power distance measurement to be achieved.

[0064] Regarding the camera device of the fourth technical solution of the present disclosure, in the camera device of the second technical solution, the above-mentioned driving circuit includes a first voltage supply circuit that supplies voltage to the above-mentioned first semiconductor layer, the above-mentioned first voltage supply circuit includes a first signal line, a second signal line and a first connecting circuit, the above-mentioned first signal line is set to a first potential, the above-mentioned second signal line is set to a second potential different from the above-mentioned first potential, and the above-mentioned first connecting circuit switches the above-mentioned first signal line and the above-mentioned second signal line according to the above-mentioned action mode and connects the above-mentioned first signal line and the above-mentioned second signal line to the above-mentioned first semiconductor layer.

[0065] Thus, a plurality of voltage levels (potentials) are set for the two signal lines, and the voltage level of the voltage supplied to the first semiconductor layer can be easily changed by switching the connection relationship between the first semiconductor layer and the two signal lines.

[0066] Regarding the camera device of the 5th technical solution of the present disclosure, in the camera device related to the 4th technical solution, the above-mentioned second potential is lower than the above-mentioned first potential, and when the above-mentioned first action mode is selected, the above-mentioned first connection circuit connects the above-mentioned first signal line to the above-mentioned first semiconductor layer, and when the above-mentioned second action mode is selected, the above-mentioned first connection circuit connects the above-mentioned second signal line to the above-mentioned first semiconductor layer.

[0067] Thus, in the second operation mode, by lowering the voltage level of the voltage supplied to the first semiconductor layer, the signal charge can be effectively read out from the photoelectric conversion unit even if the voltage variation (amplitude) of the transfer transistor is small. Thus, the signal charge can be read out at a high speed with good accuracy, and the distance measurement system can be improved.

[0068] Regarding the camera device of the 6th technical solution of the present disclosure, in the camera device related to any one of the 2nd technical solution, the 4th technical solution and the 5th technical solution, the above-mentioned drive circuit includes a second voltage supply circuit that supplies voltage to at least one of the above-mentioned first control terminal and the above-mentioned second control terminal, the above-mentioned second voltage supply circuit includes one or more third signal lines, one or more fourth signal lines and a second connecting circuit, the above-mentioned one or more third signal lines are set to at least one of the third potential and a fourth potential higher than the above-mentioned third potential, the above-mentioned one or more fourth signal lines are set to at least one of the fifth potential and a sixth potential higher than the above-mentioned fifth potential, and the above-mentioned second connecting circuit switches the above-mentioned one or more third signal lines and the above-mentioned one or more fourth signal lines according to the above-mentioned action mode and connects them to at least one of the above-mentioned first control terminal and the above-mentioned second control terminal.

[0069] Thus, a plurality of voltage levels (potentials) are set for a plurality of signal lines, and the connection relationship between the first semiconductor layer and each control terminal and each signal line is switched, thereby making it possible to easily change the voltage level supplied to the first semiconductor layer and each control terminal.

[0070] The imaging device according to a seventh technical solution of the present disclosure is, in the imaging device according to the sixth technical solution, a potential difference between the fourth potential and the third potential and a potential difference between the sixth potential and the fifth potential are different.

[0071] Thus, a plurality of voltage levels (potentials) are set for a plurality of signal lines, and the connection relationship between the first semiconductor layer and each control terminal and each signal line is switched, thereby making it possible to easily change the voltage level supplied to the first semiconductor layer and each control terminal.

[0072] Regarding the camera device of the 8th technical solution of the present disclosure, in the camera device related to the 6th technical solution or the 7th technical solution, the potential difference between the above-mentioned 4th potential and the above-mentioned 3rd potential is larger than the potential difference between the above-mentioned 6th potential and the above-mentioned 5th potential; when the above-mentioned 1st action mode is selected, the above-mentioned 2nd connecting circuit connects the above-mentioned 1 or more 3rd signal lines to at least one of the above-mentioned 1st control terminal and the above-mentioned 2nd control terminal, and when the above-mentioned 2nd action mode is selected, the above-mentioned 2nd connecting circuit connects the above-mentioned 1 or more 4th signal lines to at least one of the above-mentioned 1st control terminal and the above-mentioned 2nd control terminal.

[0073] Thus, in the second operation mode, the fluctuation range (amplitude) of the voltage of the transfer transistor can be reduced, and thus power consumption can be reduced.

[0074] Regarding the camera device of the 9th technical solution of the present disclosure, in the camera device related to the 2nd technical solution, the 4th technical solution or the 5th technical solution, the above-mentioned drive circuit includes a second voltage supply circuit that supplies voltage to at least one of the above-mentioned first control terminal and the above-mentioned second control terminal, the above-mentioned second voltage supply circuit includes a 7th signal line, an 8th signal line, and a 3rd connecting circuit, the above-mentioned 7th signal line is set to a 7th potential, the above-mentioned 8th signal line is set to an 8th potential different from the above-mentioned 7th potential, and the above-mentioned 3rd connecting circuit switches the above-mentioned 7th signal line and the above-mentioned 8th signal line according to the above-mentioned action mode so as to connect them to at least one of the above-mentioned 1st control terminal and the above-mentioned 2nd control terminal.

[0075] Thus, multiple voltage levels (potentials) are set for the two signal lines, and the connection relationship between at least one of the first control terminal and the second control terminal and the two signal lines is switched, so that the voltage level supplied to at least one of the first control terminal and the second control terminal can be simply changed.

[0076] Regarding the camera device of the 10th technical solution of the present disclosure, in the camera device related to the 9th technical solution, the above-mentioned 8th potential is lower than the above-mentioned 7th potential, and when the above-mentioned 1st action mode is selected, the above-mentioned 3rd connecting circuit connects the above-mentioned 7th signal line to at least one of the above-mentioned 1st control terminal and the above-mentioned 2nd control terminal, and when the above-mentioned 2nd action mode is selected, the above-mentioned 3rd connecting circuit connects the above-mentioned 8th signal line to at least one of the above-mentioned 1st control terminal and the above-mentioned 2nd control terminal.

[0077] Thus, in the second operation mode, by lowering the voltage level of the voltage supplied to at least one of the first control terminal and the second control terminal, the signal charge can be effectively read out from the photoelectric conversion unit even if the voltage variation (amplitude) of the transfer transistor is small. Thus, the signal charge can be read out at a high speed with good accuracy, and the ranging system can be improved.

[0078] In the camera device of the 11th technical solution of the present disclosure, in the camera device of any one of the second technical solution and the fourth technical solution to the tenth technical solution, the unit cell includes a capacitor having a first electrode and a second electrode, and a switching element connected in series between the first electrode and the charge accumulation section, and in the second action mode, the switching element maintains the capacitor and the charge accumulation section in a conductive state, and in the first action mode, the switching element makes the capacitor and the charge accumulation section non-conductive.

[0079] Thus, in the second operation mode, a part of the charge accumulated in the photoelectric conversion unit can also be accumulated in the capacitor, so that high saturation can be achieved.

[0080] The imaging device according to the 12th technical solution of the present disclosure is, in the imaging device according to the 11th technical solution, wherein in the second operation mode, the driving circuit makes the potential supplied to the second electrode lower than the potential supplied to the fourth input / output terminal.

[0081] This makes it possible to lower the potential of the charge storage unit and the capacitor, so that the signal charge from the photoelectric conversion unit can be read out at high speed and with high accuracy. Therefore, the distance measurement system can be further improved.

[0082] A distance measuring device according to a thirteenth technical solution of the present disclosure includes: a light source; the imaging device according to any one of the first to eighth technical solutions; and a calculation circuit for calculating a distance to an object based on a signal output from the imaging device.

[0083] Thus, similar to the above-mentioned imaging device, it is possible to achieve both acquisition of a high-definition image and distance measurement with low power consumption.

[0084] A control method for an imaging device according to the 14th technical solution of the present disclosure is as follows: in an operation mode of exposing at least one of the n pixels to a flashing light of a second wavelength, during the exposure to the flashing light of the second wavelength, the conduction and non-conduction states are repeatedly switched in such a manner that the first transfer transistor and the second transfer transistor are each turned on at different times; in an operation mode of exposing at least one of the n pixels to light of a first wavelength, during the exposure to the light of the first wavelength, the first transfer transistor and the second transfer transistor are maintained in a non-conduction state, and only the first transfer transistor is turned on at a specified timing.

[0085] Thus, similar to the above-mentioned imaging device, it is possible to achieve both acquisition of a high-definition image and distance measurement with low power consumption.

[0086] In each of the above-mentioned technical aspects, the unit cell is formed in the first semiconductor layer, but the first semiconductor layer is, for example, a substrate, a well, or an epitaxial layer.

[0087] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0088] In addition, the embodiments described below all represent general or specific examples. The numerical values, shapes, materials, components, configuration positions and connection forms of components, steps, and the order of steps shown in the following embodiments are examples, and their main purpose is not to limit the present disclosure. In addition, among the components of the following embodiments, the components not described in the independent claims are described as arbitrary components.

[0089] In addition, each figure is a schematic diagram and does not necessarily illustrate the figure strictly. Therefore, for example, the scales in each figure are not necessarily the same. In addition, in each figure, the same reference numerals are given to substantially the same structure, and repeated descriptions are omitted or simplified.

[0090] In addition, in this specification, terms such as parallel or perpendicular that indicate the relationship between elements, terms such as rectangle that indicate the shape of an element, and numerical ranges do not express only strict meanings, but mean that substantially equivalent ranges also include differences of, for example, a few percent.

[0091] In addition, in this specification, the terms "above" and "below" do not refer to above (vertically above) and below (vertically below) in absolute spatial recognition, but are terms defined by relative positional relationships based on the stacking order in the stacking structure. In addition, the terms "above" and "below" are applicable not only to the case where two components are arranged at a distance from each other and there is another component between the two components, but also to the case where two components are arranged closely to each other and the two components are in contact.

[0092] In this specification, the term "thickness direction" refers to the thickness direction of the substrate, which is a direction perpendicular to the main surface of the substrate. In addition, the term "plan view" refers to a view viewed from a direction perpendicular to the main surface of the substrate unless otherwise specified.

[0093] In this specification, the visible light band can be regarded as a wavelength range of 380 nm to 780 nm, and the near infrared light band can be regarded as a wavelength range of 780 nm to 2500 nm.

[0094] In addition, in this specification, the "input and output terminals" of a transistor refer to terminals for inputting or outputting current (charge) or voltage, or both. In the case where the transistor is a field effect transistor (FET) such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a TFT (Thin Film Transistor), the source and the drain are input and output terminals, respectively. In the case where the transistor is a bipolar transistor, the emitter and the collector are input and output terminals, respectively. In addition, the gate of the FET and the base of the bipolar transistor are control terminals.

[0095] In addition, in this specification, unless otherwise specified, ordinal numbers such as "first" and "second" do not refer to the number or order of components, but are used to avoid confusion between the same components and to distinguish them.

[0096] (Implementation Method)

[0097] [Endoscopic system]

[0098] First, use Figure 1 An endoscope system according to an embodiment will be described. Figure 1 It is a diagram showing the configuration of an endoscope system 1 according to the present embodiment.

[0099] The endoscope system 1 is an example of a distance measuring device including an imaging device. Figure 1As shown, the endoscope system 1 irradiates light L1 to the object 2 and receives reflected light L2 of the irradiated light L1 reflected by the object 2, thereby being able to measure the distance to the object 2. In addition, the endoscope system 1 can obtain a visible light image of the object 2. The endoscope system 1 related to this embodiment has a plurality of operation modes. The plurality of operation modes include a camera mode for generating a visible light image and a distance measurement mode for generating a distance image.

[0100] like Figure 1 As shown, the endoscope system 1 includes a main body 10 and an insertion portion 20. The endoscope system 1 is used to insert the insertion portion 20 into a body of a human or an animal. That is, the object 2 is a part of the body.

[0101] The main body 10 is the portion of the endoscope system 1 that is not inserted into the body. Figure 1 As shown, the main body 10 includes a light source 11 , a light source driving circuit 12 , an ISP (Image Signal Processor) 13 , an output unit 14 , a system control circuit 15 , and a power supply IC (Integrated Circuit) 16 .

[0102] The light source 11 emits light for irradiating the object 2. Specifically, the light source 11 can emit light of a first wavelength for the camera mode and flickering light of a second wavelength for the distance measurement mode. The first wavelength is, for example, included in the visible light band. The light of the first wavelength is, for example, white light. The second wavelength is a wavelength different from the first wavelength. For example, the second wavelength is included in the near-infrared light band. The flickering light is light whose brightness changes periodically. The period of the flickering light is, for example, greater than 1 MHz and less than 200 MHz, and as an example, is 50 MHz, but is not limited to this.

[0103] The light source 11 includes, for example, an LED (Light Emitting Diode), a semiconductor laser element, or an organic EL (Electroluminescence) element. As an example, the light source 11 includes a blue LED or a blue laser element that emits blue light, and a yellow phosphor that is excited by the blue light and emits yellow light, and emits white light as a mixed light of the blue light and the yellow light as the first wavelength. In addition, the light source 11 includes a near-infrared laser element that emits near-infrared light as a scintillation light of the second wavelength.

[0104] The light source driving circuit 12 is a circuit that drives the light source 11, and specifically controls the timing of lighting up and lighting down the light source 11. The light source driving circuit 12 generates power for lighting up the light source 11 based on the power supplied from the power supply IC 16, for example, and supplies the generated power to the light source 11. The light source driving circuit 12 adjusts the timing of starting and stopping the supply of power to the light source 11, thereby being able to control the timing of lighting up and lighting down the light source 11.

[0105] The light source driving circuit 12 is formed by combining one or more electronic components such as IC, resistor, transistor, diode, capacitor, inductor and transformer, etc. The light source driving circuit 12 may be integrated with other components such as the power supply IC 16 and the system control circuit 15 .

[0106] ISP13 is an example of a computing circuit, and processes the signal output from the imaging device 100, that is, the sensor output data. In the imaging mode, ISP13 generates a visible light image using the sensor output data. In the ranging mode, ISP13 calculates the distance to the object 2 using the sensor output data. ISP13 generates a distance image that indicates the distance to the object 2 for each pixel. The visible light image and the distance image are respectively a still image or a moving image (video).

[0107] The output unit 14 outputs the visible light image and the distance image generated by the ISP 13. For example, the output unit 14 is a communication IF used to communicate with an external device such as a display in a wired or wireless manner. For example, the output unit 14 is an output terminal that can be connected to a communication cable. Alternatively, the output unit 14 may also include an antenna and a wireless processing circuit.

[0108] The system control circuit 15 controls the entire endoscope system 1. Specifically, the system control circuit 15 selects (switches) the operation mode of the endoscope system 1 and outputs control signals to various components of the endoscope system 1 according to the selected operation mode.

[0109] The system control circuit 15 is implemented, for example, by an LSI (Large Scale Integration) which is an integrated circuit. In addition, the integrated circuit is not limited to LSI, and may also be a dedicated circuit or a general-purpose processor. For example, the system control circuit 15 may also be a microcontroller. The microcontroller includes, for example, a non-volatile memory storing a program, a volatile memory as a temporary storage area for executing the program, an input / output port, a processor for executing the program, and the like. In addition, the system control circuit 15 may also be a programmable FPGA (Field Programmable Gate Array) or a reconfigurable processor capable of reconfiguring the connection and setting of the circuit units within the LSI. The functions performed by the system control circuit 15 may be implemented by software or by hardware.

[0110] The power IC 16 is a power circuit that processes electric power supplied from a commercial power source or an external power source such as a power storage device, etc. For example, the power IC 16 includes an AC / DC converter and / or a DC / DC converter.

[0111] Although in Figure 1 Although not shown in the figure, the endoscope system 1 may also include an operation unit for accepting operation input from the user. The operation unit may be a physical operation button or operation switch, or a touch panel, etc. The operation unit may also be a communication IF for accepting operation input via a remote operation terminal such as a remote controller.

[0112] The insertion portion 20 is a flexible portion, and at least the front end portion (the end portion opposite to the main body portion 10) is inserted into the body when the endoscope system 1 is used. The length of the insertion portion 20 is not less than 3 m and not more than 5 m, but is not particularly limited. Figure 1 As shown, the insertion portion 20 includes a light guide member 21 , an objective lens 22 , a condenser lens 23 , and an imaging device 100 .

[0113] The light guide member 21 guides the light emitted from the light source 11 to the front end portion, and emits the light as the light L1 from the front end portion toward the object 2. The light guide member 21 is, for example, an optical fiber, but is not limited thereto.

[0114] The objective lens 22 and the condenser lens 23 are optical systems for allowing the imaging device 100 to receive the reflected light L2 from the object 2. The type and number of lenses are not particularly limited as long as the imaging device 100 can receive the reflected light L2. In addition, optical elements other than lenses may be provided.

[0115] The imaging device 100 outputs an image signal obtained by photoelectrically converting the reflected light L2 from the object 2. Specifically, in the imaging mode, the imaging device 100 performs photoelectric conversion on the light (reflected light L2) reflected by the object 2 in the light of the first wavelength emitted from the light source 11. In the ranging mode, the imaging device 100 performs photoelectric conversion on the light (reflected light L2) reflected by the object 2 in the flashing light of the second wavelength emitted from the light source 11.

[0116] The camera device 100 is connected to the ISP 13 via one or more cables (not shown). The camera device 100 operates based on the sensor control pulse sent from the ISP 13 via the cable. The sensor control pulse is, for example, the main clock MCLK, the vertical synchronization signal VD, etc. In addition, the camera device 100 outputs the image signal as sensor output data to the ISP 13. In this embodiment, the camera device 100 is a so-called CMOS (Complementary Metal-Oxide-Semiconductor) image sensor (CIS). The camera device 100 is, for example, a back-illuminated CIS.

[0117] [Camera device]

[0118] Next, use Figure 2 The specific structure of the imaging device 100 will be described. Figure 2 It is a diagram showing the structure of the imaging device 100 according to the present embodiment.

[0119] like Figure 2 As shown, the imaging device 100 includes a sensor array 110, a drive circuit 130, and a signal output circuit 140. In addition, the imaging device 100 includes a plurality of control lines 150, a plurality of power supply lines (not shown), and a plurality of vertical signal lines 160.

[0120] The sensor array 110 includes a plurality of unit cells 120 arranged two-dimensionally in a matrix. The number of unit cells 120 is, for example, several hundred or several thousand or more in each of the row direction and the column direction, but is not limited thereto. The plurality of unit cells 120 are provided in the first semiconductor layer. The first semiconductor layer is, for example, a substrate. The substrate is, for example, a semiconductor substrate containing a semiconductor such as silicon as a main component. The first semiconductor layer may also be a well region or an epitaxial layer.

[0121] Each of the plurality of unit cells 120 has n pixels. Here, n is a natural number. Each of the n pixels includes a photoelectric conversion unit. The specific structure of the pixel and the unit cell 120 will be described later.

[0122] In addition, Figure 2In FIG. 1 , the area surrounded by the dotted line in the sensor array 110 is the effective pixel area. The effective pixel is a pixel that is recorded and output as an image signal and used in the distance measurement operation. Pixels other than the effective pixels are also called dummy pixels. Figure 2 In addition, the dummy pixels may not be provided, and the pixels of all the unit cells 120 included in the sensor array 110 may be effective pixels.

[0123] The driving circuit 130 is a circuit for controlling each of the plurality of unit cells 120. The driving circuit 130 and each unit cell 120 are electrically connected by a plurality of control lines 150. The driving circuit 130 drives each control line 150 according to one operation mode selected from a plurality of operation modes. Specifically, the driving circuit 130 controls the exposure timing of each pixel included in each unit cell 120, the output timing of the signal, etc. by outputting a control signal to each control line 150. In addition, the driving circuit 130 may also change the value (potential, voltage level) of the power supply voltage supplied to the plurality of power supply lines. The specific structure and operation examples of the driving circuit 130 will be described later.

[0124] The signal output circuit 140 is connected to each unit cell 120 via a plurality of vertical signal lines 160. The signal output circuit 140 outputs a signal read out from each unit cell 120 or each pixel via the plurality of vertical signal lines 160 to the ISP 13 as an image signal.

[0125] [Unit cell]

[0126] Next, use Figure 3 A specific circuit structure of the unit cell 120 will be described. Figure 3 1 is a diagram showing a circuit configuration of a unit cell 120 according to the present embodiment.

[0127] In addition, since the plurality of unit cells 120 provided in the sensor array 110 have the same structure, one of them will be described below as a representative. In addition, in this embodiment, the case where the number n of pixels included in the unit cell 120 is 4 is described as an example.

[0128] like Figure 3 As shown, the unit cell 120 includes four pixels 201, 202, 203, and 204, and a charge storage unit FD for storing charges generated by the four pixels 201, 202, 203, and 204. Furthermore, the unit cell 120 includes a reset transistor 121, a capacitor connection transistor 122, a capacitor 123, a readout transistor 124, and a selection transistor 125.

[0129] In addition, in the unit cell 120, control lines TG1, TG2, TG3, and TG4, PRS1, PRS2, PRS3, and PRS4, as well as RS, GC, and SEL are connected as a plurality of control lines 150. The control lines TG1, TG2, TG3, and TG4, PRS1, PRS2, PRS3, and PRS4, as well as RS, GC, and SEL are connected to the same components of each of the plurality of unit cells 120 arranged in the row direction. For example, the control line TG1 is an example of a first control line, and is connected to the gate of the first transfer transistor 221 of each pixel 201 of each of the plurality of unit cells 120 arranged in the row direction. The control line PRS1 is an example of a second control line, and is connected to the gate of the second transfer transistor 231 of each pixel 201 of each of the plurality of unit cells 120 arranged in the row direction. In addition, for example, the control line RS is connected to the gate of the reset transistor 121 of each of the plurality of unit cells 120 arranged in the row direction.

[0130] In addition, in the unit cell 120, power lines AVDDP and VMIM, and a power line GND (not shown) set to a ground potential are provided as a plurality of power lines. In addition, the ground potential is an example of a reference potential, for example, 0V. The power lines AVDDP, VMIM, and GND are respectively connected to the same components of each of the plurality of unit cells 120 arranged in at least one of the row direction and the column direction. For example, the power line VMIM is connected to one of the electrodes (the second electrode) of the capacitor 123 of each of the plurality of unit cells 120 arranged in a matrix. In addition, at least one of the plurality of power lines may also be a power line for supplying a voltage (substrate voltage) to a substrate on which the plurality of unit cells 120 (a plurality of pixels) are provided.

[0131] The four pixels 201, 202, 203, and 204 correspond to red pixels (R), green pixels (Gr, Gb), and blue pixels (B) required to generate an RGB image (color image) as an example of a visible light image. Specifically, pixels 201 and 204 are green pixels (Gr, Gb), pixel 202 is a red pixel (R), and pixel 203 is a blue pixel (B). RGB is arranged in a so-called Bayer array. In addition, the arrangement of RGB is not particularly limited.

[0132] Furthermore, the four pixels 201, 202, 203 and 204 are sensitive not only to the visible light band but also to the second wavelength (near infrared light band). Thus, the four pixels 201, 202, 203 and 204 can receive the scintillation light of the second wavelength respectively, and a distance image can be generated.

[0133] The pixel 201 includes a photoelectric conversion unit 211, and a first transfer transistor 221 and a second transfer transistor 231 connected to the photoelectric conversion unit 211. In addition, the pixel 201 may also have a filter (not shown) that allows green light (light of the first wavelength) and near-infrared light (light of the second wavelength) in incident light to pass through and suppresses the passage of light other than these.

[0134] The photoelectric conversion unit 211 performs photoelectric conversion on the incident light and generates electric charges in an amount corresponding to the light intensity. The photoelectric conversion unit 211 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 211 has sensitivity to each of green light and near-infrared light.

[0135] The anode of the photoelectric converter 211 (photodiode) is connected to the ground potential. The cathode of the photoelectric converter 211 is connected to the first transfer transistor 221 and the second transfer transistor 231. The connection point between the first transfer transistor 221, the second transfer transistor 231 and the photoelectric converter 211 is shown as a node N1.

[0136] The first transfer transistor 221 is a FET having a gate, a source, and a drain. The gate of the first transfer transistor 221 is an example of a first control terminal and is connected to the control line TG1. One of the source and the drain of the first transfer transistor 221 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 211. The other of the source and the drain of the first transfer transistor 221 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0137] The second transfer transistor 231 is a FET having a gate, a source, and a drain. The gate of the second transfer transistor 231 is an example of a second control terminal and is connected to the control line PRS1. One of the source and the drain of the second transfer transistor 231 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 211. The other of the source and the drain of the second transfer transistor 231 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to the power supply line AVDDP.

[0138] The pixel 202 includes a photoelectric conversion unit 212, and a first transfer transistor 222 and a second transfer transistor 232 connected to the photoelectric conversion unit 212. In addition, the pixel 202 may also have a filter (not shown) that allows red light (light of the first wavelength) and near-infrared light (light of the second wavelength) in incident light to pass through and suppresses the passage of light other than these.

[0139] The photoelectric conversion unit 212 performs photoelectric conversion on the incident light and generates electric charges in an amount corresponding to the light intensity. The photoelectric conversion unit 212 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 212 has sensitivity to each of red light and near-infrared light.

[0140] The anode of the photoelectric converter 212 (photodiode) is connected to the ground potential. The cathode of the photoelectric converter 212 is connected to the first transfer transistor 222 and the second transfer transistor 232. The connection point between the first transfer transistor 222, the second transfer transistor 232 and the photoelectric converter 212 is shown as a node N2.

[0141] The first transfer transistor 222 is a FET having a gate, a source, and a drain. The gate of the first transfer transistor 222 is an example of a first control terminal and is connected to the control line TG2. One of the source and the drain of the first transfer transistor 222 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 212. The other of the source and the drain of the first transfer transistor 222 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0142] The second transfer transistor 232 is a FET having a gate, a source, and a drain. The gate of the second transfer transistor 232 is an example of a second control terminal and is connected to the control line PRS2. One of the source and the drain of the second transfer transistor 232 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 212. The other of the source and the drain of the second transfer transistor 232 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to the power supply line AVDDP.

[0143] The pixel 203 includes a photoelectric conversion unit 213, and a first transfer transistor 223 and a second transfer transistor 233 connected to the photoelectric conversion unit 213. In addition, the pixel 203 may also have a filter (not shown) that allows blue light (light of the first wavelength) and near-infrared light (light of the second wavelength) in the incident light to pass and suppresses the passage of light other than these.

[0144] The photoelectric conversion unit 213 performs photoelectric conversion on the incident light and generates electric charges in an amount corresponding to the light intensity. The photoelectric conversion unit 213 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 213 has sensitivity to each of blue light and near-infrared light.

[0145] The anode of the photoelectric converter 213 (photodiode) is connected to the ground potential. The cathode of the photoelectric converter 213 is connected to the first transfer transistor 223 and the second transfer transistor 233. The connection point between the first transfer transistor 223, the second transfer transistor 233 and the photoelectric converter 213 is shown as a node N3.

[0146] The first transfer transistor 223 is a FET having a gate, a source, and a drain. The gate of the first transfer transistor 223 is an example of a first control terminal and is connected to the control line TG3. One of the source and the drain of the first transfer transistor 223 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 213. The other of the source and the drain of the first transfer transistor 223 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0147] The second transfer transistor 233 is a FET having a gate, a source, and a drain. The gate of the second transfer transistor 233 is an example of a second control terminal and is connected to the control line PRS3. One of the source and the drain of the second transfer transistor 233 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 213. The other of the source and the drain of the second transfer transistor 233 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to the power supply line AVDDP.

[0148] The pixel 204 includes a photoelectric conversion unit 214, and a first transfer transistor 224 and a second transfer transistor 234 connected to the photoelectric conversion unit 214. In addition, the pixel 204 may also have a filter (not shown) that allows green light (light of the first wavelength) and near-infrared light (light of the second wavelength) in incident light to pass through and suppresses the passage of light other than these.

[0149] The photoelectric conversion unit 214 performs photoelectric conversion on the incident light and generates electric charges in an amount corresponding to the light intensity. The photoelectric conversion unit 214 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 214 has sensitivity to each of green light and near-infrared light.

[0150] The anode of the photoelectric converter 214 (photodiode) is connected to the ground potential. The cathode of the photoelectric converter 214 is connected to the first transfer transistor 224 and the second transfer transistor 234. The connection point between the first transfer transistor 224, the second transfer transistor 234 and the photoelectric converter 214 is shown as a node N4.

[0151] The first transfer transistor 224 is a FET having a gate, a source, and a drain. The gate of the first transfer transistor 224 is an example of a first control terminal and is connected to the control line TG4. One of the source and the drain of the first transfer transistor 224 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 214. The other of the source and the drain of the first transfer transistor 224 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0152] The second transfer transistor 234 is a FET having a gate, a source, and a drain. The gate of the second transfer transistor 234 is an example of a second control terminal and is connected to the control line PRS4. One of the source and the drain of the second transfer transistor 234 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 214. The other of the source and the drain of the second transfer transistor 234 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to the power supply line AVDDP.

[0153] The charge storage unit FD is shared by the four pixels 201, 202, 203, and 204. Specifically, the charge storage unit FD can store charges generated by the photoelectric conversion units 211, 212, 213, and 214 of each pixel. The charge storage unit FD is an impurity region provided in a semiconductor substrate, and a plug and wiring connected to the impurity region.

[0154] The reset transistor 121 is provided to reset the potential of the charge accumulation section FD. The reset transistor 121 is an example of a switching element, and is connected in series between the power line AVDDP and the charge accumulation section FD. In the present embodiment, the reset transistor 121 is connected to the charge accumulation section FD via the capacitor connection transistor 122. The reset transistor 121 is a FET having a gate, a source, and a drain. The gate of the reset transistor 121 is connected to the control line RS. One of the source and drain of the reset transistor 121 is connected to the power line AVDDP. The other of the source and drain of the reset transistor 121 is connected to the charge accumulation section FD via the capacitor connection transistor 122. When the reset transistor 121 is turned on (in the present embodiment, the capacitor connection transistor 122 is further turned on), since the charge accumulation section FD is connected to the power line AVDDP, the potential of the charge accumulation section FD is reset.

[0155] The capacitor connection transistor 122 is provided for switching the connection between the capacitor 123 and the charge accumulation section FD. The capacitor connection transistor 122 is an example of a switching element, which is connected in series between the capacitor 123 and the charge accumulation section FD. The capacitor connection transistor 122 is a FET having a gate, a source, and a drain. The gate of the capacitor connection transistor 122 is connected to the control line GC. One of the source and drain of the capacitor connection transistor 122 is connected to one of the electrodes (the first electrode) of the capacitor 123. The other of the source and drain of the capacitor connection transistor 122 is connected to the charge accumulation section FD. In addition, the capacitor connection transistor 122 can also be used to reset the potential of the charge accumulation section FD.

[0156] The capacitor 123 is provided to increase the amount of charge that can be stored in the unit cell 120 and to expand the dynamic range. The capacitor 123 has a first electrode and a second electrode. The first electrode of the capacitor 123 is connected to the charge storage unit FD via the capacitor connection transistor 122. The second electrode of the capacitor 123 is connected to the power line VMIM. When the capacitor connection transistor 122 is turned on, a portion of the charge flowing from each pixel into the charge storage unit FD can be accumulated in the capacitor 123. The capacitor 123 is, for example, a capacitor having a MIM (Metal Insulator Metal) structure provided above a semiconductor substrate, but the specific structure is not particularly limited. For example, parasitic capacitance caused by wiring and electrodes, etc. can also be used as the capacitor 123.

[0157] The read transistor 124 is provided to read out the charge accumulated in the charge accumulation section FD, specifically, to output a signal corresponding to the charge amount to the vertical signal line 160. The read transistor 124 is a FET having a gate, a source, and a drain. The gate of the read transistor 124 is connected to the charge accumulation section FD. One of the source and the drain of the read transistor 124 is connected to the power supply line AVDDP. The other of the source and the drain of the read transistor 124 is connected to the vertical signal line 160 via the selection transistor 125.

[0158] The selection transistor 125 is provided to control the timing of reading out the charge accumulated in the charge accumulation section FD by the readout transistor 124. The selection transistor 125 is a FET having a gate, a source, and a drain. The gate of the selection transistor 125 is connected to the control line SEL. One of the source and the drain of the selection transistor 125 is connected to the readout transistor 124. The other of the source and the drain of the selection transistor 125 is connected to the vertical signal line 160. When the selection transistor 125 is turned on, the charge is read out by the readout transistor 124.

[0159] Each transistor included in the unit cell 120 includes an impurity region provided in a semiconductor substrate as a source and a drain, and includes an electrode provided above the semiconductor substrate via a gate insulating film as a gate. Two transistors connected in series may also share an impurity region. For example, the other of the source and drain of the reset transistor 121 and one of the source and drain of the capacitor connection transistor 122 may share one impurity region.

[0160] In addition, the structure of the above-mentioned unit cell 120 is only an example and can be appropriately changed. For example, the number n of pixels included in the unit cell 120 can be 1, 2, or 5 or more. In addition, for example, the selection transistor 125 can also be connected between the readout transistor 124 and the power line AVDDP. In addition, for example, the capacitor connection transistor 122 and the capacitor 123 can also be not provided. In addition, for example, each transistor included in the unit cell 120 is an n-channel transistor, but it can also be a p-channel transistor. Alternatively, each transistor can also be a bipolar transistor.

[0161] [action]

[0162] Next, the operation of the endoscope system 1 according to the present embodiment will be described.

[0163] As described above, the endoscope system 1 has a plurality of operation modes including an imaging mode and a distance measurement mode. The imaging device 100 included in the endoscope system 1 performs different operations according to the operation mode.

[0164] The imaging mode is an example of the first operation mode of the imaging device 100, and is an operation mode in which at least one of the n pixels 201 to 204 included in the unit cell 120 is exposed to light of the first wavelength. In the present embodiment, the imaging mode is an RGB mode for generating an RGB image (color image), so all of the four pixels 201 to 204 included in the unit cell 120 are exposed. In the RGB mode, the light source 11 emits white light as light of the first wavelength, and each pixel of the imaging device 100 receives its reflected light. In addition, the RGB image is an image in which each pixel of the image corresponds to the unit cell 120 of the imaging device 100 and includes respective RGB values ​​(brightness values).

[0165] The ranging mode is an example of the second operation mode of the camera device 100, and is an operation mode in which at least one of the n pixels 201 to 204 included in the unit cell 120 is exposed to a scintillation light of a second wavelength. In the present embodiment, the ranging mode is a ToF mode using a ToF (Time of Flight) method. In the ToF mode, the distance to the object 2 is calculated based on the time (light flight time) for the light emitted from the light source 11 to return to each pixel via the object 2, and a distance image is generated. Specifically, in the ToF mode, the light source 11 emits scintillation light in the near-infrared light band as scintillation light of the second wavelength, so that at least one of the multiple pixels of the camera device 100 receives its reflected light. In addition, the distance image is an image in which each pixel represents the distance to the object 2.

[0166] Figure 4 FIG. 1 is a diagram showing an example of switching of the operation mode of the imaging device 100 according to the present embodiment. Figure 4As shown, the RGB mode and the ToF mode are switched alternately and executed continuously. Thus, an RGB image and a distance image can be obtained by one measurement (one insertion of the insertion unit 20 into the body). It is possible to prevent the insertion unit 20 from contacting the body based on the distance image, while visual confirmation of the body can be performed simultaneously and in parallel based on the RGB image. In addition, the switching between the RGB mode and the ToF mode can also be switched manually based on the user's operation input, etc.

[0167] The details will be described later, but in the control method of the camera device 100 of the present embodiment, in the ToF mode, during the exposure period to the flash light of the second wavelength (reflected light L2), the first transfer transistor and the second transfer transistor are repeatedly switched between conduction and non-conduction in such a way that the first transfer transistor and the second transfer transistor are not in the conduction state at the same time. In addition, in the RGB mode, during the exposure period to the light of the first wavelength (reflected light L2), the first transfer transistor and the second transfer transistor are maintained in the non-conduction state, and only the first transfer transistor is turned on at a predetermined timing (within the pulse period). In this way, both high-precision distance measurement and high-definition RGB image acquisition can be achieved.

[0168] [ToF mode]

[0169] Next, a specific example of the ToF mode will be described.

[0170] The ToF mode is performed by irradiating the object 2 with scintillation light, receiving the reflected light (scintillation light) reflected by the object 2, and processing the electrical signal obtained by photoelectric conversion. In the ToF mode, there are CW (Continuous-Wave)-ToF method using continuous wave (light) and pulse ToF method using pulse light.

[0171] Figure 5 This is a diagram used to illustrate the distance measurement method based on the CW-ToF method. Figure 5 As shown, the intensity of the irradiation light irradiated to the object 2 changes continuously at a predetermined cycle. The irradiation light is a continuous wave with a constant cycle and amplitude. The cycle of intensity change is expressed as 1 / fmod using the modulation frequency fmod.

[0172] The reflected light has a phase delay φ compared to the irradiated light according to the distance to the object 2. In the CW-ToF method, light is received in each exposure interval obtained by dividing the cycle of the irradiated light into four parts, and the phase delay φ is calculated based on formula (1) using the intensities C0, C1, C2 and C3 of each exposure interval.

[0173] [Formula 1]

[0174] (1)

[0175] Assuming the speed of light is c, the distance Z to the object 2 is expressed by equation (2) using the phase delay φ.

[0176] [Formula 2]

[0177] (2)

[0178] In addition, although the reflected light includes a background light component (noise component), the background light component is canceled out because the difference in intensity is calculated in each of the denominator and the numerator on the right side of the equation (1).

[0179] In the CW-ToF method, the accuracy of distance measurement can be improved by increasing the modulation frequency fmod. On the other hand, if the modulation frequency fmod is increased, the range of distance measurement (distance measurement range) becomes smaller. This is because the maximum value Z of the distance Z that can be measured is max When φ=2π(=360°) in equation (2), it is expressed by c / (2fmod). To reduce the distance measurement range, the distance measurement can be performed using a plurality of different modulation frequencies and the distance measurement results can be combined, thereby expanding the distance measurement range.

[0180] Figure 6 This is a diagram used to illustrate the distance measurement method based on the pulse ToF method. Figure 6 As shown, pulse light having a pulse width (period) Tp is repeatedly irradiated onto the object 2 at predetermined time intervals as irradiation light.

[0181] The reflected light is delayed by a certain time ΔT compared to the pulse light according to the distance to the object 2. In the pulse ToF method, the pulse light is received in at least two exposure intervals set to relatively different times. Figure 6 In the example shown, the same interval as the pulse light is set as the first exposure interval, the interval starting at the same time as the pulse light stops is set as the second exposure interval, and the interval in which the reflected light cannot be received is set as the third exposure interval. The third exposure interval is set to detect the background light component BG. When the background light component BG is sufficiently small, the third exposure interval may not be set.

[0182] The distance Z to the object 2 is expressed by the following equation (3) based on the delay time ΔT.

[0183] [Formula 3]

[0184] (3)

[0185] A0 and A1 are the intensities of the reflected light received in the first exposure interval and the second exposure interval, respectively. Specifically, A0 is obtained by subtracting the signal intensity (background light component BG) obtained in the third exposure interval from the signal intensity obtained in the first exposure interval. A1 is obtained by subtracting the signal intensity (background light component BG) obtained in the third exposure interval from the signal intensity obtained in the second exposure interval.

[0186] In the pulse ToF method, the accuracy of distance measurement can be improved by shortening the pulse width Tp. On the other hand, if the pulse width Tp is lengthened, the range of distance measurement (distance measurement range) becomes smaller. This is because the maximum value Z of the distance Z that can be measured is max When A0=0 in equation (3), it is expressed by (c×Tp) / 2. In order to reduce the distance measurement range, the distance measurement can be performed by a plurality of exposures and the distance measurement results can be combined to expand the distance measurement range.

[0187] [CW-ToF method]

[0188] Hereinafter, a specific operation of the imaging device 100 in the distance measurement mode of the CW-ToF method will be described.

[0189] In addition, in this embodiment, the reset transistor 121, the capacitor connection transistor 122, the selection transistor 125, the first transfer transistors 221, 222, 223 and 224, and the second transfer transistors 231, 232, 233 and 234 included in the unit cell 120 are all in a conductive state (connected) when the voltage level (potential) supplied to the gate is a high level (High, high level), and are in a non-conductive state (cut off) when the voltage level (potential) supplied to the gate is a low level (Low, low level).

[0190] <First driving example>

[0191] First, use Fig. 7A and Figure 7B A first driving example of the imaging device 100 in the CW-ToF method will be described. In the first driving example, all of the four pixels 201 to 204 included in the unit cell 120 are used for distance measurement.

[0192] Fig. 7A This is a timing chart showing a first driving example of the distance measurement mode of the CW-ToF method. Figure 7B is Fig. 7A The diagram shows the relationship between the irradiated light and the reflected light and each frame period in the first driving example shown.

[0193] exist Fig. 7A, RS represents the time variation of the voltage level (potential) of the control line RS connected to the gate of the reset transistor 121. GC represents the time variation of the voltage level (potential) of the control line GC connected to the gate of the capacitor connection transistor 122. VMIM represents the time variation of the voltage level (potential) of the power supply line VMIM connected to the second electrode of the capacitor 123.

[0194] PRSn (n=1 to 4) respectively represents the time change of the voltage level (potential) of the control lines PRS1, PRS2, PRS3 and PRS4 connected to the gates of the second transfer transistors 231, 232, 233 and 234. TG1, TG2, TG3 and TG4 respectively represent the time change of the voltage level (potential) of the control lines TG1, TG2, TG3 and TG4 connected to the gates of the first transfer transistors 221, 222, 223 and 224. In addition, in this specification, TG1 to TG4 may be expressed as TGn (n=1 to 4).

[0195] Frame 1, frame 2, frame 3, and frame 4 are frame periods of the same length. A frame period corresponds to a unit period of processing performed by the imaging device 100 (endoscopic system 1). Frame 1, frame 2, frame 3, and frame 4 each include an exposure period and a readout period.

[0196] The exposure period is a period during which each pixel included in the unit cell 120 receives reflected light. The readout period is a period during which the charge accumulated in the charge accumulation unit FD (and the capacitor 123) is read out to the vertical signal line 160. The readout process is the same as the readout process performed by a general CMOS image sensor, so the description is omitted. In addition, by making the control line RS a high level during the readout period, the potential of the charge accumulation unit FD is reset. As a result, the mixing of signals between frames is suppressed, and the ranging accuracy can be improved.

[0197] exist Fig. 7A The four squares arranged in two rows and two columns shown in the bottom section correspond to the four pixels 201, 202, 203, and 204 included in the unit cell 120. C0, C1, C2, and C3 shown in the squares represent the types of signal strengths obtained by each pixel in each frame, specifically, corresponding to Figure 5 C0, C1, C2 and C3 shown.

[0198] During the exposure period, the voltage levels of the control lines TG1 to TG4 and the control lines PRS1 to PRS4 are repeatedly high and low, that is, the first transfer transistors 221 to 224 and the second transfer transistors 231 to 234 are alternately turned on and off.

[0199] Here, the voltage levels of the control lines TG1 to TG4 change in phase. That is, the first transfer transistors 221 to 224 are turned on at the same timing and turned off at the same timing. Similarly, the voltage levels of the control lines PRS1 to PRS4 change in phase. The second transfer transistors 231 to 234 are turned on at the same timing and turned off at the same timing.

[0200] Furthermore, if one pixel is considered, the high level and the low level of the control line PRSn and the control line TGn are mutually exclusive. In other words, the voltage level of the control line PRSn and the voltage level of the control line TGn are in a 180° phase-inverted relationship.

[0201] That is, in one pixel, the on and off of the first transfer transistor and the on and off of the second transfer transistor are mutually exclusive. For example, while the first transfer transistor 221 is on, the second transfer transistor 231 is off, and while the first transfer transistor 221 is off, the second transfer transistor 231 is on.

[0202] In each frame and each pixel, when the second transfer transistors 231 to 234 are turned off (the control line PRSn is switched from a high level to a low level), the charge generated by the photoelectric conversion units 211 to 214 can be accumulated (the charge accumulation period starts). The charge generated by the photoelectric conversion units 211 to 214 is accumulated in the charge accumulation unit FD (and the capacitor 123) via the first transfer transistors 221 to 224. When the first transfer transistors 221 to 224 are turned off (the control line TGn is switched from a high level to a low level), the accumulation of the charge generated by the photoelectric conversion units 211 to 214 ends (the charge accumulation period ends). When the first transfer transistors 221 to 224 are turned off, the second transfer transistors 231 to 234 are turned on, so the potentials of the photoelectric conversion units 211 to 214 and the nodes N1 to N4 can be reset. In this embodiment, the charge accumulation period of each pixel is substantially the same as the on-period of the first transfer transistor (or the off-period of the second transfer transistor).

[0203] exist Fig. 7A In the example shown, each charge accumulation period of frame 1 to frame 4 corresponds to Figure 5 The first to fourth exposure intervals are shown. Here, the length of the charge accumulation period is 1 / 2 of the period of the irradiated light (equivalent to 180°), and is set so that the phase changes by 90° in the order of frame 1 to frame 4. Therefore, there is no repetition of the charge accumulation period in frame 1 and frame 3, and there is no repetition of the charge accumulation period in frame 2 and frame 4.

[0204] like Figure 7BAs shown, during each charge accumulation period (a period during which the signal level becomes high) of frame 1 to frame 4, signal intensities C0 to C3 can be obtained respectively corresponding to the intensity of the reflected light. During each frame, since the charge accumulation period is repeatedly set during the exposure period, even if the signal intensity obtained during each charge accumulation period is weak, a sufficient signal intensity can be obtained during the exposure period. In addition, the deviation of each charge accumulation period can be suppressed. As a result, the SN ratio can be improved.

[0205] In the first driving example, all four pixels 201 to 204 are used for detecting reflected light. Signal charges obtained from the four pixels 201 to 204 can be accumulated in the charge accumulation unit FD. Therefore, variations between pixels can be suppressed, and the SN ratio can be further improved.

[0206] Thus, in the first driving example, the four pixels 201 to 204 included in the unit cell 120 are exposed to the reflected light L2 at different timings during each frame period. During the frame period, the timings of the start and end of the exposure of the four pixels 201 to 204 are the same. Signal intensities C0 to C3 can be obtained in the exposure period in frames 1 to 4 in sequence. The signal intensities C0 to C3 are read out from the plurality of unit cells 120, respectively, and output from the imaging device 100 as sensor output data to the ISP 13. The ISP 13 can use the signal intensities C0 to C3 of each unit cell 120 to calculate the distance to the object 2 for each unit cell 120 according to the above-mentioned equations (1) and (2), and can generate a distance image.

[0207] In addition, Fig. 7A In the example shown, the voltage level of the control line GC is maintained at a high level. That is, the capacitor connection transistor 122 is always in an on state, and the charge accumulation unit FD is connected to the capacitor 123. Therefore, charge accumulation can also be performed in the capacitor 123. Therefore, the amount of charge that can be accumulated can be increased, so the dynamic range can be increased.

[0208] <Second driving example>

[0209] Next, use Figure 8 A second driving example of the imaging device 100 in the CW-ToF method will be described. In the second driving example, only two of the four pixels 201 to 204 included in the unit cell 120 are used for distance measurement.

[0210] Figure 8 : is a timing chart showing a second driving example of the distance measurement mode of the CW-ToF method. Figure 8 RS, GC, VMIM, PRS1 to PRS4, TG1 to TG4 respectively indicate the contents of Fig. 7AThe following description will focus on the differences from the first driving example, and description of the common points will be omitted.

[0211] In this driving example, pixels 201 and 204 are used for distance measurement, and pixels 202 and 203 are not used. Specifically, during each frame period, the voltage levels of control lines PRS2 and PRS3 are maintained at a high level, and the voltage levels of control lines TG2 and TG3 are maintained at a low level, so that the charges generated by pixels 202 and 203 are not accumulated in the charge accumulation unit FD. The temporal changes in the voltage levels of control lines PRS1 and PRS4, and control lines TG1 and TG4 are similar to those of the control lines PRS1 and PRS4. Fig. 7A Therefore, in each of frames 1 to 4, signal charges generated by the photoelectric conversion section 211 of the pixel 201 and the photoelectric conversion section 214 of the pixel 204 are accumulated in the charge accumulation section FD.

[0212] In addition, in this driving example, an example of using only two pixels out of four pixels is shown, but it is not limited to this. The number of pixels used may be only one or only three. That is, in the case where the unit cell 120 includes n pixels, only m (m is a natural number less than n) pixels may be used for the ranging mode of the CW-ToF method. That is, in the ranging mode, instead of using all n pixels, m pixels may be exposed to the reflected light L2. Since the number of pixels to be driven can be reduced, power consumption can be reduced.

[0213] <Third driving example>

[0214] Next, use Fig.9A and Fig. 9B A third driving example of the imaging device 100 in the CW-ToF method will be described.

[0215] Fig.9A : is a timing chart showing the third driving example of the distance measurement mode of the CW-ToF method. Fig.9A The contents of RS, GC, VMIM, PRS1 to PRS4, TG1 to TG4 are the same as Fig. 7A The following description will focus on the differences from the first driving example, and description of the common points will be omitted.

[0216] like Fig.9A As shown, in one frame period, the charge accumulation period is different for each Pix group (unit cell 120). Specifically, it is set so that the phase of the time change of the voltage level of the control line PRSn (n=1 to 4) changes by 90° in the order of Pix group 0, Pix group 1, Pix group 2, and Pix group 3. In the Pix group (unit cell 120), the voltage level of PRSn (n=1 to 4) changes in the same phase.

[0217] The same is true for the control line TGn (n=1-4). The phase of the time change of the voltage level of the control line TGn (n=1-4) is set to change by 90 degrees in the order of Pix group 0, Pix group 1, Pix group 2, and Pix group 3. Within the Pix group (unit cell 120), the voltage level of TGn (n=1-4) changes in the same phase.

[0218] In this way, by making the charge accumulation period different for each unit cell 120 within one frame period, the occurrence of motion blur can be suppressed.

[0219] In addition, in this embodiment, an example is shown in which a charge storage unit FD is provided in common to four pixels 201 to 204, but a charge storage unit (memory) may be provided in each pixel. Fig. 9B As shown, the charge accumulation period of each pixel can be made different within one frame period. That is, the timing of starting and ending exposure of four pixels can be made different within a frame period. Fig. 9B This is a timing chart showing a modification of the third driving example of the distance measurement mode of the CW-ToF method.

[0220] Specifically, the time variation of each voltage level of the control lines PRS1 to PRS4 is set so that each phase varies by 90 degrees in this order. The time variation of each voltage level of the control lines TG1 to TG4 is set so that each phase varies by 90 degrees in this order. In this case, motion blur can also be suppressed.

[0221] [Pulse ToF method]

[0222] Next, use Fig. 10A , Fig. 10B and Fig. 10C The specific operation of the imaging device 100 in the pulse ToF distance measurement mode will be described.

[0223] Fig. 10A It is a timing chart showing a driving example of the distance measurement mode of the pulse ToF method. Fig. 10B is Fig. 10A The illustrated example is a diagram showing the relationship between the irradiated light and the reflected light and each frame period. Fig. 10C is Fig. 10A The example shown is a diagram showing an example of control signals supplied to two transfer transistors. Fig. 10A RS, GC, VMIM, PRS1 to PRS4, TG1 to TG4 respectively indicate the contents of Fig. 7A The following description will focus on the differences from the first driving example of the CW-ToF method, and description of the common points will be omitted.

[0224] like Fig. 10A As shown, each charge accumulation period of frame 1 to frame 3 corresponds to Figure 6 Specifically, Fig. 10B As shown, in frame 1, the charge accumulation period is set in the same interval as the irradiation light (pulse light). In frame 2, the charge accumulation period is set in the interval that starts at the same time as the irradiation light stops. In frame 3, the charge accumulation period is set in the interval where there is no reflected light. That is, in frame 3, the light source 11 stops emitting light. The length of the charge accumulation period in each frame is the same as the pulse width of the irradiation light. In frame 3, the signal intensity A2 (equivalent to Figure 6 By using the signal intensity A2 of the background light, the signal intensities A0 and A1 of the reflected light can be obtained from the detection results of frame 1 and frame 2, respectively. The obtained signal intensities A0 and A1 can be used to calculate the distance to the object 2 for each unit cell 120 according to the above formula (3), and a distance image can be generated.

[0225] In addition, during the charge accumulation period, Fig. 10C As shown, it is the period from the timing when the second transfer transistors 231 to 234 are turned off (the control line PRSn is switched from high level to low level) to the timing when the first transfer transistors 221 to 224 are turned off (the control line TGn is switched from high level to low level).

[0226] like Fig. 10C As shown, the rising edge of the voltage level of the control line TGn is delayed compared to the falling edge of the voltage level of the control line PRSn. In addition, the rising edge of the voltage level of the control line PRSn is delayed compared to the falling edge of the voltage level of the control line TGn. Thus, it is possible to suppress the first transfer transistors 221 to 224 and the second transfer transistors 231 to 234 from being turned on at the same time. It is possible to suppress the accidental inflow and / or outflow of the charge accumulated in the charge accumulation unit FD, so that the accuracy of the distance measurement can be improved. Such a driving method can also be used in the CW-ToF method.

[0227] In the pulse ToF method, it is also possible not to use part of the four pixels included in the unit cell 120. That is, when the unit cell 120 includes n pixels, only m (m is a natural number less than n) pixels can be used for the distance measurement mode of the pulse ToF method. By reducing the number of pixels to be driven, power consumption can be reduced.

[0228] [RGB Mode]

[0229] Next, the specific operation of the imaging device 100 in the RGB mode will be described.

[0230] <First driving example>

[0231] First, use Fig.11 A first driving example of the imaging device 100 in the RGB mode will be described. In the first driving example, the capacitor connection transistor 122 is used to reset the charge storage unit FD.

[0232] Fig.11 This is a timing chart showing the first driving example of the RGB mode. Fig.11 The contents of RS, GC, VMIM, PRS1 to PRS4, TG1 to TG4 are the same as Fig. 7A The following description will focus on the differences between the CW-ToF method and the first driving example, and description of the common points will be omitted.

[0233] Fig.11 The 1 / 2H shown is a period (1 / 2 horizontal period) of half the length of the horizontal period H, and corresponds to a frame period in the distance measurement mode. The horizontal period H is a period for reading out pixels arranged in the row direction among a plurality of pixels provided in the imaging device 100 .

[0234] exist Fig.11 In the example shown, the potential of the charge accumulation unit FD is reset by making the voltage level of the control line GC high at the beginning of the 1 / 2 horizontal period. In addition, since the voltage level of the control line RS is maintained at a high level, the reset transistor 121 is maintained in an on state (on). Therefore, by turning on the capacitor connection transistor 122, the charge accumulation unit FD and the power line AVDDP can be connected. In addition, the power line VMIM is maintained at a certain voltage level. The voltage level of the power line VMIM is maintained at the same voltage level as the power line AVDDP, for example. In addition, the voltage level of the power line VMIM is not particularly limited, and for example, it can also be maintained at 0V.

[0235] In the RGB mode, the voltage level of the control line PRSn is maintained at a low level. The voltage levels of the control lines TG1 to TG4 are maintained at a low level except for the specified pulse period (charge accumulation period). For example, in frame 1, the voltage level of the control line TG1 becomes a high level, and the first transfer transistor 221 is turned on. As a result, the charge generated by the photoelectric conversion unit 211 (equivalent to the intensity of the green light) is accumulated in the charge accumulation unit FD. Regarding the reading of the charge accumulated in the charge accumulation unit FD, Fig.11 Although not shown, after the voltage level of the control line TG1 is switched from high level to low level, at a predetermined timing in the period of frame 1 during which the voltage level is maintained at low level, the selection transistor 125 is turned on and the signal is read to the vertical signal line 160 .

[0236] In frame 2, by making the voltage level of the control line TG2 high, the first transfer transistor 222 is turned on. As a result, the charge generated by the photoelectric conversion unit 212 (equivalent to the intensity of red light) is accumulated in the charge accumulation unit FD and then read out. In frame 3, by making the voltage level of the control line TG3 high, the first transfer transistor 223 is turned on. As a result, the charge generated by the photoelectric conversion unit 213 (equivalent to the intensity of blue light) is accumulated in the charge accumulation unit FD and then read out. In frame 4, by making the voltage level of the control line TG4 high, the first transfer transistor 224 is turned on. As a result, the charge generated by the photoelectric conversion unit 214 (equivalent to the intensity of green light) is accumulated in the charge accumulation unit FD and then read out.

[0237] Thus, the signal strength of each RGB can be obtained from the unit cell 120. The signal strength of RGB is read out from each of the plurality of unit cells 120 and output as sensor output data from the imaging device 100 to the ISP 13. The ISP 13 can generate an RGB image using the signal strength of RGB for each unit cell 120.

[0238] According to the first driving example, the signal is read out while the capacitor connection transistor 122 is turned off, and the charge storage unit FD is reset by turning on the capacitor connection transistor 122. By making the capacitance component connected to the gate of the readout transistor 124 a small capacitance of only the charge storage unit FD, the signal can be read out at a higher gain.

[0239] <Second driving example>

[0240] Next, use Fig.12 A second driving example of the RGB mode imaging device 100 will be described. In the second driving example, the reset transistor 121 is used to reset the charge storage unit FD.

[0241] Fig.12 This is a timing chart showing the second driving example of the RGB mode. Fig.12 The contents of RS, GC, VMIM, PRS1 to PRS4, TG1 to TG4 are the same as Fig. 7A The following description will focus on the differences between the CW-ToF method and the first driving example, and description of the common points will be omitted.

[0242] exist Fig.12In the example shown, the potential of the charge accumulation unit FD is reset by making the voltage level of the control line RS high at the beginning of the 1 / 2 horizontal period. In addition, since the voltage level of the control line GC is maintained at a high level, the capacitor connection transistor 122 maintains the on state (on). Therefore, by turning on the reset transistor 121, the charge accumulation unit FD and the power line AVDDP can be connected. In addition, the power line VMIM is maintained at a certain voltage level. The voltage level of the power line VMIM is maintained at the same voltage level as the power line AVDDP, for example. In addition, the voltage level of the power line VMIM is not particularly limited, and for example, it can also be maintained at 0V.

[0243] According to the second driving example, the capacitor connection transistor 122 is maintained in the on state, and the signal is read out while the reset transistor 121 is turned off. By turning on the reset transistor 121, the charge storage unit FD is reset. The capacitance component connected to the gate of the readout transistor 124 can be increased by the charge storage unit FD and the capacitor 123, and the signal can be read out at a lower gain. By lowering the gain, the saturated signal can be read out without departing from the dynamic range of the subsequent circuit.

[0244] [Capacitors]

[0245] Next, use Fig.13A and Fig. 13B The function of the capacitor 123 will be described.

[0246] Fig.13A 3 is a diagram showing the potential within the unit cell 120 in the RGB mode. Fig. 13B is a diagram showing the potential within the unit cell 120 in the ToF mode.

[0247] exist Fig.13A and Fig. 13B , PRS, TG, GC and RS correspond to the control lines PRS, TG, GC and RS, respectively, and represent the gates of the second transfer transistor 231 (or any one of 232 to 234), the first transfer transistor 221 (or any one of 222 to 224), the capacitor connection transistor 122 and the reset transistor 121. Low means that the voltage level of the corresponding control line is low, and the corresponding transistor is in the off state. High means that the voltage level of the corresponding control line is high, and the corresponding transistor is in the on state. Pulse means a signal that is alternately supplied with high and low levels. PD represents the photoelectric conversion unit 211 (or any one of 212 to 214), FD represents the charge accumulation unit FD, and MIM represents the capacitor 123. The circular marks represented near PD and FD represent signal charges.

[0248] In RGB mode, such as Fig.13A As shown, during the period when the photoelectric conversion unit 211 is exposed, the first transfer transistor 221 and the second transfer transistor 231 are in the off state. Therefore, the generated signal charge is accumulated in the photoelectric conversion unit 211 and the node N1. When the signal is read out, after the first transfer transistor 221 is turned on, the select transistor 125 (not shown) is turned on, and the signal is read out to the vertical signal line 160. In the RGB mode, the capacitor 123 is not used and the reading is performed at a higher gain, so that noise can be suppressed.

[0249] On the other hand, in the ToF mode, the capacitor connection transistor 122 is maintained in the on state. Fig. 13B As shown, the signal charges generated by the photoelectric conversion units 211 to 214 are accumulated in the charge accumulation unit FD and the capacitor 123. As the accumulated amount of charges increases, high saturation can be achieved.

[0250] Thus, in this embodiment, the capacitive connection transistor 122 maintains the capacitor 123 and the charge storage unit FD in the conductive state in the ToF mode and makes the capacitor 123 and the charge storage unit FD non-conductive in the RGB mode. Thus, both high-precision distance measurement and high-quality RGB image acquisition can be achieved.

[0251] [Relationship between transfer transistor and control line]

[0252] Next, use Fig.14 The relationship between the first transfer transistor and the second transfer transistor in each pixel and the control line connected to each gate is described. Hereinafter, the pixel 201 is described as a representative, but the same applies to the pixels 202 to 204.

[0253] Fig.14 2 is a schematic plan view showing an example of a pixel 201 according to the present embodiment. The plan view shape of the photoelectric conversion unit 211 is, for example, a rectangle (square or rectangular). The photoelectric conversion unit 211 includes a p-type semiconductor region and an n-type semiconductor region (see the following) provided on a semiconductor substrate. Fig.23A ). The n-type semiconductor region and the p-type semiconductor region are stacked in the thickness direction of the substrate. The p-type semiconductor region is provided on the surface (upper surface) side of the semiconductor substrate than the n-type semiconductor region.

[0254] like Fig.14As shown, in the plan view, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are provided in a manner overlapping with a portion of the photoelectric conversion unit 211. An insulating film (not shown) is provided between the gates 221g and 231g and the photoelectric conversion unit 211 (p-type semiconductor region). The gates 221g and 231g are respectively formed using a conductive material such as metal or conductive polysilicon. The plan view shapes of the gates 221g and 231g are rectangular, but are not limited to this. In the present embodiment, the gates 221g and 231g have the same material, shape, and size.

[0255] In addition, the same size means not only that the areas (or volumes) are completely equal to each other, but also means that the difference between the areas (or volumes) is less than 5% of the area (or volume) of one side. In addition, the same shape means not only that the shapes are completely consistent with each other, but also means that the difference in area (or volume) caused by the difference in shapes is less than 5% of the area (or volume) of one side. In addition, the same material means not only that the composition ratio of the material is completely consistent, but also means that the difference in composition ratio is less than 5% of the composition ratio of one side. In the case of differences in size, shape and material caused by manufacturing errors, and differences in composition ratio caused by impurities inevitably mixed in during manufacturing, it is also regarded as "same". In view of the current manufacturing errors, it is set to less than 5%, but in the case of tolerance errors as manufacturing factors or design elements, it is not necessarily limited to 5%. These apply not only to gates 221g and 231g, but also to the materials, shapes and sizes of other components (for example, control lines described later).

[0256] The gate 221g is connected to the drive circuit 130 via the wiring 241 and the via 241v. Specifically, the wiring 241 is arranged above the gate 221g via an interlayer insulating film (not shown) so as to overlap with the gate 221g in a plan view. The via 241v penetrates the interlayer insulating film and connects the wiring 241 to the gate 221g. The wiring 241 and the via 241v constitute a control line TG1 as an example of a first control line.

[0257] The gate 231g is connected to the drive circuit 130 via the wiring 251 and the via 251v. Specifically, the wiring 251 is arranged above the gate 231g via an interlayer insulating film (not shown) so as to overlap with the gate 231g in a plan view. The via 251v penetrates the interlayer insulating film and connects the wiring 251 to the gate 231g. The wiring 251 and the via 251v constitute a control line PRS1 as an example of a second control line.

[0258] In this embodiment, the load of the control line TG1 is equal to the load of the control line PRS1. Specifically, the load of the control line TG1 from the drive circuit 130 to the gate 221g is equal to the load of the control line PRS1 from the drive circuit 130 to the gate 231g. The load of the control line is the parasitic resistance and parasitic capacitance (RC component) of the control line. Specifically, the RC component of the wiring 241 and the via 241v is equal to the RC component of the wiring 251 and the via 251v.

[0259] In addition, the equal load (RC component) mentioned above does not only mean that the loads are completely equal to each other, but also includes the case where the difference between the loads is less than 5% of the load of one side. In addition, when the error can be allowed as a manufacturing factor or design factor, it is not necessarily limited to 5%.

[0260] For example, the control line TG1 and the control line PRS1 have the same material, shape, and size. Specifically, the wiring 241 and the wiring 251 have the same material, shape, and size. The via 241v and the via 251v have the same material, shape, and size. By making the material, shape, and size the same, it is possible to easily make the mutual loads of the wirings and the vias equal. That is, it is possible to easily select the material and design the layout for making the loads equal.

[0261] In the present embodiment, in the plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are connected by a straight line ( Fig.14 The control lines TG1 and PRS1 are arranged in line symmetry with the single dot-dash line of FIG. 1 as the axis. By arranging in line symmetry, the loads of the control lines TG1 and PRS1 can be easily made equal. That is, the layout for making the loads equal can be easily designed.

[0262] The load of the control line may cause the waveform of the control signal output from the driving circuit 130 to be blunted. In particular, in the ToF mode, since the control lines TG1 and PRS1 are mutually exclusive and repeatedly high and low at a high speed, if the waveform of one is blunted more than the other, a difference occurs in the amount of accumulated charge, which may lead to a decrease in the ranging accuracy.

[0263] In contrast, in the present embodiment, the load of the control line TG1 is equal to the load of the control line PRS1. Thus, even if the waveform of the control signal output from the drive circuit 130 is blunted, the blunting difference between the control lines TG1 and PRS1 can be reduced. Therefore, the reduction in distance measurement accuracy can be suppressed.

[0264] In this embodiment, the number of effective pixels connected to the control line TG1 is equal to the number of effective pixels connected to the control line PRS1. This makes it easy to make the loads of the control line TG1 and the control line PRS1 equal, and can suppress the reduction of distance measurement accuracy.

[0265] In addition, Fig.14 In FIG. 1 , an example is shown in which the control line TG1 and the control line PRS1 have the same material, shape, and size and are arranged line-symmetrically, but the present invention is not limited thereto. Fig.15A As shown, the control line TG1 and the control line PRS1 have different shapes.

[0266] Fig.15A FIG. 2 is a schematic plan view showing another example of the pixel 201 according to the present embodiment. Fig.15A In the illustrated example, the gate 221g of the first transfer transistor 221 is connected to the drive circuit 130 via wirings 241a and 241b and vias 241v, 241c, and 241d.

[0267] Wiring 241b is located at a height different from wiring 241a and connected to wiring 241a via vias 241c and 241d. For example, control line TG1 and control line PRS1 may not be arranged at the same height (same layer) due to the arrangement of other wirings or electrodes. Fig.15A The shown example is an example corresponding to such a case.

[0268] In addition, when the control line includes a plurality of wirings located at different heights, the wiring that occupies the largest proportion of the total distance from the drive circuit 130 to the connection with the first transfer transistor or the second transfer transistor is called the main wiring. Fig.15A In the total distance from the drive circuit 130 to the gate 221g, if the distance between the wiring 241a and the wiring 241b is set to a ratio of 1:9, the main wiring in the control line TG1 is the wiring 241b. Fig.14 In the example shown, the main wiring of the control line TG1 is the wiring 241, and the main wiring of the control line PRS1 is the wiring 251. The heights of the wiring 241 and the wiring 251 are equal. Fig.15A An example is shown in which the heights of the wiring 241 b which is a main wiring of the control line TG1 and the wiring 251 which is a main wiring of the control line PRS1 are different from each other.

[0269] The path of the control line TG1 becomes longer than that of the control line PRS1. Generally, if the path becomes longer, the wiring resistance becomes larger. Therefore, the wiring 241b is made thicker than the wiring 241a. That is, by making the cross-sectional area of ​​the wiring 241b larger than the cross-sectional area of ​​the wiring 241a, the wiring resistance of the wiring 241b can be reduced. In this way, by adjusting the wiring resistance, the load of the control line TG1 can be equal to the load of the control line PRS1. In addition, the load of the control line TG1 can be equal to the load of the control line PRS1 by making the materials of the control line TG1 and the control line PRS1 different. As long as the load of the control line TG1 can be equal to the load of the control line PRS1, the specific implementation method is not particularly limited.

[0270] Figure 15B to Figure 15F Each of them is a schematic plan view showing another example of the pixel 201 related to this embodiment. Fig. 15B In the example shown, the number of the vias 241v is different from the number of the vias 251v. The number of the vias 241v is an example of the number of first contacts connecting the first control line (control line TG1) and the first transfer transistor 221. The number of the vias 251v is an example of the number of second contacts connecting the second control line (control line PRS1) and the second transfer transistor 231. Fig. 15B In the example shown, the number of the via holes 241v is 3, whereas the number of the via hole 251v is 1. Alternatively, the number of the via holes 241v and the shape of the via hole 251v may be the same, but the shape of the via hole 241v may be different from that of the via hole 251v. Alternatively, the number and shape of the via hole 241v and the via hole 251v may be different.

[0271] In this way, the loads of the two control lines TG1 and PRS1 can be adjusted by making the number of contacts different. Since the difference in blunting of the waveforms of the control signals transmitted through the two control lines TG1 and PRS1 can be reduced, a decrease in distance measurement accuracy can be suppressed.

[0272] In addition, Fig. 15C In the example shown, in the plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are arranged at positions rotated 180° with respect to the center Q of the photoelectric conversion unit 211. That is, the first transfer transistor 221 and the second transfer transistor 231 have a point-symmetric positional relationship and shape with the center Q of the photoelectric conversion unit 211 as the symmetry center.

[0273] exist Fig.15DIn the example shown, in the plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are arranged line-symmetrically with a straight line (single-dot chain line in the figure) passing through the center of the photoelectric conversion unit 211 as an axis. Fig.15D In the example shown, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are respectively arranged so that their plan view shapes overlap with the same side of the four sides of the rectangular photoelectric conversion unit 211. In this way, the first transfer transistor 221 and the second transfer transistor 231 may be arranged at positions offset to one side from the center of the photoelectric conversion unit 211.

[0274] exist Fig.15E In the example shown, in the plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are arranged at positions rotated 90° with respect to the center Q of the photoelectric conversion unit 211. Specifically, the control line TG1 and the first transfer transistor 221 are arranged at positions obtained by rotating the control line PRS1 and the second transfer transistor 231 90° clockwise. In addition, the rotation direction may also be counterclockwise.

[0275] In each figure, only the first transfer transistor 221 and the second transfer transistor 231 may be arranged line-symmetrically with respect to the straight line passing through the center of the photoelectric conversion portion 211 as an axis, or may be arranged at a position rotated 90° or 180° with respect to the center Q of the photoelectric conversion portion 211. That is, the control lines TG1 and PRS2 may not necessarily be arranged line-symmetrically with respect to the straight line passing through the center of the photoelectric conversion portion 211 as an axis, and may not be arranged at a position rotated 90° or 180° with respect to the center Q of the photoelectric conversion portion 211.

[0276] In addition, Fig.15F In the example shown, the first transfer transistor 221 and the second transfer transistor 231 are not symmetrical, and the control line TG1 and the control line PRS1 are not symmetrical. Fig.15F In the example shown in the plan view, at least one of the distance D1 between the first side 221ga of the gate 221g and the first straight line VL1 and the distance D2 between the second side 231ga of the gate 231g and the second straight line VL2 is greater than the length D of one side of the photoelectric conversion unit 211. PDThe first side 221ga is the side closest to the center Q of the photoelectric conversion unit 211 among the four sides of the gate 221g. The second side 231ga is the side closest to the center Q of the photoelectric conversion unit 211 among the four sides of the gate 231g. The first straight line VL1 is the side that passes through the center Q of the photoelectric conversion unit 211 and is parallel to the first side 221ga. The second straight line VL2 is the side that passes through the center Q of the photoelectric conversion unit 211 and is parallel to the second side 231ga. In addition, the length D PD For example, it is the length of the shortest side among the four sides of the photoelectric conversion body 211 , but the present invention is not limited thereto.

[0277] In this way, the positions of the gates 221g and 231g can be adjusted so as not to be too far away from the photoelectric conversion unit 211. That is, the load of parasitic capacitance and the like can be adjusted. As a result, the difference in the blunting of the waveform of the control signal transmitted in the two control lines TG1 and PRS1 can be reduced, so that the reduction in the distance measurement accuracy can be suppressed.

[0278] You can also Figures 15A to 15F As shown, by appropriately adjusting the configuration of the control line TG1 and PRS1, and the first transfer transistor 221 and the second transfer transistor 231 according to their materials, shapes, and sizes, the configuration is performed so that the load of the control line TG1 is equal to the load of the control line PRS1. That is, as long as the load of the control line TG1 can be equal to the load of the control line PRS1, the specific implementation method is not particularly limited.

[0279] [Specific structure and operation of the drive circuit]

[0280] Next, the specific structure and operation of the driving circuit 130 will be described. The following description will be given by taking the pixel 201 as an example among the plurality of pixels to be controlled by the driving circuit 130. Pixels 202 to 204 are the same as the pixel 201, and thus their description will be omitted.

[0281] <Structure>

[0282] First, use Fig.16 and Fig.17 The structure of the driving circuit 130 will be described. Fig.16 It is a diagram showing the structure of the driving circuit 130 according to the present embodiment. Fig.17 It is a diagram showing the circuit configuration of the pixel control circuit 136 and the substrate voltage supply circuit 134 according to this embodiment.

[0283] The driving circuit 130 of the present embodiment supplies a voltage corresponding to one operation mode selected from a plurality of operation modes to the substrate 170 or the first control terminal of the first transfer transistor or the second control terminal of the second transfer transistor. Specifically, the driving circuit 130 changes the voltage level of the voltage supplied to the substrate 170 according to the operation mode. In addition, the driving circuit 130 changes the magnitude (potential) of at least one of the high level and the low level of the voltage supplied to the gate of the first transfer transistor and the gate of the second transfer transistor according to the operation mode.

[0284] like Fig.16 As shown, the driving circuit 130 includes an operation mode control circuit 132 , a substrate voltage supply circuit 134 , and a pixel control circuit 136 .

[0285] The operation mode control circuit 132 is an example of a mode control circuit, and controls the substrate voltage supply circuit 134 and the pixel control circuit 136 according to the operation mode. Specifically, the operation mode control circuit 132 outputs a first control signal corresponding to one operation mode selected from a plurality of operation modes to the substrate voltage supply circuit 134. In addition, the operation mode control circuit 132 outputs a second control signal corresponding to one operation mode selected from a plurality of operation modes to the pixel control circuit 136.

[0286] The substrate voltage supply circuit 134 is an example of a first voltage supply circuit, and supplies voltage to the substrate 170. The substrate voltage supply circuit 134 can change the value (voltage level) of the voltage supplied to the substrate 170 based on the first control signal output from the operation mode control circuit 132. Fig.17 As shown, it includes two signal lines 311 and 312 and a first connecting circuit 321 .

[0287] The signal line 311 is an example of a first signal line set to a first potential. The first potential is, for example, a ground potential (0 V). The signal line 311 is a ground wiring set to a ground potential.

[0288] The signal line 312 is an example of a second signal line set to a second potential different from the first potential. Specifically, the second potential is a potential lower than the first potential. The second potential is, for example, -1 V, but is not limited thereto.

[0289] The first connection circuit 321 switches the signal lines 311 and 312 according to the operation mode and connects to the substrate 170. In the present embodiment, the first connection circuit 321 switches the signal lines 311 and 312 based on the first control signal and connects to the substrate 170. Specifically, when the imaging mode is selected, the first connection circuit 321 connects the signal line 311 to the substrate 170. When the distance measurement mode is selected, the first connection circuit 321 connects the signal line 312 to the substrate 170.

[0290] like Fig.17 As shown, the first connection circuit 321 includes two switch elements 301 and 302. For example, the switch elements 301 and 302 are FETs each having a gate, a source, and a drain.

[0291] The switch element 301 switches between conduction and non-conduction of the signal line 311 and the substrate 170. The gate of the switch element 301 is connected to the operation mode control circuit 132 and receives input of the first control signal. One of the source and drain of the switch element 301 is connected to the signal line 311. The other of the source and drain of the switch element 301 is connected to the substrate 170.

[0292] The switch element 302 switches between the conduction and non-conduction of the signal line 312 and the substrate 170. The gate of the switch element 302 is connected to the operation mode control circuit 132 via the inverter 135, and receives the input of the first control signal. One of the source and the drain of the switch element 302 is connected to the signal line 312. The other of the source and the drain of the switch element 302 is connected to the substrate 170.

[0293] The gate of the switch element 302 receives an inverted signal of the first control signal input to the gate of the switch element 301 via the inverter 135. Therefore, the switch elements 301 and 302 operate mutually exclusively. Specifically, when the switch element 301 is turned on, the switch element 302 is turned off, and when the switch element 302 is turned on, the switch element 301 is turned off.

[0294] The pixel control circuit 136 is an example of a second voltage supply circuit, and supplies a voltage to at least one of the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231. The pixel control circuit 136 can change the value (voltage level) of the voltage supplied to the gates 221g and 231g based on the second control signal output from the operation mode control circuit 132. Fig.17 As shown, signal lines 313 a , 313 b , 314 a , and 314 b and a second connection circuit 322 are provided.

[0295] Signal lines 313a and 313b are examples of one or more third signal lines that are set to at least one of a third potential and a fourth potential higher than the third potential. Specifically, signal line 313a is set to the third potential (low level). The third potential is, for example, -1.4V, but is not limited to this, and may be, for example, -1V. In the present embodiment, signal line 313a is the same as signal line 312, but may be different. Signal line 313b is set to the fourth potential (high level). The fourth potential is, for example, 3.3V, but is not limited to this, and may be, for example, 2.8V or 3.8V.

[0296] Signal lines 314a and 314b are examples of at least one of the fourth signal lines set to at least one of the fifth potential and the sixth potential higher than the fifth potential. Specifically, signal line 314a is set to the fifth potential (low level). The fifth potential is, for example, ground potential (0V). Signal line 314a is a ground wiring set to the ground potential. Signal line 314a may also be the same as signal line 311. Signal line 314b is set to the sixth potential (high level). The sixth potential is, for example, 2V, but is not limited thereto, and may also be 1.2V.

[0297] In addition, the signal line 314a is also an example of the 7th signal line set to the 7th potential, and the signal line 313a is also an example of the 8th signal line set to the 8th potential. The 8th potential in this case is a potential lower than the 7th potential, and corresponds to the above-mentioned 3rd potential (for example, -1.4V). The 7th potential in this case corresponds to the above-mentioned 5th potential (for example, 0V).

[0298] In addition, the signal line 313b is also an example of the 7th signal line set to the 7th potential, and the signal line 314b is also an example of the 8th signal line set to the 8th potential. The 8th potential in this case is a potential lower than the 7th potential, and corresponds to the 6th potential (for example, 2V) described above. The 7th potential in this case corresponds to the 4th potential (for example, 3.3V) described above.

[0299] In this embodiment, the potential difference between the 4th potential and the 3rd potential is different from the potential difference between the 6th potential and the 5th potential. Specifically, the potential difference between the 4th potential and the 3rd potential is greater than the potential difference between the 6th potential and the 5th potential. As an example, the potential difference between the 4th potential and the 3rd potential is more than twice the potential difference between the 6th potential and the 5th potential, but may also be more than three times.

[0300] The second connection circuit 322 switches the signal lines 313a and 313b and the signal lines 314a and 314b according to the operation mode and connects to at least one of the gates 221g and 231g. In the present embodiment, the second connection circuit 322 switches the signal lines 313a and 313b and the signal lines 314a and 314b based on the second control signal and connects to the gates 221g and 231g. Specifically, when the camera mode is selected, the second connection circuit 322 connects the signal lines 313a and 313b to the gates 221g and 231g. Specifically, the second connection circuit 322 connects one of the signal lines 313a and 313b to one of the gates 221g and 231g, and connects the other of the signal lines 313a and 313b to the other of the gates 221g and 231g. That is, the signal lines 313a and 313b are not connected to one gate at the same time. Furthermore, when the distance measurement mode is selected, the second connection circuit 322 connects the signal lines 314a and 314b to the gates 221g and 231g. Specifically, the second connection circuit 322 connects one of the signal lines 314a and 314b to one of the gates 221g and 231g, and connects the other of the signal lines 314a and 314b to the other of the gates 221g and 231g. That is, the signal lines 314a and 314b are not connected to one gate at the same time.

[0301] like Fig.17 As shown, the second connection circuit 322 includes switch elements 301n, 302n, 303n, 304n, 305n, 306n, 301p, 302p, 303p, 304p, 305p and 306p, and a control signal generating circuit 323.

[0302] The switch elements 301n to 306n are n-channel FETs each having a gate, a source, and a drain, and the switch elements 301p to 306p are p-channel FETs each having a gate, a source, and a drain.

[0303] The switch elements 301n and 301p are configured to select one of the combination of the signal lines 313a and 314a on the low level side and the combination of the signal lines 313b and 314b on the high level side and connect to the control line TG1. Specifically, the connection point of the switch elements 301n and 301p (one of the source and drain of each other) is connected to the control line TG1 (gate 221g). The gates of the switch elements 301n and 301p are connected to each other, and the control signal from the control signal generating circuit 323 is input. Therefore, when one of the switch elements 301n and 301p is in the conducting state (on), the other is in the non-conducting state (off). Specifically, when the switch element 301n is on, the potential of one of the signal lines 313a and 314a is supplied to the control line TG1 (gate 221g), and when the switch element 301p is on, the potential of one of the signal lines 313b and 314b is supplied to the control line TG1 (gate 221g).

[0304] The switch elements 302n and 302p are configured to select one of the combination of the signal lines 313a and 314a on the low level side and the combination of the signal lines 313b and 314b on the high level side and connect to the control line PRS1. Specifically, the connection point of the switch elements 302n and 302p (one of the source and drain of each other) is connected to the control line PRS1 (gate 231g). The gates of the switch elements 302n and 302p are connected to each other, and the control signal from the control signal generating circuit 323 is input. Therefore, when one of the switch elements 302n and 302p is in the conducting state (on), the other becomes non-conducting (off). Specifically, when the switch element 302n is turned on, the potential of one of the signal lines 313a and 314a is supplied to the control line PRS1 (gate 231g), and when the switch element 302p is turned on, the potential of one of the signal lines 313b and 314b is supplied to the control line PRS1 (gate 231g).

[0305] The switch element 303n is provided to switch the conduction and non-conduction between the signal line 313a and the control line TG1 (gate 221g). The switch element 304n is provided to switch the conduction and non-conduction between the signal line 313a and the control line PRS1 (gate 231g). The gates of the switch elements 303n and 304n are connected to each other, and the control signal from the control signal generating circuit 323 is input. Therefore, the switch elements 303n and 304n are turned on at the same time and turned off at the same time. When the switch element 303n is turned on and the switch element 301n is turned on, the potential of the signal line 313a is supplied to the control line TG1. When the switch element 304n is turned on and the switch element 302n is turned on, the potential of the signal line 313a is supplied to the control line PRS1.

[0306] The switch element 303p is provided to switch the conduction and non-conduction between the signal line 313b and the control line TG1 (gate 221g). The switch element 304p is provided to switch the conduction and non-conduction between the signal line 313b and the control line PRS1 (gate 231g). The gates of the switch elements 303p and 304p are connected to each other, and the control signal from the control signal generating circuit 323 is input. Therefore, the switch elements 303p and 304p are turned on at the same time and turned off at the same time. When the switch element 303p is turned on and the switch element 301p is turned on, the potential of the signal line 313b is supplied to the control line TG1. When the switch element 304p is turned on and the switch element 302p is turned on, the potential of the signal line 313b is supplied to the control line PRS1.

[0307] The switch element 305n is provided to switch the conduction and non-conduction between the signal line 314a and the control line TG1 (gate 221g). The switch element 306n is provided to switch the conduction and non-conduction between the signal line 314a and the control line PRS1 (gate 231g). The gates of the switch elements 305n and 306n are connected to each other, and the control signal from the control signal generating circuit 323 is input. Therefore, the switch elements 305n and 306n are turned on at the same time and turned off at the same time. When the switch element 305n is turned on and the switch element 301n is turned on, the potential of the signal line 314a is supplied to the control line TG1. When the switch element 306n is turned on and the switch element 302n is turned on, the potential of the signal line 314a is supplied to the control line PRS1.

[0308] The switch element 305p is provided to switch the conduction and non-conduction between the signal line 314b and the control line TG1 (gate 221g). The switch element 306p is provided to switch the conduction and non-conduction between the signal line 314b and the control line PRS1 (gate 231g). The gates of the switch elements 305p and 306p are connected to each other, and the control signal from the control signal generating circuit 323 is input. Therefore, the switch elements 305p and 306p are turned on at the same time and turned off at the same time. When the switch element 305p is turned on and the switch element 301p is turned on, the potential of the signal line 314b is supplied to the control line TG1. When the switch element 306p is turned on and the switch element 302p is turned on, the potential of the signal line 314b is supplied to the control line PRS1.

[0309] The control signal generation circuit 323 controls the switching elements 301n to 306n and 301p to 304p to be turned on and off based on the second control signal from the operation mode control circuit 132. The control signal generation circuit 323 is connected to the gates of the switching elements 301n to 306n and 301p to 304p, and outputs a control signal to each gate. The control signal can be either a high level or a low level.

[0310] <Action>

[0311] Next, use Fig.18A , Fig.18B and Fig.18C The specific operation of the driving circuit 130 will be described.

[0312] Fig.18A 2 is a diagram showing an example of a potential supplied to the gate 221g of the first transfer transistor 221 in the RGB mode. Fig.18B and Fig.18C Each of them is a diagram showing an example of a potential supplied to the gate 221g of the first transfer transistor 221 in the ToF mode. Figures 18A to 18C In each of TG and SUB, respectively, they represent the time changes of the voltage level (potential) of the control line TG1 and the substrate 170.

[0313] like Fig.18A As shown in FIG. 1 , in the RGB mode, the low level of the control line TG1 is -1.4V and the high level is 3.3V. Fig.18B and Fig.18C As shown, in the ToF mode, the low level of the control line TG1 is 0 V and the high level is 2.0 V. Thus, the level difference (potential difference, amplitude) between the high level and the low level of the control line TG1 in the ToF mode is smaller than the level difference (potential difference, amplitude) between the high level and the low level of the control line TG1 in the RGB mode.

[0314] In the RGB mode, in order to obtain a high-definition RGB image, a highly saturated photoelectric conversion unit 211 is desired. In order to realize a highly saturated photoelectric conversion unit 211, it is necessary to make the potential of the photoelectric conversion unit 211 deeper (higher), so when reading the signal charge, it is necessary to make the potential of the first transfer transistor 221 higher. In this case, it is necessary to make the voltage level supplied to the gate 221g of the first transfer transistor 221 higher. In this embodiment, as shown in FIG. Fig.18A As shown in FIG. 2 , the difference between the high level and the low level of the control line TG1 (gate 221g) is ensured to be large. Thus, a high-definition RGB image can be obtained.

[0315] On the other hand, in the ToF mode, in order to improve the distance measurement accuracy, it is required to repeatedly switch the high level and low level of the control line TG1 at a high speed. However, when the voltage level of the high level is high, the power consumption increases due to the high-speed switching.

[0316] Therefore, in this embodiment, if Fig.18B As shown, the voltage level of the high level is suppressed, and the level difference between the high level and the low level is made small. Thus, the increase of power consumption can be suppressed. In this way, according to the camera device 100 and the endoscope system 1 related to this embodiment, it is possible to take into account both the acquisition of high-definition RGB images and the distance measurement with suppressed power consumption.

[0317] In addition, in the ToF mode, if the level difference of the control line TG1 is reduced, the potential of the photoelectric conversion unit 211 is deep, so the signal charge from the photoelectric conversion unit 211 may not be fully read out. Fig.18C As shown, by lowering the voltage level of the substrate 170, the potential of the photoelectric conversion unit 211 can be lowered, and high-speed readout of signal charges can be achieved. In this way, according to the imaging device 100 and the endoscope system 1 related to this embodiment, it is possible to achieve both high-definition RGB image acquisition and high-precision distance measurement with suppressed power consumption.

[0318] Below, refer to Fig.17 To illustrate the use of Figures 18A to 18C The operation of the driving circuit 130 in the operation mode shown.

[0319] exist Fig.18A In the case of the RGB mode shown in the figure, in the substrate voltage supply circuit 134, the switch element 301 is maintained in the on state, and the switch element 302 is maintained in the off state. As a result, the ground potential (0V) is supplied to the substrate 170 from the signal line 311. In the pixel control circuit 136, when the voltage level of the control line TG1 is to be low, the switch elements 301n and 303n are turned on, and the potential (-1.4V) set to the signal line 313a is supplied to the control line TG1. When the voltage level of the control line TG1 is to be high, the switch elements 301p and 303p are turned on, and the potential (3.3V) set to the signal line 313b is supplied to the control line TG1.

[0320] In the RGB mode, the second transfer transistor 231 is maintained in the off state. Specifically, the switch elements 302n and 304n are turned on, and the potential (-1.4 V) set to the signal line 313a is supplied to the control line PRS1.

[0321] exist Fig.18BIn the ToF mode shown in FIG. 1 , in the substrate voltage supply circuit 134, the switch element 301 is maintained in the on state, and the switch element 302 is maintained in the off state. Thus, the ground potential (0V) is supplied to the substrate 170 from the signal line 311. In the pixel control circuit 136, when the voltage level of the control line TG1 is to be low, the switch elements 301n and 305n are turned on, and the potential (0V) set to the signal line 314a is supplied to the control line TG1. When the voltage level of the control line TG1 is to be high, the switch elements 301p and 305p are turned on, and the potential (2.0V) set to the signal line 314b is supplied to the control line TG1.

[0322] In the ToF mode, the second transfer transistor 231 is repeatedly switched on and off in a phase-inverted state with respect to the first transfer transistor 221. Specifically, when the voltage level of the control line PRS1 is to be low, the switch elements 302n and 306n are turned on, and the potential (0V) set to the signal line 314a is supplied to the control line PRS1. When the voltage level of the control line PRS1 is to be high, the switch elements 302p and 306p are turned on, and the potential (2.0V) set to the signal line 314b is supplied to the control line PRS1.

[0323] exist Fig.18C In the case of ToF mode shown, Fig.18B Compared with the ToF mode shown in FIG. 1 , the operation of the substrate voltage supply circuit 134 is different. Specifically, in the substrate voltage supply circuit 134, the switch element 302 is kept on and the switch element 301 is kept off. Thus, a potential lower than the ground potential (-1.4 V) is supplied to the substrate 170 from the signal line 312.

[0324] in addition, Figures 18A to 18C The operation shown is just an example. Various changes can be made in the RGB mode and the ToF mode.

[0325] Fig.19A 1 is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221 and the reset transistor 121 in the RGB mode. Fig.19B is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221, the second transfer transistor 231, and the reset transistor 121 in the ToF mode. Fig.19A and Fig.19B In FIG. 1 , TG, PRS, and RS represent time changes in the voltage levels (potentials) of the control lines TG1, PRS1, and RS, respectively.

[0326] In RGB mode, as in Fig.11 and Fig.12 As shown in , the first transfer transistor 221 is turned on once in one frame. Fig.19A As shown, the voltage level of the control line TG1 is maintained at a low level (-1 V), switched to a high level (2.8 V) at a predetermined timing, and then maintained at a low level again. In this case, the level difference between the high level and the low level of the control line TG1 is 3.8 V. As described above, a high-definition RGB image can be obtained.

[0327] In contrast, in ToF mode, as in Fig.11 and Fig.12 As shown in , within one frame, the first transfer transistor 221 and the second transfer transistor 231 are exclusively turned on and off repeatedly at high speed. Fig.19B As shown in FIG. 1 , the voltage level of the control line TG1 repeatedly becomes a low level (1.2V) and a high level (2.8V). This is also the case with the control line PRS1. In this case, the level difference between the high level and the low level of the control line TG1 is 2.6V. As a result, in the ToF mode, since the level difference of the control line TG1 can be made smaller than in the RGB mode, the increase in power consumption associated with high-speed switching can be suppressed.

[0328] In this way, Fig.19A and Fig.19B In the example shown, the high level value of the control line TG1 is the same. That is, only the low level value of the control line TG1 may be changed, and even in this case, both high-definition RGB image acquisition and distance measurement with reduced power consumption can be achieved.

[0329] In addition, if Fig.18C As shown, the voltage level supplied to the substrate 170 may also be changed. Fig. 20A 1 is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221 and the reset transistor 121 , and the substrate 170 in the RGB mode. Fig. 20B 1 is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221 , the second transfer transistor 231 , and the reset transistor 121 , and the substrate 170 in the ToF mode.

[0330] like Fig. 20A As shown, in the RGB mode, the voltage level supplied to the substrate 170 is 0V. Fig. 20A In the example shown, the high level of the control line TG1 is 3.8 V, and in the RGB mode, a higher saturation of the photoelectric conversion unit 211 is achieved. That is, a highly saturated signal of the photodiode can be read out.

[0331] In contrast, Fig. 20BAs shown, in the ToF mode, the voltage level supplied to the substrate 170 is -1 V, which is lower than that in the RGB mode. This makes it possible to lower the potential of the photoelectric converter 211 in the ToF mode, thereby realizing faster signal reading.

[0332] In addition, in this embodiment, an example of changing both the voltage supplied to the substrate by the drive circuit 130 and the voltage supplied to the gate of the transfer transistor according to the operation mode is shown, but it is not limited to this. The drive circuit 130 may not change one of the voltage supplied to the substrate and the voltage supplied to the gate of the transfer transistor. Specifically, the drive circuit 130 may supply a certain voltage to the substrate regardless of the operation mode. Alternatively, the drive circuit 130 may supply the same value of the high level and the low level of the voltage supplied to the gate of the transfer transistor regardless of the operation mode.

[0333] Alternatively, you can Fig. 20C As shown, the drive circuit 130 changes the voltage supplied to the substrate 170 during the exposure period and the readout period. Fig. 20C 1 is a diagram showing a modification of the potentials supplied to the gates of the first transfer transistor 221 , the second transfer transistor 231 , and the reset transistor 121 , and the substrate 170 in the ToF mode.

[0334] In addition, in this embodiment, an example is shown in which two third signal lines and four signal lines are provided, but one of each may be provided. In this case, the voltage level (potential) set for one third signal line is switched between the third potential and the fourth potential. Similarly, the voltage level (potential) set for one fourth signal line is switched between the fifth potential and the sixth potential.

[0335] Furthermore, in this embodiment, the driving circuit 130 may also control the voltage level of the power line VMIM. Fig.21 1 is a diagram showing the potential in the unit cell 120 when the voltage of the capacitor 123 is controlled in the ToF mode.

[0336] In the RGB mode, the driving circuit 130 supplies a voltage level V1 to the power line VMIM, and in the ToF mode, the driving circuit 130 supplies a voltage level V2 to the power line VMIM. The voltage level V2 is higher than the voltage level V1. In addition, the voltage level V1 is, for example, the same as the voltage level supplied to the power line AVDDP. That is, in the ToF mode, the driving circuit 130 makes the potential supplied to the second electrode of the capacitor 123 higher than the potential supplied to the power line AVDDP.

[0337] exist Fig.21 In FIG. 1 , the potential of the charge storage unit FD and the capacitor 123 in the RGB mode are indicated by dotted lines. Fig.21 As shown, in the ToF mode, since the potential of the charge storage unit FD and the capacitor 123 becomes deeper, it is possible to easily read out the signal from the photoelectric conversion unit 211. Therefore, high-speed reading is possible, so that the distance measurement accuracy can be improved.

[0338] The capacitor 123 is a capacitor having an MIM structure, but is not limited thereto. For example, a parasitic capacitance generated between a wiring connected to the source or drain of the charge storage unit FD or the capacitor connection transistor 122 and a power line may be used as the capacitor 123 .

[0339] [Positional Relationship between Photoelectric Converter and Gate of Transfer Transistor]

[0340] Next, the positional relationship between the photoelectric conversion unit 211 and the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 is described. In addition, the following description takes the pixel 201 as an example among the multiple pixels that are the control targets of the drive circuit 130. Pixels 202 to 204 are the same as pixel 201, so the description is omitted.

[0341] Fig. 22 It is a plan view of the photoelectric conversion unit 211 according to this embodiment. Fig.23A yes Fig. 22 The cross-sectional view of the XXIII-XXIII line. Fig.23A As shown, the photoelectric conversion portion 211 includes an n-type impurity region 211n and a p-type impurity region 211p.

[0342] The n-type is an example of the first conductivity type. A so-called heavily doped state in which the concentration of n-type impurities is high is referred to as n-type. + The so-called lightly doped state with a low concentration of n-type impurities is called n － The p-type is an example of the second conductivity type, which is opposite to the first conductivity type. The so-called heavily doped state in which the concentration of p-type impurities is high is called p + The so-called lightly doped state with a low concentration of p-type impurities is called p － When the substrate 170 is a silicon substrate, pentavalent elements such as phosphorus and arsenic can be used as n-type impurities, and trivalent elements such as boron and aluminum can be used as p-type impurities.

[0343] The n-type impurity region 211n is an example of a first semiconductor region, and is provided in the substrate 170. The impurity region 211n is provided on the back side (light incident side) of the substrate 170 relative to the impurity region 211p.

[0344] The p-type impurity region 211p is an example of a second semiconductor region and is provided on the impurity region 211n in the substrate 170. The impurity region 211p is provided on the surface side of the substrate 170 (the side opposite to the light incident side) relative to the impurity region 211n. The upper surface of the impurity region 211p corresponds to the upper surface of the substrate 170.

[0345] The impurity regions 211n and 211p are formed by doping predetermined regions of the substrate 170 with n-type impurities or p-type impurities by ion implantation or the like. Alternatively, the impurity regions 211n and 211p may be formed by epitaxial growth while selectively introducing impurities into the substrate body.

[0346] In this embodiment, the thickness of the photoelectric conversion unit 211 is 3 μm or less. In addition, the thickness of the photoelectric conversion unit 211 corresponds to the depth of the photoelectric conversion unit 211, which is the distance from the upper surface of the substrate 170, that is, the upper surface of the p-type impurity region 211p to the lower surface of the n-type impurity region. By reducing the thickness (depth) of the photoelectric conversion unit 211, high-speed readout of signal charges can be achieved.

[0347] If the thickness of the photoelectric conversion unit 211 is greater than 6 μm, defects are likely to occur at the interface with the element isolation region (DTI: Deep Trench Isolation) used to separate the photoelectric conversion unit 211 for each pixel, and the dark current passing through the defect increases. By setting the thickness of the photoelectric conversion unit 211 to less than 3 μm, the occurrence of dark current can be suppressed and the ranging accuracy can be improved. In particular, when the visible light band is used as the light for ranging, even if the thickness of the photoelectric conversion unit 211 is less than 3 μm, ranging can be performed with higher accuracy. In addition, if the defects at the interface can be sufficiently suppressed, the thickness of the photoelectric conversion unit 211 can be made larger than 3 μm.

[0348] In this embodiment, if Fig. 22As shown, in the plan view of the substrate 170, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 overlap with the impurity region 211n, respectively. At this time, the area S1 of the gate 221g overlapping with the impurity region 211n is more than half of the area Sg1 of the gate 221g. The area S2 of the gate 231g overlapping with the impurity region 211n is more than half of the area Sg2 of the gate 231g. In addition, the area S1 of the gate 221g overlapping with the impurity region 211n may be more than 55%, more than 60%, more than 70%, or more than 80% of the area Sg1 of the gate 221g. The area S2 of the gate 231g overlapping with the impurity region 211n may be more than 55%, more than 60%, more than 70%, or more than 80% of the area Sg2 of the gate 231g.

[0349] Alternatively, the total value of the area S1 where the gate 221g overlaps with the impurity region 211n and the area S2 where the gate 231g overlaps with the impurity region 211n is the area S of the photoelectric conversion unit 211. PD Alternatively, the total value of the area S1 where the gate 221g overlaps with the impurity region 211n and the area S2 where the gate 231g overlaps with the impurity region 211n may be equal to or greater than the area S2 of the photoelectric conversion unit 211. PD It may be more than 30%, or more than 40%, or more than 50%, or more than 60%, or more than 70%, or more than 80%.

[0350] In addition, in the arrangement direction of the gate electrodes 221g and 231g (the first direction, Fig. 22 In the direction parallel to the line XXIII-XXIII in FIG. 1 ), the total value of the length L1 of the gate 221g overlapping with the impurity region 211n and the length L2 of the gate 231g overlapping with the impurity region 211n is greater than or equal to 20% of the length L of the photoelectric conversion unit 211. In addition, the total value of the length L1 and the length L2 may be greater than or equal to 30% of the length L, or greater than or equal to 40%, or greater than or equal to 50% (half).

[0351] As described above, in the present embodiment, the gate 221 g of the first transfer transistor 221 and the gate 231 g of the second transfer transistor 231 are provided so as to overlap with the photoelectric conversion unit 211 in the plan view of the substrate 170 .

[0352] Conventionally, in the plan view of the substrate 170, the gate electrodes 221g and 231g do not cover the photoelectric conversion unit 211 but are arranged to sandwich the photoelectric conversion unit 211. In addition, in order to suppress the dark current flowing between the gate electrodes 221g and 231g via the surface of the substrate 170, as shown in Fig. 23BAs shown in FIG. 1 , a p-type region having a higher impurity concentration than the impurity region 211p is formed. + Type or sufficiently high p ++ type impurity region 211pp. In addition, Fig. 23B is equivalent to Fig. 22 A cross-sectional view of a pixel of the comparative example taken along line XXIII-XXIII.

[0353] However, when miniaturizing the pixel, since the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are close to each other, it is not possible to form the gate 221g of the first transfer transistor 221 with high precision. ++ In particular, in the case of a pixel including multiple gates for ranging or global shutter, it is difficult to ensure p ++ As a result, dark current increases, resulting in a decrease in ranging accuracy.

[0354] In contrast, in the present embodiment, each of the gate electrodes 221g and 231g is provided so as to overlap with the p-type impurity region 211p in a plan view of the substrate 170. Fig.24 As shown, when the drive circuit 130 supplies a negative voltage to the gates 221g and 231g, a hole accumulation region 211pa in which holes are accumulated is formed in the region directly below the gates 221g and 231g in the impurity region 211p. Fig.24 It is a cross-sectional view showing the cross-sectional structure of the photoelectric conversion unit 211 when a negative voltage is supplied to each gate of the first transfer transistor 221 and the second transfer transistor 231 .

[0355] The hole accumulation region 211pa is an example of the fifth semiconductor region and is a part of the impurity region 211p. The carrier concentration of the hole accumulation region 211pa is higher than that of the fourth semiconductor region, specifically the impurity region 211pb, which is another part of the impurity region 211p. Therefore, even if p ++ The type of impurity region can also suppress dark current.

[0356] By suppressing the dark current, the dynamic range of the imaging device 100 can be expanded. The dynamic range is a parameter indicating the range of light intensity that can be measured by the imaging device 100. The dynamic range is determined based on the saturation of the photoelectric conversion unit 211 and the size of the dark current. The saturation of the photoelectric conversion unit 211 is related to the area S of the photoelectric conversion unit 211. PD The dark current is inversely proportional to the area S1+S2 of the hole accumulation region 211pa.

[0357] The area S of the photoelectric conversion unit 211 PDUsually, it is a predetermined fixed value because it is determined by the size of the unit cell 120. Therefore, in order to expand the dynamic range, it is required to increase the area of ​​the hole accumulation region 211pa.

[0358] Fig.25 2 is a diagram showing the dynamic range of the imaging device 100 corresponding to the area ratio of the hole accumulation region 211pa. Fig.25 In the figure, the horizontal axis represents the area S1+S2 of the hole accumulation region 211pa relative to the area S PD The vertical axis represents the dynamic range of the imaging device 100. The area of ​​the hole accumulation region 211pa corresponds to the total value of the area S1 where the gate 221g overlaps with the impurity region 211n and the area S2 where the gate 231g overlaps with the impurity region 211n.

[0359] like Fig.25 As shown in FIG. 1 , the larger the area S1+S2 of the hole accumulation region 211pa is, the larger the dynamic range of the imaging device 100 is. In particular, the area S1+S2 of the hole accumulation region 211pa is relative to the area S PD The dynamic range is greatly expanded when the ratio of the hole accumulation region 211pa is from 10% to 20%. PD The ratio is 20% or more, which can sufficiently increase the dynamic range.

[0360] In addition, if the relationship between the area ratio of the hole accumulation region 211pa and the dynamic range is improved with the development of future process technology, the area S1+S2 of the hole accumulation region 211pa relative to the area S PD For example, the area S1+S2 of the hole accumulation region 211pa relative to the area S1 of the photoelectric conversion unit 211 is not necessarily greater than 20%. PD The ratio may also be 10% or more.

[0361] In addition, the photoelectric conversion unit may include a third semiconductor region provided on the p-type second semiconductor region. + Type or p ++ In this case, p + Type or p ++The impurity region of the type is a hole accumulation region, which can suppress the dark current caused by interface defects. In this case, the total value of the overlapping area of ​​the control terminal (gate) of the first transfer transistor and the photoelectric conversion unit and the overlapping area of ​​the control terminal (gate) of the second transfer transistor and the photoelectric conversion unit can also be more than 10% of the area of ​​the photoelectric conversion unit, and the same dark current suppression effect as the above embodiment can be expected.

[0362] In addition, the imaging device may also include an electrode arranged in a portion of the region where the control terminal (gate) of the first transfer transistor and the control terminal (gate) of the second transfer transistor are not arranged on the photoelectric conversion unit, and a driving circuit that supplies a voltage below the potential of the substrate to the electrode. In this case, a hole accumulation layer can be formed in the region directly below the electrode. Thus, the hole accumulation layer can play a function equivalent to that of a high-concentration p-type impurity layer. Thus, the area of ​​the hole accumulation layer can be increased, so the total value of the area where the control terminal (gate) of the first transfer transistor overlaps with the photoelectric conversion unit and the area where the control terminal (gate) of the second transfer transistor overlaps with the photoelectric conversion unit can also be more than 10% of the area of ​​the photoelectric conversion unit, and the same dark current suppression effect as in the above-mentioned embodiment can be foreseen.

[0363] In addition, the dark current caused by the gate insulating film is affected by the energy band gap width. When using an insulating film material with a wider energy band gap width, it is possible to suppress the dark current caused by the gate insulating film. In this case, the total value of the area where the control terminal (gate) of the first transfer transistor overlaps with the photoelectric conversion unit and the area where the control terminal (gate) of the second transfer transistor overlaps with the photoelectric conversion unit can also be more than 10% of the area of ​​the photoelectric conversion unit, and the same dark current suppression effect as the above-mentioned embodiment can be foreseen. In addition, the above embodiment is an example of suppressing the dark current caused by the gate insulating film.

[0364] Such a method of manufacturing the imaging device 100 includes: a first step of forming the photoelectric conversion unit 211 in the substrate 170 ; and a second step of forming the first transfer transistor 221 and the second transfer transistor 231 connected to the photoelectric conversion unit 211 .

[0365] In the first step, the photoelectric conversion unit 211 including the impurity region 211p is formed on the impurity region 211n. In the first step, for example, the impurity regions 211n and 211p are formed by doping n-type impurities or p-type impurities by ion implantation into a predetermined region of the substrate 170. Alternatively, the impurity regions 211n and 211p may be formed by selectively introducing impurities into the substrate body while performing epitaxial growth.

[0366] In the second step, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are formed so as to overlap with the impurity region 211p in the plan view of the substrate 170. For example, in the second step, the gates 221g and 231g are respectively arranged on the impurity region 211p via an insulating film in the plan view of the substrate 170. Specifically, in the second step, the gates 221g and 231g are respectively formed so as to overlap with the impurity region 211p, so that in the plan view of the substrate 170, the area S1 where the gate 221g overlaps with the impurity region 211p becomes more than half of the area Sg1 of the gate 221g, and the area S2 where the gate 231g overlaps with the impurity region 211p becomes more than half of the area Sg2 of the gate 231g. Alternatively, in the second step, the gates 221g and 231g are respectively formed to overlap with the impurity region 211p, so that in the plan view of the substrate 170, the total value of the area S1 where the gate 221g overlaps with the impurity region 211p and the area S2 where the gate 231g overlaps with the impurity region 211p becomes the area S PD Alternatively, in the second step, the gates 221g and 231g are respectively formed to overlap with the impurity region 211p so that in the plan view of the substrate 170, in the arrangement direction of the gates 221g and 231g, the total value of the overlapping length L1 of the gate 221g and the impurity region 211p and the overlapping length L2 of the gate 231g and the impurity region 211p is greater than 20% of the length L of the photoelectric conversion unit 211.

[0367] For example, first, an insulating film is formed in a manner that covers the surface of the substrate 170. The insulating film is formed, for example, by plasma CVD (Chemical Vapor Deposition). After the insulating film is formed, a conductive film is formed. The conductive film is formed by sputtering, evaporation, or the like. The gates 221g and 231g are formed by patterning the formed conductive film. The patterning is performed by photolithography and dry etching or wet etching. At this time, the gates 221g and 231g are formed by overlapping the photoelectric conversion portion 211 in the plan view of the substrate 170 by patterning in a manner that retains a portion that covers the photoelectric conversion portion 211 in the conductive film.

[0368] (Other embodiments)

[0369] The above describes the camera device, the distance measuring device, the control method and the manufacturing method of the camera device, etc. related to one or more technical solutions based on the embodiments, but the present disclosure is not limited to these embodiments. As long as it does not deviate from the main purpose of the present disclosure, various deformed forms that can be thought of by those skilled in the art are applied to the present embodiment, and forms constructed by combining the constituent elements of different embodiments are also included in the scope of the present disclosure.

[0370] For example, in the above-mentioned embodiment, the endoscope system 1 is shown as an example of a distance measuring device, but it is not limited to this. The distance measuring device may be, for example, a surveillance camera or an object detection device installed in a predetermined building or structure. Alternatively, the distance measuring device may be a sensor device mounted on a moving body such as an autonomous driving vehicle or an unmanned aerial vehicle. In addition, in these cases, the object 2 is a stationary object or a moving body, etc.

[0371] In addition, for example, the visible light image may not be an RGB image. The visible light image may also be a monochrome image such as a black and white image. In addition, for example, the first wavelength of light used in the first operation mode and the second wavelength of the flashing light used in the second operation mode may be the same. In addition, the image obtained in the camera mode may be either a still image or a moving image.

[0372] Furthermore, the first operation mode and the second operation mode may not be the imaging mode and the distance measurement mode. For example, the first operation mode and the second operation mode may be the short exposure mode and the long exposure mode in the imaging mode.

[0373] Alternatively, the first operation mode and the second operation mode may be two modes with different frequencies in the ToF mode, or two modes with different pulse widths, etc. Alternatively, the first operation mode and the second operation mode may be a pulse ToF mode or a CW-ToF mode.

[0374] In addition, there is no particular limitation on the communication method between the devices described in the above embodiment. When wireless communication is performed between devices, the method of wireless communication (communication specification) is, for example, short-range wireless communication such as ZigBee (registered trademark), Bluetooth (registered trademark) or wireless LAN (Local Area Network). Alternatively, the method of wireless communication (communication specification) may also be communication via a wide area communication network such as the Internet. In addition, wired communication may be performed between devices instead of wireless communication. Specifically, wired communication is communication using power line communication (PLC: Power Line Communication) or wired LAN.

[0375] In addition, in the above-mentioned embodiment, the processing performed by a specific processing unit may be performed by another processing unit. In addition, the order of multiple processing may be changed, or multiple processing may be performed in parallel. In addition, the allocation of the components of the ranging device (ranging system) to multiple devices is an example. For example, the components of one device may be possessed by other devices.

[0376] For example, the processing described in the above embodiment can also be implemented by centralized processing using a single device (system), or can also be implemented by decentralized processing using multiple devices. In addition, the processor that executes the above program can be either single or multiple. That is, centralized processing can also be performed, or decentralized processing can also be performed.

[0377] In addition, in the above-mentioned embodiment, all or part of the components such as the control unit may be formed by dedicated hardware, or may be implemented by executing a software program suitable for each component. Each component may also be implemented by a program execution unit such as a CPU (Central Processing Unit) or a processor reading and executing a software program recorded in a recording medium such as a HDD (Hard Disk Drive) or a semiconductor memory.

[0378] Furthermore, components such as the control unit may be constituted by one or more electronic circuits. The one or more electronic circuits may be general-purpose circuits or dedicated circuits.

[0379] For example, a semiconductor device, IC or LSI may be included in one or more electronic circuits. IC or LSI may be integrated in one chip or in multiple chips. Here, it is called IC or LSI, but the name changes depending on the degree of integration, and it may also be called system LSI, VLSI (Very Large Scale Integration) or ULSI (Ultra Large Scale Integration). In addition, FPGA programmed after the manufacture of LSI can also be used for the same purpose.

[0380] In addition, the global or specific technical solutions of the present disclosure may also be implemented by a system, device, method, integrated circuit or computer program. Alternatively, it may also be implemented by a computer-readable non-temporary recording medium such as an optical disk, HDD or semiconductor memory storing the computer program. In addition, it may also be implemented by any combination of a system, device, method, integrated circuit, computer program and recording medium.

[0381] In addition, various changes, substitutions, additions, omissions, etc. can be made to the above-mentioned embodiments within the scope of the claims or their equivalents.

[0382] Industrial Applicability

[0383] The present disclosure can be used as an imaging device that can be used for high-precision distance measurement, and can be used for, for example, an endoscope system, a surveillance camera, and the like.

[0384] Description of symbols

[0385] 1 Endoscope system; 2 Object; 10 Main body; 11 Light source; 12 Light source driving circuit; 13 ISP; 14 Output unit; 15 System control circuit; 16 Power supply IC; 20 Insertion unit; 21 Light guide member; 22 Objective lens; 23 Condenser lens; 100 Camera device; 110 Sensor array; 120 Unit cell; 121 Reset transistor; 122 Capacitor connection transistor; 123 Capacitor; 124 Readout transistor; 125 Select transistor; 130 Drive circuit; 132 Operation mode control circuit; 134 Substrate voltage supply circuit; 135 Inverter; 136 Pixel control circuit; 140 Signal output circuit; 150 Control line; 160 Vertical signal line; 170 Substrate; 201, 202, 203, 204 Pixel; 211, 212, 213, 214 Photoelectric conversion unit; 211n, 212 1p, 211pb, 211pp impurity regions; 211pa hole accumulation region; 221, 222, 223, 224 first transfer transistors; 221g, 231g gates; 221ga first side; 231, 232, 233, 234 second transfer transistors; 231ga second side; 241, 241a, 241b, 251 wiring; 241c, 241d, 241v, 251v conduction hole; 301, 301n, 301p, 302, 302n, 302p, 303n, 303p, 304n, 304p, 305n, 305p, 306n, 306p switching elements; 311, 312, 313a, 313b, 314a, 314b signal lines; 321 first connecting circuit; 322 second connecting circuit; 323 control signal generating circuit.

Claims

1. A camera device, characterized in that: have: A first semiconductor layer; A unit cell, provided in the first semiconductor layer, comprising n pixels and a charge accumulation section for accumulating charges generated by the n pixels, wherein n is a natural number; as well as Drive circuit, The n pixels mentioned above respectively include: Photoelectric conversion unit; a first transfer transistor having a first control terminal, a first input / output terminal connected to the photoelectric conversion unit, and a second input / output terminal connected to the charge storage unit; and The second transfer transistor has a second control terminal, a third input / output terminal connected to the photoelectric conversion unit, and a fourth input / output terminal different from the third input / output terminal. The driving circuit supplies a voltage corresponding to one operation mode selected from a plurality of operation modes to the first semiconductor layer, or the first control terminal, or the second control terminal.

2. The imaging device according to claim 1, wherein: The above-mentioned multiple action modes include: a first operation mode, exposing at least one pixel of the n pixels to light of a first wavelength; and In the second operation mode, at least one pixel among the n pixels is exposed to scintillation light having a second wavelength.

3. The imaging device according to claim 1 or 2, wherein: The driving circuit comprises: a first voltage supply circuit for supplying a voltage to the first semiconductor layer; and The second voltage supply circuit supplies a voltage to at least one of the first control terminal and the second control terminal.

4. The imaging device according to claim 2, wherein: The driving circuit includes a first voltage supply circuit for supplying a voltage to the first semiconductor layer. The first voltage supply circuit comprises: The first signal line is set to a first potential; a second signal line set to a second potential different from the first potential; and The first connection circuit connects the first signal line and the second signal line to the first semiconductor layer according to the switching of the operation mode.

5. The imaging device according to claim 4, wherein: The second potential is lower than the first potential. When the first operation mode is selected, the first connection circuit connects the first signal line to the first semiconductor layer, and when the second operation mode is selected, the first connection circuit connects the second signal line to the first semiconductor layer.

6. The imaging device according to any one of claims 2, 4 and 5, characterized in that: The drive circuit includes a second voltage supply circuit for supplying a voltage to at least one of the first control terminal and the second control terminal. The second voltage supply circuit comprises: One or more third signal lines are set to at least one of a third potential and a fourth potential, the fourth potential being higher than the third potential; One or more fourth signal lines are set to at least one of a fifth potential and a sixth potential, the sixth potential being higher than the fifth potential; and The second connection circuit connects the one or more third signal lines and the one or more fourth signal lines to at least one of the first control terminal and the second control terminal according to the switching of the operation mode.

7. The imaging device according to claim 6, wherein: A potential difference between the fourth potential and the third potential is different from a potential difference between the sixth potential and the fifth potential.

8. The imaging device according to claim 6 or 7, wherein: The potential difference between the fourth potential and the third potential is greater than the potential difference between the sixth potential and the fifth potential, When the first action mode is selected, the second connection circuit connects the one or more third signal lines to at least one of the first control terminal and the second control terminal. When the second action mode is selected, the second connection circuit connects the one or more fourth signal lines to at least one of the first control terminal and the second control terminal.

9. The imaging device according to any one of claims 2, 4 and 5, characterized in that: The drive circuit includes a second voltage supply circuit for supplying a voltage to at least one of the first control terminal and the second control terminal. The second voltage supply circuit comprises: The seventh signal line is set to the seventh potential; an eighth signal line set to an eighth potential different from the seventh potential; and The third connection circuit connects the seventh signal line and the eighth signal line to at least one of the first control terminal and the second control terminal according to the switching of the operation mode.

10. The imaging device according to claim 9, wherein: The eighth potential is lower than the seventh potential. When the first action mode is selected, the third connection circuit connects the seventh signal line to at least one of the first control terminal and the second control terminal. When the second action mode is selected, the third connection circuit connects the eighth signal line to at least one of the first control terminal and the second control terminal.

11. The imaging device according to any one of claims 2 and 4 to 10, wherein: The unit cell includes a capacitor having a first electrode and a second electrode, and a switch element connected in series between the first electrode and the charge storage unit. In the second operation mode, the switching element maintains the capacitor and the charge storage unit in a conductive state, and in the first operation mode, the switching element makes the capacitor and the charge storage unit non-conductive.

12. The imaging device according to claim 11, wherein: In the second operation mode, the drive circuit makes the potential supplied to the second electrode lower than the potential supplied to the fourth input / output terminal.

13. A distance measuring device, characterized in that: have: light source; The imaging device according to any one of claims 1 to 12; and The calculation circuit calculates the distance to the object based on the signal output from the imaging device.

14. A method for controlling an imaging device, the method for controlling an imaging device according to any one of claims 1 to 12, characterized in that: In an operation mode for exposing at least one pixel of the n pixels to a flashing light of a second wavelength, during the exposure to the flashing light of the second wavelength, the first transfer transistor and the second transfer transistor are repeatedly switched between conduction and non-conduction in such a manner that the first transfer transistor and the second transfer transistor are not turned on at the same time. In an operation mode of exposing at least one of the n pixels to light of a first wavelength, during the exposure to the light of the first wavelength, the first transfer transistor and the second transfer transistor are maintained in a non-conducting state, and only the first transfer transistor is turned on at a specified timing.

Images