Intelligent detection method and system for hybrid integrated circuit

Abstract

The invention relates to the technical field of circuit detection management, in particular to an intelligent detection method and system for a hybrid integrated circuit. The method comprises the following steps: installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer corresponding to different ports and key parts in the hybrid integrated circuit, and carrying out preparation before detection, so as to generate a test complete hybrid integrated circuit; starting synchronous acquisition according to a preset synchronous acquisition frequency to generate an electrical parameter set, chip working temperature distribution and a circuit operation electromagnetic radiation spectrum; performing fault detection according to the electrical parameter set, the chip working temperature distribution and the circuit operation electromagnetic radiation spectrum, and generating a corresponding fault detection result; and performing fault recommendation repair on the corresponding hybrid integrated circuit, and generating a fault degree recommendation repair scheme corresponding to the hybrid integrated circuit so as to execute corresponding hybrid integrated circuit fault repair work. According to the invention, the detection result can be accurately analyzed and fed back in real time.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit detection management, and in particular to a hybrid integrated circuit intelligent detection method and system. Background Art

[0002] Hybrid integrated circuits integrate multiple processes such as semiconductor integrated circuits, thick film integrated circuits, and thin film integrated circuits. They have complex internal structures, including active devices, passive components, and multi-layer wiring interconnections. They are usually composed of different types of circuit components (such as silicon chips, ceramic substrates, inorganic materials, and organic materials). The coordinated work of their electrical and thermal properties has an important impact on the stability and efficiency of the entire system. However, traditional detection methods mainly rely on manual operation of professional detection instruments, such as oscilloscopes and multimeters, to measure circuit parameters point by point. This is not only time-consuming and labor-intensive, but also extremely susceptible to human factors. There are also problems such as internal micro-short circuits, potential thermal problems, and electromagnetic crosstalk between multi-layer interconnections, which leads to inaccurate detection results. Summary of the invention

[0003] Based on this, it is necessary for the present invention to provide a hybrid integrated circuit intelligent detection method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, a hybrid integrated circuit intelligent detection method comprises the following steps: Step S1: installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at corresponding different ports and key positions in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed testing equipment on a test fixture for pre-test preparation to generate a fully tested hybrid integrated circuit; Step S2: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate an electrical parameter set corresponding to the hybrid integrated circuit, a chip operating temperature distribution and a circuit operation electromagnetic radiation spectrum; performing electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generating a circuit electrical fault detection result; Step S3: performing thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate a circuit thermal failure fault detection result and a circuit electromagnetic interference fault detection result; Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, fault repair recommendations are made for the corresponding hybrid integrated circuit, and a recommended repair plan corresponding to the fault degree of the hybrid integrated circuit is generated to perform the corresponding hybrid integrated circuit fault repair work.

[0005] Further, step S1 includes the following steps: Step S11: performing high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structure information corresponding to the hybrid integrated circuit to clearly present circuit layouts at different levels and electronic component connection methods; Step S12: using an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain micro structural detail information corresponding to the hybrid integrated circuit, so as to capture micro solder joints and wire details of the circuit parts; Step S13: fusing the internal three-dimensional structure information and the structure micro-detail information corresponding to the hybrid integrated circuit to generate a mapping map of the internal structure of the hybrid integrated circuit; Step S14: predicting key detection points of each port part in the hybrid integrated circuit based on the internal structure mapping map of the hybrid integrated circuit, so as to predict and extract nodes on the high-frequency signal transmission path of the circuit and pins of electronic components with large power dissipation, and generate different ports and key detection points corresponding to the hybrid integrated circuit; installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key detection points corresponding to the hybrid integrated circuit; Step S15: obtaining the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit; fixing the hybrid integrated circuit after installing the detection equipment on the test fixture, and performing adaptation and installation calibration on the corresponding detection equipment on the hybrid integrated circuit based on the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit, so as to adaptively adjust the corresponding measurement range and sensitivity of the detection equipment, and generate adaptation and installation parameters of the calibration detection equipment; performing pre-detection preparation on the corresponding detection equipment on the hybrid integrated circuit based on the adaptation and installation parameters of the calibration detection equipment, so as to generate a fully tested hybrid integrated circuit.

[0006] Further, step S2 includes the following steps: Step S21: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; Step S22: performing time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate an electrical parameter set corresponding to the hybrid integrated circuit in the same timing range; Step S23: obtaining the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit; Step S24: acquiring characteristic parameters of electronic components corresponding to the hybrid integrated circuit, and performing an acceptable fluctuation range analysis on various electrical parameters corresponding to the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, so as to obtain the acceptable fluctuation range values ​​corresponding to various electrical parameters of the hybrid integrated circuit; determining the maximum and minimum threshold values ​​of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit, so as to obtain the maximum and minimum threshold values ​​corresponding to various electrical parameters of the hybrid integrated circuit; Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range, electrical fault detection is performed on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit to generate a circuit electrical fault detection result.

[0007] Furthermore, the electrical parameter set in step S21 specifically includes current, voltage, resistance and capacitance parameters corresponding to the hybrid integrated circuit.

[0008] Further, step S25 includes the following steps: Extracting the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range at the timing point, and obtaining the specific value of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific value of current, voltage, resistance and capacitance; If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is less than the minimum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, then it is detected that the hybrid integrated circuit has an open circuit fault; If the specific value of the current corresponding to the hybrid integrated circuit at each timing point is greater than the maximum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to the hybrid integrated circuit at each timing point is less than the minimum voltage threshold corresponding to the hybrid integrated circuit, then the hybrid integrated circuit is detected and judged to have a short circuit fault; If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is zero and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, it is detected that the hybrid integrated circuit has a circuit breaker fault; If the specific value of resistance corresponding to the hybrid integrated circuit at each timing point is greater than the maximum resistance threshold or less than the minimum resistance threshold, or the specific value of capacitance corresponding to the hybrid integrated circuit at each timing point is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, then the detection determines that the hybrid integrated circuit has a parameter drift fault.

[0009] Further, step S3 includes the following steps: Step S31: obtaining the size, spacing and arrangement of electronic components corresponding to the chip in the tested hybrid integrated circuit; Step S32: performing chip thermal conduction topology analysis on the tested hybrid integrated circuit based on the size, spacing and arrangement of electronic components, so as to clearly display the thermal conduction network from the heating components to the heat dissipation path, and obtain the internal thermal conduction topology network of the circuit chip; Step S33: performing a thermal stress distribution analysis on the tested hybrid integrated circuit based on the internal heat conduction topology network of the circuit chip to generate a thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit; Step S34: performing thermal failure fault detection on the corresponding tested complete hybrid integrated circuit based on the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit, so as to determine each thermal abnormality sensitive area according to the thermal stress distribution corresponding to each part of the chip, and determining whether a corresponding thermal failure phenomenon occurs according to the temperature change corresponding to each thermal abnormality sensitive area according to a preset thermal failure critical temperature threshold, so as to generate a circuit thermal failure fault detection result; Step S35: performing electromagnetic interference fault detection on the tested hybrid integrated circuit based on the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to generate a circuit electromagnetic interference fault detection result.

[0010] Further, step S35 includes the following steps: Step S351: obtaining the layout and connection mode of each electronic component and wire in the tested hybrid integrated circuit, and performing electromagnetic radiation interference impact assessment on the tested hybrid integrated circuit based on the layout and connection mode of each electronic component and wire to generate an electromagnetic radiation interference impact factor; Step S352: obtaining a normal working electromagnetic spectrum of the circuit corresponding to the hybrid integrated circuit, and performing an electromagnetic phase difference analysis on the circuit operation electromagnetic radiation spectrum based on the normal working electromagnetic spectrum of the circuit corresponding to the hybrid integrated circuit to obtain the integrated circuit operation electromagnetic radiation phase difference; Step S353: performing electromagnetic interference amplitude and frequency analysis on the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to obtain the electromagnetic interference amplitude and the electromagnetic interference frequency of the integrated circuit; Step S354: Based on the electromagnetic radiation interference influencing factor, the integrated circuit operation electromagnetic radiation phase difference, the integrated circuit electromagnetic interference amplitude and the integrated circuit electromagnetic interference frequency, the electromagnetic interference calculation formula is used to calculate the electromagnetic interference of the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to obtain the electromagnetic radiation interference value corresponding to the hybrid integrated circuit; Step S355: Compare and judge the electromagnetic radiation interference value corresponding to the hybrid integrated circuit according to the preset circuit electromagnetic interference fault threshold. If the electromagnetic radiation interference value is greater than or equal to the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has external electromagnetic source interference; if the electromagnetic radiation interference value is less than the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has electromagnetic interference generated by the internal circuit, so as to generate a circuit electromagnetic interference fault detection result.

[0011] Furthermore, the electromagnetic radiation interference calculation formula described in step S354 is specifically: ; In the formula, is the electromagnetic radiation interference value, Calculate the time interval for electromagnetic interference, is the time variable parameter, It is the total component of the corresponding frequency components in the electromagnetic radiation spectrum of the circuit operation. For circuit operation within the electromagnetic radiation spectrum The electromagnetic interference amplitude of the integrated circuit corresponding to the frequency component is For circuit operation within the electromagnetic radiation spectrum The integrated circuit electromagnetic interference frequency corresponding to the frequency component is For circuit operation within the electromagnetic radiation spectrum The electromagnetic radiation phase difference between the frequency component and the normal working electromagnetic spectrum is is the frequency component of electromagnetic radiation, For the The electromagnetic radiation attenuation factor corresponding to the frequency component is: For the The electromagnetic interference suppression constant corresponding to the frequency component is: It is the correction factor of electromagnetic radiation interference value.

[0012] Further, step S4 includes the following steps: Step S41: performing fault mode feature analysis on the corresponding hybrid integrated circuit based on the circuit electrical fault detection result, the circuit thermal failure fault detection result or the circuit electromagnetic interference fault detection result, so as to extract the abnormal current and voltage fluctuation of the corresponding electrical fault, the uneven temperature distribution of the thermal failure fault and the abnormal spectrum feature of the electromagnetic interference fault for each fault type, and clarify the relationship between different fault types and features, so as to obtain the abnormal fault mode feature corresponding to the hybrid integrated circuit; Step S42: performing a deep analysis of the fault root cause of the hybrid integrated circuit based on the abnormal characteristics of the fault mode corresponding to the hybrid integrated circuit, so as to identify clues of the fault root cause hidden under the fault phenomenon of the hybrid integrated circuit, so as to generate: a clue set of deep analysis of the circuit fault root cause; Step S43: Recommend fault repair for the hybrid integrated circuit based on the clue set of the circuit fault root cause in-depth analysis, and generate a recommended repair plan for the fault level of the hybrid integrated circuit, including electronic component replacement and circuit rewiring strategies for electrical faults, heat dissipation system optimization and electronic component derating for thermal failures, and electromagnetic interference faults. If it is caused by an external electromagnetic source, an electromagnetic shielding cover is added to effectively block external interference from entering the hybrid integrated circuit; if it is electromagnetic interference generated by an internal circuit, the circuit layout is replanned to reduce crosstalk between signals, so as to perform the corresponding hybrid integrated circuit fault repair work.

[0013] Furthermore, the present invention also provides a hybrid integrated circuit intelligent detection system for executing the hybrid integrated circuit intelligent detection method as described above, the hybrid integrated circuit intelligent detection system comprising: The circuit test preparation module is used to prepare for the test by installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at the corresponding different ports and key parts in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed test equipment on a test fixture to generate a fully tested hybrid integrated circuit; The synchronous acquisition and electrical detection module is used to start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to synchronously acquire multi-modal data of the tested complete hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; based on the electrical parameter set corresponding to the hybrid integrated circuit, the electrical fault detection of the tested complete hybrid integrated circuit is performed, so as to generate the circuit electrical fault detection result; The thermal failure and electromagnetic interference detection module is used to perform thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results; The circuit fault recommendation repair module is used to recommend fault repair for the corresponding hybrid integrated circuit based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, and generate a recommended repair plan for the fault degree corresponding to the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

[0014] Beneficial effects of the present invention: 1. Compared with the prior art, the hybrid integrated circuit intelligent detection method proposed in the present invention has the beneficial effect of laying the foundation for subsequent multimodal data acquisition by installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at key positions in the hybrid integrated circuit. The key to this process is that by accurately selecting the test instrument, detailed electrical and physical detection can be performed on different ports and key positions of the hybrid integrated circuit. Through this multi-dimensional test and detection, the working state of the hybrid integrated circuit can be comprehensively evaluated, and strong support can be provided for subsequent fault diagnosis. By fixing the detection equipment and placing the circuit on the test fixture for fixing, it can ensure that the equipment is not affected by external interference or vibration during the test process, and further improve the accuracy and reliability of the test data. Secondly, by presetting the synchronous acquisition frequency, the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer are started for synchronous data acquisition. The key to this process is the synchronous acquisition of multimodal data, including electrical parameters, chip operating temperature distribution and electromagnetic radiation spectrum, so that fault detection can be comprehensively analyzed from multiple angles, improving the accuracy of fault diagnosis. Electrical fault detection based on these data can detect electrical anomalies in the circuit in real time, such as overcurrent, short circuit or open circuit, so as to detect potential fault risks in the early stage and ensure the reliability and safety of the circuit. Then, by using the chip operating temperature distribution and electromagnetic radiation spectrum, the hybrid integrated circuit is tested for thermal failure and magnetic interference faults. The thermal failure fault detection can identify the overheating phenomenon in the circuit through the temperature data collected by the infrared thermal imager. In the operation of electronic equipment, excessive temperature is often the key factor causing circuit failure. Overheating can cause component performance degradation or even damage. In addition, electromagnetic interference fault detection can evaluate whether the electromagnetic radiation generated during circuit operation exceeds the safety range or interferes with other equipment by analyzing the electromagnetic radiation spectrum collected by the electromagnetic compatibility analyzer. The circuit design can be adjusted in time or effective shielding measures can be taken to reduce the impact of electromagnetic interference on other systems, so that the internal micro short circuit, potential thermal failure and crosstalk between multi-layer interconnections in the circuit can be detected in real time, which provides important support for ensuring the reliability of hybrid integrated circuits in extreme working environments and helps to optimize the overall performance and anti-interference ability of the circuit.Finally, by recommending fault repairs for hybrid integrated circuits based on the detection results of electrical faults, thermal failure faults, or electromagnetic interference faults, we can fully understand the types of faults and their severity in different aspects of the circuit. For example, electrical faults involve performance degradation or short circuits or open circuits of components; thermal failures are related to improper heat dissipation design or component overload; and electromagnetic interference problems are caused by poor electromagnetic shielding or grounding design. By systematically analyzing these faults, we can provide customized repair solutions for hybrid integrated circuits, including replacing damaged components, optimizing circuit design, improving heat dissipation performance, adding electromagnetic shielding layers, etc. This process not only helps to improve the stability and performance of the circuit, but also extends the service life of the circuit and prevents equipment downtime and production losses caused by faults. It can greatly improve the efficiency of fault handling while ensuring the scientificity and effectiveness of the repair solution.

[0015] 2. The hybrid integrated circuit intelligent detection system proposed in the present invention is generally composed of a circuit detection preparation module, a synchronous acquisition and electrical detection module, a thermal failure and electromagnetic interference detection module, and a circuit fault recommendation and repair module. It can implement any hybrid integrated circuit intelligent detection method described in the present invention, and is used to combine the operations between computer programs running on each module to implement the hybrid integrated circuit intelligent detection method. The internal structures of the system cooperate with each other, which can greatly reduce duplication of work and manpower investment, and can quickly and effectively provide a more accurate and efficient hybrid integrated circuit intelligent detection process, thereby simplifying the operating procedures of the hybrid integrated circuit intelligent detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments thereof made with reference to the following drawings: Figure 1 A schematic diagram of the steps of the hybrid integrated circuit intelligent detection method of the present invention; Figure 2 for Figure 1 Detailed step flow diagram of step S1; Figure 3 for Figure 1 Detailed step flow chart of step S2 in FIG. DETAILED DESCRIPTION

[0017] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0018] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0019] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0020] To achieve this, please refer to Figures 1 to 3 The present invention provides a hybrid integrated circuit intelligent detection method, the method comprising the following steps: Step S1: installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at corresponding different ports and key positions in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed testing equipment on a test fixture for pre-test preparation to generate a fully tested hybrid integrated circuit; Step S2: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate an electrical parameter set corresponding to the hybrid integrated circuit, a chip operating temperature distribution and a circuit operation electromagnetic radiation spectrum; performing electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generating a circuit electrical fault detection result; Step S3: performing thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate a circuit thermal failure fault detection result and a circuit electromagnetic interference fault detection result; Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, fault repair recommendations are made for the corresponding hybrid integrated circuit, and a recommended repair plan corresponding to the fault degree of the hybrid integrated circuit is generated to perform the corresponding hybrid integrated circuit fault repair work.

[0021] In the embodiment of the present invention, please refer to Figure 1 FIG. 1 is a schematic diagram of the steps of the hybrid integrated circuit intelligent detection method of the present invention. In this example, the hybrid integrated circuit intelligent detection method includes the following steps: Step S1: installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at corresponding different ports and key positions in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed testing equipment on a test fixture for pre-test preparation to generate a fully tested hybrid integrated circuit; In the embodiment of the present invention, by accurately selecting and installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer, it is ensured that the equipment can respectively perform comprehensive measurements on the electrical parameters, thermal parameters and electromagnetic radiation of the hybrid integrated circuit. The specific operation is to install an electrical parameter tester at different ports and key parts of the hybrid integrated circuit, such as the input and output terminals, the power amplifier and the power supply part, so as to capture electrical data such as voltage, current, resistance and capacitance; at the same time, the infrared thermal imager should be installed on the surface of the chip and the surface of the circuit board to ensure that the temperature distribution of the hybrid integrated circuit can be monitored in real time; the electromagnetic compatibility analyzer is installed around the circuit to detect the intensity and spectrum of the electromagnetic radiation. After installation, all detection instruments need to be fixed in a standard test fixture to prevent positional displacement during the test process, thereby ensuring the accuracy of the test results. The fixture should not only stabilize the position of the equipment, but also ensure good contact between it and the circuit to ensure smooth signal transmission. Through the implementation of this step, the preliminary detection preparation work of the hybrid integrated circuit is completed, ensuring the smooth progress of the subsequent multimodal data acquisition work, and finally generating a fully tested hybrid integrated circuit.

[0022] Step S2: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate an electrical parameter set corresponding to the hybrid integrated circuit, a chip operating temperature distribution and a circuit operation electromagnetic radiation spectrum; performing electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generating a circuit electrical fault detection result; In an embodiment of the present invention, the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer are started to perform synchronous data acquisition according to the preset synchronous acquisition frequency. First, after the electrical parameter tester is started, it automatically scans the key nodes of the circuit according to its acquisition frequency, including electrical parameters such as voltage, current, resistance and capacitance, and records these data to form an electrical parameter set; the infrared thermal imager starts to scan the circuit surface in real time, generates a temperature distribution map of the chip working area, and detects the hot spot area of ​​the circuit through thermal imaging technology; the electromagnetic compatibility analyzer starts to collect the electromagnetic radiation generated when the circuit is running, measures the electromagnetic radiation spectrum, and pays special attention to the generation of high-frequency noise. The three instruments work synchronously to ensure multi-dimensional coverage of the data, covering important indicators such as electrical performance, thermal performance and electromagnetic compatibility. Through this operation, the system can obtain the complete working status data of the hybrid integrated circuit in real time. At the same time, based on these multimodal data, the electrical faults are further detected, and by analyzing the electrical parameter set, the electrical faults existing in the circuit, such as open circuit, short circuit, disconnection, parameter drift overload, etc., are timely identified, and finally the circuit electrical fault detection results are generated.

[0023] Step S3: performing thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate a circuit thermal failure fault detection result and a circuit electromagnetic interference fault detection result; In an embodiment of the present invention, thermal failure and electromagnetic interference fault detection are implemented based on the previously collected temperature distribution and electromagnetic radiation spectrum information. In this step, the temperature distribution diagram recorded by the infrared thermal imager is first used to analyze the temperature rise of various areas of the circuit, especially the current-intensive areas, such as power pins, driver chips, connecting components, etc., to see if there is an abnormally high temperature phenomenon. The part with excessive temperature rise will cause thermal failure of the component or cause a circuit short circuit. Therefore, through the thermal failure detection algorithm, the part where the temperature exceeds the normal working range can be identified, thereby generating a thermal failure fault detection result. At the same time, the electromagnetic radiation spectrum data provided by the electromagnetic compatibility analyzer is used to detect whether the circuit generates too much electromagnetic interference, especially high-frequency noise. By comparing the standard electromagnetic radiation value, it can be identified whether there is an electromagnetic radiation spectrum that does not meet the specifications, and then electromagnetic interference fault detection is performed, and finally the circuit thermal failure fault detection result and the circuit electromagnetic interference fault detection result are generated.

[0024] Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, fault repair recommendations are made for the corresponding hybrid integrated circuit, and a recommended repair plan corresponding to the fault degree of the hybrid integrated circuit is generated to perform the corresponding hybrid integrated circuit fault repair work.

[0025] In an embodiment of the present invention, a corresponding fault repair scheme is automatically generated based on the previous fault detection results and the electrical fault, thermal failure fault or electromagnetic interference fault detection results. Specifically, if the electrical fault detection result shows that the circuit has an open circuit, a short circuit, a broken circuit or an overload, it is recommended to replace the relevant components or adjust the circuit design to reduce the current load; if the thermal failure fault detection result shows that some components are overheated, it is recommended to add a heat sink or improve the circuit layout to improve heat dissipation; and the electromagnetic interference fault detection result indicates that the shielding design of the circuit needs to be optimized or the operating frequency needs to be reduced. According to the severity and impact range of the fault type, a fault repair scheme is generated, and a repair priority is specified for each repair scheme to guide subsequent repair operations. The repair scheme includes not only specific repair suggestions, but also redesign of the circuit board or chip to ensure that the most effective measures are taken during the repair process, so as to ensure that the hybrid integrated circuit can resume normal operation after the repair. The core of this process is to customize the solution through comprehensive multimodal data analysis to ensure the accuracy and efficiency of the fault repair process, and finally generate a recommended repair scheme corresponding to the fault degree of the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

[0026] Further, step S1 includes the following steps: Step S11: performing high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structure information corresponding to the hybrid integrated circuit to clearly present circuit layouts at different levels and electronic component connection methods; Step S12: using an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain micro structural detail information corresponding to the hybrid integrated circuit, so as to capture micro solder joints and wire details of the circuit parts; Step S13: fusing the internal three-dimensional structure information and the structure micro-detail information corresponding to the hybrid integrated circuit to generate a mapping map of the internal structure of the hybrid integrated circuit; Step S14: predicting key detection points of each port part in the hybrid integrated circuit based on the internal structure mapping map of the hybrid integrated circuit, so as to predict and extract nodes on the high-frequency signal transmission path of the circuit and pins of electronic components with large power dissipation, and generate different ports and key detection points corresponding to the hybrid integrated circuit; installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key detection points corresponding to the hybrid integrated circuit; Step S15: obtaining the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit; fixing the hybrid integrated circuit after installing the detection equipment on the test fixture, and performing adaptation and installation calibration on the corresponding detection equipment on the hybrid integrated circuit based on the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit, so as to adaptively adjust the corresponding measurement range and sensitivity of the detection equipment, and generate adaptation and installation parameters of the calibration detection equipment; performing pre-detection preparation on the corresponding detection equipment on the hybrid integrated circuit based on the adaptation and installation parameters of the calibration detection equipment, so as to generate a fully tested hybrid integrated circuit.

[0027] As an embodiment of the present invention, refer to Figure 2 As shown, Figure 1 Detailed step flow diagram of step S1 in FIG. 1 , in this embodiment, step S1 includes the following steps: Step S11: performing high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structure information corresponding to the hybrid integrated circuit to clearly present circuit layouts at different levels and electronic component connection methods; In an embodiment of the present invention, when performing high-resolution X-ray tomography on a hybrid integrated circuit, firstly, a hybrid integrated circuit sample is placed on a sample holder of an X-ray tomography scanner to ensure that its position is fixed, and appropriate X-ray energy is selected, usually lower energy X-rays are selected to ensure that the circuit board can be effectively penetrated and detailed information can be obtained without damaging the circuit. Through X-ray scanning at multiple angles, the device will form different tomographic images according to the difference in absorption rate of rays at different angles. Based on the tomographic images, a reconstruction algorithm such as filtered back projection or iterative reconstruction algorithm is used to generate a three-dimensional structure diagram of the hybrid integrated circuit. The image shows the internal structure of each layer of the circuit board, wiring, and the position of electronic components, and can clearly present the hierarchical structure of the circuit board and the complex connection method between circuits, which is particularly helpful for identifying high-frequency signal paths and key nodes of power transmission, and finally generates internal three-dimensional structure information corresponding to the hybrid integrated circuit.

[0028] Step S12: using an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain micro structural detail information corresponding to the hybrid integrated circuit, so as to capture micro solder joints and wire details of the circuit parts; In an embodiment of the present invention, a hybrid integrated circuit sample is processed into a size suitable for microscopic observation, which usually requires cutting into thin slices or using other methods such as polishing to ensure that the sample surface is flat. The sample is placed on a sample stage of an electron microscope, the acceleration voltage and current parameters are adjusted, and a suitable scanning mode (such as a scanning electron microscope SE mode or a backscattered electron microscope BSE mode) is selected to ensure that the required high-resolution image can be obtained. During the scanning process, the electron microscope interacts with the sample surface through an electron beam to capture reflected or scattered electron signals to form an image showing solder joints and circuit connection lines. By adjusting the focal length and image enhancement algorithm, minute details of the circuit board, such as wire details, solder joint morphology, contact quality of circuit connection points, etc., can be observed. These microscopic imaging details help to reveal microscopic defects or welding problems in the circuit, and ultimately obtain microscopic structural detail information corresponding to the hybrid integrated circuit.

[0029] Step S13: fusing the internal three-dimensional structure information and the structure micro-detail information corresponding to the hybrid integrated circuit to generate a mapping map of the internal structure of the hybrid integrated circuit; In an embodiment of the present invention, a three-dimensional image generated by a high-resolution X-ray tomography is aligned with a microscopic image of an electron microscope, and an image matching algorithm, such as a feature point-based matching method, is used to ensure that the spatial positions of the two are consistent. Then, a data fusion algorithm (such as a weighted average method or a mutual information method) is used to synthesize the structural data from two different sources. The fused structural information will display the internal and surface structures of the circuit board, including multi-level details from macro to micro, and can accurately describe the position of each electronic component, wire and soldering point and their mutual relationship. This information will constitute a complete internal structure mapping map of the hybrid integrated circuit, which can help subsequent circuit performance analysis and defect location, and finally generate an internal structure mapping map of the hybrid integrated circuit.

[0030] Step S14: predicting key detection points of each port part in the hybrid integrated circuit based on the internal structure mapping map of the hybrid integrated circuit, so as to predict and extract nodes on the high-frequency signal transmission path of the circuit and pins of electronic components with large power dissipation, and generate different ports and key detection points corresponding to the hybrid integrated circuit; installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key detection points corresponding to the hybrid integrated circuit; In an embodiment of the present invention, by analyzing the key areas in the circuit, especially the high-frequency signal transmission path and the component pins with large power dissipation according to the generated hybrid integrated circuit internal structure mapping map, in this step, first identify the part of the circuit diagram related to high-frequency signal transmission, usually these signal paths are closely related to the layout of the circuit, signal integrity and the flow of current, use simulation analysis tools (such as electromagnetic field simulation software) to predict the signal transmission path, and determine the possible current density concentration area, especially the wire through which the current passes or the electronic component pins with large resistance, then, through the data extracted from the map, determine the key detection points in the high-frequency signal transmission path and the area with large power, so as to generate different ports and key parts detection points corresponding to the hybrid integrated circuit, in order to further improve the detection accuracy, it is also possible to predict the temperature rise area on the circuit through thermal simulation software, assist in locating the electronic components with more serious heat generation, and install electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key parts detection points corresponding to the hybrid integrated circuit.

[0031] Step S15: obtaining the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit; fixing the hybrid integrated circuit after installing the detection equipment on the test fixture, and performing adaptation and installation calibration on the corresponding detection equipment on the hybrid integrated circuit based on the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit, so as to adaptively adjust the corresponding measurement range and sensitivity of the detection equipment, and generate adaptation and installation parameters of the calibration detection equipment; performing pre-detection preparation on the corresponding detection equipment on the hybrid integrated circuit based on the adaptation and installation parameters of the calibration detection equipment, so as to generate a fully tested hybrid integrated circuit.

[0032] In an embodiment of the present invention, after completing the prediction of key detection points of the hybrid integrated circuit, the detection equipment is adapted and installed. First, the physical size and surface material characteristics of the hybrid integrated circuit are determined, including the size, shape, surface coating, material, etc. of the circuit board. Then, according to these physical information, the previously installed detection equipment, such as electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer, is adapted and calibrated. For example, by adaptively adjusting the measurement range and sensitivity of the equipment, it is ensured that they can accurately respond to the electrical signals and thermal characteristics of the circuit. When installing the equipment, a precision fixture is used to stabilize the hybrid integrated circuit on the test bench, and the installation angle and contact method of the equipment are adjusted according to the specific form of the circuit to ensure that the data during the test process is accurate and reliable. Through these calibration steps, the corresponding detection equipment adaptation and installation parameters are generated. At the same time, after completing the equipment adaptation and calibration, the final pre-test preparation is carried out. At this time, the HIC has been fixed on the test fixture, and the interfaces of all test equipment and circuits have been accurately connected. First, check the working status of all instruments to ensure that the electrical parameter tester can accurately read the current and voltage values ​​of the circuit, the infrared thermal imager can normally obtain the temperature distribution on the circuit surface, and the electromagnetic compatibility analyzer can normally monitor electromagnetic radiation and interference. On this basis, set the test parameters (such as voltage range, temperature range, frequency response, etc.) through the software interface to put all test equipment in the best state, so as to perform high-precision measurements, generate corresponding test reports, record equipment status, test results and calibration parameters, and finally generate a fully tested hybrid integrated circuit.

[0033] Further, step S2 includes the following steps: Step S21: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; Step S22: performing time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate an electrical parameter set corresponding to the hybrid integrated circuit in the same timing range; Step S23: obtaining the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit; Step S24: acquiring characteristic parameters of electronic components corresponding to the hybrid integrated circuit, and performing an acceptable fluctuation range analysis on various electrical parameters corresponding to the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, so as to obtain the acceptable fluctuation range values ​​corresponding to various electrical parameters of the hybrid integrated circuit; determining the maximum and minimum threshold values ​​of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit, so as to obtain the maximum and minimum threshold values ​​corresponding to various electrical parameters of the hybrid integrated circuit; Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range, electrical fault detection is performed on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit to generate a circuit electrical fault detection result.

[0034] As an embodiment of the present invention, refer to Figure 3 As shown, Figure 1 Detailed step flow diagram of step S2 in FIG. 1 , in this embodiment, step S2 includes the following steps: Step S21: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; In an embodiment of the present invention, an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer are set according to a preset synchronous acquisition frequency. These devices are set to start collecting data at the same time interval. The electrical parameter tester is responsible for measuring the electrical parameters of the hybrid integrated circuit, such as current, voltage, resistance and capacitance; the infrared thermal imager detects the temperature distribution of the chip through infrared radiation, records the thermal effects of each component, and forms a temperature map; the electromagnetic compatibility analyzer records the electromagnetic interference and its frequency characteristics generated by the circuit when it is working by capturing the electromagnetic radiation spectrum. The synchronous acquisition process needs to ensure that the timestamps of all devices are accurately aligned to ensure that reasonable fusion and analysis can be performed during subsequent data processing, and finally generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution, and the circuit operation electromagnetic radiation spectrum. Step S22: performing time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate an electrical parameter set corresponding to the hybrid integrated circuit in the same timing range; In an embodiment of the present invention, time synchronization processing is performed on a previously collected electrical parameter set. The specific operation is to use a high-precision clock source to calibrate the time data of different test instruments to ensure that the current, voltage, resistance, capacitance and other collected electrical data can be compared and analyzed at the same timing. Through time synchronization, data deviations caused by acquisition delays between different devices can be eliminated. The synchronization process uses a dedicated synchronization processing algorithm to interpolate and align according to the timestamps of each data to ensure that all electrical parameters are completely consistent on the time axis. At this time, the processed electrical parameter set represents the electrical state of the hybrid integrated circuit at the same time, and finally generates the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range.

[0035] Step S23: obtaining the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit; In an embodiment of the present invention, the rated current, rated voltage, calibrated resistance and calibrated capacitance of the hybrid integrated circuit are extracted from an electrical parameter tester and other measuring equipment. This operation first requires obtaining these basic electrical parameters by consulting circuit design documents or measuring under standard conditions. These parameters are usually specified in the technical specification of the hybrid integrated circuit, or confirmed by a calibration tool provided by the equipment manufacturer. The rated current and rated voltage are usually basic electrical indicators for the normal operation of the circuit, while the calibrated resistance and calibrated capacitance are usually obtained by laboratory testing or design calibration. These parameters provide a reference for subsequent fluctuation range analysis to ensure that the circuit operates within a preset safety range, and finally the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit are obtained.

[0036] Step S24: acquiring characteristic parameters of electronic components corresponding to the hybrid integrated circuit, and performing an acceptable fluctuation range analysis on various electrical parameters corresponding to the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, so as to obtain the acceptable fluctuation range values ​​corresponding to various electrical parameters of the hybrid integrated circuit; determining the maximum and minimum threshold values ​​of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit, so as to obtain the maximum and minimum threshold values ​​corresponding to various electrical parameters of the hybrid integrated circuit; In an embodiment of the present invention, characteristic parameters of each electronic component in a hybrid integrated circuit are obtained, and these characteristic parameters include the operating voltage, current load capacity, frequency response, temperature sensitivity, etc. of the component, which are usually provided by the manufacturer of the component. On this basis, the acceptable fluctuation range of the electrical parameters in the hybrid integrated circuit is analyzed, and the circuit simulation software is used to simulate under various working conditions. In combination with the tolerance requirements during circuit design, the acceptable fluctuation range of each electrical parameter is obtained, including the acceptable fluctuation range corresponding to the current, voltage, resistance and capacitance. Through this fluctuation range analysis, the variation limit of each electrical parameter under normal working conditions can be determined. Then, based on the rated current, rated voltage, calibrated resistance and calibrated capacitance, the fluctuation range of these electrical parameters is further limited, and the maximum threshold value (that is, the sum of each calibrated parameter and the fluctuation range) and the minimum threshold value (that is, the difference between each calibrated parameter and the fluctuation range) of each parameter are calculated. These threshold values ​​will be used as the standard for subsequent fault detection to ensure that the electrical parameters will not deviate from the predetermined range and avoid the occurrence of circuit faults, and finally the maximum and minimum threshold values ​​corresponding to each electrical parameter of the hybrid integrated circuit are obtained.

[0037] Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range, electrical fault detection is performed on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit to generate a circuit electrical fault detection result.

[0038] In an embodiment of the present invention, fault detection is performed on each electrical parameter according to the calculated maximum and minimum thresholds based on the electrical parameter set that has been previously processed by time synchronization. The specific method is to compare each parameter value with its corresponding maximum and minimum thresholds to detect whether it exceeds a preset range. If the value of an electrical parameter exceeds its maximum or minimum threshold, it is determined to be an electrical fault. The electrical fault detection can be automatically completed through a fault detection algorithm. The algorithm will generate an alarm signal according to the set threshold to indicate the specific fault type (including open circuit, short circuit, disconnection and parameter drift fault). This process can timely discover electrical anomalies or temperature, electromagnetic and other aspects that affect circuit functions by continuously tracking the electrical parameters monitored in real time, and finally generate circuit electrical fault detection results.

[0039] Further, step S25 includes the following steps: Extracting the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range at the timing point, and obtaining the specific value of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific value of current, voltage, resistance and capacitance; In an embodiment of the present invention, a timing analysis is performed on a hybrid integrated circuit by designing a special timing analysis tool. The timing analysis tool needs to have the function of extracting electrical parameters such as current, voltage, resistance and capacitance of the circuit at different time points. The specific operation process includes first setting the working timing range of the circuit, that is, defining the range of each time point when the circuit is running, and then using timing simulation software (such as SPICE simulation tool) to simulate each timing point of the circuit and record various electrical parameters of the circuit, mainly including current, voltage, resistance and capacitance values. For the measurement of current and voltage, the circuit simulation tool will record the current and voltage changes of each node at each timing point; for resistance and capacitance, the simulation tool will calculate the changes of resistance and capacitance based on the design parameters and physical characteristics of the circuit, obtain a mapping relationship between a set of timing points and corresponding electrical parameter values, and finally obtain the specific values ​​of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific values ​​of current, voltage, resistance and capacitance.

[0040] Preferably, if the specific value of the current corresponding to the hybrid integrated circuit at each timing point is less than the minimum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to the hybrid integrated circuit at each timing point is normal, then it is detected and determined that the hybrid integrated circuit has an open circuit fault; In an embodiment of the present invention, the relationship between current and voltage is checked based on the electrical parameters of the timing points previously obtained. In specific operations, the current value of each timing point is first compared. If the current value of the timing point is lower than the minimum current threshold set by the circuit (for example, lower than a specific current value), and at the same time it is confirmed that the voltage value of the timing point is normal (the voltage value is within the set normal range), then it is determined that there is an open circuit fault based on this condition. An open circuit fault is usually manifested as the inability of current to flow, while the voltage value is not significantly affected, which is consistent with the characteristics of circuit interruption in the open circuit situation. When the above conditions are met, an open circuit fault is immediately reported in the circuit, and further positioning and analysis are performed.

[0041] Preferably, if the specific value of the current corresponding to the hybrid integrated circuit at each timing point is greater than the maximum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to the hybrid integrated circuit at each timing point is less than the minimum voltage threshold corresponding to the hybrid integrated circuit, then it is detected and judged that the hybrid integrated circuit has a short circuit fault; In an embodiment of the present invention, by combining previously determined timing electrical parameter data, short-circuit faults are detected by setting maximum thresholds of current and voltage. The specific operation is: first, the current and voltage values ​​of each timing point are extracted. If the current value at a certain timing point exceeds the preset maximum current threshold (for example, when the current exceeds a certain current value), and the voltage value is lower than the preset minimum voltage threshold (for example, the voltage value is too low), it can be determined that a short-circuit fault exists at the timing point. A short-circuit fault usually causes excessive current and reduced voltage because the current flows directly through the short-circuit path, causing an overcurrent phenomenon. Through this method, the system can detect short-circuit faults in real time and make further positioning processing.

[0042] Preferably, if the specific value of the current corresponding to each timing point of the hybrid integrated circuit is zero and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, it is detected and determined that the hybrid integrated circuit has a circuit breaker fault; In an embodiment of the present invention, by analyzing the states of current and voltage based on previously obtained electrical parameters, if at a certain timing point, the current value is zero (usually meaning that no current is flowing in the circuit), and the voltage value at that timing point is within a normal range (for example, the voltage value is within a set operating voltage range), then it can be determined that a circuit breaker fault has occurred at that timing point. A circuit breaker fault usually manifests itself as obstruction of current flow, while the voltage value may not necessarily change significantly. Therefore, by detecting that the current is zero and the voltage is normal, it can be determined that a circuit breaker problem exists in a certain part of the circuit, and the system will then issue an alarm and perform further fault location.

[0043] Preferably, if the specific value of resistance corresponding to the hybrid integrated circuit at each timing point is greater than the maximum resistance threshold or less than the minimum resistance threshold, or the specific value of capacitance corresponding to the hybrid integrated circuit at each timing point is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, then it is detected and determined that the hybrid integrated circuit has a parameter drift fault.

[0044] In an embodiment of the present invention, the resistance and capacitance values ​​are monitored based on the previously extracted electrical parameter data. The operation process includes comparing the resistance and capacitance values ​​at each timing point to check whether they exceed the set maximum or minimum thresholds. If the resistance value at a certain timing point in the circuit is greater than the set maximum resistance threshold, or less than the minimum resistance threshold, or the capacitance value at the timing point is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, it can be determined that the circuit has a parameter drift fault. Parameter drift is usually caused by changes in resistance or capacitance due to aging of components in the circuit or environmental changes (such as temperature fluctuations), which affects the normal operation of the circuit. Through this fault detection method, parameter drift problems in the circuit can be discovered in a timely manner, and engineers can be reminded to conduct further analysis and repairs.

[0045] Further, step S3 includes the following steps: Step S31: obtaining the size, spacing and arrangement of electronic components corresponding to the chip in the tested hybrid integrated circuit; In an embodiment of the present invention, a fully tested hybrid integrated circuit is scanned by using a high-resolution scanning electron microscope (SEM) to accurately obtain the size information of each electronic component in the chip, and by comparing with the circuit design file, the size data of each electronic component in the circuit is extracted, especially the key components such as resistors, capacitors, transistors, etc., and then the circuit layout is digitally modeled using CAD software, and the spacing and arrangement of each component are accurately measured through the model. For complex multi-layer circuits, dedicated 3D modeling software (such as ANSYS or SolidWorks) is used to perform three-dimensional modeling on them, and the inter-layer distance and the relative position relationship of the components are extracted, and finally the corresponding electronic component size, spacing and arrangement are obtained.

[0046] Step S32: performing chip thermal conduction topology analysis on the tested hybrid integrated circuit based on the size, spacing and arrangement of electronic components, so as to clearly display the thermal conduction network from the heating components to the heat dissipation path, and obtain the internal thermal conduction topology network of the circuit chip; In an embodiment of the present invention, a heat conduction model of a circuit chip is constructed by utilizing previously obtained data on the size, spacing, and arrangement of electronic components. This model needs to consider the thermal conductivity of the material, the shape of the heat dissipation channel, and the position of the heating element. On this basis, computational fluid dynamics (CFD) software (such as ANSYS Fluent or COMSOL Multiphysics) is used to perform heat conduction topological analysis. The software calculates the heat source distribution of each heating element in the chip, analyzes the heat transfer path between it and other elements, and generates a heat conduction network diagram inside the circuit chip. Through simulation, it can clearly display the path of heat transfer from the heating element to the heat dissipation device, determine potential areas of poor heat dissipation, and further optimize the circuit design based on the results of the heat conduction analysis to ensure the temperature control and stability of the circuit during operation, and finally obtain the internal heat conduction topological network of the circuit chip.

[0047] Step S33: performing a thermal stress distribution analysis on the tested hybrid integrated circuit based on the internal heat conduction topology network of the circuit chip to generate a thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit; In an embodiment of the present invention, by relying on the previously obtained circuit chip thermal conduction topological network, firstly, thermal stress analysis is performed on each component inside the chip, and the thermal conduction network is simulated by using a finite element analysis (FEA) method (such as ANSYS Mechanical or ABAQUS). The analysis takes into account the difference in thermal expansion coefficients of different materials in the chip, the stress effect of temperature gradient on the material, and the geometric shape of the internal structure. By analyzing the thermal stress distribution, a thermal stress distribution field diagram of the circuit chip is generated, showing the thermal stress changes of each part caused by temperature changes. Based on this distribution field, the areas inside the chip that are most susceptible to thermal stress and the possible thermal failure risk areas can be determined, and finally a circuit chip thermal stress distribution field corresponding to the hybrid integrated circuit is generated.

[0048] Step S34: performing thermal failure fault detection on the corresponding tested complete hybrid integrated circuit based on the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit, so as to determine each thermal abnormality sensitive area according to the thermal stress distribution corresponding to each part of the chip, and determining whether a corresponding thermal failure phenomenon occurs according to the temperature change corresponding to each thermal abnormality sensitive area according to a preset thermal failure critical temperature threshold, so as to generate a circuit thermal failure fault detection result; In an embodiment of the present invention, thermal failure fault detection is performed on a hybrid integrated circuit based on a previously generated circuit chip thermal stress distribution field. By analyzing the thermal stress distribution of different regions inside the chip, a thermal failure model (such as a thermal cycle fatigue model, a thermal expansion failure model, etc.) is used, combined with a thermal failure critical temperature threshold of the chip design, to determine which regions have thermal failures due to excessive thermal stress. For each region where a failure occurs, a thermal simulation analysis tool is used to further calculate its temperature change, and the temperature is compared with a preset thermal failure critical temperature to determine whether a thermal failure phenomenon exists. If a thermal failure occurs, the region is marked as a fault region, and a corresponding thermal failure fault detection result is generated, and finally a circuit thermal failure fault detection result is generated.

[0049] Step S35: performing electromagnetic interference fault detection on the tested hybrid integrated circuit based on the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to generate a circuit electromagnetic interference fault detection result.

[0050] In an embodiment of the present invention, an electromagnetic radiation spectrum of a hybrid integrated circuit is analyzed in detail by electromagnetic simulation software (such as CST Studio or HFSS). The process includes measuring the electromagnetic radiation spectrum of the circuit under different working conditions, identifying the corresponding electromagnetic interference source, and detecting whether there is abnormal electromagnetic noise or interference signal in a specific frequency band of the circuit by analyzing the radiation spectrum of the circuit. After the electromagnetic interference phenomenon is detected, the circuit is improved by electromagnetic shielding, filtering design and other methods, and an electromagnetic interference fault detection report is generated based on the simulation results, which clearly points out the source of the electromagnetic interference fault and its impact on the circuit performance, and finally generates the circuit electromagnetic interference fault detection result.

[0051] Further, step S35 includes the following steps: Step S351: obtaining the layout and connection mode of each electronic component and wire in the tested hybrid integrated circuit, and performing electromagnetic radiation interference impact assessment on the tested hybrid integrated circuit based on the layout and connection mode of each electronic component and wire to generate an electromagnetic radiation interference impact factor; In an embodiment of the present invention, by obtaining the layout and connection mode between the electronic components and wires of the hybrid integrated circuit, this process adopts the layout diagram in the circuit design file (such as PCB design diagram or circuit diagram), and identifies and classifies the electronic components therein, such as capacitors, resistors, transistors, etc., one by one, and marks the electrical connection between each component and other components. Subsequently, electromagnetic interference (EMI) simulation is performed on the circuit layout using an electromagnetic field simulation tool (such as ANSYS HFSS or COMSOL Multiphysics). Through these tools, the coupling effect between the wires, the current flow, and the electromagnetic wave propagation between different components can be analyzed, and then the electromagnetic radiation interference influence factor is generated. The factor quantifies the influence of each component and wire layout in the circuit on the electromagnetic radiation. It should be noted that all connection modes and component layouts must be accurately reproduced in the simulation model to ensure the accuracy of the electromagnetic impact assessment, and finally generate the electromagnetic radiation interference influence factor.

[0052] Step S352: obtaining a normal working electromagnetic spectrum of the circuit corresponding to the hybrid integrated circuit, and performing an electromagnetic phase difference analysis on the circuit operation electromagnetic radiation spectrum based on the normal working electromagnetic spectrum of the circuit corresponding to the hybrid integrated circuit to obtain the integrated circuit operation electromagnetic radiation phase difference; In an embodiment of the present invention, the normal working electromagnetic spectrum of the hybrid integrated circuit is obtained. This spectrum reflects the electromagnetic radiation characteristics of the circuit under normal working conditions, including the radiation intensity and waveform of each frequency band. The electromagnetic radiation signal generated when the circuit is running is measured by using a spectrum analyzer (such as Keysight N9030A) to obtain its spectrum data. Then, based on the circuit working spectrum, the phase difference of the signals in different frequency bands is calculated using a phase difference analysis algorithm (such as Fourier transform). The change in phase difference reflects the electromagnetic wave interference of the circuit under different working conditions. By comparing the phase differences at different time points or in different circuit conditions, the electromagnetic radiation phase difference of the integrated circuit during normal working conditions is obtained, which helps to identify potential electromagnetic interference sources and provide data support for subsequent electromagnetic interference analysis, and finally the electromagnetic radiation phase difference of the integrated circuit is obtained.

[0053] Step S353: performing electromagnetic interference amplitude and frequency analysis on the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to obtain the electromagnetic interference amplitude and the electromagnetic interference frequency of the integrated circuit; In an embodiment of the present invention, the electromagnetic radiation spectrum of the hybrid integrated circuit is further analyzed to obtain the amplitude and frequency of the electromagnetic interference, and the electromagnetic radiation spectrum of the circuit is scanned by using a high-precision spectrum analyzer to record the radiation intensity of each frequency band during the operation of the circuit. The spectrum analyzer can accurately measure the radiation power of each frequency point, so as to obtain the interference amplitude of each frequency band. By statistically analyzing these data, the frequency segment of high-amplitude radiation can be identified, and then the frequency and amplitude characteristics of the electromagnetic interference can be inferred. During the analysis process, special attention should be paid to the distinction between noise signals and normal signals to ensure that only real electromagnetic interference signals are processed and are not misjudged as normal working signals, and finally the electromagnetic interference amplitude of the integrated circuit and the electromagnetic interference frequency of the integrated circuit are obtained.

[0054] Step S354: Based on the electromagnetic radiation interference influencing factor, the integrated circuit operation electromagnetic radiation phase difference, the integrated circuit electromagnetic interference amplitude and the integrated circuit electromagnetic interference frequency, the electromagnetic interference calculation formula is used to calculate the electromagnetic interference of the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to obtain the electromagnetic radiation interference value corresponding to the hybrid integrated circuit; In the embodiment of the present invention, a suitable electromagnetic radiation interference calculation formula is formed by combining the total component of the corresponding frequency component in the circuit operation electromagnetic radiation spectrum, the integrated circuit electromagnetic interference amplitude corresponding to the frequency component component, the integrated circuit electromagnetic interference frequency, the electromagnetic radiation phase difference between the normal working electromagnetic spectrum, the electromagnetic radiation frequency component, the electromagnetic radiation attenuation factor, the electromagnetic interference suppression constant and related parameters to calculate the electromagnetic interference of the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit, so as to calculate the electromagnetic wave propagation and interference by combining the structural features such as the wires, power supply, and grounding in the circuit, and use electromagnetic simulation software (such as CST Studio) to perform more detailed electromagnetic field simulation on the circuit, accurately calculate the interference value of each frequency band, and finally obtain the electromagnetic radiation interference value corresponding to the hybrid integrated circuit.

[0055] Step S355: Compare and judge the electromagnetic radiation interference value corresponding to the hybrid integrated circuit according to the preset circuit electromagnetic interference fault threshold. If the electromagnetic radiation interference value is greater than or equal to the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has external electromagnetic source interference; if the electromagnetic radiation interference value is less than the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has electromagnetic interference generated by the internal circuit, so as to generate a circuit electromagnetic interference fault detection result.

[0056] In an embodiment of the present invention, by comparing the obtained electromagnetic radiation interference value with a preset electromagnetic interference fault threshold, it is determined whether the hybrid integrated circuit is interfered by an external electromagnetic source. First, the electromagnetic interference fault threshold is set, and the threshold can be determined by historical fault data or electromagnetic compatibility standards (such as IEC 61000). If the calculated electromagnetic radiation interference value is greater than or equal to the threshold, it means that the circuit is affected by an external electromagnetic source and there is a risk of external interference. If the electromagnetic radiation interference value is lower than the threshold, it means that the interference comes from inside the circuit. Through this step, the source type of interference can be accurately determined, and finally a circuit electromagnetic interference fault detection result is generated.

[0057] Furthermore, the electromagnetic radiation interference calculation formula described in step S354 is specifically: ; In the formula, is the electromagnetic radiation interference value, Calculate the time interval for electromagnetic interference, is the time variable parameter, It is the total component of the corresponding frequency components in the electromagnetic radiation spectrum of the circuit operation. For circuit operation within the electromagnetic radiation spectrum The electromagnetic interference amplitude of the integrated circuit corresponding to the frequency component is For circuit operation within the electromagnetic radiation spectrum The integrated circuit electromagnetic interference frequency corresponding to the frequency component is For circuit operation within the electromagnetic radiation spectrum The electromagnetic radiation phase difference between the frequency component and the normal working electromagnetic spectrum is is the frequency component of electromagnetic radiation, For the The electromagnetic radiation attenuation factor corresponding to the frequency component is: For the The electromagnetic interference suppression constant corresponding to the frequency component is: It is the correction factor of electromagnetic radiation interference value.

[0058] The present invention obtains an electromagnetic radiation interference calculation formula by using a specific mathematical model and verifying it, which is used to calculate the electromagnetic interference of the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit. The electromagnetic radiation interference calculation formula models each frequency component in the circuit operation electromagnetic radiation spectrum, so that the calculation of electromagnetic interference is not limited to a single frequency, but covers multiple frequency components. The contribution of each frequency component to the electromagnetic radiation interference is evaluated separately, which can capture complex electromagnetic interference phenomena in more detail. By introducing the electromagnetic radiation phase difference, the formula can accurately reflect the relative time delay or displacement between different frequency components, which helps to simulate the interference superposition effect caused by phase differences in actual circuits. In the formula, The frequency attenuation factor is introduced, which represents the attenuation effect of the signal as the frequency of electromagnetic radiation changes. This calculation method can reflect the attenuation phenomenon that may occur in high-frequency signals in actual circuits and help to more accurately evaluate the contribution of high-frequency parts to electromagnetic interference. Suppression term, the formula further considers the suppression effect of electromagnetic interference, especially in the high-frequency part, the circuit usually suppresses the signal of a specific frequency (such as the effect of a filter), which can improve the calculation accuracy of high-frequency noise or interference. It also combines multiple circuits and electromagnetic parameters (such as electromagnetic radiation phase difference, amplitude, frequency, etc.) for calculation, which can fully simulate the electromagnetic environment during the operation of the circuit. This comprehensive consideration of the circuit's working state, phase difference, electromagnetic spectrum and other multi-dimensional factors helps to more comprehensively evaluate the impact of electromagnetic interference on circuit performance. Secondly, the formula involves integral calculation. Through time integration, the formula considers the dynamic process of electromagnetic interference changing with time, which can more realistically simulate the accumulation effect of electromagnetic interference in the circuit changing with time. The formula finally provides a specific electromagnetic radiation interference value, which can be used to compare with the preset electromagnetic interference fault threshold, so as to realize the electromagnetic interference fault detection of hybrid integrated circuits. This quantitative evaluation can effectively help engineers determine whether the circuit is subject to electromagnetic interference and distinguish whether the interference source is an internal circuit fault or an external electromagnetic source interference. In summary, the formula fully considers the electromagnetic radiation interference value , electromagnetic interference calculation time interval , time variable parameter , the total component of the corresponding frequency component in the electromagnetic radiation spectrum of the circuit operation , the circuit operates within the electromagnetic radiation spectrum The electromagnetic interference amplitude of the integrated circuit corresponding to the frequency component , the circuit operates within the electromagnetic radiation spectrum The frequency component of the integrated circuit electromagnetic interference frequency , the circuit operates within the electromagnetic radiation spectrum The electromagnetic radiation phase difference between the frequency component and the normal working electromagnetic spectrum , the frequency component of electromagnetic radiation , No. The electromagnetic radiation attenuation factor corresponding to the frequency component , No. The electromagnetic interference suppression constant corresponding to the frequency component , correction factor for electromagnetic radiation interference value , according to the electromagnetic radiation interference value The mutual correlation between the above parameters constitutes a functional relationship: ; This formula can realize the electromagnetic interference calculation process of the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit. At the same time, the correction coefficient of the electromagnetic radiation interference value is used. The introduction of can be adjusted according to the errors that occur in the calculation process, thereby improving the accuracy and applicability of the electromagnetic radiation interference calculation formula.

[0059] Further, step S4 includes the following steps: Step S41: performing fault mode feature analysis on the corresponding hybrid integrated circuit based on the circuit electrical fault detection result, the circuit thermal failure fault detection result or the circuit electromagnetic interference fault detection result, so as to extract the abnormal current and voltage fluctuation of the corresponding electrical fault, the uneven temperature distribution of the thermal failure fault and the abnormal spectrum feature of the electromagnetic interference fault for each fault type, and clarify the relationship between different fault types and features, so as to obtain the abnormal fault mode feature corresponding to the hybrid integrated circuit; In an embodiment of the present invention, a hybrid integrated circuit is analyzed for a fault mode feature through a circuit electrical fault detection result, a circuit thermal failure fault detection result, or a circuit electromagnetic interference fault detection result. The specific operation includes collecting current and voltage signals through current and voltage sensors installed in the circuit, and using an oscilloscope or a data acquisition device to monitor the fluctuation of these signals in real time. In the electrical fault analysis, the abnormal fluctuation of the monitored current and voltage signals will be used as an electrical fault feature, which is manifested as a sudden change or a continuous abnormal waveform of the current and voltage. For a thermal failure fault, a temperature distribution map of the hybrid integrated circuit is obtained through a thermal imager, and the distribution of the temperature abnormality area is analyzed to identify the temperature uneven area, and then determine the potential thermal failure fault. For an electromagnetic interference fault, a spectrum analyzer is used to perform a spectrum scan on the signal generated in the circuit to identify the abnormal peak or electromagnetic noise in the spectrum. These spectrum features can be used to diagnose the electromagnetic interference source. All analysis results will be mapped to the corresponding fault mode, and matching analysis will be performed on different types of fault features, so as to identify the typical abnormal features of each fault type. According to these features, the corresponding relationship between the electrical fault, the thermal failure fault, and the electromagnetic interference fault can be clearly defined, and finally the fault mode abnormal features corresponding to the hybrid integrated circuit are obtained.

[0060] Step S42: performing a deep analysis of the fault root cause of the hybrid integrated circuit based on the abnormal characteristics of the fault mode corresponding to the hybrid integrated circuit, so as to identify clues of the fault root cause hidden under the fault phenomenon of the hybrid integrated circuit, so as to generate: a clue set of deep analysis of the circuit fault root cause; In an embodiment of the present invention, the previously extracted abnormal characteristics of the fault mode are deeply analyzed to identify the potential root cause hidden under the fault appearance. In the specific operation process, firstly, based on the data such as current, voltage, temperature and spectrum, professional fault diagnosis software is used to perform multi-dimensional data fusion and processing to classify and identify the fault mode. Then, by further analyzing the current and voltage fluctuation characteristics and circuit component layout, connection relationship, etc. shown by the electrical fault, it is inferred that the root cause of the fault is due to the aging or damage of a certain component, or the circuit design defect; in the thermal failure fault, the core component in the overheating area is found through the temperature distribution map analysis, and it is further inferred that it is due to the heat accumulation caused by the poor design of the heat dissipation system or the excessive load of the component; and the root cause of the electromagnetic interference fault is to find out the source of the abnormal interference signal through spectrum analysis, and combined with the circuit design, find out the corresponding electromagnetic interference source, whether it is caused by external environmental factors, or the internal wiring problem of the circuit, and generate a deep analysis clue set of the fault root cause containing all the clues of the fault root cause according to the analysis results. The set contains detailed possible fault points and inferred roots, and finally generates: the circuit fault root cause deep analysis clue set.

[0061] Step S43: Recommend fault repair for the hybrid integrated circuit based on the clue set of the circuit fault root cause in-depth analysis, and generate a recommended repair plan for the fault level of the hybrid integrated circuit, including electronic component replacement and circuit rewiring strategies for electrical faults, heat dissipation system optimization and electronic component derating for thermal failures, and electromagnetic interference faults. If it is caused by an external electromagnetic source, an electromagnetic shielding cover is added to effectively block external interference from entering the hybrid integrated circuit; if it is electromagnetic interference generated by an internal circuit, the circuit layout is replanned to reduce crosstalk between signals, so as to perform the corresponding hybrid integrated circuit fault repair work.

[0062] In the embodiment of the present invention, by deeply analyzing the clue set based on the circuit fault root cause, the recommended repair plan for the hybrid integrated circuit fault is determined. For electrical faults, first, according to the specific situation of abnormal current and voltage fluctuations, the electronic components that need to be replaced are determined, such as replacing aging or damaged resistors, capacitors and other components, and rewiring according to circuit design requirements to ensure the stability and reliability of the circuit; for thermal failures, after analyzing the temperature distribution map, if it is found that the temperature in some areas is too high, the heat dissipation system in the circuit is optimized for repair, such as adding heat sinks or improving the layout of the heat sink to reduce the temperature of key components. In addition, the electronic components can be reduced according to the actual temperature tolerance. Extra use, that is, choose components that are more suitable for high temperature environment; for electromagnetic interference failure, if the external electromagnetic source is the interference source, the external interference signal is isolated by adding an electromagnetic shielding cover or improving the electromagnetic compatibility of the external environment. If the electromagnetic interference is caused by internal design defects of the circuit, it is necessary to re-plan the circuit layout, especially in the transmission path of high-frequency signals, optimize the routing layout to reduce crosstalk between signals, or add electromagnetic isolators to eliminate unnecessary interference. The repair plan will combine the characteristics of different fault types to formulate a targeted and efficient repair strategy to ensure that the hybrid integrated circuit can be restored to the best working state, and finally perform the corresponding hybrid integrated circuit fault repair work.

[0063] Furthermore, the present invention also provides a hybrid integrated circuit intelligent detection system for executing the hybrid integrated circuit intelligent detection method as described above, the hybrid integrated circuit intelligent detection system comprising: The circuit test preparation module is used to prepare for the test by installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at the corresponding different ports and key parts in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed test equipment on a test fixture to generate a fully tested hybrid integrated circuit; The synchronous acquisition and electrical detection module is used to start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to synchronously acquire multi-modal data of the tested complete hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; based on the electrical parameter set corresponding to the hybrid integrated circuit, the electrical fault detection of the tested complete hybrid integrated circuit is performed, so as to generate the circuit electrical fault detection result; The thermal failure and electromagnetic interference detection module is used to perform thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results; The circuit fault recommendation repair module is used to recommend fault repair for the corresponding hybrid integrated circuit based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, and generate a recommended repair plan for the fault degree corresponding to the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

[0064] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0065] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A hybrid integrated circuit intelligent detection method, characterized in that: The following steps are involved: Step S1: installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at corresponding different ports and key positions in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed testing equipment on a test fixture for pre-test preparation to generate a fully tested hybrid integrated circuit; Step S2: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate an electrical parameter set corresponding to the hybrid integrated circuit, a chip operating temperature distribution and a circuit operation electromagnetic radiation spectrum; performing electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generating a circuit electrical fault detection result; Step S3: performing thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate a circuit thermal failure fault detection result and a circuit electromagnetic interference fault detection result; Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, fault repair recommendations are made for the corresponding hybrid integrated circuit, and a recommended repair plan corresponding to the fault degree of the hybrid integrated circuit is generated to perform the corresponding hybrid integrated circuit fault repair work.

2. The hybrid integrated circuit intelligent detection method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: performing high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structure information corresponding to the hybrid integrated circuit to clearly present circuit layouts at different levels and electronic component connection methods; Step S12: using an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain micro structural detail information corresponding to the hybrid integrated circuit, so as to capture micro solder joints and wire details of the circuit parts; Step S13: fusing the internal three-dimensional structure information and the structure micro-detail information corresponding to the hybrid integrated circuit to generate a hybrid integrated circuit internal structure mapping map; Step S14: predicting key detection points of each port part in the hybrid integrated circuit based on the internal structure mapping map of the hybrid integrated circuit, so as to predict and extract nodes on the high-frequency signal transmission path of the circuit and pins of electronic components with large power dissipation, and generate different ports and key detection points corresponding to the hybrid integrated circuit; installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key detection points corresponding to the hybrid integrated circuit; Step S15: obtaining the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit; fixing the hybrid integrated circuit after installing the detection equipment on the test fixture, and performing adaptation and installation calibration on the corresponding detection equipment on the hybrid integrated circuit based on the physical dimensions and surface material characteristics corresponding to the hybrid integrated circuit, so as to adaptively adjust the corresponding measurement range and sensitivity of the detection equipment, and generate adaptation and installation parameters of the calibration detection equipment; performing pre-detection preparation on the corresponding detection equipment on the hybrid integrated circuit based on the adaptation and installation parameters of the calibration detection equipment, so as to generate a fully tested hybrid integrated circuit.

3. The hybrid integrated circuit intelligent detection method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: starting the electrical parameter tester, the infrared thermal imager and the electromagnetic compatibility analyzer to synchronously collect multi-modal data of the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; Step S22: performing time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate an electrical parameter set corresponding to the hybrid integrated circuit in the same timing range; Step S23: obtaining the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit; Step S24: acquiring characteristic parameters of electronic components corresponding to the hybrid integrated circuit, and performing an acceptable fluctuation range analysis on various electrical parameters corresponding to the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, so as to obtain the acceptable fluctuation range values ​​corresponding to various electrical parameters of the hybrid integrated circuit; determining the maximum and minimum threshold values ​​of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, calibrated resistance and calibrated capacitance corresponding to the hybrid integrated circuit, so as to obtain the maximum and minimum threshold values ​​corresponding to various electrical parameters of the hybrid integrated circuit; Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range, electrical fault detection is performed on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit to generate a circuit electrical fault detection result.

4. The hybrid integrated circuit intelligent detection method according to claim 3, characterized in that: The electrical parameter set in step S21 specifically includes current, voltage, resistance and capacitance parameters corresponding to the hybrid integrated circuit.

5. The hybrid integrated circuit intelligent detection method according to claim 3, characterized in that: Step S25 includes the following steps: Extracting the electrical parameter set corresponding to the hybrid integrated circuit in the same timing range at the timing point, and obtaining the specific value of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific value of current, voltage, resistance and capacitance; If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is less than the minimum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, then it is detected that the hybrid integrated circuit has an open circuit fault; If the specific value of the current corresponding to the hybrid integrated circuit at each timing point is greater than the maximum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to the hybrid integrated circuit at each timing point is less than the minimum voltage threshold corresponding to the hybrid integrated circuit, then the hybrid integrated circuit is detected and judged to have a short circuit fault; If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is zero and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, it is detected that the hybrid integrated circuit has a circuit breaker fault; If the specific value of resistance corresponding to the hybrid integrated circuit at each timing point is greater than the maximum resistance threshold or less than the minimum resistance threshold, or the specific value of capacitance corresponding to the hybrid integrated circuit at each timing point is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, then the detection determines that the hybrid integrated circuit has a parameter drift fault.

6. The hybrid integrated circuit intelligent detection method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: obtaining the size, spacing and arrangement of electronic components corresponding to the chip in the tested hybrid integrated circuit; Step S32: performing chip thermal conduction topology analysis on the tested hybrid integrated circuit based on the size, spacing and arrangement of electronic components, so as to clearly display the thermal conduction network from the heating components to the heat dissipation path, and obtain the internal thermal conduction topology network of the circuit chip; Step S33: performing a thermal stress distribution analysis on the tested hybrid integrated circuit based on the internal heat conduction topology network of the circuit chip to generate a thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit; Step S34: performing thermal failure fault detection on the corresponding tested complete hybrid integrated circuit based on the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit, so as to determine each thermal abnormality sensitive area according to the thermal stress distribution corresponding to each part of the chip, and determining whether a corresponding thermal failure phenomenon occurs according to the temperature change corresponding to each thermal abnormality sensitive area according to a preset thermal failure critical temperature threshold, so as to generate a circuit thermal failure fault detection result; Step S35: performing electromagnetic interference fault detection on the tested hybrid integrated circuit based on the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to generate a circuit electromagnetic interference fault detection result.

7. The hybrid integrated circuit intelligent detection method according to claim 6, characterized in that: Step S35 includes the following steps: Step S351: obtaining the layout and connection mode of each electronic component and wire in the tested hybrid integrated circuit, and performing electromagnetic radiation interference impact assessment on the tested hybrid integrated circuit based on the layout and connection mode of each electronic component and wire to generate an electromagnetic radiation interference impact factor; Step S352: obtaining a normal working electromagnetic spectrum of the circuit corresponding to the hybrid integrated circuit, and performing an electromagnetic phase difference analysis on the circuit operation electromagnetic radiation spectrum based on the normal working electromagnetic spectrum of the circuit corresponding to the hybrid integrated circuit to obtain the integrated circuit operation electromagnetic radiation phase difference; Step S353: performing electromagnetic interference amplitude and frequency analysis on the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to obtain the electromagnetic interference amplitude and the electromagnetic interference frequency of the integrated circuit; Step S354: Based on the electromagnetic radiation interference influencing factor, the integrated circuit operation electromagnetic radiation phase difference, the integrated circuit electromagnetic interference amplitude and the integrated circuit electromagnetic interference frequency, the electromagnetic interference calculation formula is used to calculate the electromagnetic interference of the circuit operation electromagnetic radiation spectrum corresponding to the hybrid integrated circuit to obtain the electromagnetic radiation interference value corresponding to the hybrid integrated circuit; Step S355: Compare and judge the electromagnetic radiation interference value corresponding to the hybrid integrated circuit according to the preset circuit electromagnetic interference fault threshold. If the electromagnetic radiation interference value is greater than or equal to the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has external electromagnetic source interference; if the electromagnetic radiation interference value is less than the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has electromagnetic interference generated by the internal circuit, so as to generate a circuit electromagnetic interference fault detection result.

8. The hybrid integrated circuit intelligent detection method according to claim 7, characterized in that: The electromagnetic radiation interference calculation formula described in step S354 is specifically: ； In the formula, is the electromagnetic radiation interference value, Calculate the time interval for electromagnetic interference, is the time variable parameter, It is the total component of the corresponding frequency components in the electromagnetic radiation spectrum of the circuit operation. For circuit operation within the electromagnetic radiation spectrum The electromagnetic interference amplitude of the integrated circuit corresponding to the frequency component is For circuit operation within the electromagnetic radiation spectrum The integrated circuit electromagnetic interference frequency corresponding to the frequency component is For circuit operation within the electromagnetic radiation spectrum The electromagnetic radiation phase difference between the frequency component and the normal working electromagnetic spectrum is is the frequency component of electromagnetic radiation, For the The electromagnetic radiation attenuation factor corresponding to the frequency component is: For the The electromagnetic interference suppression constant corresponding to the frequency component is: It is the correction factor of the electromagnetic radiation interference value.

9. The hybrid integrated circuit intelligent detection method according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: performing fault mode feature analysis on the corresponding hybrid integrated circuit based on the circuit electrical fault detection result, the circuit thermal failure fault detection result or the circuit electromagnetic interference fault detection result, so as to extract the abnormal current and voltage fluctuation of the corresponding electrical fault, the uneven temperature distribution of the thermal failure fault and the abnormal spectrum feature of the electromagnetic interference fault for each fault type, and clarify the relationship between different fault types and features, so as to obtain the abnormal fault mode feature corresponding to the hybrid integrated circuit; Step S42: performing a deep analysis of the fault root cause of the hybrid integrated circuit based on the abnormal characteristics of the fault mode corresponding to the hybrid integrated circuit, so as to identify clues of the fault root cause hidden under the fault phenomenon of the hybrid integrated circuit, so as to generate: a clue set of deep analysis of the circuit fault root cause; Step S43: Recommend fault repair for the hybrid integrated circuit based on the clue set of the circuit fault root cause in-depth analysis, and generate a recommended repair plan for the fault level of the hybrid integrated circuit, including electronic component replacement and circuit rewiring strategies for electrical faults, heat dissipation system optimization and electronic component derating for thermal failures, and electromagnetic interference faults. If it is caused by an external electromagnetic source, an electromagnetic shielding cover is added to effectively block external interference from entering the hybrid integrated circuit; if it is electromagnetic interference generated by an internal circuit, the circuit layout is replanned to reduce crosstalk between signals, so as to perform the corresponding hybrid integrated circuit fault repair work.

10. A hybrid integrated circuit intelligent detection system, characterized in that: Used to execute the hybrid integrated circuit intelligent detection method according to claim 1, the hybrid integrated circuit intelligent detection system comprises: The circuit test preparation module is used to prepare for the test by installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer at the corresponding different ports and key parts in the hybrid integrated circuit, and fixing the hybrid integrated circuit with the installed test equipment on a test fixture to generate a fully tested hybrid integrated circuit; The synchronous acquisition and electrical detection module is used to start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to synchronously acquire multi-modal data of the tested complete hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set corresponding to the hybrid integrated circuit, the chip operating temperature distribution and the circuit operation electromagnetic radiation spectrum; based on the electrical parameter set corresponding to the hybrid integrated circuit, the electrical fault detection of the tested complete hybrid integrated circuit is performed, so as to generate the circuit electrical fault detection result; The thermal failure and electromagnetic interference detection module is used to perform thermal failure and magnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution corresponding to the hybrid integrated circuit and the circuit operation electromagnetic radiation spectrum, so as to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results; The circuit fault recommendation repair module is used to recommend fault repair for the corresponding hybrid integrated circuit based on the circuit electrical fault detection results, circuit thermal failure fault detection results or circuit electromagnetic interference fault detection results, and generate a recommended repair plan for the fault degree corresponding to the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

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