Linear frequency digit generation method and system

Abstract

The invention relates to a linear frequency digit generation method and system. The method comprises the following steps: determining a total cycle period, a maximum frequency coefficient, minimum frequency division precision, a frequency coefficient and a linear frequency range based on an application scene; acquiring a current frequency division clock corresponding to the current application scene, and calculating control parameters required during current frequency division control; waiting for completion of control parameter calculation and taking effect; performing frequency division control based on the control parameter, and when the falling edge of the original clock arrives, generating a clock gating signal according to the value of the counter in the period; and the steps are sequentially alternated until the total cycle period is reached. According to the invention, linear frequency generation and application scenes are combined, frequency division control is realized by adopting a digital logic mode, different requirements of different application scenes can be adapted, and EMC performance can be effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of clock control, and in particular relates to a linear frequency digital generation method and system. Background Art

[0002] Clock signals can be distributed throughout the processor to facilitate the operation of the processor. For example, state elements (e.g., flip-flops, latches, etc.) located at different points on the processor chip can be synchronized by operating according to the clock signal. When a large, sudden current demand occurs, the on-chip voltage supply provided to the state element will "drop" (e.g., within a few nanoseconds), while the PLL continues to generate a clock signal at a fixed frequency. Traditional fractional frequency phase-locked loop multi-mode divider (MMD); reference frequency source (Reference), used to generate the basic comparison frequency of the phase-locked loop; voltage-controlled oscillator (VCO), used to output a signal with a frequency that is N times the output frequency of the reference source (N can be an integer or a fraction); phase frequency detector (PFD), used to compare the phase difference between the reference frequency and the feedback output frequency of the divider; charge pump (CP) and loop filter circuit (LPF), used to negatively feedback control the output frequency of the voltage-controlled oscillator to produce the desired output frequency; and fractional modulator (Modulator), used to control the multi-mode divider to produce the desired fractional division ratio.

[0003] The main methods for generating linear frequency (such as linear frequency modulation signal, LFM) based on digital circuits are: linear frequency modulation based on DDS (Direct Digital Synthesis) technology; DDS technology is a high-precision frequency synthesis method that generates frequency signals in a digital way, with the advantages of high frequency resolution, fast switching speed, and phase continuity. DDS generates a linear frequency modulation signal by changing the frequency control word (Fword) so that the output frequency changes linearly with time. In terms of hardware implementation, FPGA can be used to implement the DDS module, such as Xilinx's FPGA and the DDS IP core it provides;

[0004] The problems existing in the prior art are as follows: on the one hand, the conventional method of dividing the clock frequency by N means converting the clock frequency into the original clock frequency. , the frequency division only follows the inverse proportional curve, and cannot generate a dynamic linear frequency that adapts to the specific application scenario; on the other hand, the traditional use of PLL to achieve precise clock output will significantly increase the cost of the chip; finally, the traditional clock frequency generation method cannot adapt to the specific application scenario, and thus cannot provide sufficient flexibility and provide the greatest adaptability support for application implementation. In some application scenarios, for example: PLL is not needed in medical scenarios, such as high-voltage chips with integrated charge pumps on-chip, the clock signal of the charge pump can be realized through digital design to achieve linear frequency; similarly, the PWM control signal of the switching power supply application can also be generated using a linear frequency clock to achieve low-cost and high-precision control; based on the above problems, the present invention combines the generation of linear frequency with the application scenario, and uses digital logic to achieve frequency division control, which can adapt to the different needs of different application scenarios, for example: for scenarios that focus on electromagnetic compatibility, it can effectively improve EMC performance. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present invention proposes a linear frequency digital generation method and system, the method comprising:

[0006] Step S1: Determine the total cycle period based on the application scenario , Maximum frequency coefficient , minimum frequency division accuracy , frequency coefficient And the linear frequency range ;in: is the total cycle period of the original clock; That is, the value corresponding to the maximum value of the linear frequency coefficient; Indicates the minimum frequency division accuracy; N indicates the frequency coefficient, and its value range is ; and Respectively represent the minimum and maximum frequency clock;

[0007] Step S2: For each divided clock , set the first cycle period and the second cycle period for frequency division control; obtain the current frequency division clock corresponding to the current application scenario and its frequency division coefficient N, calculate the control parameters required for the current frequency division control, including: the first cycle , the first cycle number of the first cycle , the second cycle , the second cycle number of the second cycle , used to control parameters in the generation process of each divided clock;

[0008] Step S3: Wait for the control parameter calculation to be completed and take effect;

[0009] Step S4: Cycle Type Counter When it is 0, the counter in the preload cycle for or ; Reset the first and second cycle times to default values; when Reset to default value after reaching N; set the intra-cycle counter when entering this step for the first time , and set ; When entering this step again, set the cycle counter to , and set ; Alternate in sequence until the total cycle is reached;

[0010] Step S5: When the original clock When the falling edge arrives, according to the counter in the cycle The value of generates a clock gating signal; the counter is set during the update cycle .

[0011] Furthermore, the application scenario includes system scenario, application scenario and user scenario; the system scenario is information related to the operating system and / or the underlying chip, the application scenario information is information related to the application type and its use, and the user information is information related to the current user;

[0012] When the original clock When the falling edge arrives, according to the counter in the cycle The value of generates a clock gating signal, specifically: in each cycle in which the counter counts within the cycle, each cycle is the first cycle or the second cycle, when the original clock When the falling edge arrives, the counter in the cycle is judged If the value of , the clock gating signal is set to 1, otherwise it is cleared to 0; when the clock gating signal is set to 1, the corresponding clock gating signal is , shield the current original clock The clock pulse generates the divided part of the clock in this cycle. ,set up , return to step S4; when the clock gating signal is 0, the current original clock is not shielded The clock pulse of In a fixed total cycle, N clock pulses are shielded to achieve the following The linear frequency shown in the figure makes the shielded N clock pulses evenly distributed on within the total cycle.

[0013] Furthermore, setting The initial value is the original clock , that is, when N=0 ; is the minimum frequency clock, is the linear frequency coefficient The frequency corresponding to .

[0014] Furthermore, the calculation of the expected maximum frequency clock , specifically: Set the maximum frequency clock .

[0015] Furthermore, the minimum expected frequency clock is determined based on the application scenario in the application scenario. , specifically: Get the expected minimum frequency clock required from the application scenario requirement information .

[0016] Furthermore, the divided clock In addition to meeting the need , In addition, it is necessary to further optimize parameters to meet the logic requirements of digital circuit design while satisfying the application scenarios.

[0017] A linear frequency digital generation system is provided, and the linear frequency digital generation system is used to implement the linear frequency digital generation method.

[0018] A linear frequency digital generation control device is provided, and the linear frequency digital generation control device is used to implement the linear frequency digital generation method.

[0019] A linear frequency digital generation control chip is used to implement the linear frequency digital generation method.

[0020] A linear frequency digital generation control circuit, wherein the linear frequency digital generation module is used to implement the linear frequency digital generation method.

[0021] The beneficial effects of the present invention include:

[0022] (1) To adapt to and subdivide the requirements of application scenarios, it is necessary to set the clock change interval and frequency division according to the different layer requirements of the application scenarios, and then make specific frequency selection according to different system settings, application types, and the characteristics and stages of users in the application scenarios; it is able to combine the frequency division settings of the underlying hardware with the application scenarios of the operating system layer and the application layer, so that the frequency division settings can pass through the operating system layer to provide an application scenario adaptation interface; thus, for scenarios that focus on electromagnetic compatibility, the EMC performance can be effectively improved; starting from the resource demand characteristics, the present invention guides the entry into the operating mode or low power consumption mode through quantitative analysis based on the combination of dynamic and static information, thereby improving the accuracy of entering the operating mode or low power consumption mode.

[0023] (2) The linear frequency is uniformly generated through digital logic, so that the linear frequency is evenly distributed in the frequency range that meets the requirements of the application scenario. Low-cost and high-precision control is achieved based on digital logic design, which solves the problem of the inverse proportional frequency division curve having fewer gears in the high-frequency area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application, but do not constitute an improper limitation of the present invention. In the drawings:

[0025] Figure 1 This is a schematic diagram of the linear frequency digital generation method provided by the present invention.

[0026] Figure 2 The maximum frequency coefficient provided by the present invention is Schematic diagram of the linear frequency digitally generated waveform when .

[0027] Figure 3 The maximum frequency coefficient provided by the present invention is Schematic diagram of control parameters when . DETAILED DESCRIPTION

[0028] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the illustrative embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0029] The present invention provides a linear frequency digital generation method and system, such as Figure 1 As shown, the method comprises the following steps:

[0030] Step S1: Determine the total cycle period based on the application scenario , Maximum frequency coefficient , minimum frequency division accuracy , frequency coefficient And the linear frequency range ;in: is the total cycle period of the original clock; That is, the value corresponding to the maximum value of the linear frequency coefficient; where: Indicates the minimum frequency division accuracy or the minimum step size of frequency change; N represents the linear frequency coefficient, and its value range is ; and Respectively represent the minimum and maximum frequency clocks; wherein: the application scenario includes system scenario, application scenario and user scenario; the system scenario is information related to the operating system and / or the underlying chip, the application scenario information is information related to the application type and its use, and the user information is relevant information of the current user;

[0031] Preferred: Setting The initial value is the original clock , that is, when N=0 ; is the minimum frequency clock, is the linear frequency coefficient The frequency corresponding to the time

[0032] The step S1 specifically includes the following steps:

[0033] Step S11: Obtaining the original clock according to the application scenario , expected frequency division accuracy Or expected maximum frequency coefficient One of the desired minimum frequency clock , expected maximum frequency clock ; Specifically: Get the original clock based on the system scenario in the application scenario ; Determine the expected frequency division accuracy based on the application scenario in the application scenario Or expected maximum frequency coefficient , the expected minimum frequency clock , calculate the expected maximum frequency clock ; These parameters are limited by the frequency division requirements of the application scenario;

[0034] The calculation of the expected maximum frequency clock , specifically: Set the maximum frequency clock ;

[0035] Alternative: The calculation of the expected maximum frequency clock , specifically: Determine the expected maximum frequency clock based on the application scenario in the application scenario ;

[0036] The method of determining the expected minimum frequency clock based on the application scenario in the application scenario , specifically: Get the expected minimum frequency clock required from the application scenario requirement information ;

[0037] Step S12: Based on the expected minimum frequency clock Determine the minimum frequency clock ; Specifically: Set Of course, the pre-minimum frequency clock can be adjusted according to the system resource settings; for example, the precision of a specific number of bits can be adjusted to reduce the precision limit to meet the system resource settings or the implementation requirements of the underlying hardware;

[0038] Step S13: Determine the pre-scaling accuracy , Pre-maximum frequency coefficient ; Specifically: obtain the application type from the application scenario. When the application type is sensitive to frequency accuracy, obtain the expected minimum frequency division accuracy from the application scenario. When the application scenario is sensitive to the number of divided clocks, obtain the expected maximum frequency coefficient from the application scenario ;

[0039] Step S14: Based on the information obtained from the application scenario or Get one of or ; Specifically:

[0040] The or Get one of or , specifically: when the application scenario When known, the parameters are calculated by the following formula (1) (2) :

[0041] (1);

[0042] (2);

[0043] when When known, the parameters are calculated by the following formula (3) (4) ;

[0044] (3);

[0045] (4);

[0046] Divided clock In addition to meeting the need , In addition, it is necessary to further optimize the parameters to meet the logic requirements of digital circuit design under the premise of meeting the application scenario, mainly involving and Adjustment of

[0047] Step S15: Fine-tuning parameters or , , in order to obtain the digital circuit design requirements or , ; The parameters obtained in the above steps or , It may not meet the requirements of digital circuit design, for example: is the frequency, calculated It may be a decimal, but the frequency Usually an integer; in addition, Needs to be satisfied It must be an integer to meet one of the requirements for digital circuit design;

[0048] The step S14 specifically includes: performing fine adjustment based on the following conditions 1 to 4;

[0049] Condition 1: ,and Close to ;

[0050] Condition 2: ,and Close to ;

[0051] Condition 3: ,and Close to ;

[0052] Condition 4: is an integer;

[0053] Step S16: Calculate the total cycle time ; Specifically: Set the total cycle of the original clock ;and can be divided evenly, that is is an integer; by In a fixed cycle, N clock pulses are shielded to achieve the following The linear frequency shown; further, the shielded N clock pulses are evenly distributed in The total cycle period can better meet the needs of the application scenario; therefore, the total cycle period needs to be determined according to the specific application scenario;

[0054] Step S2: For each current divided clock , set the first cycle period and the second cycle period for frequency division control; obtain the current frequency division clock corresponding to the current application scenario and its frequency division coefficient N, calculate the control parameters required for the current frequency division control, including: the first cycle , the first cycle number of the first cycle , the second cycle , the second cycle number of the second cycle , used to control parameters in the generation process of each divided clock;

[0055] The current frequency division clock corresponding to the current application scenario is obtained. And its division coefficient N, specifically: Get the user division clock based on the user scenario in the application scenario ; Determine the user divided clock required at the maximum frequency The closest corresponding calculation of the current divided clock and its frequency division coefficient N; the current frequency division clock and its frequency division coefficient N are used to calculate the control parameters; when the user uses the application (the application may need to work with the supporting hardware, which will not be described in detail here), the user frequency division clock is obtained based on the user attributes or user settings To meet this user scenario;

[0056] Preferred: The user sets the user frequency division clock through software or hardware The corresponding gear value, based on which the application obtains the corresponding user frequency division clock ;

[0057] The user frequency division clock is obtained based on the user scenario in the application scenario Specifically, the application program writes the user frequency division clock corresponding to the user attribute or user setting into the shared storage space based on the user's needs, wherein: the shared storage space is set in the operating system; the user frequency division clock in the shared storage space is obtained by reading ;

[0058] One implementation method is: the shared storage space is shared by the hardware part of the linear frequency digital generation system and the software part where the application scenario related data is located; the software part obtains the application scenario based on the application scenario, and obtains the maximum frequency from the application scenario , and the current divided clock frequency determined based on the user needs of the current user of the application and its frequency division coefficient N; the current frequency division clock and its frequency division coefficient N are written into the shared storage space; of course, the linear frequency digital generation system itself can be set to include a hardware part and a software part where the application scenario related data is located, and the software part is used to interact with the application to obtain application scenario related information; the software part where the application scenario related data is located can also be set as a part of the application itself;

[0059] The control parameters required for calculating the current frequency division control are as follows: Based on the following formulas (5) to (8), the first cycle period is calculated: , the first cycle number of the first cycle , the second cycle , the second cycle number of the second cycle ;in: and ; ; It can be seen that the quotient of formula (5) is the first cycle period The remainder of formula (4) is the second cycle period. Number of cycles; N=0 means maintaining the maximum frequency, When, because of the symmetry , , and Select The corresponding value;

[0060] (5);

[0061] (6);

[0062] (7);

[0063] (8);

[0064] Preferred: Setting , , , , so that it satisfies formula (9); In the fixed cycle, there are two types of cycles: the first cycle and the second cycle. The total count of the two cycles is equivalent to Fixed cycle count period;

[0065] (9);

[0066] Preferably: the linear frequency digital generation hardware device is used to calculate the control parameters required for the current frequency division control;

[0067] Step S3: waiting for the control parameter calculation to be completed and to take effect; specifically: waiting for the digital logic to complete the control parameter calculation and take effect;

[0068] The waiting for the digital logic to complete the calculation of the control parameter and take effect is specifically as follows: after the digital logic of the hardware part of the linear frequency digital generation system completes the calculation of the control parameter, it writes it into the storage space of the hardware part of the linear frequency digital generation system; after reading the storage space of the hardware part and being able to read out a valid value, it indicates that the calculation of the control parameter is completed and , , , The loading has been completed; the valid flag FLAG is set as the control parameter to take effect; at this time: the storage space of the hardware part is implemented by a register device;

[0069] Alternatively: when the calculation of the control parameter is completed by the software part, after the software part completes the calculation of the control parameter, it is written into the storage space of the hardware part of the linear frequency digital generation system;

[0070] Step S4: Cycle Type Counter When it is 0, the counter in the preload cycle for or ; Reset the first and second cycle times to default values; when Reset to default value after reaching N; set the intra-cycle counter when entering this step for the first time , and set ; When entering this step again, set the cycle counter to , and set ; Alternate in sequence;

[0071] Preferred: During the alternation process, if or If it is 0, the counter in the cycle is set is non-zero and corresponds to the cycle period (the first cycle period or the second cycle period); when both are 0, It will also reach N accordingly, and then be reset to the default value, and then enter a new round of total cycle cycle;

[0072] Preferred: Periodic type counter The default value is 0. Obviously, when entering the total cycle for the first time, the cycle type counter The default values ​​of the first and second cycle times are the values ​​calculated and effective in step S3;

[0073] Alternative: When first entering this step, set the cycle counter , when entering this step again, set the cycle counter to ; Alternate in sequence;

[0074] Step S5: When the original clock When the falling edge arrives, according to the counter in the cycle The value of generates a clock gating signal; the counter is set during the update cycle ;

[0075] like Figure 2 As shown, when the original clock When the falling edge arrives, according to the counter in the cycle The value of generates a clock gating signal, specifically: in each cycle (first cycle or second cycle) during which the counter counts within the cycle, when the original clock When the falling edge arrives, the counter in the cycle is judged If the value of , the clock gating signal is set to 1, otherwise it is cleared to 0; when the clock gating signal is set to 1, the corresponding clock gating signal is , shield the current original clock The clock pulse generates the divided part of the clock in this cycle. ,set up , return to step S4; when the clock gating signal is 0, the current original clock is not shielded That is, at In a fixed total cycle, N clock pulses are shielded to achieve the following The linear frequency shown in the figure makes the shielded N clock pulses evenly distributed on During the total cycle;

[0076] The shielding current original clock The clock pulse generates the divided clock ; Specifically: Generate a gating signal Signal; Generates a divided clock signal ; By repeating the first cycle or the second cycle and the total cycle , and repeat the above process to cyclically generate a divided clock that meets the requirements of the application scenario;

[0077] Further: When performing frequency division control, use a periodic type counter The cycle type counting is performed so that the first cycle and the second cycle are evenly distributed in the total cycle, so that the value of the counter in the cycle is counted repeatedly in a uniformly distributed manner; the alternating control method is: in setting When; Set the cycle type controller ;like , then set ; Otherwise, set , return to step S5; it can be seen that each time After decreasing to 1, according to Determine the next load still , to achieve uniform distribution, The counting is repeated in this way; Of course, during the alternating process, if or If it is 0, the counter in the cycle is set is non-zero and corresponds to the cycle period (the first cycle period or the second cycle period); when both are 0, will also reach N accordingly, and then be reset to the default value, and then enter a new round of total cycle cycle; in the alternating process, if or If it is 0, the counter in the cycle is set is non-zero and corresponds to the cycle period (the first cycle period or the second cycle period); when both are 0, It will also reach N accordingly, and then be reset to the default value, and then enter a new round of total cycle cycle;

[0078] In order to further improve the uniformity, alternatively, the alternating control method is to make the first cycle period and the second cycle period in the total cycle period. The total cycle period is In this way, the shielded N original clock pulses are evenly distributed in In each total cycle Within, the first cycle period and the second cycle period are uniformly cross-distributed based on the first cycle number and the second cycle number respectively; when satisfying On the basis of the two types of cycle periods and cycle times, the two types of cycle periods and cycle times are evenly distributed as a whole, so that the shielded N clock pulses are evenly distributed in During the total cycle; set the binary control variable , the two types of cycle periods and cycle times are evenly cross-distributed to achieve uniform distribution of the shielded N clock pulses in In the total cycle, due to the symmetry relationship, only Therefore, setting the binary control variable The bit width is , for the current frequency coefficient N, High bit Invalid ignored, each bit in the low bit [N-1:0] is used to indicate the total cycle period The cycle type of each of the N loops executed in the loop. Each bit is used to control the cycle type of the current loop. A value of 1 indicates that the second cycle is executed, and a value of 0 indicates that the first cycle is executed.

[0079] Setting the binary control variable , the two types of cycle periods and the number of cycles are reasonably cross-allocated, specifically:

[0080] Scenario 1: If And N≠0, set CTRL[N-1:0] to all 0;

[0081] Scenario 2: If , N≠0, and , then set The corresponding bit is equal to 0, ; The remaining bits are equal to 1; where: ;

[0082] Scenario 3: If , N≠0, and , then set The corresponding bit is equal to 1, ; The rest of the bits are equal to 0; where: ;

[0083] Scenario 4: , N≠0, , then set it according to the symmetric relationship; The symbol is the mathematical symbol used to indicate rounding up.

[0084] like Figure 2 In the example The following are several cases when the current frequency coefficient N=3, 8 and 12 are shown in detail; the frequency N=3 means a total cycle period Three original clocks need to be shielded The pulse, Figure 2 The gating signal is indicated in Signal, the gate signal is set to 1 to indicate the original clock that needs to be shielded The location of the pulse;

[0085] Example 1

[0086] The actual application scenario is , , ;Optimize parameters ; ; Substitute get , to ensure For integers, select ,at this time, , and satisfies ; Therefore, the optimized parameters are obtained: , , , N can take values ​​ranging from 0 to 15; the current value of N can be determined according to the user scenario; based on the linear frequency division calculation formula: ; Then when The first cycle , the first cycle number of the first cycle , the second cycle , the second cycle number of the second cycle will change as N changes within the range of 0 to 15, and the uniformly distributed control variables In the calculation, The control parameters are as follows Figure 3 As shown; Based on the same inventive concept, the present invention also provides a linear frequency digital generation system, the system is used to complete the above linear frequency digital generation method;

[0087] The linear frequency digital generation system is implemented by hardware, for example: a digital logic circuit obtains application scenario related data through a shared storage space; after the digital logic of the hardware part of the linear frequency digital generation system completes the calculation of the control parameter, it writes it into the storage space of the hardware part of the linear frequency digital generation system; after reading the storage space of the hardware part and being able to read out a valid value, it indicates that the control parameter calculation is completed and , , , The loading has been completed; set the valid flag FLAG as the control parameter to take effect;

[0088] Alternatively: the linear frequency digital generation system includes a hardware part and a software part; the hardware part works after waiting for the digital logic to complete the calculation of the control parameter and take effect, while the software part works before waiting for the digital logic to complete the calculation of the control parameter and take effect; the software part obtains application scenario related data through application layer data interaction; after the digital logic of the hardware part of the linear frequency digital generation system completes the calculation of the control parameter, it writes it into the storage space of the hardware part of the linear frequency digital generation system; after reading the storage space of the hardware part and being able to read out a valid value, it indicates that the control parameter calculation is completed and , , , The loading has been completed; set the valid flag FLAG as the control parameter to take effect;

[0089] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of a programming language, including an assembled or interpreted language, a declarative or procedural language, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0090] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0091] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0092] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0093] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A linear frequency digital generation method, characterized in that: The method comprises: Step S1: Determine the total cycle period based on the application scenario , Maximum frequency coefficient , minimum frequency division accuracy , frequency coefficient And the linear frequency range ;in: is the total cycle period of the original clock; That is, the value corresponding to the maximum value of the linear frequency coefficient; Indicates the minimum frequency division accuracy; N indicates the frequency coefficient, and its value range is ; and Respectively represent the minimum and maximum frequency clock; Step S2: For each divided clock , set the first cycle and the second cycle to perform frequency division control; obtain the current frequency division clock corresponding to the current application scenario and its frequency division coefficient N, calculate the control parameters required for the current frequency division control, including: the first cycle , the first cycle number of the first cycle , the second cycle , the second cycle number of the second cycle , used to control parameters in the generation process of each divided clock; Step S3: Wait for the control parameter calculation to be completed and take effect; Step S4: Cycle Type Counter When it is 0, the counter in the preload cycle for or ; Reset the first and second cycle times to default values; when Reset to default value after reaching N; set the intra-cycle counter when entering this step for the first time , and set ; When entering this step again, set the cycle counter to , and set ; Alternate in sequence until the total cycle is reached; Step S5: When the original clock When the falling edge arrives, according to the counter in the cycle The value of generates a clock gating signal; the counter is set during the update cycle .

2. The linear frequency digital generation method according to claim 1, characterized in that: The application scenarios include system scenarios, application scenarios and user scenarios; the system scenario is information related to the operating system and / or underlying chip, the application scenario information is information related to the application type and its use, and the user information is information related to the current user; When the original clock When the falling edge arrives, according to the counter in the cycle The value of generates a clock gating signal, specifically: in each cycle in which the counter counts within the cycle, each cycle is the first cycle or the second cycle, when the original clock When the falling edge arrives, the counter in the cycle is judged If the value of , the clock gating signal is set to 1, otherwise it is cleared to 0; when the clock gating signal is set to 1, the corresponding clock gating signal is , shield the current original clock The clock pulse generates the divided part of the clock in this cycle. ,set up , return to step S4; when the clock gating signal is 0, the current original clock is not shielded The clock pulse of In a fixed total cycle, N clock pulses are shielded to achieve the following The linear frequency shown in the figure makes the shielded N clock pulses evenly distributed on within the total cycle.

3. The linear frequency digital generation method according to claim 2, characterized in that: set up The initial value is the original clock , that is, when N=0 ; is the minimum frequency clock, is the linear frequency coefficient The frequency corresponding to .

4. The linear frequency digital generation method according to claim 3, characterized in that: Calculate the expected maximum frequency clock , specifically: Set the maximum frequency clock .

5. The linear frequency digital generation method according to claim 4, characterized in that: The method of determining the expected minimum frequency clock based on the application scenario in the application scenario , specifically: Get the required minimum frequency clock from the application scenario requirement information .

6. The linear frequency digital generation method according to claim 5, characterized in that: Divided clock In addition to meeting the need , In addition, it is necessary to further optimize parameters to meet the logic requirements of digital circuit design while satisfying the application scenarios.

7. A linear frequency digital generation system, characterized in that: The linear frequency digital generation system is used to implement the linear frequency digital generation method described in any one of claims 1 to 6.

8. A linear frequency digital generation control device, characterized in that: The linear frequency digital generation control device is used to implement the linear frequency digital generation method described in any one of claims 1 to 6.

9. A linear frequency digital generation control chip, characterized in that: The linear frequency digital generation control chip is used to implement the linear frequency digital generation method described in any one of claims 1 to 6.

10. A linear frequency digital generation control circuit, characterized in that: The linear frequency digital generation module is used to implement the linear frequency digital generation method described in any one of claims 1 to 6.

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